Semiconductor device

Abstract

To ensure a high breakdown voltage and reduce an on-resistance.SOLUTION: A semiconductor substrate of a semiconductor device includes a first conductivity type upper region, a second conductivity type electric field relaxation region, a super junction region, and a plurality of first conductivity type connection regions. When the semiconductor substrate is viewed from above, each second conductivity type column region and each first conductivity type column region of the super junction region extend linearly along a first direction and are alternately arranged along a second direction. A plurality of opening parts provided in the electric field relaxation region is disposed in a dispersed manner. Each first conductivity type connection region is disposed in the corresponding opening part and connects the first conductivity type upper region and the corresponding first conductivity type column region. A second conductivity type impurity concentration of each second conductivity type column region is lower than a second conductivity type impurity concentration of the electric field relaxation region. When the semiconductor substrate is viewed from above, each second conductivity type column region does not overlap each opening part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a MOSFET (metal-oxide-semiconductor field-effect transistor) including a semiconductor substrate, a source electrode, and a drain electrode. In this MOSFET, the semiconductor substrate has an upper parallel pn structure and a lower parallel pn structure. The upper parallel pn structure has an upper p-type column region and an upper n-type column region. When viewed from above the semiconductor substrate, the upper p-type column region and the upper n-type column region extend linearly along a first direction and are alternately arranged along a second direction perpendicular to the first direction. The lower parallel pn structure is arranged below the upper parallel pn structure and has a lower p-type column region and a lower n-type column region. When viewed from above the semiconductor substrate, the lower p-type column region and the lower n-type column region extend linearly along the second direction and are alternately arranged along the first direction.

[0003] When this MOSFET is turned off, the depletion layer extending from the upper p-type column region to the upper n-type column region relaxes the electric field applied to the gate oxide film. Also, when this MOSFET is turned off, the depletion layer quickly spreads laterally from the pn junction at the interface between the upper p-type column region and the upper n-type column region, and from the pn junction at the interface between the lower p-type column region and the lower n-type column region. This allows this MOSFET to ensure a high breakdown voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-150182 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, the upper p-type column region and the upper n-type column region both extend linearly and are arranged alternately. With this configuration, there is a limit to how fine the pitch of each of the upper parallel pn structure and the lower parallel pn structure can be. Therefore, if the n-type impurity concentration of each n-type column region is increased to reduce the on-resistance, each n-type column region becomes less likely to be depleted when the MOSFET is turned off, resulting in a decrease in the breakdown voltage of the MOSFET. Thus, with the MOSFET of Patent Document 1, it is difficult to ensure both a high breakdown voltage and a reduced on-resistance. This specification proposes a technology for ensuring a high breakdown voltage while reducing the on-resistance. [Means for solving the problem]

[0006] The semiconductor device disclosed in this specification comprises a semiconductor substrate, an upper electrode provided on an upper surface of the semiconductor substrate, and a lower electrode provided on a lower surface of the semiconductor substrate. A current flows between the upper electrode and the lower electrode. The semiconductor substrate has a first-conductivity-type upper region, a second-conductivity-type electric field relaxation region disposed below the first-conductivity-type upper region and connected to the upper electrode, a superjunction region disposed below the electric field relaxation region, and multiple first-conductivity-type connection regions. The superjunction region has multiple second-conductivity-type column regions and multiple first-conductivity-type column regions. When viewed from above, the second-conductivity-type column regions and the first-conductivity-type column regions extend linearly along a first direction and are alternately arranged along a second direction perpendicular to the first direction. The electric field relaxation region has multiple openings penetrating from the upper end to the lower end of the electric field relaxation region. The multiple openings are distributed and arranged within a plane parallel to the upper surface of the semiconductor substrate. Each of the first-conductivity-type connection regions is disposed in a corresponding one of the openings, connecting the first-conductivity-type upper region and the corresponding one of the first-conductivity-type column regions. The second-conductivity-type impurity concentration of each of the second-conductivity-type column regions is lower than the second-conductivity-type impurity concentration of the electric field relaxation region. When the semiconductor substrate is viewed from above, each of the second-conductivity-type column regions does not overlap with each of the openings.

[0007] In this specification, the first conductivity type is either n-type or p-type, and the second conductivity type is the other of n-type and p-type. When the first conductivity type is n-type, the second conductivity type is p-type, and when the first conductivity type is p-type, the second conductivity type is n-type.

[0008] In the semiconductor device described above, an opening is provided in the second-conductivity-type electric field relaxation region, and a first-conductivity-type connection region is provided within the opening. Because the electric field relaxation region is connected to the upper electrode, when the semiconductor device is turned off, a reverse voltage is applied to the pn junction at the interface between the electric field relaxation region and the first-conductivity-type semiconductor region (the first-conductivity-type upper region, the first-conductivity-type connection region, and the first-conductivity-type column region). This causes a depletion layer to extend from the electric field relaxation region to the first-conductivity-type semiconductor region, thereby relaxing the electric field applied within the semiconductor region. Furthermore, because the openings in the electric field relaxation region are dispersed within a plane parallel to the upper surface of the semiconductor substrate, the first-conductivity-type connection region can be more finely partitioned within the plane than in a conventional configuration in which the second-conductivity-type regions and the first-conductivity-type regions are alternately arranged in stripes. Therefore, even if the first-conductivity-type impurity concentration in the first-conductivity-type connection region is high, the depletion layer extends from the electric field relaxation region to almost the entire first-conductivity-type connection region when the semiconductor device is turned off. In this manner, in this semiconductor device, the first conductivity type impurity concentration in the first conductivity type connection region can be made sufficiently high, thereby reducing the on-resistance.

[0009] In this semiconductor device, a superjunction region is disposed below the electric field reduction region. The second-conductivity-type column region and the first-conductivity-type column region of the superjunction region extend linearly in the first direction and are alternately disposed in the second direction. When the semiconductor device is turned off, a depletion layer spreads from the pn junction at the interface between the second-conductivity-type column region and the first-conductivity-type column region into the second-conductivity-type column region and the first-conductivity-type column region. Because the second-conductivity-type column region and the first-conductivity-type column region are arranged in a stripe pattern, when the semiconductor device is turned off, the second-conductivity-type column region and the first-conductivity-type column region (i.e., the superjunction region) are likely to be uniformly depleted. This allows the semiconductor device to ensure a high breakdown voltage. In addition, in this semiconductor device, the second-conductivity-type column regions are disposed at positions that do not overlap with the openings, so the current path is not restricted by the second-conductivity-type column regions. Therefore, current flows efficiently from the lower electrode to the upper electrode via the first conductivity type column region, the first conductivity type connection region, and the first conductivity type upper region, thereby preventing deterioration of on-resistance. As described above, this semiconductor device can ensure high breakdown voltage and reduce on-resistance. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view in plane II of FIG. 1; [Figure 3] 1. FIG. 3 is a cross-sectional view in plane III of FIG. [Figure 4] 3A to 3C are diagrams for explaining the manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] 3A to 3C are diagrams for explaining the manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are diagrams for explaining the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are diagrams for explaining the manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] FIG. 10 is a perspective cross-sectional view of a semiconductor device according to a second embodiment. [Figure 9]FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 11] 10 is a cross-sectional view taken along plane XI of FIG. 9; [Figure 12] 10 is a cross-sectional view of FIG. 9 in plane XII. [Figure 13] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 15] 13. A cross-section in plane XV of FIG. [Figure 16] 13 in plane XVI. DETAILED DESCRIPTION OF THE INVENTION

[0011] In one example semiconductor device disclosed in this specification, when the semiconductor substrate is viewed from above, the openings may be arranged to form a plurality of rows spaced apart along the first direction. The rows may be spaced apart in the second direction. The intervals between adjacent openings in the first direction may be equal. The intervals between adjacent rows in the second direction may be equal.

[0012] In this configuration, the first conductivity type connection regions in the openings are regularly arranged in a plane, which makes it possible to make the on-resistance uniform across the entire semiconductor device.

[0013] In one example of a semiconductor device disclosed in this specification, the super junction region may be a first super junction region, the second conductivity type column region may be a first second conductivity type column region, and the first conductivity type column region may be a first first conductivity type column region. The semiconductor device may further include a second super junction region arranged below the first super junction region. The second super junction region may include a plurality of second second conductivity type column regions and a plurality of second first conductivity type column regions. When viewed from above the semiconductor substrate, the second second conductivity type column regions and the second first conductivity type column regions may extend linearly along a third direction intersecting the first direction and be alternately arranged along a fourth direction perpendicular to the third direction. The second conductivity type impurity concentration of each of the second second conductivity type column regions may be lower than the second conductivity type impurity concentration of the electric field relaxation region.

[0014] In this configuration, by further providing a second superjunction region, the overall length of the superjunction region in the thickness direction of the semiconductor substrate can be increased, thereby ensuring a higher breakdown voltage. Furthermore, the first second-conductivity-type column region and the first first-conductivity-type column region are arranged to intersect with the second second-conductivity-type column region and the second first-conductivity-type column region. Therefore, even if a misalignment occurs between the first superjunction region and the second superjunction region, variations in the area of the current path can be suppressed.

[0015] The semiconductor device disclosed in this specification as an example may further include a second conductivity type connection region that extends upward from the upper surface of the electric field relaxation region and connects the electric field relaxation region and the upper electrode.

[0016] In this configuration, the potential of the electric field relaxation region can be easily fixed to the potential of the upper electrode, while allowing the electric field relaxation region to exhibit its function.

[0017] In one example of the semiconductor device disclosed in this specification, the semiconductor device may further include a trench provided on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of the trench, and a gate electrode provided inside the trench and insulated from the semiconductor substrate by the gate insulating film.The semiconductor substrate may further include a first conductivity type source region exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film, and a second conductivity type body region in contact with the gate insulating film below the source region and separating the first conductivity type upper region from the source region.The first conductivity type upper region may be in contact with the gate insulating film below the body region.Furthermore, when the semiconductor substrate is viewed from above, each of the openings may not overlap with the trench.

[0018] In this configuration, when the semiconductor substrate is viewed from above, each opening is located so as not to overlap with the trench (i.e., the electric field relaxation region overlaps with the trench), so that when the semiconductor device is turned off, the electric field relaxation region can suitably relax the electric field applied to the bottom end of the trench.

[0019] In one example of the semiconductor device disclosed in this specification, the semiconductor device may further include a gate electrode provided on the upper surface of the semiconductor substrate via a gate insulating film. The semiconductor substrate may further include a first conductivity type source region exposed on the upper surface of the semiconductor substrate, and a second conductivity type body region provided adjacent to the source region and exposed on the upper surface of the semiconductor substrate. The first conductivity type upper region may be provided adjacent to the body region, separated from the source region by the body region, and exposed on the upper surface of the semiconductor substrate. The gate electrode may face the first conductivity type upper region and the body region located between the source region and the first conductivity type upper region via the gate insulating film. Furthermore, when the semiconductor substrate is viewed from above, each of the openings may overlap the gate electrode.

[0020] In this configuration, when the semiconductor device is turned on, a channel is formed in the body region facing the gate electrode, and electrons flow from the source region to the first-conductivity-type upper region through the channel. In this configuration, when the semiconductor substrate is viewed from above, each opening is positioned to overlap with the gate electrode. That is, each opening is positioned to overlap with the first-conductivity-type upper region facing the gate electrode. This shortens the current path from the first-conductivity-type connection region in each opening through the first-conductivity-type upper region, the channel, and the source region, thereby reducing on-resistance.

[0021] In one example of the semiconductor device disclosed herein, the first conductivity type upper region may be exposed on the upper surface of the semiconductor substrate. The upper electrode and the upper surface of the semiconductor substrate may form a Schottky junction. Furthermore, when the semiconductor substrate is viewed from above, each opening may overlap with a Schottky junction surface.

[0022] In this configuration, when the semiconductor substrate is viewed from above, each opening is positioned to overlap with the Schottky junction surface, which shortens the current path from the Schottky junction surface through the first-conductivity-type upper region, the first-conductivity-type connection region in the opening, and the first-conductivity-type column region, thereby reducing the on-resistance.

[0023] Example 1 A semiconductor device 10 according to a first embodiment will be described below with reference to the drawings. The semiconductor device 10 shown in FIG. 1 is a vertical MOSFET (metal-oxide-semiconductor field-effect transistor) and includes a semiconductor substrate 12, electrodes, an insulating film, and the like. The semiconductor substrate 12 is made of SiC. However, the material constituting the semiconductor substrate 12 is not particularly limited and may be other semiconductor materials such as Si or GaN. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction.

[0024] A plurality of trenches 22 are formed on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 1, the trenches 22 are spaced apart in the x direction. Each trench 22 extends longitudinally in the y direction. A gate insulating film 24 and a gate electrode 26 are disposed within each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of the gate electrode 26 is covered by an interlayer insulating film 28. A source electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The source electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 in a portion where the interlayer insulating film 28 is not provided. The source electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A drain electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The drain electrode 72 is in contact with substantially the entire lower surface 12b of the semiconductor substrate 12.

[0025] Inside the semiconductor substrate 12, there are provided a plurality of source regions 30, a body region 32, an n-type upper region 34, an electric field relaxation region 36, a super junction (hereinafter referred to as "SJ") region 38, a plurality of n-type connection regions 40, a plurality of p-type connection regions 42, a drift region 44, and a drain region 46.

[0026] Each source region 30 is n-type and exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the source electrode 70. Each source region 30 contacts the gate insulating film 24 at the upper end of the trench 22.

[0027] The body region 32 is p-type. The body region 32 has a contact region 32a and a main region 32b. The contact region 32a is exposed on the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the source electrode 70. The contact region 32a is disposed in a range sandwiched between two source regions 30. The contact region 32a extends longitudinally along the y direction. The main region 32b is disposed below the source regions 30 and the contact region 32a. The main region 32b is in contact with the gate insulating film 24 below the source region 30. The p-type impurity concentration of the main region 32b is lower than the p-type impurity concentration of the contact region 32a.

[0028] The n-type upper region 34 is disposed below the body region 32. The n-type upper region 34 is separated from each source region 30 by the body region 32. The n-type upper region 34 contacts the gate insulating film below the body region 32 in an area where a p-type connection region 42 (described later) does not exist.

[0029] The electric field relaxation region 36 is p-type. The electric field relaxation region 36 is located below the n-type upper region 34. As shown in FIG. 2, when the semiconductor substrate 12 is viewed from above, the electric field relaxation region 36 is composed of multiple portions 36a extending in the x-direction and multiple portions 36b extending in the y-direction. Each portion 36b is located in an area exposed at the bottom surface of the corresponding trench 22. Each portion 36b contacts the gate insulating film 24 at the bottom surface of the trench 22. The multiple portions 36a and multiple portions 36b are arranged in a lattice pattern in the electric field relaxation region 36. The electric field relaxation region 36 has multiple openings 37. The openings 37 are distributed within the plane shown in FIG. 2. Specifically, each opening 37 is formed by two portions 36b adjacent in the x-direction and two portions 36a adjacent in the y-direction. Therefore, when the semiconductor substrate 12 is viewed from above, each opening 37 does not overlap with the trench 22. The distances d1 between adjacent openings 37 in the x direction are equal to each other. The distances d2 between adjacent openings 37 in the y direction are equal to each other. Each opening 37 penetrates the electric field buffer region 36 from the top to the bottom. An n-type connection region 40 is disposed within each opening 37.

[0030] The SJ region 38 is disposed below the electric field buffer region 36. The SJ region 38 has a plurality of p-type column regions 38a and a plurality of n-type column regions 38b.

[0031] 3, when the semiconductor substrate 12 is viewed from above, the p-type column regions 38a and the n-type column regions 38b extend linearly along the x direction and are alternately arranged along the y direction. The p-type impurity concentration of each p-type column region 38a is lower than the p-type impurity concentration of the electric field buffer region 36. Each p-type column region 38a is arranged directly below and connected to a portion 36a of the electric field buffer region 36. In other words, when the semiconductor substrate 12 is viewed from above, each p-type column region 38a does not overlap with each opening 37.

[0032] 1, each n-type connection region 40 is disposed within a corresponding opening 37, as described above. Each n-type connection region 40 connects the n-type upper region 34 and the corresponding n-type column region 38b.

[0033] When the semiconductor substrate 12 is viewed from above, each p-type connection region 42 extends linearly in the x-direction. Each p-type connection region 42 is disposed directly above a portion 36a of the electric field relaxation region 36. That is, when the semiconductor substrate 12 is viewed from above, each p-type connection region 42 does not overlap with each opening 37. Each p-type connection region 42 extends upward from the upper surface of the electric field relaxation region 36. Each p-type connection region 42 connects the electric field relaxation region 36 and the body region 32. That is, the electric field relaxation region 36 and the p-type column region 38a are connected to the source electrode 70 via each p-type connection region 42 and the body region 32.

[0034] The drift region 44 is n-type and contacts the SJ region 38 from below. The n-type impurity concentration of the drift region 44 is lower than the n-type impurity concentrations of the n-type upper region 34, the n-type connection region 40, and the n-type column region 38b.

[0035] The drain region 46 contacts the drift region 44 from below. The drain region 46 is exposed at the lower surface 12b of the semiconductor substrate 12. The drain region 46 is in ohmic contact with the drain electrode 72. The n-type impurity concentration of the drain region 46 is higher than the n-type impurity concentration of the drift region 44.

[0036] Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is in use, a higher voltage is applied to the drain electrode 72 than to the source electrode 70. When a voltage equal to or greater than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the area adjacent to the gate insulating film 24, and the semiconductor device 10 turns on. When the voltage applied to the gate electrode 26 is reduced to below the gate threshold, the channel disappears, and the semiconductor device 10 turns off.

[0037] When the semiconductor device 10 is in an off state, the potential of the drain electrode 72 is much higher than the potential of the source electrode 70. In this state, the n-type upper region 34 and the n-type connection region 40 have potentials close to that of the drain electrode 72. As described above, the electric field relaxation region 36 has a potential substantially equal to that of the source electrode 70. Therefore, a depletion layer spreads from the electric field relaxation region 36 into the n-type upper region 34 and the n-type connection region 40. In particular, because the electric field relaxation region 36 is disposed directly below the trench 22, the depletion layer spreading from the electric field relaxation region 36 to the n-type upper region 34 can effectively prevent the electric field from concentrating near the bottom end of the trench 22.

[0038] Furthermore, in this embodiment, the openings 37 provided in the electric field relaxation region 36 are dispersed within a plane (xy plane) parallel to the upper surface 12a of the semiconductor substrate 12. This allows the n-type connection region 40 to be more finely defined within this plane than in a conventional configuration in which p-type and n-type regions are alternately arranged in stripes. Therefore, even if the n-type impurity concentration in the n-type connection region 40 is high, a depletion layer spreads from the electric field relaxation region 36 to almost the entire n-type connection region 40 when the semiconductor device 10 is turned off. In this manner, the n-type impurity concentration in the n-type connection region 40 can be sufficiently high in this semiconductor device 10, thereby reducing the resistance, i.e., the on-resistance, of the n-type connection region 40. In particular, in this embodiment, the spacings d1 and d2 between the openings 37 are equal to each other. Since the openings 37 are regularly arranged within this plane, the on-resistance can be made uniform throughout the entire semiconductor device 10.

[0039] Furthermore, when the semiconductor device 10 is in an off state, the n-type column region 38b of the SJ region 38 has a potential close to that of the drain electrode 72, and the p-type column region 38a has a potential substantially equal to that of the source electrode 70. As a result, a high reverse voltage is applied to the pn junction at the interface between the p-type column region 38a and the n-type column region 38b. As a result, a depletion layer spreads laterally (in the xy plane) from the p-type column region 38a into the n-type column region 38b. A depletion layer also spreads laterally from the n-type column region 38b into the p-type column region 38a. This depletion layer maintains the voltage applied between the drain electrode 72 and the source electrode 70.

[0040] The p-type column regions 38a and n-type column regions 38b of the SJ region 38 extend linearly along the x direction and are alternately arranged along the y direction. Because the p-type column regions 38a and n-type column regions 38b are arranged in stripes, the p-type column regions 38a and n-type column regions 38b (i.e., the SJ region 38) are likely to be uniformly depleted when the semiconductor device 10 is turned off. This allows the semiconductor device 10 to ensure a high breakdown voltage. Furthermore, because the p-type column regions 38a are positioned so as not to overlap with the openings 37, the current path is not restricted by the p-type column regions 38a when the semiconductor device 10 is turned on. Therefore, current flows smoothly from the drain electrode 72 to the source electrode 70 via the n-type column regions 38b, the n-type connection region 40, and the n-type upper region 34, suppressing deterioration of on-resistance. As described above, the semiconductor device 10 of this embodiment can ensure a high breakdown voltage and reduce on-resistance.

[0041] 4 to 7, a method for manufacturing the semiconductor device 10 will be described. First, as shown in Fig. 4, a semiconductor substrate 12x is prepared in which an n-type drift region 44 and an n-type semiconductor layer 50 having a higher n-type impurity concentration than the drift region 44 are formed in this order on the upper surface of an n-type drain region 46. The semiconductor substrate 12x can be manufactured by, for example, growing the drift region 44 and the semiconductor layer 50 in this order by epitaxial growth on the upper surface of the drain region 46.

[0042] Next, as shown in FIG. 5, p-type impurities (e.g., aluminum) are selectively ion-implanted from the upper surface of the semiconductor layer 50. This forms a plurality of p-type column regions 38a and a plurality of portions 36a of the electric field reduction region 36 shown in FIG. 2. Here, the p-type column regions 38a and portions 36a are formed by adjusting the implantation energy of the p-type impurities so that the p-type column regions 38a are located below the corresponding portions 36a. Furthermore, the dose of the p-type impurities is adjusted so that the p-type impurity concentration of the p-type column regions 38a is lower than the p-type impurity concentration of the portions 36a. In the depth range where the p-type column regions 38a are formed, the n-type semiconductor regions adjacent to the p-type column regions 38a become n-type column regions 38b.

[0043] 6, p-type impurities are ion-implanted from the upper surface of the semiconductor layer 50 to form p-type connection regions 42 directly above the portions 36a. Next, p-type impurities and n-type impurities are selectively ion-implanted to form the body region 32 and the source region 30, respectively.

[0044] Next, as shown in FIG. 7 , trenches 22 are formed in the upper surface of the semiconductor layer 50, and p-type impurities are ion-implanted into the bottom of the trenches 22 to form portions 36b of the electric field buffer region 36 shown in FIG. 2 at the bottom of the trenches 22. Here, the depth of the trenches 22 and the implantation energy of the p-type impurities are adjusted so that portion 36b is formed in the same depth range as portion 36a. As a result, when the semiconductor layer 50 is viewed from above, the electric field buffer region 36 having a plurality of openings 37 is formed. Furthermore, within the depth range where the electric field buffer region 36 is formed, the n-type semiconductor region surrounded by the electric field buffer region 36 becomes the n-type connection region 40. Thereafter, the gate insulating film 24, the gate electrode 26, the interlayer insulating film 28, the source electrode 70, and the drain electrode 72 are formed by conventionally known methods, thereby completing the semiconductor device 10 shown in FIG. 1 and other figures.

[0045] Example 2 The semiconductor device 100 of the second embodiment further includes an SJ region 138, as compared with the first embodiment. For ease of explanation, the SJ region 38 will be referred to as the first SJ region 38, and the SJ region 138 will be referred to as the second SJ region 138. In the second embodiment, as shown in FIG. 8 , the second SJ region 138 contacts the first SJ region 38 from below.

[0046] The second SJ region 138 has multiple p-type column regions 138a and multiple n-type column regions 138b. As shown in FIG. 8, when the semiconductor substrate 112 is viewed from above, each p-type column region 138a and each n-type column region 138b extends linearly along the y direction and is alternately arranged along the x direction. That is, each p-type column region 138a and each n-type column region 138b extends linearly in a direction perpendicular to each p-type column region 38a and each n-type column region 38b of the first SJ region 38. Each p-type column region 138a is arranged below the corresponding trench 22. Each p-type column region 138a is arranged spaced apart from the portion 36b of the electric field buffer region 36. The p-type impurity concentration of each p-type column region 138a is lower than the p-type impurity concentration of the electric field buffer region 36. Each p-type column region 138a is connected to each p-type column region 38a. That is, the potential of each p-type column region 138a is approximately equal to the potential of the source electrode .

[0047] In the semiconductor device 100 of Example 2, by further providing the second SJ region 138, the overall length of the SJ region in the thickness direction (z direction) of the semiconductor substrate 112 can be increased, thereby ensuring a higher breakdown voltage. Furthermore, the p-type column region 38a and the n-type column region 38b are arranged so that the p-type column region 138a and the n-type column region 138b are perpendicular to each other in the xy plane. Therefore, even if a misalignment occurs between the first SJ region 38 and the second SJ region 138, variations in the area of the current path can be suppressed.

[0048] Example 3 The semiconductor devices 10 and 100 of Examples 1 and 2 are vertical MOSFETs having a trench gate structure, whereas the semiconductor device 200 of Example 3 is a vertical MOSFET having a planar gate structure. The semiconductor device 200 includes a semiconductor substrate 212, electrodes, an insulating film, and the like.

[0049] As shown in FIG. 9, a source electrode 270 and a gate electrode 226 are disposed on the upper surface 212a of the semiconductor substrate 212. The gate electrode 226 is disposed on the upper surface 212a of the semiconductor substrate 212 via a gate insulating film 224. The source electrode 270 contacts the upper surface 212a of the semiconductor substrate 212 in a portion where the gate insulating film 224 is not provided. The gate electrode 226 is insulated from the source electrode 270 by the gate insulating film 224. As shown in FIG. 10, the gate electrode 226 extends in a lattice pattern along the x and y directions when the semiconductor substrate 212 is viewed from above. Note that the source electrode 270 is not shown in FIG.

[0050] Within the semiconductor substrate 212, there are provided a plurality of source regions 230, a plurality of body regions 232, an n-type upper region 234, an electric field relaxation region 236, an SJ region 238, a plurality of n-type connection regions 240, a plurality of p-type connection regions 242, a drift region 244, and a drain region 246.

[0051] Each source region 230 is exposed on the upper surface 212a of the semiconductor substrate 212. Each source region 230 is in ohmic contact with a source electrode 270.

[0052] Each body region 232 is exposed on the upper surface 212a of the semiconductor substrate 212. Each body region 232 extends from a position adjacent to the side surface of the source region 230 to an underside of the source region 230. The body region 232 is in ohmic contact with the source electrode 270.

[0053] The n-type upper regions 234 are exposed at the upper surface 212a of the semiconductor substrate 212. The n-type upper regions 234 are provided adjacent to the side surfaces of the body regions 232. The n-type upper regions 234 are separated from the corresponding source regions 230 by the respective body regions 232.

[0054] The gate electrode 226 faces the n-type upper region 234 via the gate insulating film 224. The gate electrode 226 also faces the body region 232 located between the source region 230 and the n-type upper region 234.

[0055] The electric field relaxation region 236 is disposed below the n-type upper region 234. As shown in FIG. 11, a plurality of openings 237 are provided in the electric field relaxation region 236. When the semiconductor substrate 212 is viewed from above, each opening 237 has a substantially circular shape, and is disposed in a dispersed manner within the plane shown in FIG. 11. When the semiconductor substrate 212 is viewed from above, each opening 237 is provided at a position overlapping with the gate electrode 226 (i.e., directly below the gate electrode 226). Each opening 237 penetrates the electric field relaxation region 236 from its upper end to its lower end. An n-type connection region 240 is disposed within each opening 237.

[0056] The SJ region 238 is disposed below the electric field reduction region 236. The SJ region 238 has a plurality of p-type column regions 238a and a plurality of n-type column regions 238b.

[0057] 12, when the semiconductor substrate 212 is viewed from above, the p-type column regions 238a and the n-type column regions 238b extend linearly in a direction intersecting both the x-axis and the y-axis (hereinafter referred to as the s-direction) and are alternately arranged in a direction perpendicular to the s-direction (hereinafter referred to as the t-direction). The p-type impurity concentration of each p-type column region 238a is lower than the p-type impurity concentration of the electric field relaxation region 236. Each p-type column region 238a is connected to the electric field relaxation region 236 directly below the electric field relaxation region 236. In other words, when the semiconductor substrate 212 is viewed from above, each p-type column region 238a does not overlap with each opening 237. Note that, as in Example 1, the intervals between adjacent openings 237 in the s-direction are equal to each other, and the intervals between adjacent openings 237 in the t-direction are equal to each other.

[0058] As described above, each n-type connection region 240 is disposed in a corresponding opening 237. The n-type impurity concentration of each n-type connection region 240 is higher than the n-type impurity concentration of the n-type upper region 234. However, the n-type impurity concentration of each n-type connection region 240 may be substantially equal to the n-type impurity concentration of the n-type upper region 234. Each n-type connection region 240 connects the n-type upper region 234 and the corresponding n-type column region 238b.

[0059] Each p-type connection region 242 extends from a position exposed on the upper surface 212a of the semiconductor substrate 212, through the source region 230 and the body region 232, and to the upper surface of the electric field relaxation region 236. Each p-type connection region 242 connects the source electrode 270 and the electric field relaxation region 236.

[0060] The configurations of the drift region 244 and the drain region 246 are the same as those in the first embodiment.

[0061] In the semiconductor device 200 of Example 3, similarly to Example 1, the electric field relaxation region 236 and the SJ region 238 can ensure both high breakdown voltage and reduced on-resistance. Furthermore, in this example, when the semiconductor substrate 212 is viewed from above, each opening 237 is provided at a position overlapping the gate electrode 226. That is, each opening 237 is provided at a position overlapping the n-type upper region 234 facing the gate electrode 226. Therefore, in this semiconductor device 200, the current path from the drain electrode 272 through the drain region 246, the drift region 244, the n-type column region 238b, the n-type connection region 240, and the n-type upper region 234 is short, thereby further reducing the on-resistance.

[0062] Example 4 The semiconductor device 300 of the fourth embodiment is a Schottky barrier diode, and includes a semiconductor substrate 312, electrodes, and the like.

[0063] 13, an upper electrode 370 is provided on the upper surface 312a of the semiconductor substrate 312. The upper electrode 370 covers substantially the entire upper surface 312a of the semiconductor substrate 312.

[0064] Within the semiconductor substrate 312, an n-type upper region 334, a field relaxation region 336, an SJ region 338, a plurality of n-type connection regions 340, a plurality of p-type connection regions 342, a drift region 344, and an n-type region 346 are provided.

[0065] The n-type upper region 334 is exposed on the upper surface 312a of the semiconductor substrate 312. As shown in Fig. 14, the n-type upper region 334 extends in a lattice pattern along the x and y directions when the semiconductor substrate 312 is viewed from above. The n-type upper region 334 forms a Schottky junction with the upper electrode 370. Note that the upper electrode 370 is not shown in Fig. 14.

[0066] The electric field relaxation region 336 is disposed below the n-type upper region 334. As shown in FIG. 15, the electric field relaxation region 336 has a plurality of openings 337. When the semiconductor substrate 312 is viewed from above, each opening 337 has a substantially circular shape and is dispersedly disposed within the plane shown in FIG. 15. When the semiconductor substrate 312 is viewed from above, each opening 337 is disposed at a position overlapping with a Schottky junction 350 between the upper electrode 370 and the n-type upper region 334 (i.e., directly below the n-type upper region 334). Each opening 337 penetrates the electric field relaxation region 336 from its upper end to its lower end. An n-type connection region 340 is disposed within each opening 337.

[0067] The SJ region 338 is disposed below the electric field reduction region 336. The SJ region 338 has a plurality of p-type column regions 338a and a plurality of n-type column regions 338b.

[0068] 16, when the semiconductor substrate 312 is viewed from above, the p-type column regions 338a and the n-type column regions 338b extend linearly in a direction intersecting both the x-axis and the y-axis (hereinafter referred to as the u-direction) and are alternately arranged in a direction perpendicular to the u-direction (hereinafter referred to as the v-direction). The p-type impurity concentration of each p-type column region 338a is lower than the p-type impurity concentration of the electric field relaxation region 336. Each p-type column region 338a is connected to the electric field relaxation region 336 directly below the electric field relaxation region 336. In other words, when the semiconductor substrate 312 is viewed from above, each p-type column region 338a does not overlap with each opening 337. Note that, as in Example 1, the intervals between adjacent openings 337 in the u-direction are equal to each other, and the intervals between adjacent openings 337 in the v-direction are equal to each other.

[0069] As described above, each n-type connection region 340 is disposed in a corresponding opening 337. The n-type impurity concentration of each n-type connection region 340 is higher than the n-type impurity concentration of the n-type upper region 334. However, the n-type impurity concentration of each n-type connection region 340 may be approximately equal to the n-type impurity concentration of the n-type upper region 334. Each n-type connection region 340 connects the n-type upper region 334 and the corresponding n-type column region 338b.

[0070] Each p-type connection region 342 extends from a position exposed on the upper surface 312a of the semiconductor substrate 312 to the upper surface of the electric field relaxation region 336. Each p-type connection region 342 is provided adjacent to a side surface of the n-type upper region 334. Each p-type connection region 342 connects the upper electrode 370 and the electric field relaxation region 336.

[0071] The drift region 344 and the n-type region 346 have the same configurations as the drift region 44 and the drain region 46 of the first embodiment, respectively.

[0072] Next, the operation of the semiconductor device 300 will be described. When the semiconductor device 300 is in use, a higher voltage is applied to the upper electrode 370 than to the lower electrode 372. This lowers the Schottky barrier between the upper electrode 370 and the n-type upper region 334. As a result, electrons injected from the lower electrode 372 into the n-type upper region 334 via the n-type region 346, the drift region 344, the n-type column region 338b, and the n-type connection region 340 flow over the lowered Schottky barrier to the upper electrode 370, turning on the semiconductor device 300.

[0073] In the semiconductor device 300 of Example 4, similarly to Example 1, it is possible to ensure a high breakdown voltage and reduce on-resistance at the same time by using the electric field relaxation region 336 and the SJ region 338. Furthermore, in this example, when the semiconductor substrate 312 is viewed from above, each opening 337 is provided at a position overlapping the Schottky junction surface 350. Therefore, in this semiconductor device 300, the current path from the Schottky junction surface 350 through the n-type upper region 334, the n-type connection region 340 in the opening 337, the n-type column region 338b, the drift region 344, and the n-type region 346 is short, thereby further reducing the on-resistance.

[0074] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples exemplified above.

[0075] In the first embodiment described above, the openings 37 are regularly arranged along the x and y directions. However, the openings 37 may be arranged, for example, randomly in the plane shown in FIG. 2 as long as they do not overlap with the p-type column regions 38a when the semiconductor substrate 12 is viewed from above. This also applies to the other embodiments. The shape of the openings 37, etc. is not particularly limited. As in the above-described embodiments, they may be rectangular or circular, or may have other shapes.

[0076] The second SJ region 138 described in the second embodiment may be applied to the third and fourth embodiments.

[0077] In the second embodiment, the p-type column region 138a and the n-type column region 138b of the second SJ region 138 do not have to be perpendicular to the p-type column region 38a and the n-type column region 38b of the first SJ region 38. It is sufficient that the p-type column region 138a and the n-type column region 138b extend so as to intersect with the p-type column region 38a and the n-type column region 38b.

[0078] In the above-described first embodiment, the p-type column region 38a of the SJ region 38 does not have to be in contact with the electric field buffer region 36. This is also true for the other embodiments. In the second embodiment, the second SJ region 138 does not have to be in contact with the first SJ region 38.

[0079] In the first embodiment, the p-type connection region 42 does not have to be provided. It is sufficient that the electric field relaxation region 36 is connected to the source electrode 70 at a position not shown. The same applies to the other embodiments.

[0080] The configurations of the semiconductor device disclosed in this specification are listed below. (Configuration 1) A semiconductor device, a semiconductor substrate; an upper electrode provided on an upper surface of the semiconductor substrate; a lower electrode provided on the lower surface of the semiconductor substrate; Equipped with A current is configured to flow between the upper electrode and the lower electrode, The semiconductor substrate is a first conductivity type upper region; a second conductivity type electric field relaxation region disposed below the first conductivity type upper region and connected to the upper electrode; a superjunction region disposed below the electric field relaxation region; a plurality of first conductivity type connection regions; and the superjunction region has a plurality of second conductivity type column regions and a plurality of first conductivity type column regions; When the semiconductor substrate is viewed from above, the second conductivity type column regions and the first conductivity type column regions extend linearly along a first direction and are alternately arranged along a second direction perpendicular to the first direction; a plurality of openings are provided in the electric field relaxation region, the openings penetrating the electric field relaxation region from an upper end to a lower end thereof; the plurality of openings are distributed and arranged in a plane parallel to the top surface of the semiconductor substrate, each of the first conductivity type connection regions is disposed in a corresponding one of the openings and connects the first conductivity type upper region and the corresponding one of the first conductivity type column regions; the second conductivity type impurity concentration of each of the second conductivity type column regions is lower than the second conductivity type impurity concentration of the electric field buffer region; When the semiconductor substrate is viewed from above, the second conductivity type column regions do not overlap with the openings. Semiconductor device. (Configuration 2) When the semiconductor substrate is viewed from above, the openings are arranged to form a plurality of rows that are spaced apart along the first direction, the rows are spaced apart in the second direction; The intervals between adjacent openings in the first direction are equal, The intervals between adjacent rows in the second direction are equal. The semiconductor device according to configuration 1. (Configuration 3) the superjunction region is a first superjunction region, the second conductivity type column region is a first second conductivity type column region, the first conductivity type column region is a first first conductivity type column region, a second superjunction region disposed below the first superjunction region; the second superjunction region has a plurality of second second conductivity type column regions and a plurality of second first conductivity type column regions; When the semiconductor substrate is viewed from above, the second second-conductivity-type column regions and the second first-conductivity-type column regions extend linearly along a third direction intersecting with the first direction, and are alternately arranged along a fourth direction perpendicular to the third direction; a second conductivity type impurity concentration in each of the second second conductivity type column regions is lower than a second conductivity type impurity concentration in the electric field buffer region; 3. The semiconductor device according to configuration 1 or 2. (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, further comprising a second conductivity type connection region extending upward from the upper surface of the electric field relaxation region and connecting the electric field relaxation region and the upper electrode. (Configuration 5) a trench provided on the top surface of the semiconductor substrate; a gate insulating film covering the inner surface of the trench; a gate electrode provided inside the trench and insulated from the semiconductor substrate by the gate insulating film; The semiconductor substrate is a first conductivity type source region exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film; a body region of a second conductivity type contacting the gate insulating film below the source region and separating the first conductivity type upper region from the source region; and 5. The semiconductor device according to any one of configurations 1 to 4, wherein the first conductivity type upper region is in contact with the gate insulating film below the body region. (Configuration 6) 6. The semiconductor device according to configuration 5, wherein the openings do not overlap the trenches when the semiconductor substrate is viewed from above. (Configuration 7) a gate electrode provided on the upper surface of the semiconductor substrate via a gate insulating film; The semiconductor substrate is a first conductivity type source region exposed on the upper surface of the semiconductor substrate; a second conductivity type body region provided adjacent to the source region and exposed on an upper surface of the semiconductor substrate; and the first conductivity type upper region is adjacent to the body region, is separated from the source region by the body region, and is exposed at the top surface of the semiconductor substrate; The semiconductor device according to any one of structures 1 to 4, wherein the gate electrode faces the first conductivity type upper region via the gate insulating film and faces the body region located between the source region and the first conductivity type upper region. (Configuration 8) 8. The semiconductor device according to claim 7, wherein each of the openings overlaps with the gate electrode when the semiconductor substrate is viewed from above. (Configuration 9) the first conductivity type upper region is exposed at the upper surface of the semiconductor substrate; 5. The semiconductor device according to any one of configurations 1 to 4, wherein the upper electrode and the upper surface of the semiconductor substrate form a Schottky junction. (Configuration 10) 10. The semiconductor device according to configuration 9, wherein each of the openings overlaps a Schottky junction surface when the semiconductor substrate is viewed from above.

[0081] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0082] 10, 100, 200, 300: semiconductor device, 12: semiconductor substrate, 12a: upper surface, 12b: lower surface, 22: trench, 24: gate insulating film, 26: gate electrode, 28: interlayer insulating film, 30: source region, 32: body region, 34: n-type upper region, 36: electric field relaxation region, 37: opening, 38: first superjunction region, 38a: p-type column region, 38b: n-type column region, 40: n-type connection region, 42: p-type connection region, 44: drift region 46: drain region, 70: source electrode, 72: drain electrode, 138: second superjunction region, 138a: p-type column region, 138b: n-type column region

Claims

1. A semiconductor device (10, 100, 200, 300), a semiconductor substrate (12, 212, 312); an upper electrode (70, 270, 370) provided on an upper surface (12a, 112a, 212a, 312a) of the semiconductor substrate; a lower electrode (72, 272, 372) provided on the lower surface (12b, 112b, 212b, 312b) of the semiconductor substrate; Equipped with A current is configured to flow between the upper electrode and the lower electrode, The semiconductor substrate is a first conductivity type upper region (34, 234, 334); a second conductivity type field relaxation region (36, 236, 336) disposed below the first conductivity type upper region and connected to the upper electrode; a superjunction region (38, 238, 338) disposed below the electric field relaxation region; a plurality of first conductivity type connection regions (40, 240, 340); and the superjunction region has a plurality of second conductivity type column regions (38a, 238a, 338a) and a plurality of first conductivity type column regions (38b, 238b, 338b); When the semiconductor substrate is viewed from above, the second conductivity type column regions and the first conductivity type column regions extend linearly along a first direction and are alternately arranged along a second direction perpendicular to the first direction, A plurality of openings (37, 237, 337) penetrating from the upper end to the lower end of the electric field relaxation region are provided in the electric field relaxation region, the plurality of openings are distributed and arranged in a plane parallel to the top surface of the semiconductor substrate, each of the first conductivity type connection regions is disposed in a corresponding one of the openings and connects the first conductivity type upper region and the corresponding one of the first conductivity type column regions; a second conductivity type impurity concentration in each of the second conductivity type column regions is lower than a second conductivity type impurity concentration in the electric field buffer region; When the semiconductor substrate is viewed from above, the second conductivity type column regions do not overlap with the openings. Semiconductor device.

2. When the semiconductor substrate is viewed from above, the openings are arranged to form a plurality of rows that are spaced apart along the first direction, The rows are spaced apart in the second direction, The intervals between adjacent openings in the first direction are equal, The intervals between adjacent rows in the second direction are equal. The semiconductor device according to claim 1 .

3. the superjunction region is a first superjunction region (38); the second conductivity type column region is a first second conductivity type column region (38a), the first conductivity type column region is a first first conductivity type column region (38b); a second superjunction region (138) disposed below the first superjunction region; the second superjunction region has a plurality of second column regions (138a) of a second conductivity type and a plurality of second column regions (138b) of a first conductivity type; When the semiconductor substrate is viewed from above, the second second-conductivity-type column regions and the second first-conductivity-type column regions extend linearly along a third direction intersecting the first direction, and are alternately arranged along a fourth direction perpendicular to the third direction, a second conductivity type impurity concentration of each of the second second conductivity type column regions is lower than a second conductivity type impurity concentration of the electric field buffer region; The semiconductor device according to claim 1 .

4. 2. The semiconductor device according to claim 1, further comprising a second conductivity type connection region (42, 242, 342) extending upward from an upper surface of said electric field relaxation region and connecting said electric field relaxation region and said upper electrode.

5. a trench (22) formed in the upper surface of the semiconductor substrate; a gate insulating film (24) covering the inner surface of the trench; a gate electrode (26) provided inside the trench and insulated from the semiconductor substrate by the gate insulating film; The semiconductor substrate is a first conductivity type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film; a body region (32) of a second conductivity type contacting the gate insulating film below the source region and separating the first conductivity type upper region from the source region; and 5. The semiconductor device according to claim 1, wherein said first conductivity type upper region is in contact with said gate insulating film below said body region.

6. The semiconductor device according to claim 5 , wherein each of the openings does not overlap with the trench when the semiconductor substrate is viewed from above.

7. a gate electrode (226) provided on the upper surface of the semiconductor substrate via a gate insulating film (224); The semiconductor substrate is a source region (230) of a first conductivity type exposed on the upper surface of the semiconductor substrate; a body region (232) of a second conductivity type provided adjacent to the source region and exposed on the upper surface of the semiconductor substrate; and the first conductivity type upper region is adjacent to the body region, is separated from the source region by the body region, and is exposed at the top surface of the semiconductor substrate; 5. The semiconductor device according to claim 1, wherein the gate electrode faces the first conductivity type upper region via the gate insulating film and faces the body region located between the source region and the first conductivity type upper region.

8. 8. The semiconductor device according to claim 7, wherein each of said openings overlaps with said gate electrode when said semiconductor substrate is viewed from above.

9. the first conductivity type upper region is exposed at the top surface of the semiconductor substrate; 5. The semiconductor device according to claim 1, wherein said upper electrode and said upper surface of said semiconductor substrate form a Schottky junction.

10. 10. The semiconductor device according to claim 9, wherein each of the openings overlaps a Schottky junction surface (350) when the semiconductor substrate is viewed from above.

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