Design of semiconductor package including terminal for connection to external capacitor

Abstract

To provide a semiconductor package having a contact point to achieve low parasitic inductance for connection to an external capacitor, and a manufacturing method for the semiconductor package.SOLUTION: In a circuit assembly 100A, a packaged semiconductor component 110 includes a semiconductor die including a field effect transistor, side source terminals 132A and 132B that are positioned to a first side part of the packaged semiconductor component and connected to a source of the field effect transistor, and a drain terminal 122 that is positioned to a second side part of the packaged semiconductor component and connected to a drain of the field effect transistor. The first side part is adjacent to the second side part. A capacitor 150 is electrically connected between the side source terminal and the drain terminal.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 550,927, filed February 7, 2024, entitled "SEMICONDUCTOR PACKAGE DESIGN WITH CONTACTS FOR CONNECTING TO EXTERNAL CAPACITOR," the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor packages. In particular, embodiments of the present disclosure relate to semiconductor packages having contacts for achieving low parasitic inductance for connection to an external capacitor and related manufacturing methods. [Background technology]

[0003] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices may incorporate multiple electrical components that are electrically connected to each other. Such electrical connections can result in undesirable parasitic inductance. Technical problems associated with parasitic inductance can exist, such as distortion of electrical signals between components. Summary of the Invention [Means for solving the problem]

[0004] Each claimed innovation has several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some prominent features of this disclosure will now be discussed briefly.

[0005] One aspect of the present disclosure is a circuit assembly including a packaged semiconductor component and a capacitor. The packaged semiconductor component includes a semiconductor die including a field effect transistor, a side source terminal positioned on a first side of the packaged semiconductor component and connected to a source of the field effect transistor, and a drain terminal positioned on a second side of the packaged semiconductor component and connected to a drain of the field effect transistor. The capacitor is electrically connected between the source terminal and the drain terminal. The first side is adjacent to the second side. The capacitor is external to the packaged semiconductor component, and the capacitor is electrically connected between the source terminal and the drain terminal.

[0006] In one embodiment, the circuit assembly further includes a printed circuit board, the packaged semiconductor component and capacitor are positioned on the printed circuit board, and the packaged semiconductor component further includes a heat spreader facing the printed circuit board, and the side source terminals provide mechanical support for the heat spreader.

[0007] In one embodiment, the packaged semiconductor component further includes a plurality of additional drain terminals on a second side connected to the drains of the field effect transistors, and a plurality of source terminals on a third side of the packaged semiconductor component connected to the sources of the field effect transistors, the third side being opposite the second side. In one embodiment, the packaged semiconductor component further includes a second side source terminal on a side opposite the first side.

[0008] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a lead frame.

[0009] In one embodiment, the circuit assembly further includes a second packaged semiconductor component and a second capacitor electrically connected between the side source and drain terminals of the second packaged semiconductor component, the second packaged semiconductor component being rotated 180 degrees relative to the packaged semiconductor component.

[0010] In one embodiment, the circuit assembly further includes a printed circuit board including traces, the capacitor being connected to one of the traces.

[0011] Another aspect of the present disclosure is a packaged semiconductor component. The packaged semiconductor component includes a semiconductor die including a field effect transistor having a source, a gate, and a drain; a plurality of drain terminals on a first side of the packaged semiconductor component and connected to the drain; a side source terminal on a second side of the packaged semiconductor component and connected to the source; and a plurality of source terminals on a third side of the packaged semiconductor component and connected to the side source terminals within the packaged semiconductor component. The third side is opposite the first side, and the second side is adjacent to both the first side and the third side. Additionally, the side source terminal is located closer to the first side than the third side.

[0012] In one embodiment, the packaged semiconductor component further includes a surface configured to be coupled to a printed circuit board and a heat spreader facing the surface. Additionally, the side source terminal provides mechanical support for the heat spreader. Furthermore, the heat spreader has a notch around the side source terminal. Furthermore, the heat spreader has a notch around the side source terminal.

[0013] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a lead frame, and the lead frame additionally includes a stamped flat end.

[0014] In one embodiment, the gate is positioned on a third side of the packaged semiconductor component. In one embodiment, the packaged semiconductor component further includes a gate terminal positioned on a third side of the packaged semiconductor component.

[0015] Another aspect of the present disclosure is a circuit assembly including a packaged semiconductor component. The packaged semiconductor component includes a semiconductor die including a field effect transistor having a source, a gate, and a drain, a drain terminal connected to the drain, and a source terminal connected to the source, the drain terminal and the source terminal being on the same side of the packaged semiconductor component. The circuit assembly further includes a capacitor external to the packaged semiconductor component, the capacitor being electrically connected between the source terminal and the drain terminal.

[0016] In one embodiment, the circuit assembly further includes a second capacitor external to the packaged semiconductor component, the packaged semiconductor component including a second source terminal on the same side of the packaged semiconductor component as the drain and source terminals, and the second capacitor electrically connected between the second source terminal and the drain. In one embodiment, the circuit assembly further includes a printed circuit board, the packaged semiconductor component and the capacitor are positioned on the printed circuit board, and the packaged semiconductor component further includes a heat spreader facing the printed circuit board. In one embodiment, the packaged semiconductor component includes a gate terminal and a Kelvin source terminal on a side opposite the same side on which the drain and source terminals are located. In one embodiment, the packaged semiconductor component includes a plurality of additional source terminals on a side opposite the same side on which the drain and source terminals are located. In one embodiment, the packaged semiconductor component includes at least one additional drain terminal on the same side as the drain terminal and the source terminal, the at least one additional drain terminal electrically connected to a capacitor external to the packaged semiconductor component.

[0017] Another aspect of the present disclosure is a circuit assembly including a packaged semiconductor component. The packaged semiconductor component includes a semiconductor die having a field effect transistor having a source, a gate, and a drain; a plurality of drain terminals on a first side of the packaged semiconductor component and connected to the drain; a side source terminal on a second side of the packaged semiconductor component and connected to the source; and a plurality of source terminals on a third side of the packaged semiconductor component and connected to the side source terminals within the packaged semiconductor component. The first side is opposite the second side, and the third side is orthogonal to the first and second sides. The circuit assembly further includes a printed circuit board, where the packaged semiconductor component is positioned on the printed circuit board, and a capacitor is positioned on the printed circuit board. The capacitor is electrically connected between one of the plurality of drain terminals and the side source terminal.

[0018] In one embodiment, the packaged semiconductor component further includes a heat spreader facing the printed circuit board, the heat spreader having a notch around the side source terminal, and the side source terminal further providing mechanical support for the heat spreader.

[0019] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a lead frame, the lead frame further including a stamped flat end.

[0020] For purposes of summarizing the disclosure, certain aspects, advantages, and novel features of the innovations have been described herein. It should be understood that not all such advantages may necessarily be achieved in accordance with any particular embodiment. Thus, the innovations may be embodied or implemented to achieve or optimize one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. [Brief explanation of the drawings]

[0021] These and other features, aspects, and advantages of the present disclosure will be described with reference to drawings of specific embodiments. It should be understood that the accompanying drawings, which are incorporated in and constitute a part of this specification, are for the purpose of illustrating the concepts disclosed herein and are not to scale.

[0022] [Figure 1A] FIG. 1 illustrates an example of a circuit assembly according to some embodiments.

[0023] [Figure 1B] FIG. 1B shows an example of a schematic circuit diagram of the circuit assembly and external capacitor of FIG. 1A.

[0024] [Figure 1C] FIG. 1 illustrates another example of a circuit assembly according to some embodiments.

[0025] [Figure 2A] FIG. 2 illustrates an example of a top view of a semiconductor component according to an embodiment of the present disclosure.

[0026] [Figure 2B] 2B is a diagram showing an example of a bottom view of the semiconductor component of FIG. 2A. FIG.

[0027] [Figure 3A] FIG. 1 illustrates an example of an exploded view of a packaged semiconductor component according to an embodiment of the present disclosure.

[0028] [Figure 3B] FIG. 1 illustrates an example of an array assembly of packaged semiconductor components according to an embodiment of the present disclosure.

[0029] [Figure 4] FIG. 1 illustrates an example cross-sectional view of a semiconductor component according to an embodiment of the present disclosure.

[0030] [Figure 5] FIG. 1 illustrates an example of a circuit assembly system having two semiconductor packages according to an embodiment of the present disclosure.

[0031] [Figure 6] FIG. 1 illustrates an example of a circuit assembly system with a capacitor mounted on top of the circuit assembly system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0032] In the following detailed description of several embodiments, various descriptions of specific embodiments are presented. However, the innovations described herein can be embodied in many different ways, for example, as defined and encompassed by the claims. This description refers to the drawings, in which like reference numbers and / or terminology may indicate identical or functionally similar elements. It will be understood that the elements depicted in the figures are not necessarily drawn to scale. It will also be understood that some embodiments may include more elements and / or a subset of the elements depicted in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more figures. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims. Introduction

[0033] Electronic components including one or more integrated circuit (IC) dies can be deployed in a wide variety of applications and in a wide variety of environmental conditions. For example, such components can form part of a power electronics system. In some cases, power electronics systems can be used to power electric vehicles. In some applications, power electronics systems can be part of stationary energy storage systems, such as systems for storing solar energy or systems for delivering power to destinations. These are merely examples; there are many other uses for such systems. In some cases, components can include diode switches, field-effect transistors (FETs) such as metal-oxide-semiconductor FETs (MOSFETs) (e.g., silicon MOSFETs, GaN MOSFETs, etc.), insulated-gate bipolar transistors (IGBTs), other bipolar transistors, the like, or any suitable combination thereof. Such switches can be included in inverters. In certain applications, the switches in the packaged semiconductor components disclosed herein can switch voltages within a range of 1 volt (V) to 150 V, e.g., 12 V to 150 V.

[0034] Snubber capacitors may be utilized with certain switching components to reduce and / or eliminate voltage transients and / or ringing associated with switching. It may be desirable to reduce and / or minimize parasitic inductance associated with snubber capacitors connected across the terminals of switching devices. Embodiments of the present disclosure may provide low parasitic inductance associated with snubber capacitors connected across the terminals of switching devices and associated packaged components for connecting with the snubber capacitors.

[0035] Power electronics systems can generate significant amounts of heat. Such heat can present significant problems. For example, excessive heat can lead to reduced performance, reduced reliability, and shortened lifespan. For example, excessive thermal stress can weaken solder joints, damage semiconductor components, or both. In some applications, surge loads can result in rapid temperature increases. High surge loads can be encountered in various applications, such as when starting portable compressors, HVAC systems, refrigeration systems, electric motors, power converters, etc. In certain semiconductor package designs, cooling solutions can be implemented within the semiconductor package to dissipate heat. In some cases, semiconductor packages can be designed to dissipate heat through the printed circuit board (PCB). For example, top-side cooling can be used to cool ICs, as described in U.S. Pat. No. 10,658,276, entitled "Device with top-side base plate," the entire disclosure of which is incorporated herein by reference for all purposes.

[0036] Certain semiconductor packages (e.g., semiconductor component packages) may include die connection terminals (e.g., contact terminals), such as the source, drain, and gate of a field-effect transistor semiconductor component. The source and drain terminals may be mounted on opposite ends of the body of the semiconductor component. For example, the switching terminals of the semiconductor component may be arranged with the source and drain mounted opposite each other. Some semiconductor components may include an exposed heat spreader that faces downward toward the surface of a carrier, such as a PCB. In top-side cooled devices with an exposed heat spreader at drain potential, terminals on the sides of the device adjacent to the side with the source and drain terminals may not be in electrical contact with the PCB. The source and drain terminals may be in electrical contact with other components through traces embedded and / or etched on a printed circuit board (PCB). For example, these terminals may be electrically connected to a power generating component that provides a high-frequency switching input power signal (e.g., a signal utilized by a digital-to-analog converter and / or an analog-to-digital converter) through PCB traces. However, these traces may introduce parasitic effects, such as parasitic inductance. Such parasitic inductance can lead to signal distortion, impedance mismatch, signal noise, etc., or any combination thereof for fast switching signals.

[0037] The shape and height of conductive elements in semiconductor packages can also have detrimental parasitic inductance at certain switching frequencies. Therefore, there is a need for die packaging that can facilitate operation with relatively low parasitic effects such as parasitic inductance. Such semiconductor chip packaging can be designed with internal elements that are low-profile and close to the PCB when mounted. Package Design

[0038] Aspects of the present disclosure relate to semiconductor chip packages (e.g., semiconductor packages) having lead frames and electrical components that can reduce and / or minimize parasitic effects. In particular, semiconductor chip packages can include various traces for electrically connecting between integrated components of the semiconductor chip package. Such traces can generate undesirable parasitic inductance, and electrical components can be integrated into the semiconductor chip package to mitigate these undesirable parasitic inductances. In addition, each semiconductor component can include a lead frame to mount the electrical components. Such lead frames can be formed in a desired shape and can provide a heating solution for the semiconductor package. In some cases, the lead frame also provides electrical connections between terminals of the semiconductor component. For example, the lead frame can provide electrical connections to the backside of the die and the top side of the semiconductor die. The lead frame can also be in a formable shape (e.g., a preformed lead frame) and can be implemented as pre-positioned or arranged conductors of a desired shape during the assembly process.

[0039] In some cases, electrical components can be implemented to reduce and / or minimize parasitic effects. For example, capacitors and their connections to a semiconductor package can be arranged to achieve low parasitic inductance. When fast switching signals are applied to the input of a semiconductor component, parasitic inductance can occur between traces on a carrier such as a PCB. Capacitors, such as snubber capacitors, can be implemented between the traces to reduce and / or minimize the parasitic inductance.

[0040] In embodiments disclosed herein, a capacitor can be mounted with the source and drain terminals to reduce and / or minimize parasitic inductance. The source and drain terminals of a semiconductor package can be connected via a capacitor. The arrangement of the source and drain leads of the semiconductor package can enable a compact connection between the capacitor and the source and drain leads. This capacitor connected between the source and drain of a switching device can be generally referred to as a "snubber capacitor" in this disclosure. During operation of the semiconductor component, such as high-speed switching, the source and drain leads can be connected by a snubber capacitor component via a PCB trace. The source-capacitor-drain influences ringing or voltage overshoot in semiconductor switch waveforms, forming a tight current path and / or a "triangle" loop region. Experiments in which a snubber capacitor is mounted on the semiconductor package to directly bridge the drain and source have demonstrated reduced parasitic inductance. In some embodiments, two source lead frames can be extended to both sides of the semiconductor component, with snubber capacitors positioned on either side for PCB layout.

[0041] In the embodiments disclosed herein, heat transfer can be concentrated on the topside of the semiconductor package. Topside cooling may be desirable in certain applications due to, for example, bottom-side mounting surface temperature, PCB layout, and / or feature considerations. The techniques disclosed herein can be applied to double-sided cooled semiconductor packages. Certain designs can have exposed conductive elements on the top and bottom, and can have design features to maintain position during assembly and molding. This can control molding flash and resin bleed. Therefore, the need for grinding can be reduced or eliminated.

[0042] FIG. 1A illustrates a circuit assembly 100A according to an embodiment of the present disclosure. For illustrative purposes, the circuit assembly 100A is shown with a single packaged semiconductor component 110. However, the circuit assembly 100A can include multiple packaged semiconductor components 110, and the present disclosure does not limit the number of packaged semiconductor components 110. As illustrated in FIG. 1A , the circuit assembly 100A can include the packaged semiconductor component 110, traces 120, 130, 140, and a capacitor 150. The packaged semiconductor component 110 can be mounted on a carrier such as a PCB (not shown in FIG. 1A ). The packaged semiconductor component 110 can be electrically connected to other components, such as other power components or other semiconductor components, via the PCB. For example, the traces 120, 130, 140 can be etched on the PCB and configured to provide electrical contact areas or lines between the packaged semiconductor component 110 and the other components. The traces 120, 130, 140 can each have any shape and / or area suitable for a particular application.

[0043] Trace 120 may provide electrical contact to a designated terminal (e.g., drain terminal 122 of packaged semiconductor component 110). Trace 130 may provide electrical contact to another group of designated terminals (e.g., source terminal 132 of packaged semiconductor component 110). Trace 140 may provide electrical contact to a designated terminal (e.g., gate terminal 142 of packaged semiconductor component 110). In some cases, trace 135 may be combined with trace 130 to provide a contact region for the source of packaged semiconductor component 110. Alternatively, terminal 134 and trace 135 may be arranged as a Kelvin source. These configurations are provided as examples, and configurations may be modified based on specific applications.

[0044] As further shown in FIG. 1A , capacitors 150 may have ends connected to the respective traces. For example, traces 120 and 130 may be capacitively coupled via capacitor 150. Such capacitors 150 may be referred to as snubber capacitors. Capacitors 150 may be utilized to mitigate undesired signals generated by parasitic effects (e.g., parasitic inductance caused by inductive coupling between traces 120 and 130), such as voltage spikes that may occur during high-speed switching operations of a circuit assembly. For example, parasitic inductance caused by two nearby traces, such as between traces 120 and 130, may cause parasitic inductance. In embodiments of the present disclosure, these parasitic effects caused by inductive coupling between the traces may be mitigated by capacitor 150. For example, capacitor 150 may absorb energy associated with the voltage spikes. In some cases, capacitor 150 may be soldered onto traces 120 and 130. The capacitance value of capacitor 150 may be determined based on the applied input signal (e.g., one or more of the applied voltage, frequency, or waveform) and the distance between the traces. Capacitor 150 can be any capacitor suitable for the specifications of circuit assembly 100A.

[0045] FIG. 1B shows a schematic circuit diagram of circuit assembly 100A and capacitor 150 of FIG. 1A. Drain terminal 122, source terminal 132 (including 132A and 132B), gate terminal 142, and Kelvin source 134 of packaged semiconductor component 110 may correspond to points 122, 132, 142, and 134, respectively, in the schematic diagram of FIG. 1B. Additionally, traces 120, 130, 140, and 135 of FIG. 1A are shown with the same numerical designations in FIG. 1B. As shown in FIG. 1B, capacitor 150 can be connected between drain terminal 122 and source terminal 132 of packaged semiconductor component 110. As further shown in FIG. 1A, packaged semiconductor component 110 can also have source terminals 132A and 132B on opposite sides of packaged semiconductor component 110.

[0046] FIG. 1C illustrates a circuit assembly 100B according to an embodiment of the present disclosure. As shown in FIG. 1C, circuit assembly 100B includes an additional capacitor 155 relative to circuit assembly 100A shown in FIG. 1A. Traces 120 and 130 of circuit assembly 100B are also shaped and configured to connect additional capacitor 155 between source terminal 132 and drain terminal 122 of packaged semiconductor component 110. Similar components of circuit assembly 100B can function similarly or in the same manner as similar components of circuit assembly 100A in FIG. 1A. For illustrative purposes, circuit assembly 100B is shown with a single packaged semiconductor component 110. However, circuit assembly 100B can include multiple packaged semiconductor components 110, and the present disclosure does not limit the number of packaged semiconductor components 110.

[0047] As shown in FIG. 1C , capacitor 150 and additional capacitor 155 can each have ends connected to their respective traces. For example, trace 120 and trace 130 can be capacitively coupled via capacitor 150 and additional capacitor 155 on opposite sides of packaged semiconductor component 110. Capacitor 150 and additional capacitor 155 can mitigate undesired signals generated by parasitic effects (e.g., parasitic inductance caused by inductive coupling between traces 120 and 130), such as voltage spikes that may occur during high-speed switching operations of circuit assembly 100B. For example, parasitic inductance caused by two nearby traces, such as between trace 120 and trace 130, can cause parasitic inductance. In embodiments of the present disclosure, these parasitic effects caused by inductive coupling between the traces can be mitigated by capacitor 150 and additional capacitor 155. For example, capacitor 150 and additional capacitor 155 can absorb energy associated with the voltage spikes. In some cases, capacitor 150 and additional capacitor 155 may each be soldered onto traces 120 and 130. Having two capacitors 150 and 155 in parallel with each other may be advantageous in certain applications to mitigate parasitic effects. The capacitance value of each of capacitor 150 and additional capacitor 155 may be determined based on the applied input signal (e.g., one or more of the applied voltage, frequency, or waveform) and the distance between the traces. Capacitor 150 and additional capacitor 155 may each be any capacitor suitable for the specifications of circuit assembly 100B.

[0048] FIG. 2A illustrates a top view of the packaged semiconductor component 110 of FIG. 1A according to one embodiment. The packaged semiconductor component 110 may include a packaging structure 310 that can surround the packaged semiconductor component 110. The packaging structure 310 may be made of a rigid molding compound. The packaging structure 310 may be disposed on top of a die paddle 320. The die paddle 320 may be referred to as a "clip." The die paddle 320 may function as a heat spreader in any suitable embodiment disclosed herein. In some cases, the heat spreader may be an upper heat spreader having a relatively large area. The die paddle 320 may be used to provide electrical connections to the top surface of the packaged semiconductor component 110 and may function as a heat spreader. In some examples, a semiconductor package assembly or manufacturing orientation may prioritize that the die paddle 320 be assembled last onto the die, in which case it may be referred to as a "clip." The packaging structure may also include a molding compound. The packaged semiconductor component 110 may include an underside that includes stamped leads. The stamped leads may be flat.

[0049] 2B shows a bottom view of the packaged semiconductor component 110 of FIG. 1A according to one embodiment. The packaged semiconductor component 110 can include drain terminal 122, source terminal 132 (including 132A and 132B), gate terminal 142, and Kelvin source terminal 134. The packaged semiconductor component 110 can be assembled on top of a PCB, where the top of the PCB provides various traces, such as traces 120, 130, 140, and / or 135, as described in FIG. 1A. In some embodiments, each of the drain terminal 122, source terminal 132 (including 132A and 132B), gate terminal 142, and Kelvin source terminal 134 can be electrically connected to one of the traces by assembling the packaged semiconductor component 110 on top of the PCB. For example, each of the drain terminal 122, the source terminal 132 (including 132A, 132B), the gate terminal 142, and the Kelvin source terminal 134 can contact its corresponding trace to provide a contact for monitoring the packaged semiconductor component 110 (e.g., a contact for a temperature sensor such as a thermocouple), etc. In some embodiments, the drain terminal 122, the source terminal 132 (including 132A, 132B), the gate terminal 142, and the Kelvin source terminal 134 can extend beyond the bulk of the packaged semiconductor component 110 by contacting its corresponding trace. In some embodiments, the drain terminal 122, the source terminal 132 (including 132A, 132B), the gate terminal 142, and the Kelvin source terminal 134 can be flush with the outer surface of the packaged semiconductor component 110 by contacting its corresponding trace. In some embodiments, drain terminal 122, source terminal 132 (including 132A, 132B), gate terminal 142, and Kelvin source terminal 134 may be recessed in one or more directions from the outer surface of packaged semiconductor component 110 by contacting their corresponding traces. Kelvin source terminal 134 may be provided as a terminal that separates current paths (e.g., control current paths and load current paths).In some embodiments, the Kelvin source terminal 134 can be combined with the source 132 (eg, form a signal piece).

[0050] The packaged semiconductor component 110 may include side source terminals 132A and 132B. These side source terminals 132A and 132B may be electrically connected to a common trace with the source terminal 132 within the packaged semiconductor component 110. For example, the trace 130 may be molded to cover the side source terminals 132A and 132B and the area of the source terminal 132. As shown, the side source terminals 132A and 132B are positioned on the sides of the packaged semiconductor component 110, with the other source terminal 132 and drain terminal 122 positioned on the other respective sides of the packaged semiconductor component 110. The molding compound and die paddle 320 may have respective notches around the side source terminals 132A and 132B. These notches may serve to recess the side source terminals 132A and 132B to make them less noticeable for handling or close spacing between other components in a PCB layout. The shape and location of these notches can provide sufficient electrical surface creepage distance to mitigate and / or prevent arcing to adjacent terminals of different voltages or functions. Side source terminals 132A and 132B are each located on a side of packaged semiconductor component 110 adjacent to the other source terminal 132 and adjacent to drain terminal 122. Side source terminals 132A and 132B are located closer to the nearest drain terminal 122 than the nearest other source terminal 132. Side source terminals 132A and 132B can also provide mechanical structure for packaged semiconductor component 110. For example, when packaged semiconductor component 110 is assembled, these side source terminals 132A and 132B can provide mechanical support during and / or after the manufacturing process of packaged semiconductor component 110, including die paddle 320.

[0051] In some embodiments, the packaged semiconductor component 110 can include frames 352, 310, 230, and 240. These frames can be conductive frames, such as lead frames, of the packaged semiconductor component 110. These frames can be implemented in a pattern that can provide electrical contact with terminals of the die, such as the drain, source, and gate (not shown in FIG. 2B ). For example, the drain frame 352, the source frame 310, the gate frame 230, and the Kelvin source frame 240 can be arranged based on the drain, source, gate, and Kelvin source terminals of the die, respectively. Thus, the source terminal 132 (including 132A and 132B), the drain terminal 122, the gate terminal 142, and the Kelvin source 134 of the packaged semiconductor component 110 can be electrically connected to the drain frame 352, the source frame 310, the gate frame 230, and the Kelvin source frame 240, respectively.

[0052] Although references to source, drain, and gate contacts are made in this disclosure, this is for illustrative purposes only. In general, stamped leads can be used to provide source, gate, drain, Kelvin source, control, input, output, sensor, base, emitter, collector, ground, reference, short, or any other suitable electrical terminal.

[0053] 3A-3B show exemplary embodiments of semiconductor components and assemblies in an array configuration.

[0054] 3A shows an exploded view of packaged semiconductor components 110 according to some embodiments. Each packaged semiconductor component 110 can be mounted on a frame 352 and assembled with other semiconductor components. In some embodiments, frame 352 can provide mechanical support and electrical contacts within the assembly.

[0055] As shown in FIG. 3A , the packaged semiconductor component 110 can include a layer of bonding material 312, a die 314, a layer of die attach material 316, and a packaging structure 310, as well as a die paddle 320 (e.g., a die clip). In some examples, the layer of bonding material 312 can be formed based on a pattern that can include multiple regions for providing electrical connection with corresponding die connection terminals (e.g., contact terminals), such as the source (including Kelvin source), drain, and gate of the semiconductor component. For example, die attach pads 312A, 312B, 312C, and 312D can provide electrical connection to the drain terminal, source terminal, gate terminal, and Kelvin source terminal of the die connection terminal, respectively. In some examples, the layer of die attach material 312 can be formed by a conductive material, such as solder, conductive epoxy, or the like.

[0056] 3A , in some examples, a field effect transistor (FET) such as a metal oxide semiconductor field effect transistor (MOSFET) (e.g., a GaN MOSFET) can be implemented on the die 314. Accordingly, the die 314 can include terminals such as a drain, a source (and Kelvin source), and a gate. In some cases, a layer of die attach material 316 can be assembled (e.g., bonded) on top of the die 314. In some examples, the layer of die attach material 316 can cover the top surface of the die 314. Additionally, the layer of die attach material 316 can be configured to bond the die 314 to the packaging structure 310. The layer of bonding material 314 and the layer of die attach material 316 can be formed of the same type of bonding material (e.g., a conductive bonding material). In some cases, the structure of the packaged semiconductor component 110 can be modified so that the die paddle 320 can be on top of the layer of die attach material 316. In some assembly processes, die paddle 320 may be assembled after assembling die 314 and layer of die attach material 316. In these assembly processes, die paddle 320 may be referred to as a "clip."

[0057] 3B shows an example of an array assembly 350 of packaged semiconductor components 110. As shown in FIG. 3B, a die paddle or clip 320 can be mounted on each device leadframe unit 352 of the array assembly 350. In some embodiments, the packaged semiconductor components 110 can be assembled or mounted in different orientations. During the assembly process of the array assembly 350, the device leadframe units 352 can alternatively be mounted on top of each die paddle or clip 320.

[0058] FIG. 4 illustrates a cross-sectional view of the packaged semiconductor component 110 of FIG. 1A. As shown in FIG. 4, the packaged semiconductor component 110 may include a die paddle or clip 320, a die attach structure 420, a die 314, a lead attach structure 440, a drain lead frame 312A, a source lead frame 312B, a side source terminal 132A (side source terminal 132B is not shown), and a source terminal 132 (the other side source terminal 132, the Kelvin source terminal 134, and the gate terminal 142 are not shown in FIG. 4). The die paddle 320 may function as a heat spreader. The die paddle 320 may also be used to provide electrical connections to the top surface of the packaged semiconductor component 110. The die attach structure 420 may be used to attach the die 314 and the die paddle 320. Die 314 may be implemented with a field effect transistor (FET), such as a metal oxide semiconductor field effect transistor (MOSFET) (e.g., a Si MOSFET or a GaN MOSFET), and therefore may include terminals such as a drain, a source, and a gate. Lead attach structure 440 may attach die 314 to lead frames 312A and 312B (lead frames 312C and 312D are not shown in FIG. 4).

[0059] In some embodiments, lead frame 312A can be connected to drain terminal 122, and lead frame 312B can be connected to source terminal 132 and side source terminals 132A and 132B (side source terminal 132 is not shown in FIG. 4 ). These lead frames 312A and 312B can be connected to other semiconductor components or any electrical component by connecting with corresponding terminals 122, 132, and 132A, the drain, source, and gate terminals of the die. For example, the drain terminal of die 314 can be connected to lead frame 312A and drain terminal 122. The drain terminal 122 can then be electrically coupled to trace 120, as described with reference to FIGS. 1A and 1B . Similarly, the source terminal of die 314 can be connected to lead frame 312B and source terminal 132. The source terminal 132 can then be electrically coupled to trace 130, as described with reference to FIGS. 1A and 1B . Similarly, the gate terminal of die 314 may be connected to trace 140 via lead frame 312D (shown in FIG. 3), gate terminal 135 (shown in FIG. 1A), and trace 140 (shown in FIG. 1A).

[0060] 1A and 2 are mounted in close proximity to the drain terminal 122. For example, because the drain terminal 122 and the side source terminal 132A are in close proximity to each other, the traces 120 and 130 can also be mounted in close proximity to each other, as shown in FIG. 1A. Therefore, according to embodiments disclosed herein, an electronic component 150, such as a capacitor, can be mounted between the traces 120 and 130.

[0061] In some embodiments, drain terminal 122 and source terminal 132 can provide mechanical support points when mounting packaged semiconductor component 110 on a carrier such as a PCB, or to support lead frames 312A and 312B in a desired position within a lead frame array during assembly. In some embodiments, side terminals 132A and 132B can provide additional mechanical support points.

[0062] FIG. 5 illustrates a circuit assembly 500 incorporating two packaged semiconductor components 110A and 110B. Each of these components can be packaged in a manner similar to that of semiconductor package 110, as shown in FIGS. 1A and 2B, respectively. In FIG. 5, semiconductor components 110A and 110B are demonstrated as being assembled with each rotated 180 degrees relative to the other. For example, semiconductor component 110A is oriented in the opposite direction and rotated 180 degrees relative to semiconductor component 110B. For example, drain terminal 122A of semiconductor component 110A is positioned on the top side (e.g., the top side of FIG. 5), and source terminal 132AA, Kelvin source terminal 134A, and gate terminal 142A are positioned on the bottom side (e.g., the bottom side of FIG. 5). Semiconductor component 110B can be assembled in the opposite orientation relative to semiconductor component 110A. For example, drain terminal 122B of semiconductor component 110B is positioned on the bottom side (e.g., the bottom side in FIG. 5), and source terminal 132BB, Kelvin source terminal 134B, and gate terminal 142B are positioned on the top side (e.g., the top side in FIG. 5). As further shown in FIG. 5, side source terminals 132A1 and 132B1 of semiconductor component 110A can be located on the top side relative to side source terminals 132A2 and 132B2 of semiconductor component 110B. Thus, capacitors 150A and 150B can be implemented while minimizing the form factor of circuit assembly 500.

[0063] Capacitor 150A is connected to packaged semiconductor component 110A via traces (not shown in FIG. 5 ) that couple to the component's drain and source terminals. Similarly, capacitor 150B is connected to semiconductor component 110B via traces (also not shown in FIG. 5 ) attached to its drain and source terminals. The integration of capacitors 150A and 150B creates capacitor loops 514 and 524, respectively. In certain designs, it is possible to implement more than two semiconductor components. For example, an array containing multiple semiconductor components can be created by rotating each component 180 degrees relative to adjacent components.

[0064] FIG. 6 illustrates a circuit assembly system 600 with a capacitor mounted on top of the circuit assembly system 600 according to an embodiment of the present disclosure. The circuit assembly system 600 includes a packaged semiconductor component 650 and capacitors 680 and 690 on a PCB. The packaged semiconductor component 650 includes source and drain terminals on a common side. This allows snubber capacitor 680 to be electrically connected between source terminal 632A and drain terminal 622A by a trace with low parasitic inductance. Similarly, snubber capacitor 690 can be electrically connected between source terminal 632B and drain terminal 622C by a trace with low parasitic inductance. The location of the terminals on the packaged semiconductor component 650 allows the snubber capacitor to be connected between the source and drain in a compact layout with low parasitic inductance.

[0065] For illustrative purposes, FIG. 6 shows a bottom view of a packaged semiconductor component 650 and two capacitors 680 and 690, without showing the PCB and showing a portion of the traces on the PCB. The packaged semiconductor component 650 and capacitors 680, 690 may be mounted on a PCB, for example, similar to that described in one or more of the above embodiments. The capacitors 680 and / or 690 may be electrically connected between the source and drain in any suitable manner. As shown in FIG. 6, the PCB may include traces 660A, 660B, and 670 (e.g., only a portion of the PCB traces are shown in FIG. 6) that are shown connected to source terminal 632A, source terminal 632B, and drain terminals 622A-C, respectively. The gate terminal 642, the other source terminal 632, and the Kelvin source terminal 634 may be connected to traces on the PCB that are not shown in FIG. 6. In some embodiments, source terminal 632A and drain terminals 622A-622C can be coupled by implementing a capacitor 680 between trace 660A and trace 670. In some cases, source terminal 632B and drain terminals 622A-622C can be coupled by implementing a capacitor 690 between trace 660B and trace 670. In some embodiments, traces 660A and 660B can be formed within the same trace.

[0066] The layout of the source frame 610, the drain frame 620, the gate frame 630, and the Kelvin source frame 640 can be arranged as shown in FIG. 6 . In some implementations, the layout can be determined based on the layout of the die's terminals (e.g., drain, source (and Kelvin source), and gate). For example, as shown in FIG. 6 , the source frame 610 can be patterned to cover the die's source terminals such that the die's source terminals are electrically connected to terminals on opposite sides of the packaged semiconductor component 650. In the packaged semiconductor component 650, the die's source terminals are electrically connected to source terminals 632A and 632B and source terminal 632. Furthermore, the drain frame 620 can be patterned to cover the die's drain terminals. The drain frame 620 can electrically connect the die's drain terminals to drain terminals 622A-622C as shown in FIG. 6 . Additionally, the gate frame 630 and the Kelvin source frame 640 can electrically connect the die's terminals to the gate terminal 642 and the Kelvin source terminal 634, respectively.

[0067] In some embodiments, the circuit assembly system 600 may include two capacitors 680 and 690. These capacitors 680, 690 may be implemented between source and drain terminals via source traces 660A and 660B (for illustrative purposes, only portions of the source traces are shown in FIG. 6 ) and drain trace 670. For example, as shown in FIG. 6 , source terminal 632A is electrically connected to source trace 660A, and the other source terminal 632B is electrically connected to source trace 660B. In addition, drain terminals 622A-622C may be connected to drain trace 670. Thus, capacitor 680 may be electrically connected between source terminal 632A and drain terminals 622A-622C by short traces. Furthermore, capacitor 690 may be electrically connected between source terminal 632B and drain terminals 622A-622C by short traces. The traces shown in FIG. 6 may represent portions of the traces. In some embodiments, either capacitor 680 or 690 may be implemented in circuit assembly system 600. In other embodiments, both capacitors 680 and 690 may be implemented in circuit assembly system 600. Additional Embodiments

[0068] In the foregoing specification, the present disclosure has been described with reference to particular embodiments. It will, however, be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the present disclosure. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

[0069] Indeed, while the present disclosure is in the context of certain embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the present invention and its equivalents. In addition, while several variations of the embodiments have been shown and described in detail, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or subcombinations of specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another to form varying forms of the embodiments disclosed herein. Any methods disclosed herein need not be performed in the order recited. Therefore, it is not intended that the scope of the present disclosure should be limited by the specific embodiments described above.

[0070] It will be understood that the systems and methods of the present disclosure each have several innovative aspects, no single one of which is solely responsible for or required to achieve the desirable attributes disclosed herein. The various features and processes described above may be used independently of one another or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of the present disclosure.

[0071] Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, while features may be described above as working in a particular combination and may even initially be claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination. No single feature or group of features is necessary or essential to every embodiment.

[0072] It will also be understood that conditional language used herein, particularly "can," "could," "might," "may," "eg," and the like, unless otherwise specified or understood otherwise within the context of use, is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Thus, such conditional language is not generally intended to imply that features, elements, and / or steps are somehow required by one or more embodiments, or that one or more embodiments necessarily include logic for determining whether those features, elements, and / or steps should be included in or performed in any particular embodiment, with or without authorial input or prompting. Terms such as "comprise," "include," and "have" are synonymous and are used in an inclusive, open-ended manner and do not exclude additional elements, features, acts, operations, etc. Additionally, the term "or" is used in its inclusive sense (and not its exclusive sense), so that, for example, when used to connect a list of elements, the term "or" means one, some, or all of the elements in the list. Furthermore, the articles "a," "an," and "the," as used in this application and the appended claims, should be interpreted to mean "one or more" or "at least one," unless otherwise specified. Similarly, while operations may be depicted in the figures in a particular order, it should be recognized that such operations need not be performed in the particular order depicted, or in sequential order, or that all depicted operations need not be performed, to achieve desirable results. Furthermore, the figures may schematically depict one or more exemplary processes in the form of a flowchart. However, other operations not depicted may be incorporated into the schematically depicted exemplary methods and processes. For example, one or more additional operations may be performed before, after, simultaneously with, or during any of the depicted operations. Furthermore, operations may be rearranged or reordered in other embodiments.In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above-described embodiments should not be understood to require such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged in multiple software products. Furthermore, other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results.

[0073] Furthermore, the methods and devices described herein may be susceptible to various modifications and alternative forms, specific examples of which are shown in the drawings and described in detail herein. It should be understood, however, that the disclosure is not limited to the particular forms or methods disclosed; on the contrary, the disclosure encompasses all modifications, equivalents, and alternatives falling within the spirit and scope of the various implementations described and the appended claims. Furthermore, any particular feature, aspect, method, attribute, property, quality, attribute, element, etc., disclosed herein in connection with an implementation or embodiment can be used in all other implementations or embodiments described herein. Any method disclosed herein need not be performed in the order recited. While the methods disclosed herein may include specific actions performed by a practitioner, the method can also include, explicitly or implicitly, any third-party direction of those actions. Ranges disclosed herein also encompass all overlaps, subranges, and combinations thereof. Language such as "up to," "at least," "greater than," "less than," "between," and the like, includes the recited numbers. Numbers preceded by terms such as "about" or "approximately" are inclusive of the recited numbers and should be interpreted in accordance with the context (e.g., as precisely as reasonably possible under the circumstances, e.g., ±5%, ±10%, ±15%, etc.). Phrases preceded by terms such as "substantially" are inclusive of the recited terms and should be interpreted in accordance with the context (e.g., as precisely as reasonably possible under the circumstances). For example, "substantially constant" includes "constant." Unless otherwise specified, all measurements are made at standard conditions, including temperature and pressure.

[0074] As used herein, a phrase referring to "at least one" of a list of items refers to any combination of those items, including single members. As an example, "at least one of A, B, or C" is intended to encompass A, B, C, A and B, A and C, B and C, and A, B, and C. Connecting language such as "at least one of X, Y, and Z," unless otherwise specified, is otherwise understood in the context in which it is generally used to convey that an item, term, etc. may be at least one of X, Y, or Z. Thus, such connecting language is generally not intended to imply that a particular embodiment requires that at least one of X, at least one of Y, and at least one of Z are each present. Headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0075] Thus, the scope of the claims is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the present disclosure, the principles and novel features disclosed herein.

Claims

1. a packaged semiconductor component comprising: a semiconductor die including a field effect transistor; a side source terminal positioned on a first side of the packaged semiconductor component and connected to a source of the field effect transistor; and a drain terminal positioned on a second side of the packaged semiconductor component and connected to a drain of the field effect transistor, wherein the first side is adjacent to the second side of the packaged semiconductor component; a capacitor external to the packaged semiconductor component and electrically connected between the source terminal and the drain terminal; A circuit assembly comprising:

2. 10. The circuit assembly of claim 1, further comprising a printed circuit board, the packaged semiconductor component and the capacitor being positioned on the printed circuit board, the packaged semiconductor component further comprising a heat spreader facing the printed circuit board.

3. 3. The circuit assembly of claim 2, wherein the side source terminal provides a mechanical support point for the heat spreader.

4. The packaged semiconductor component comprises: a plurality of additional drain terminals on the second side and connected to the drains of the field effect transistors; 2. The circuit assembly of claim 1, further comprising: a plurality of source terminals on a third side of the packaged semiconductor component, the source terminals connected to the sources of the field effect transistors, the third side being opposite the second side.

5. 2. The circuit assembly of claim 1, wherein the packaged semiconductor component further comprises a second side source terminal on a side opposite the first side.

6. 2. The circuit assembly of claim 1, wherein the first side and the second side of the packaged semiconductor component each include a lead frame.

7. 10. The circuit assembly of claim 1, further comprising: a second packaged semiconductor component; and a second capacitor electrically connected between side source and drain terminals of the second packaged semiconductor component, the second packaged semiconductor component being rotated 180 degrees relative to the packaged semiconductor component.

8. 10. The circuit assembly of claim 1, further comprising a printed circuit board, the printed circuit board comprising traces, the capacitor being connected to one of the traces.

9. 1. A packaged semiconductor component, comprising: a semiconductor die comprising a field effect transistor having a source, a gate, and a drain; a plurality of drain terminals on a first side of the packaged semiconductor component and connected to the drain; a side source terminal on a second side of the packaged semiconductor component, the side source terminal connected to the source; a plurality of source terminals on a third side of the packaged semiconductor component and connected to the side source terminals within the packaged semiconductor component; Equipped with a packaged semiconductor component, wherein the third side is opposite the first side, the second side is adjacent to both the first side and the third side, and the side source terminal is located closer to the first side than to the third side.

10. a surface configured to couple to a printed circuit board; a heat spreader facing the surface; 10. The packaged semiconductor component of claim 9, further comprising:

11. 11. The packaged semiconductor component of claim 10, wherein the side source terminal provides mechanical support for the heat spreader.

12. 11. The packaged semiconductor component of claim 10, wherein the heat spreader has a notch around the side source terminal.

13. 10. The packaged semiconductor component of claim 9, wherein each of the first side and the second side of the packaged semiconductor component includes a lead frame.

14. 14. The packaged semiconductor component of claim 13, wherein the leadframe includes a stamped flat end.

15. 10. The packaged semiconductor component of claim 9, further comprising a gate terminal positioned on the third side of the packaged semiconductor component.

16. 1. A packaged semiconductor component, the packaged semiconductor component comprising: a semiconductor die comprising a field effect transistor having a source, a gate, and a drain; a drain terminal connected to the drain; a source terminal connected to said source, said drain terminal and said source terminal being on the same side of said packaged semiconductor component; a capacitor external to the packaged semiconductor component and electrically connected between the source terminal and the drain terminal; A circuit assembly comprising:

17. 17. The circuit assembly of claim 16, further comprising a second capacitor external to the packaged semiconductor component, the packaged semiconductor component including a second source terminal on the same side of the packaged semiconductor component as the drain terminal and the source terminal, the second capacitor being electrically connected between the second source terminal and the drain.

18. 17. The circuit assembly of claim 16, further comprising a printed circuit board, the packaged semiconductor component and the capacitor being positioned on the printed circuit board, the packaged semiconductor component further comprising a heat spreader facing the printed circuit board.

19. 17. The circuit assembly of claim 16, wherein the packaged semiconductor component comprises a plurality of additional source terminals on a side opposite the same side on which the drain terminal and the source terminal are located.

20. 17. The circuit assembly of claim 16, wherein the packaged semiconductor component comprises at least one additional drain terminal on the same side as the drain terminal and the source terminal, the at least one additional drain terminal electrically connected to the capacitor external to the packaged semiconductor component.

Images