Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of reducing the temperature coefficient of a resistor element having a first resistor and a resistor formed of the same material as the first resistor.SOLUTION: A semiconductor device (DEV1, DEV2, DEV3, DEV4, DEV5) comprises a first resistor element (RE1). The first resistor element includes a first resistor (RES1) and a second resistor (RES2) electrically connected in series with the first resistor. The first resistor and the second resistor are each made of a first material. One of a temperature coefficient of an electric resistance value of the first resistor and a temperature coefficient of an electric resistance value of the second resistor has a positive value, and the other of the temperature coefficient of the electric resistance value of the first resistor and the temperature coefficient of the electric resistance value of the second resistor has a negative value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2020-35899 (Patent Document 1) describes a semiconductor device. The semiconductor element described in Patent Document 1 has a resistive element. The resistive element is configured by connecting multiple conductive layers to each other. A first conductive layer of the multiple conductive layers has a positive temperature coefficient, and a second conductive layer of the multiple conductive layers has a negative temperature coefficient. As a result, the temperature coefficient of the resistive element is reduced in the semiconductor device described in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-35899 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, the second conductive layer is formed of a material different from that of the first conductive layer. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a first resistor element. The first resistor element has a first resistor and a second resistor electrically connected in series with the first resistor. The first resistor and the second resistor are each made of a first material. One of the temperature coefficient of the electrical resistance of the first resistor and the temperature coefficient of the electrical resistance of the second resistor is positive. The other of the temperature coefficient of the electrical resistance of the first resistor and the temperature coefficient of the electrical resistance of the second resistor is negative. [Effects of the Invention]

[0006] The semiconductor device according to the present disclosure can reduce the temperature coefficient of a resistance element including a first resistor and a second resistor formed of the same material as the first resistor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a first plan view of the semiconductor device DEV1. [Figure 2] FIG. 2 is a second plan view of the semiconductor device DEV1. [Figure 3] FIG. 3 is a cross-sectional view of the semiconductor device DEV1 taken along line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor device DEV1 taken along line IV-IV in FIG. [Figure 5] FIG. 3 is a cross-sectional view of the semiconductor device DEV1 taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view of the semiconductor device DEV1 taken along line VI-VI in FIG. [Figure 7] 1A to 1C are diagrams illustrating a manufacturing process of the semiconductor device DEV1. [Figure 8] FIG. 10 is a cross-sectional view illustrating a third interlayer insulating film forming step S7. [Figure 9] FIG. 10 is a cross-sectional view illustrating a second via plug forming step S8. [Figure 10] FIG. 10 is a cross-sectional view illustrating a resistor forming step S9. [Figure 11] FIG. 10 is a cross-sectional view illustrating a fourth interlayer insulating film forming step S10. [Figure 12] FIG. 10 is a cross-sectional view illustrating a temperature coefficient adjusting step S11. [Figure 13] 10 is a graph showing the relationship between the temperature coefficient and sheet resistance of a resistor RES2 and the annealing temperature. [Figure 14] FIG. 2 is a plan view of the semiconductor device DEV2. [Figure 15] FIG. 2 is a plan view of the semiconductor device DEV2. [Figure 16] 10A to 10C are diagrams illustrating a manufacturing process of the semiconductor device DEV2. [Figure 17] FIG. 2 is a plan view of the semiconductor device DEV3. [Figure 18] FIG. 10 is a cross-sectional view of the semiconductor device DEV4. [Figure 19] 10A to 10C are diagrams illustrating a manufacturing process of the semiconductor device DEV4. [Figure 20] FIG. 2 is a cross-sectional view of the semiconductor device DEV5. [Figure 21] FIG. 2 is a plan view of the semiconductor device DEV5. [Figure 22] 10A to 10C are diagrams illustrating a manufacturing process of the semiconductor device DEV5. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of semiconductor device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0011] 1 and 2, the semiconductor device DEV1 has, in plan view, a resistor array region R1 and an adjustment region R2. The adjustment region R2 is separate from the resistor array region R1.

[0012] As shown in FIGS. 3 to 6, the semiconductor device DEV1 has a semiconductor substrate SUB, an interlayer insulating film ILD, wiring WL, and resistors RES1, RES2, RES3, and RES4.

[0013] The semiconductor substrate SUB is made of, for example, single-crystal silicon. The semiconductor substrate SUB has an upper surface US. Although not shown, a source region and a drain region that are spaced apart from each other, and a well region that surrounds the source region and the drain region are formed on the upper surface US. Also, although not shown, a gate insulating film is disposed on a portion of the upper surface US that is located between the source region and the drain region, and a gate electrode is disposed on the gate insulating film. The source region, the drain region, the well region, the gate insulating film, and the gate electrode constitute a transistor TR (not shown).

[0014] The interlayer insulating film ILD is made of, for example, silicon oxide. A plurality of interlayer insulating films ILD are stacked on the upper surface US. The interlayer insulating film ILD has a plurality of interlayer insulating films ILD1, ILD2, and ILD3. The plurality of interlayer insulating films ILD1 are stacked on the upper surface US. The interlayer insulating film ILD2 is disposed on the uppermost interlayer insulating film ILD1 among the plurality of interlayer insulating films ILD1. The interlayer insulating film ILD3 is disposed on the interlayer insulating film ILD2. The interlayer insulating film ILD2 has a first layer ILD2a and a second layer ILD2b. The second layer ILD2b is disposed on the first layer ILD2a.

[0015] The wiring WL is made of, for example, aluminum or an aluminum alloy. The multiple wirings WL include multiple wirings WL1, WL2, and WL3. The multiple wirings WL1 are arranged on an interlayer insulating film ILD1. The wiring WL2 is arranged on an interlayer insulating film ILD2. The wiring WL3 is arranged on an interlayer insulating film ILD3. The wiring WL1 is covered with the interlayer insulating film ILD1. However, the uppermost wiring WL1 of the multiple wirings WL1 is covered with a first layer ILD2a. The wiring WL2 is covered with the interlayer insulating film ILD3. A barrier film BF1 may be arranged between the lower surface of the wiring WL and the interlayer insulating film ILD, and a barrier film BF2 may be arranged on the upper surface of the wiring WL. The constituent material of the barrier film BF1 and the barrier film BF2 is, for example, titanium nitride.

[0016] Although not shown, a contact plug CP is buried in a contact hole formed in the lowest interlayer insulating film ILD1 among the plurality of interlayer insulating films ILD1. The contact plug CP electrically connects the lowest wiring WL1 among the plurality of wirings WL1 and the transistor TR to each other.

[0017] One wiring WL and another wiring WL disposed above the one wiring WL are electrically connected to each other by a via plug VP1 embedded in a via hole formed in an interlayer insulating film ILD. The constituent material of the contact plug CP and the constituent material of the via plug VP1 are, for example, tungsten.

[0018] Resistors RES1, RES2, RES3, and RES4 are disposed on the first layer ILD2a. Resistors RES1, RES2, RES3, and RES4 are covered by the second layer ILD2b. Resistors RES1, RES2, and RES3 are electrically connected to the uppermost wiring WL1 of the multiple wirings WL1 by via plugs VP2. Resistor RES4 does not have to be electrically connected to the wiring WL. In other words, resistor RES4 may be a dummy resistor. Via plug VP2 is embedded in a via hole formed in the first layer ILD2a. The via plug VP2 is made of, for example, tungsten.

[0019] The second layer ILD2b is disposed on the first layer ILD2a so as to cover the resistors RES1, RES2, RES3, and RES4. An interlayer insulating film ILD3 is disposed on the second layer ILD2b. The wiring WL (wiring WL2, wiring WL3) disposed above the resistors RES1 to RES4 is disposed so as not to overlap the resistor RES2 in a plan view. Note that the wiring WL2 and wiring WL3 disposed above the resistors RES1 to RES4 may be disposed so as to overlap the resistor RES1 (resistor RES3, resistor RES4), or may be disposed so as not to overlap the resistor RES1 (resistor RES3, resistor RES4).

[0020] 1 and 2, resistors RES1, RES3, and RES4 are arranged inside resistor array region R1 in plan view. Resistor RES2 is arranged inside adjustment region R2 in plan view. That is, resistor RES2 is arranged outside resistor array region R1 in plan view.

[0021] The resistor array region R1 includes a region R1a, a region R1b, and a region R1c. In a plan view, the regions R1a, R1b, and R1c are arranged in a row. The multiple regions included in the resistor array region R1 are arranged along a first direction DR1.

[0022] Within one region R1a, a plurality of resistors RES1 are arranged along a first direction DR1. The longitudinal direction of the resistors RES1 in a plan view is aligned along a second direction DR2 perpendicular to the first direction DR1 in a plan view. The number of resistors RES1 arranged within one region R1a may be different from the number of resistors RES1 arranged within another region R1a. Within one region R1b, a plurality of resistors RES3 are arranged along the first direction DR1. The longitudinal direction of the resistors RES3 in a plan view is aligned along the second direction DR2. The number of resistors RES3 arranged within one region R1b may be different from the number of resistors RES3 arranged within another region R1b. Within one region R1c, a plurality of resistors RES4 are arranged along the first direction DR1.

[0023] The region R1a is located between the two regions R1b in the first direction DR1. That is, each of the multiple regions R1a is located closer to the center C of the resistor array region R1 in the first direction DR1 than either the region R1b or the region R1c. The region R1b is located between the region R1a and the region R1c in the first direction DR1. That is, each of the multiple regions R1b is located closer to the center C in the first direction DR1 than the region R1c. From another perspective, the regions R1c are located at both ends of the resistor array region R1 in the first direction DR1.

[0024] The constituent material of resistor RES1, the constituent material of resistor RES2, the constituent material of resistor RES3, and the constituent material of resistor RES4 is a first material. The first material is, for example, silicon chromium (SiCr). However, the first material is not limited to this.

[0025] One of the temperature coefficients of resistor RES1 and resistor RES2 is a positive value, and the other of the temperature coefficients of resistor RES1 and resistor RES2 is a negative value. For example, the temperature coefficient of resistor RES1 is a negative value, and the temperature coefficient of resistor RES2 is a positive value. The temperature coefficient of a resistor is the rate of change of the electrical resistance value of the resistor per unit temperature. Note that if the electrical resistance value of a resistor increases with increasing temperature, the temperature coefficient of the resistor will be a positive value. On the other hand, if the electrical resistance value of a resistor decreases with increasing temperature, the temperature coefficient of the resistor will be a negative value.

[0026] A plurality of resistors RES1 arranged in one region R1a are electrically connected in series with each other. A plurality of resistors RES1 arranged in one region R1a and electrically connected in series with each other are electrically connected in series with a resistor RES2 to form a resistor element RE1. A plurality of resistors RES3 arranged in one region R1b are electrically connected in series with each other to form a resistor element RE2. In other words, the resistor element RE2 is arranged inside the resistor array region R1.

[0027] The length of resistor RES2 in the longitudinal direction is preferably greater than the length of resistor RES1 in the longitudinal direction. The width of resistor RES2 in the direction perpendicular to the longitudinal direction is preferably greater than the width of resistor RES1 in the direction perpendicular to the longitudinal direction. The width of resistor RES4 is, for example, greater than the width of resistor RES1.

[0028] The semiconductor device DEV1 has a plurality of circuits each composed of a transistor TR. The circuits included in the semiconductor device DEV1 include a first circuit and a second circuit. The precision of the resistor elements required for the first circuit is higher than the precision of the resistor elements required for the second circuit.

[0029] The first circuit is, for example, a reference voltage generating circuit, a first digital-to-analog conversion circuit, or a second digital conversion circuit. The second circuit is, for example, a third digital-to-analog conversion circuit. Note that the precision required for the resistor elements in the third digital-to-analog conversion circuit is lower than the precision required for the resistor elements in the first digital-to-analog conversion circuit and the second digital-to-analog conversion circuit. The resistor element RE1 is connected, for example, to the first circuit. The resistor element RE2 is connected, for example, to the second circuit. The resistor element RE2 may be used as a feedback resistor.

[0030] <Method of Manufacturing Semiconductor Device DEV1> A method for manufacturing the semiconductor device DEV1 will be described below.

[0031] As shown in FIG. 7, the manufacturing method of the semiconductor device DEV1 includes a preparation step S1, a first interlayer insulating film forming step S2, a contact plug forming step S3, a wiring forming step S4, a second interlayer insulating film forming step S5, a first via plug forming step S6, a third interlayer insulating film forming step S7, a second via plug forming step S8, a resistor forming step S9, a fourth interlayer insulating film forming step S10, and a temperature coefficient adjusting step S11.

[0032] In the preparation step S1, a semiconductor substrate SUB is prepared. A transistor TR has already been formed on the semiconductor substrate SUB prepared in the preparation step S1. In the first interlayer insulating film formation step S2, the lowest interlayer insulating film ILD1 of the multiple interlayer insulating films ILD1 is formed so as to cover the transistor TR. In the first interlayer insulating film formation step S2, first, a constituent material of the lowest interlayer insulating film ILD1 of the multiple interlayer insulating films ILD1 is deposited on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. Second, the constituent material of the lowest interlayer insulating film ILD of the multiple interlayer insulating films ILD1 that has been deposited is planarized by, for example, a CMP (Chemical Mechanical Polishing) method.

[0033] In the contact plug formation step S3, a contact plug CP is buried in the lowest interlayer insulating film ILD1 of the plurality of interlayer insulating films ILD1. In the contact plug formation step S3, first, a contact hole is formed in the lowest interlayer insulating film ILD1 of the plurality of interlayer insulating films ILD1 by etching using a resist pattern formed on the lowest interlayer insulating film ILD1 of the plurality of interlayer insulating films ILD1 by photolithography as a mask. Second, a constituent material of the contact plug CP is buried in the contact hole by, for example, CVD. Third, the constituent material of the contact plug CP formed outside the contact hole is removed by, for example, CMP.

[0034] In the wiring formation process S4, the wiring WL1 is formed on the interlayer insulating film ILD1. In the wiring formation process S4, first, constituent materials of the barrier film BF1, the wiring WL1, and the barrier film BF2 are sequentially deposited on the interlayer insulating film ILD1 by, for example, sputtering. Second, each deposited constituent material is patterned by etching using a resist pattern formed by photolithography on the deposited constituent material of the barrier film BF2 as a mask.

[0035] In the second interlayer insulating film forming step S5, the interlayer insulating film ILD1 is formed so as to cover the wiring WL1. In the second interlayer insulating film forming step S5, first, a constituent material of the interlayer insulating film ILD1 is formed on the interlayer insulating film ILD1 by, for example, a CVD method. Second, the formed constituent material of the interlayer insulating film ILD1 is planarized by, for example, a CMP method.

[0036] In the first via plug formation process S6, a via plug VP1 is buried in the interlayer insulating film ILD1. In the first via plug formation process S6, first, a via hole is formed in the interlayer insulating film ILD1 by etching using a resist pattern formed on the interlayer insulating film ILD1 by photolithography as a mask. Second, a constituent material of the via plug VP1 is buried in the via hole by, for example, CVD. Third, the constituent material of the via plug VP1 formed outside the via hole is removed by, for example, CMP.

[0037] Thereafter, the wiring formation step S4, the second interlayer insulating film formation step S5, and the first via plug formation step S6 may be repeatedly performed to further form a wiring WL1, an interlayer insulating film ILD1, and a via plug VP1.

[0038] 8, in the third interlayer insulating film formation step S7, a first layer ILD2a is formed so as to cover the uppermost wiring WL1 of the multiple wirings WL1. In the third interlayer insulating film formation step S7, first, a constituent material of the first layer ILD2a is deposited on the uppermost interlayer insulating film ILD1 of the multiple interlayer insulating films ILD1 by, for example, a CVD method. Second, the deposited constituent material of the first layer ILD2a is planarized by, for example, a CMP method.

[0039] 9, in the second via plug formation process S8, a via plug VP2 is buried in the first layer ILD2a. In the second via plug formation process S8, first, a via hole is formed in the first layer ILD2a by etching using a resist pattern formed on the first layer ILD2a by photolithography as a mask. Second, a constituent material of the via plug VP2 is buried in the via hole by, for example, CVD. Third, the constituent material of the via plug VP2 formed outside the via hole is removed by, for example, CMP.

[0040] 10, in the resistor formation step S9, a resistor RES2 is formed on the first layer ILD2a. In the resistor formation step S9, first, a constituent material of the resistor RES2 is deposited on the first layer ILD2a by, for example, sputtering. Second, the deposited constituent material of the resistor RES2 is patterned by etching using a resist pattern formed on the deposited constituent material of the resistor RES2 by photolithography as a mask. Although not shown, resistors RES1, RES3, and RES4 are also formed in the resistor formation step S9 in a similar manner.

[0041] 11, in the fourth interlayer insulating film forming step S10, a second layer ILD2b is formed to cover the resistors RES1, RES2, RES3, and RES4. In the fourth interlayer insulating film forming step S10, first, a material for the second layer ILD2b is deposited on the first layer ILD2a by, for example, CVD. Second, the deposited material for the second layer ILD2b is planarized by, for example, CMP.

[0042] After the fourth interlayer insulating film forming step S10 is performed, a wiring forming step S4, a second interlayer insulating film forming step S5, and a first via plug forming step S6 are performed, thereby further forming wiring WL2, wiring WL3, an interlayer insulating film ILD3, and a via plug VP1. In this way, the structure of the semiconductor device DEV1 is formed.

[0043] 12, in the temperature coefficient adjusting step S11, the temperature coefficient of the resistor RES2 is adjusted. More specifically, in the temperature coefficient adjusting step S11, the resistor RES2 is irradiated with laser light L through the interlayer insulating film ILD (second layer ILD2b, interlayer insulating film ILD3) disposed on the resistor RES2, thereby performing local annealing on the resistor RES2. This changes the temperature coefficient of the resistor RES2, so that one of the resistors RES1 and RES2 has a positive temperature coefficient and the other of the resistors RES1 and RES2 has a negative temperature coefficient. Note that the annealing conditions in the temperature coefficient adjusting step S11 are determined, for example, after measuring the temperature coefficients of the resistors RES1 and RES2 before annealing.

[0044] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0045] In the semiconductor device DEV1, one of the temperature coefficients of the resistors RES1 and RES2 is positive, and the other of the temperature coefficients of the resistors RES1 and RES2 is negative. Therefore, even when the temperature changes, the changes in the electrical resistance value of the resistors RES1 and RES2 cancel each other out, thereby suppressing changes in the electrical resistance value of the entire resistor RE1 that accompany temperature changes. Therefore, the semiconductor device DEV1 can reduce the temperature coefficient of the resistor RE1, which has the resistor RES1 and the resistor RES2 made of the same material as the resistor RES1.

[0046] In the semiconductor device DEV1, the wiring WL (wiring WL2, wiring WL3) arranged above the resistor RES2 is arranged so as not to overlap with the resistor RES2 in a plan view, so that local annealing of the resistor RES2 is possible by irradiating it with laser light L. This makes it possible to form a resistance element including a resistor having a positive temperature coefficient and a resistor having a negative temperature coefficient.

[0047] In Figure 13, the vertical axis represents the sheet resistance and temperature coefficient of resistor RES2, and the horizontal axis represents the annealing temperature. The graph in Figure 13 shows an example in which resistor RES2 is made of SiCr. As shown in Figure 13, when resistor RES2 is annealed, the temperature coefficient of resistor RES2 changes from negative to positive. Therefore, by performing local annealing on resistor RES2 as described above, it is possible to form a resistance element including a resistor with a positive temperature coefficient and a resistor with a negative temperature coefficient.

[0048] On the other hand, the electrical resistance (sheet resistance) of the resistor RES2 decreases as a result of annealing. The resistor RE1 is configured by electrically connecting resistors RES1 and RES2 in series, and the electrical resistance of the resistor RE1 is expressed as the sum of the electrical resistances of the resistors RES1 and RES2. Therefore, even if local annealing is performed on the resistor RES2 to adjust the temperature coefficient, the effect on the electrical resistance of the entire resistor RE1 is negligible. Note that by making the length and width of the resistor RES2 larger than the length and width of the resistor RES1, the effect of the decrease in the electrical resistance of the resistor RES2 due to local annealing on the resistor RES2 can be further reduced.

[0049] The temperature coefficient of the resistance element RE2 is not adjusted using the resistor RES2, which makes it possible to suppress an increase in the number of steps involved in adjusting the temperature coefficient. Note that, since the requirement for accuracy in the electrical resistance value of the resistance element RE2 is relatively low, it is not necessarily necessary to adjust the temperature coefficient of the resistance element RE2.

[0050] In the semiconductor device DEV1, the resistor RES2 is arranged in a region (adjustment region R2) separate from the resistor array region R1, so that local annealing can be easily performed on the adjustment region R2 without affecting the resistors arranged in the resistor array region R1.

[0051] (Second embodiment) A semiconductor device DEV2 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0052] <Configuration of semiconductor device DEV2> The configuration of the semiconductor device DEV2 will be described below.

[0053] The semiconductor device DEV2 has a semiconductor substrate SUB, an interlayer insulating film ILD, wiring WL, contact plugs CP, via plugs VP1 and VP2, and resistors RES1, RES2, RES3, and RES4. Except for the region where the resistor RES2 is arranged, the configuration of the semiconductor device DEV2 is the same as the configuration of the semiconductor device DEV1.

[0054] As shown in FIG. 14, in the semiconductor device DEV2, the wiring WL3 has pads PD1 and PD2. The pads PD1 and PD2 are electrically connected to the resistor RES2 via the wiring WL and via plugs VP1 and VP2. As shown in FIG. 15, in the semiconductor device DEV2, the resistor RES2 is arranged inside the region R1a alongside the resistor RES1 in a plan view. That is, in the semiconductor device DEV2, the resistive element RE1 is arranged inside the resistor array region R1. In these respects, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1.

[0055] In the semiconductor device DEV2, the wirings WL (wirings WL2 and WL3) arranged above the resistors RES1 to RES4 may be arranged to overlap the resistor RES2.

[0056] <Method of manufacturing semiconductor device DEV2> A method for manufacturing the semiconductor device DEV2 will be described below.

[0057] 16, the method for manufacturing the semiconductor device DEV2 includes a preparation step S1, a first interlayer insulating film forming step S2, a contact plug forming step S3, a wiring forming step S4, a second interlayer insulating film forming step S5, a first via plug forming step S6, a third interlayer insulating film forming step S7, a second via plug forming step S8, a resistor forming step S9, and a fourth interlayer insulating film forming step S10. In this respect, the method for manufacturing the semiconductor device DEV2 is common to the method for manufacturing the semiconductor device DEV1.

[0058] The manufacturing method of the semiconductor device DEV2 includes a temperature coefficient adjustment step S12 instead of the temperature coefficient adjustment step S11. In the temperature coefficient adjustment step S12, a voltage is applied between the pad PD1 and the pad PD2. This causes a current to flow through the resistor RES2, causing the resistor RES2 to heat up and perform local annealing of the resistor RES2. The temperature coefficient adjustment step S12 may be performed in a wafer test step or an assembly step. In this respect, the manufacturing method of the semiconductor device DEV2 differs from the manufacturing method of the semiconductor device DEV1.

[0059] <Effects of semiconductor device DEV2> The effects of the semiconductor device DEV2 will be described below.

[0060] In the semiconductor device DEV2, it is possible to locally anneal the resistor RES2 by locally passing a current through the resistor RES2. Therefore, in the semiconductor device DEV2, it is possible to make one of the temperature coefficients of the resistors RES1 and RES2 a positive value and the other of the temperature coefficients of the resistors RES1 and RES2 a negative value. Therefore, in the semiconductor device DEV2, it is possible to reduce the temperature coefficient of the resistor RE1.

[0061] Furthermore, when annealing the resistor RES2 by irradiating it with laser light L as in the semiconductor device DEV1, if the resistors RES1 and RES2 are arranged side by side, there is a risk that the laser light L will also be irradiated onto the resistor RES1, so the resistor RES2 cannot be arranged side by side near the resistor RES1. On the other hand, in the semiconductor device DEV2, annealing of the resistor RES2 is performed by locally flowing a current through the resistor RES2, so even if the resistor RES1 is arranged side by side near the resistor RES2, local annealing of the resistor RES2 is possible. As a result, in the semiconductor device DEV2, it is not necessary to arrange a region (e.g., an adjustment region R2) for arranging the resistor RES2 other than the resistor array region R1, and the chip area can be reduced.

[0062] (Third embodiment) The semiconductor device DEV3 according to the third embodiment will be described below. Here, differences from the semiconductor device DEV3 will be mainly described, and overlapping descriptions will not be repeated.

[0063] <Configuration of semiconductor device DEV3> The configuration of the semiconductor device DEV3 will be described below.

[0064] The semiconductor device DEV3 has a semiconductor substrate SUB, an interlayer insulating film ILD, wiring WL, contact plugs CP, via plugs VP1 and VP2, resistors RES1, RES2, and RES3, and pads PD1 and PD2. Except for the region where the resistor RES2 is disposed, the configuration of the semiconductor device DEV3 is the same as the configuration of the semiconductor device DEV2.

[0065] 17, the semiconductor device DEV3 does not have a resistor RES4. Furthermore, in the semiconductor device DEV3, the resistor RES2 is disposed inside the region R1c. In these respects, the configuration of the semiconductor device DEV3 differs from the configuration of the semiconductor device DEV2.

[0066] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below.

[0067] In the semiconductor device DEV3, a resistor RES2 is arranged inside the region R1c instead of the resistor RES4, which is a dummy resistor. Therefore, in the semiconductor device DEV3, by arranging the resistor RES2 inside the region where the dummy resistors are arranged, the resistor array region R1 can be made smaller, and the chip area can be reduced.

[0068] Furthermore, since the width of the resistor (resistor RES2) placed inside region R1c is larger than the width of the resistor (resistor RES1) placed inside region R1a, it is also possible to reduce the effect of the decrease in electrical resistance value that occurs when annealing resistor RES2.

[0069] (Fourth embodiment) A semiconductor device DEV4 according to the fourth embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0070] <Configuration of semiconductor device DEV4> The configuration of the semiconductor device DEV4 will be described below.

[0071] The semiconductor device DEV4 has a semiconductor substrate SUB, an interlayer insulating film ILD, wiring WL, contact plugs CP, via plugs VP1 and VP2, and resistors RES1, RES2, RES3, and RES4. Except for the layer in which the resistor RES2 is disposed and the region in which the resistor RES2 is disposed, the configuration of the semiconductor device DEV4 is the same as the configuration of the semiconductor device DEV1.

[0072] 18, in the semiconductor device DEV4, the resistor RES2 is arranged in a layer different from that of the resistor RES1. For example, in the semiconductor device DEV4, the resistor RES2 is arranged below the resistor RES1, not in the adjustment region R2.

[0073] More specifically, the interlayer insulating film ILD further includes an interlayer insulating film ILD4. The interlayer insulating film ILD4 is disposed on the uppermost interlayer insulating film ILD1 of the multiple interlayer insulating films ILD1. The interlayer insulating film ILD4 includes a first layer ILD4a and a second layer ILD4b. The first layer ILD4a is disposed on the uppermost interlayer insulating film ILD1 of the multiple interlayer insulating films ILD1 so as to cover the wiring WL1. The resistor RES2 is disposed on the first layer ILD4a and is electrically connected to the wiring WL2 covered by the first layer ILD4a through a via plug VP3 embedded in a via hole formed in the first layer ILD2a.

[0074] The second layer ILD4b is disposed on the first layer ILD4a so as to cover the resistor RES2. An interlayer insulating film ILD2 (first layer ILD2a) is disposed on the second layer ILD4b. That is, the resistor RES2 is disposed in a different layer from the resistor RES1. In these respects, the configuration of the semiconductor device DEV4 differs from the configuration of the semiconductor device DEV1. Although not shown, the resistors RES3 and RES4 are disposed in the same layer as the resistor RES1.

[0075] <Manufacturing Method of Semiconductor Device DEV4> A method for manufacturing the semiconductor device DEV4 will be described below.

[0076] 19, the method for manufacturing the semiconductor device DEV4 includes a preparation step S1, a first interlayer insulating film forming step S2, a contact plug forming step S3, a wiring forming step S4, a second interlayer insulating film forming step S5, a first via plug forming step S6, a third interlayer insulating film forming step S7, a second via plug forming step S8, a resistor forming step S9, and a fourth interlayer insulating film forming step S10. In this respect, the method for manufacturing the semiconductor device DEV4 is common to the method for manufacturing the semiconductor device DEV1.

[0077] The manufacturing method of the semiconductor device DEV4 does not include the temperature coefficient adjustment step S11. Furthermore, in the semiconductor device DEV4, the third interlayer insulating film formation step S7, the second via plug formation step S8, the resistor formation step S9, and the fourth interlayer insulating film formation step S10 are repeatedly performed, so that the resistor RES1 is formed in the first layer and the resistor RES2 is formed in the second layer different from the first layer. In these respects, the manufacturing method of the semiconductor device DEV4 differs from the manufacturing method of the semiconductor device DEV1.

[0078] <Effects of semiconductor device DEV4> The effects of the semiconductor device DEV4 will be described below.

[0079] In the semiconductor device DEV4, the resistors RES1 and RES2 are formed in different layers, so that the thermal history of the resistor RES1 differs from the thermal history of the resistor RES2 during the manufacturing process of the semiconductor device DEV4. Furthermore, an annealing process can be added between the process of forming the resistors RES1 and RES2 to change the thermal history of the resistor RES2. Therefore, in the semiconductor device DEV4, due to this difference in thermal history, it is possible to make one of the temperature coefficients of the resistors RES1 and RES2 positive and the other negative. Therefore, the temperature coefficient of the resistor RE1 can be reduced in the semiconductor device DEV4 as well.

[0080] (Fifth embodiment) A semiconductor device DEV5 according to the fifth embodiment will be described below. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0081] <Configuration of semiconductor device DEV5> The configuration of the semiconductor device DEV5 will be described below.

[0082] The semiconductor device DEV1 includes a semiconductor substrate SUB, an interlayer insulating film ILD, wiring WL, contact plugs CP, via plugs VP1 and VP2, and resistors RES1, RES2, RES3, and RES4. In this respect, the configuration of the semiconductor device DEV5 is common to the configuration of the semiconductor device DEV1.

[0083] 20, the semiconductor device DEV5 further includes a heater HT. The heater HT is arranged so as to overlap the resistor RES2 in a plan view. The heater HT is arranged on the semiconductor substrate SUB (upper surface US) with an insulating film IF interposed therebetween. The heater HT is made of the same material as the gate electrode of the transistor TR, such as polycrystalline silicon. The insulating film IF is made of the same material as the gate insulating film of the transistor TR, such as silicon oxide.

[0084] 21, in the semiconductor device DEV2, the wiring WL3 has pads PD3 and PD4. The pads PD3 and PD4 are electrically connected to the heater HT via the wiring WL and via plugs VP1 and VP2. In these respects, the configuration of the semiconductor device DEV5 differs from the configuration of the semiconductor device DEV1.

[0085] The heater HT does not have to be disposed on the semiconductor substrate SUB, and the heater HT does not have to be made of polycrystalline silicon (the same material as the gate electrode of the transistor TR). For example, the heater HT may be configured by electrically connecting the wiring WL overlapping the resistor RES2 in a plan view to the pads PD3 and PD4.

[0086] <Method of manufacturing semiconductor device DEV5> A method for manufacturing the semiconductor device DEV5 will be described below.

[0087] 22, the method for manufacturing the semiconductor device DEV5 includes a preparation step S1, a first interlayer insulating film forming step S2, a contact plug forming step S3, a wiring forming step S4, a second interlayer insulating film forming step S5, a first via plug forming step S6, a third interlayer insulating film forming step S7, a second via plug forming step S8, a resistor forming step S9, and a fourth interlayer insulating film forming step S10. In this respect, the method for manufacturing the semiconductor device DEV5 is common to the method for manufacturing the semiconductor device DEV1.

[0088] The manufacturing method of the semiconductor device DEV5 includes a temperature coefficient adjustment step S13 instead of the temperature coefficient adjustment step S11. In the temperature coefficient adjustment step S13, a voltage is applied between the pads PD3 and PD4. This causes a current to flow through the heater HT, causing the heater HT to generate heat and performing local annealing on the resistor RES2. The temperature coefficient adjustment step S13 may also be performed in a wafer test step or an assembly step. In this respect, the manufacturing method of the semiconductor device DEV5 differs from the manufacturing method of the semiconductor device DEV1.

[0089] In the manufacturing method of the semiconductor device DEV5, the insulating film IF is also formed when the gate insulating film of the transistor TR is formed, and the heater HT is also formed when the gate electrode of the transistor TR is formed.

[0090] <Effects of semiconductor device DEV5> The effects of the semiconductor device DEV5 will be described below.

[0091] In the semiconductor device DEV5, local annealing of the resistor RES2 can be performed by passing a current through the heater HT. Therefore, in the semiconductor device DEV5, it is possible to make one of the temperature coefficients of the resistor RES1 and the resistor RES2 a positive value and the other of the temperature coefficients of the resistor RES1 and the resistor RES2 a negative value. Therefore, in the semiconductor device DEV5, it is possible to reduce the temperature coefficient of the resistor RE1. Note that the heater HT is formed in the same process as the gate electrode of the transistor TR, so there is no need to add a new process for forming the heater HT.

[0092] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0093] BF1, BF2 barrier film, C center, CP contact plug, DEV1 semiconductor device, DEV2, DEV3, DEV4, DEV5 semiconductor device, DR1 first direction, DR2 second direction, HT heater, IF insulating film, ILD interlayer insulating film, ILD1, ILD2, ILD3, ILD4 interlayer insulating film, ILD2a, ILD2b first layer, ILD4b, ILD4b second layer, L laser light, PD1, PD2, PD3, PD4 pad, R1 resistor array region, R1a, R1b, R1c region, R2 adjustment region, RE1, RE2 resistive element, RES1, RES2, RES3, RES4 resistor, S1 preparation step, S2 first interlayer insulating film formation step, S3 contact plug formation step, S4 wiring formation step, S5 second interlayer insulating film formation step, S6 first via plug formation step, S7 Third interlayer insulating film forming step, S8 second via plug forming step, S9 resistor forming step, S10 fourth interlayer insulating film forming step, S11, S12, S13 temperature coefficient adjusting step, US upper surface, SUB semiconductor substrate, TR transistor, VP1, VP2, VP3 via plug, WL, WL1, WL2, WL3 wiring.

Claims

1. a first resistor element; the first resistor element has a first resistor and a second resistor electrically connected in series with the first resistor; the first resistor and the second resistor are each made of a first material; one of the temperature coefficient of the electrical resistance of the first resistor and the temperature coefficient of the electrical resistance of the second resistor is a positive value; The semiconductor device according to claim 1, wherein the other of the temperature coefficient of the electrical resistance of the first resistor and the temperature coefficient of the electrical resistance of the second resistor is a negative value.

2. a wiring formed in a layer above the second resistor; The semiconductor device according to claim 1 , wherein the wiring is arranged so as not to overlap the second resistor in a plan view.

3. the first resistor is disposed inside a resistor array region in a plan view, The semiconductor device according to claim 1 , wherein said second resistor is arranged outside said resistor array region in a plan view.

4. The semiconductor device according to claim 1 , further comprising: a first pad electrically connected to said second resistor; and a second pad electrically connected to said second resistor.

5. the first resistor element is disposed inside a resistor array region in a plan view, the resistor array region includes a plurality of regions arranged in a row in a plan view, The semiconductor device according to claim 4 , wherein the first resistor and the second resistor are arranged inside a first region of the plurality of regions.

6. further comprising a second resistor element separate from the first resistor element; the second resistor element has a third resistor, the third resistor is made of the first material, the second resistor element is disposed inside the resistor array region in a plan view, the third resistor is disposed inside a second region of the plurality of regions that is separate from the first region, 6. The semiconductor device according to claim 5, wherein said first region is arranged closer to a center of said resistor array region in a direction in which said plurality of regions are arranged than said second region.

7. the first resistor element is disposed inside a resistor array region in a plan view, the resistor array region includes a plurality of regions arranged in a row in a plan view, the first resistor is disposed inside a first region of the plurality of regions, 4. The semiconductor device according to claim 3, wherein the second resistor is arranged inside a third region of the plurality of regions, which is separate from the first region, and which is arranged at an end of the resistor array region in a direction in which the plurality of regions are arranged.

8. the first resistor is formed in a first layer; 2. The semiconductor device according to claim 1, wherein said second resistor is formed in a second layer different from said first layer.

9. The semiconductor device according to claim 8 , wherein said second resistor is formed above said first resistor.

10. Further comprising a heater; The semiconductor device according to claim 1 , wherein the heater overlaps the second resistor in a plan view.

11. Further comprising a semiconductor substrate; the heater is made of polycrystalline silicon; the heater is disposed on the semiconductor substrate; The semiconductor device according to claim 10 , wherein the heater is disposed below the second resistor.

12. The semiconductor device according to claim 1 , wherein the first material is SiCr.

13. The semiconductor device according to claim 1 , wherein the second resistor has a length and a width greater than the length and width of the first resistor, respectively.

14. forming a first resistor and a second resistor electrically connected in series with the first resistor from a first material; and adjusting the temperature coefficient of the second resistor so that one of the temperature coefficient of the electrical resistance value of the first resistor and the temperature coefficient of the electrical resistance value of the second resistor exhibits a positive value, and the other of the temperature coefficient of the electrical resistance value of the first resistor and the temperature coefficient of the electrical resistance value of the second resistor exhibits a negative value.

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the temperature coefficient of said second resistor is adjusted by irradiating said second resistor with laser light.

16. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the temperature coefficient of said second resistor is adjusted by passing a current through said second resistor.

17. the first resistor is formed in a first layer; 15. The method for manufacturing a semiconductor device according to claim 14, wherein the temperature coefficient of said second resistor is adjusted by forming said second resistor in a second layer different from said first layer.

18. forming a heater; the heater is formed so as to overlap the second resistor in a plan view, 15. The method for manufacturing a semiconductor device according to claim 14, wherein the temperature coefficient of said second resistor is adjusted by heating said second resistor with said heater.

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