Memory device

Abstract

To provide a semiconductor device including a transistor using a highly reliable oxide semiconductor by solving the problem in which transistors using oxide semiconductors are sometimes less reliable than transistors using amorphous silicon.SOLUTION: Impurities such as hydrogen, nitrogen, and carbon contained in an oxide semiconductor film become a factor that deteriorates the semiconductor characteristics of the oxide semiconductor film. For example, hydrogen and nitrogen contained in the oxide semiconductor film cause a negative shift in a threshold voltage of a transistor using the oxide semiconductor film. Furthermore, nitrogen, carbon, and rare gas contained in the oxide semiconductor film inhibit the formation of a crystalline region in the oxide semiconductor film. Therefore, by reducing the impurity concentration of the oxide semiconductor film, a highly reliable transistor is manufactured.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing an oxide semiconductor film and a method for manufacturing a semiconductor device.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor thin film materials applicable to transistors are Silicon-based semiconductor materials are widely known as such materials, but oxide semiconductors are also attracting attention. It has been done.

[0004] For example, the active layer of a transistor is 18 / cm 3 is less than A transistor using an oxide semiconductor containing In, Ga, and Zn is disclosed. The sputtering method is considered to be the best method for forming a compound semiconductor film (see Patent Document 1). .). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0006] Transistors using oxide semiconductors have the following advantages compared to transistors using amorphous silicon: Therefore, a transistor using an oxide semiconductor with high reliability was developed. The present invention provides a semiconductor device having the above structure.

[0007] A method for forming an oxide semiconductor film for this purpose will also be described. [Means for solving the problem]

[0008] Impurities such as hydrogen, nitrogen, and carbon contained in the oxide semiconductor film are This can cause a deterioration in characteristics.

[0009] For example, hydrogen and nitrogen contained in the oxide semiconductor film generate carriers in the oxide semiconductor film. Therefore, the presence of hydrogen and nitrogen makes it possible to form a transistor using an oxide semiconductor film. This shifts the threshold voltage of the transistor in the negative direction, resulting in a decrease in reliability. This will lead to a decline in performance.

[0010] In addition, nitrogen, carbon, and a rare gas contained in the oxide semiconductor film form a crystalline region in the oxide semiconductor film. For example, nitrogen and carbon dioxide molecules can inhibit the formation of The large molecular diameter particularly inhibits the formation of a crystalline region in an oxide semiconductor film. In addition, when a carbon atom replaces a metal atom in the oxide semiconductor film, a crystal is formed at the replacement site. It cuts the structure.

[0011] Therefore, obtaining an oxide semiconductor film with few impurities is important for highly reliable transistors. It is important to obtain

[0012] Specifically, the hydrogen concentration in the oxide semiconductor film was measured by secondary ion mass spectrometry (SIMS). 5×10 1 9 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferred: Or 1 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0013] The nitrogen concentration in the oxide semiconductor film was measured by SIMS. 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following do.

[0014] The carbon concentration in the oxide semiconductor film was measured by SIMS. 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following do.

[0015] A transistor using an oxide semiconductor film is a transistor that uses hydrogen (containing hydrogen in water, etc.) contained in the oxide semiconductor film. If electrons are generated due to hydrogen (including hydrogen contained in the semiconductor) and nitrogen, the gate voltage is not applied. The drain current flows even when the transistor is in a normally on state (also called a normally on state). , the current between the source and drain of a transistor. The gate voltage is the source potential The threshold voltage is the potential difference between the gate potential and the reference potential. The transistor using an oxide semiconductor film is often n-type, and the threshold The voltage shifts in the negative direction, resulting in a normally-on characteristic.

[0016] After a transistor using an oxide semiconductor film is manufactured, hydrogen or In some cases, the inclusion of nitrogen can cause the threshold voltage of the transistor to fluctuate. The variation in threshold voltage significantly reduces the reliability of the transistor.

[0017] Therefore, in order to obtain a highly reliable transistor, an oxide semiconductor film and an oxide semiconductor It is necessary to reduce the hydrogen and nitrogen content of the film in contact with the film.

[0018] Similarly, it is known that oxygen vacancies in an oxide semiconductor film generate electrons.

[0019] To prevent oxygen vacancies from occurring in the oxide semiconductor film, the oxide semiconductor film is formed by interstitial oxygen The interstitial oxygen can compensate for oxygen vacancies occurring in the oxide semiconductor film. This can be done.

[0020] In a transistor including an oxide semiconductor film, if the oxide semiconductor film is single crystal, oxygen Since there is no interstitial oxygen to compensate for the defects, the oxide semiconductor film is As a result, the threshold voltage of the transistor increases in the negative direction. Therefore, it is preferable that the oxide semiconductor film is non-single-crystal. I wish.

[0021] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0022] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor with a crystalline-amorphous mixed phase structure that has crystalline and amorphous regions in the amorphous phase. The crystal region is a size that fits within a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) The observation image using a tron ​​microscope shows that the amorphous phase in the CAAC-OS film The boundary between the amorphous and crystalline regions is not clear. The grain boundary cannot be confirmed. In this case, the decrease in electron mobility caused by the grain boundaries is suppressed.

[0023] The crystalline regions in the CAAC-OS film have c-axes aligned along the normal vector of the surface on which the CAAC-OS film is formed. The three planes are aligned parallel to the normal vector of the wall or surface and perpendicular to the ab plane. It has a square or hexagonal atomic arrangement, and the metal atoms are layered or arranged in a direction perpendicular to the c-axis. In the case of a, metal atoms and oxygen atoms are arranged in layers. The orientation of the a-axis and the b-axis may be different. , the range of 85° to 95° is also included. The range of -5° to 5° is also included.

[0024] In the CAAC-OS film, the distribution of crystalline regions does not have to be uniform. In the process of forming the AC-OS film, when crystals are grown from the surface side of the oxide semiconductor film, The proportion of crystalline regions may be higher near the surface than near the formation surface. By adding impurities to the CAAC-OS film, a crystalline region is formed in the impurity-doped region. may become amorphous.

[0025] The c-axis of the crystalline region in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film (the shape of the film) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The c-axis direction of the crystalline region is the normal vector of the surface on which the CAAC-OS film is formed. The direction is parallel to the vector or surface normal vector. Alternatively, the film is formed by performing a crystallization treatment such as a heat treatment after the film is formed.

[0026] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0027] In order to improve the crystallinity of an oxide semiconductor film, it is necessary to ensure the flatness of the surface on which the film is to be formed and the formation of the oxide semiconductor film. Membrane methods are important.

[0028] Specifically, the surface on which the oxide semiconductor film is to be formed has an average surface roughness (Ra) of 1 nm or less, preferably is set to 0.3 nm or less, and more preferably 0.1 nm or less.

[0029] The oxide semiconductor film is formed by a sputtering method in an oxygen gas atmosphere while heating the substrate. At this time, it is preferable to form the oxide semiconductor film by adding an impurity that inhibits the formation of a crystalline region in the oxide semiconductor film. The film is formed so that it contains as little as possible.

[0030] Carbon dioxide is a specific example of an impurity that inhibits the formation of a crystalline region in an oxide semiconductor film. In addition, some noble gases (helium, neon, argon, krypton, and xenon), Atoms with large atomic diameters or molecules with large molecular diameters, such as nitrogen, carbon monoxide, and hydrocarbons The atoms can also become impurities that inhibit the formation of crystalline regions in the oxide semiconductor film.

[0031] In order to prevent the above-mentioned impurities from being incorporated into the oxide semiconductor film, It is necessary to reduce impurities in the gases and deposition chamber.

[0032] Specifically, a deposition gas having a purity of 8N or more, preferably 9N or more, may be used.

[0033] Furthermore, impurities present in the film formation chamber may be reduced as follows.

[0034] The amount of impurities present in the film formation chamber is determined by the balance between the amount of exhaust and the amount of leakage. It is preferable to increase the amount of exhaust from the deposition chamber and reduce the amount of leakage.

[0035] The exhaust volume of the deposition chamber depends on the type and capacity of the vacuum pump, and the length and thickness of the connecting pipes. For example, the shorter and thicker the piping connecting the vacuum pump, the greater the displacement. It is possible.

[0036] In addition, by connecting different types of vacuum pumps in parallel, it is possible to exhaust various types of gases. For example, it is preferable to use a turbo molecular pump and a cryopump connected in parallel. I wish.

[0037] Also, vacuum pumps of the same type can be connected in parallel. For example, two cryopumps can be connected in parallel. When connected in parallel, one unit can be used for regeneration while the other unit is used for exhaust. This method also makes it possible to reduce the downtime of the equipment by regenerating the cryopump. This reduces the processing time and increases productivity. By exhausting the air in a more uniform manner, a higher exhaust capacity can be obtained.

[0038] On the other hand, it is necessary to reduce the amount of leakage from the film formation chamber.

[0039] Leaks in the deposition chamber include internal leaks caused by impurities adsorbed on the interior walls of the deposition chamber and leaks from seals. There is an external leak from the part.

[0040] For example, in order to remove impurities adsorbed on the inner wall of the film-forming chamber, the film-forming chamber is heated and evacuated. By heating the film formation chamber, impurities adsorbed on the inner wall of the film formation chamber can be removed. Since the impurities are desorbed from the wall, they can be efficiently pumped out.

[0041] It is also preferable to perform dummy film formation. Dummy film formation means forming a film on a dummy substrate. In this way, a film is deposited on the dummy substrate and the inner wall of the film formation chamber, and impurities in the film formation chamber and the inner wall of the film formation chamber are detected. The dummy film formation may be performed while the film formation chamber is heated. stomach.

[0042] In addition, in order to remove impurities present in the film formation chamber, an inert gas such as a heated rare gas or The pressure in the deposition chamber is increased by supplying oxygen gas, etc., and the deposition chamber is then opened again after a certain period of time. It is preferable to carry out a process of exhausting the gas. This allows the impurities present in the film formation chamber to be reduced. Repeated treatment is effective. In order to supply gas such as HCl, a gas heating mechanism may be provided in the deposition apparatus itself. By installing a heating mechanism, the piping distance from the gas heating mechanism to the deposition chamber, etc. can be shortened. This allows gas to be supplied to a film-forming chamber or the like while maintaining a high temperature.

[0043] Using this method, the leak rate was reduced to 3 x 10 -5 Pa·m 3 / s or less, preferably 1×10 -5 Pa·m 3 / s or less, more preferably 3 × 10 -6 Pa·m 3 / s or less, More preferably, 1 × 10 -6 Pa·m 3 / s or less, more preferably 3 × 10 -7 Pa m 3 / s or less.

[0044] The leak rate of a gas with a mass-to-charge ratio (m / z) of 28 (such as nitrogen molecules) is 1×1 0 -5 Pa·m 3 / s or less, preferably 3 × 10 -6 Pa·m 3 / s or less.

[0045] The leak rate of gas with m / z=44 (carbon dioxide molecule, etc.) is 3×10 -6 P a·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less.

[0046] The leak rate of gas with m / z=18 (e.g., water molecules) is 1×10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less.

[0047] By using this method, specifically, the pressure in the film formation chamber is reduced to 1×10 -4 Pa or less, preferably is 3 x 10 -5 Pa or less, more preferably 1×10 -5 Pa or less.

[0048] In the deposition chamber described above, an oxide semiconductor film is deposited.

[0049] When the oxide semiconductor film is formed, a surface on which the oxide semiconductor film is to be formed is previously adsorbed. It is preferable to remove impurities.

[0050] Specifically, plasma treatment is performed to remove impurities adsorbed on the surface on which the oxide semiconductor film is to be formed. The plasma treatment and the heat treatment may be performed. In this specification, a reduced pressure atmosphere means a pressure of 10 Pa or less, Pa or less, 1×10 -2 Pa or less, or 1×10 -4 It refers to an atmosphere below Pa.

[0051] After the treatment for removing impurities adsorbed on the surface on which the oxide semiconductor film is to be formed is performed, the impurities are again removed. It is preferable to move the substrate to a deposition chamber for the oxide semiconductor film without exposing it to the air so as not to adsorb any substances.

[0052] Here, the oxide semiconductor film is heated at a substrate heating temperature of 100° C. or higher and 650° C. or lower, preferably 15 The film is preferably formed at a temperature of 0°C or higher and 600°C or lower, more preferably 200°C or higher and 500°C or lower. By setting the substrate heating temperature in the above range, the impurity concentration in the oxide semiconductor film can be reduced. In addition, an oxide semiconductor film with high crystallinity can be easily obtained.

[0053] After the oxide semiconductor film is formed, heat treatment is preferably performed. , in a reduced pressure atmosphere or an oxidizing atmosphere, at 250°C or higher and 650°C or lower, preferably 30 The heat treatment is performed at a temperature of 0° C. or higher and 600° C. or lower. Therefore, the concentration of the oxide can be reduced and an oxide semiconductor film with high crystallinity can be easily obtained.

[0054] A transistor using the oxide semiconductor film formed in the above manner has high reliability and The variation in threshold voltage is also reduced. [Effects of the Invention]

[0055] The impurities such as hydrogen, nitrogen and carbon are reduced, and the carrier density is low and the crystallinity is high. Therefore, a thin oxide semiconductor film can be provided.

[0056] The transistor using the oxide semiconductor film described above has high reliability and small variation in threshold voltage. We can provide you with a GISTA.

[0057] A semiconductor device having the above-mentioned transistor and having high reliability and excellent characteristics can be provided. do. [Brief explanation of the drawings]

[0058] [Figure 1] FIG. 1 is a top view showing an example of a film forming apparatus. [Figure 2]FIG. 2 is a diagram illustrating a film formation chamber and a substrate heating chamber. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 8] 1A and 1B are a top view and a cross-sectional view illustrating an example of a transistor. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating an example of a display device. [Figure 10] 1A to 1C are a cross-sectional view, a circuit diagram, and a diagram showing electrical characteristics of an example of a semiconductor device. [Figure 11] 1A to 1C are a cross-sectional view, a circuit diagram, and a diagram showing electrical characteristics of an example of a semiconductor device. [Figure 12] 1A and 1B are a block diagram and a circuit diagram of a portion thereof showing a specific example of a CPU according to one embodiment of the present invention; [Figure 13] FIG. 10 is a perspective view illustrating an example of an electronic device according to one embodiment of the present invention. [Figure 14] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 15] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 16] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 17] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 18] FIG. 10 is a graph illustrating the Vgs dependence of the field-effect mobility obtained by calculation. [Figure 19] FIG. 10 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Figure 20] FIG. 10 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Figure 21] FIG. 10 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Figure 22] 1A and 1B are a top view and a cross-sectional view of a transistor. [Figure 23] 10 shows the Vgs-Ids characteristics and field-effect mobility of the transistors of Sample 1 and Sample 2. FIG. [Figure 24] 10 is a graph showing Vgs-Ids characteristics of a transistor of Sample 1 before and after a BT test. [Figure 25] 10 is a graph showing Vgs-Ids characteristics of a transistor of Sample 2 before and after a BT test. [Figure 26] 10 shows the relationship between the threshold voltage and the field-effect mobility of the transistor of Sample 2 and the substrate temperature. [Figure 27] 10A and 10B show off-state current of a transistor including an oxide semiconductor film. [Figure 28] 10A and 10B show XRD patterns of an oxide semiconductor film. [Figure 29] FIG. 10 is a graph showing the relationship between the pressure in the film formation chamber and the time elapsed since the vacuum pump was stopped. [Figure 30] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 31] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 32] 10A and 10B show the results of TDS analysis of oxide semiconductor films. [Figure 33] 10A and 10B show SIMS images of an oxide semiconductor film. [Figure 34] 10A and 10B show SIMS images of an oxide semiconductor film. [Figure 35] 10A and 10B show SIMS images of an oxide semiconductor film. [Figure 36] 10A and 10B show XRD results of oxide semiconductor films. [Figure 37] FIG. 10 is a graph showing the relationship between the pressure in the film formation chamber and the time elapsed since the vacuum pump was stopped. [Figure 38] FIG. 4 is a diagram illustrating a method for connecting a gas heating mechanism. [Figure 39] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0059] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. It will be easily understood. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used to indicate the same things. The numbers are used in common across different drawings. When referring to the same thing, the hatch pattern is used. Similarly, there are cases where no particular symbol is attached.

[0060] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of the processes or the order of stacking. Furthermore, in this specification, the specific name is not used as a matter for identifying the invention. It does not indicate a title.

[0061] (Embodiment 1) In this embodiment, a method for forming an oxide semiconductor film containing few impurities and a method for forming the oxide semiconductor film will be described. The transistors used will be explained.

[0062] First, the configuration of a film formation apparatus that minimizes the inclusion of impurities during film formation will be explained using FIG.

[0063] FIG. 1(A) shows a multi-chamber film-forming apparatus. The film-forming apparatus includes a cassette for accommodating substrates. The substrate supply chamber 11 has three feed ports 14, and the load lock chamber 12a and the load lock The heating chamber 12b, the transfer chamber 13, the substrate heating chamber 15, the film forming chamber 10a, the film forming chamber 10b, and the film forming chamber 10c. The substrate supply chamber 11 includes a load lock chamber 12a and a load lock The load lock chamber 12a and the load lock chamber 12b are connected to the transfer chamber 13. The substrate heating chamber 15, the film forming chamber 10a, the film forming chamber 10b, and the film forming chamber 10c are connected to the transfer chamber. It is connected only to chamber 13. Gate valves are provided at the connections between the chambers, and each chamber is independent. Although not shown, the transfer chamber 13 can be equipped with one or more substrate transfer chambers. Here, it is preferable that the substrate heating chamber 15 also serves as a plasma processing chamber. The multi-chamber deposition system does not require the substrate to be exposed to the atmosphere between treatments. It is possible to prevent impurities from adsorbing onto the plate. In addition, the order of film formation and heat treatment can be freely configured. The number of film-forming chambers, load lock chambers and substrate heating chambers can be increased by the above-mentioned number. There are no limitations and it can be determined appropriately according to the installation space and process.

[0064] An example of the film formation chamber (sputtering chamber) shown in FIG. 1(A) will be described with reference to FIG. 2(A). The film forming chamber 10 includes a target 32, a target holder 34 that supports the target, and A substrate holder 42 for supporting a substrate with a substrate heater 44 embedded therein, and a shutter shaft 46 and a shutter plate 48 that can rotate around an axis. The film forming chamber 10 is connected to an RF power supply 50 that supplies power via a matching box 52. A gas supply source 56, a vacuum pump 58 and a vacuum pump 59 are connected via the gas supply source 56 and the vacuum pump 59. Here, the film forming chamber 10, the RF power supply 50, the shutter shaft 46, the shutter plate 48, and The film forming chamber 10, the shutter shaft 46, and the substrate holder 42 are grounded. Either or both of the shutter plate 48 and the substrate holder 42 may be electrically floated.

[0065] In addition, the number of vacuum pumps is not limited to two, namely, vacuum pump 58 and vacuum pump 59, but may be three. For example, if there is another pump connected in series to the vacuum pump 58, One vacuum pump may be provided.

[0066] The vacuum pumps used for the vacuum pumps 58 and 59 include dry pumps. roughing pumps, sputter ion pumps, turbomolecular pumps, and cryopumps It is advisable to combine it with a high vacuum pump such as the turbo molecular pump. It stably exhausts large-diameter gases and requires less frequent maintenance, resulting in excellent productivity. On the other hand, it is known that the pumping ability of hydrogen and water is low. Cryopumps with high pumping capacity for highly reactive atoms and molecules It is effective to combine it with a sputter ion pump that has high pumping capacity for gases and molecules. Alternatively, a vacuum pump in which a cryotrap is connected to a turbomolecular pump may be used. The temperature of the cryotrap refrigerator is set to 100 K or less, preferably 80 K or less. If a cryotrap has multiple refrigerators, changing the temperature of each refrigerator will improve efficiency. For example, the temperature of the first stage refrigerator is set to 100 K or less, The temperature of the second stage refrigerator should be set to 20K or less.

[0067] Since the cryopump is a storage type, it needs to be regenerated periodically. The Lyopump is considered to be less productive because it cannot evacuate while regenerating. To solve this problem, cryopumps are used in Two or more units can be connected in parallel. By connecting two or more cryopumps in parallel, Even if one cryopump is regenerating, the remaining cryopump can be used to pump the gas. Alternatively, a cryopump and a turbomolecular pump may be connected in parallel. For example, a turbo molecular pump is used to evacuate the gas during film formation, and a cryopump is used outside of film formation. By pumping, the frequency of cryopump regeneration can be reduced.

[0068] In addition, a plurality of gas supply sources 56 and refiners 54 may be provided. Depending on the number of deposition chambers, deposition gas supply sources and refiners can be increased. In this case, the flow rate of the film forming gas between each refiner and the film forming chamber 10 is controlled by a Alternatively, a mass flow controller may be provided to control the flow rate of the film forming chamber 10 and the refiner 5. It is also acceptable to connect it to the piping between 4.

[0069] 38, an example of providing a gas heating mechanism between the refiner 54 and the film forming chamber 10 will be described. 38(A) to 38(C) show details of the gas supply source 56 to the film forming chamber 10. Shows.

[0070] FIG. 38(A) shows a configuration in which the film forming chamber 10 and the gas heating mechanism 57 are connected through piping. The structure 57 and the mass flow controller 55 are connected through piping. The filter 55 and the refiner 54 are connected through a pipe, and the refiner 54 and the gas supply source 56 are connected through a pipe. It is a structure in which the connection is made through

[0071] FIG. 38(B) shows a configuration in which the film forming chamber 10 and the mass flow controller 55 are directly connected through piping. The mass flow controller 55 and the gas heating mechanism 57 are connected through piping. The heat mechanism 57 and the refiner 54 are connected through piping, and the refiner 54 and the gas supply source 56 are connected through piping. The structure is connected through a pipe.

[0072] In order to use heated gas, it is necessary to control the gas flow rate accurately even for the heated gas. It is preferable to use a mass flow controller that can control the flow rate.

[0073] FIG. 38(C) shows a case in which the film forming chamber 10 and the gas heating mechanism 57 are connected through piping. The mechanism 57 and the refiner 54 are connected through a pipe, and the refiner 54 and the gas supply source 56 are connected through a pipe. It is a structure that connects through.

[0074] Figure 38(C) shows a configuration without a mass flow controller. Alternatively, a gas flow rate control mechanism different from the gas flow rate control mechanism may be provided. A mechanism for supplying the liquid may be provided.

[0075] The configuration of FIG. 38(C) may be used when there is no need to control the gas flow rate with high precision. Mass flow controllers are relatively expensive and require regular maintenance and replacement. As shown in Figure 38(C), the mass flow controller is not installed. This configuration can reduce the cost of the device.

[0076] For example, in order to reduce impurities in the film-forming chamber 10 using heated gas, which will be described later, The following configuration may also be used.

[0077] The gas supplied to the film forming chamber 10 is heated by the gas heating mechanism 57 to a temperature of 40° C. or higher and 400° C. or lower. Alternatively, it can be heated to 50°C or higher and 200°C or lower.

[0078] Next, the film formation chamber shown in FIG. 2(A) will be described. By providing a magnet inside or below 34, high density plasma can be confined near the target. This method is called magnetron sputtering, and is The deposition rate is high, plasma damage to the substrate is small, and the film quality is good. In the electron sputtering method, if the magnet is rotatable, the bias of the magnetic field can be reduced. This increases the target usage efficiency and reduces the variation in film quality within the substrate surface. It is possible.

[0079] In addition, although an RF power supply was used as the power supply for sputtering here, it is not necessarily limited to an RF power supply. It is not specified, and depending on the application, DC power or AC power may be used, or two or more types of power may be used. The power source may be switchable. When using DC or AC power, A matching box between the target holder and the laser beam is no longer necessary.

[0080] In addition, the substrate holder 42 must be provided with a chuck mechanism for supporting the substrate. The chuck mechanism includes electrostatic chuck and clamping. To improve the uniformity of the substrate, the substrate holder 42 may be provided with a rotation mechanism. A plurality of shutters may be provided to form a film formation chamber capable of forming films on a plurality of substrates at a time. The heater shaft 46, the shutter plate 48, and the substrate heater 44 may not be provided. In FIG. 2(A), the target faces upward and the substrate faces downward. The target faces downward and the substrate faces upward, or the target and substrate face each other sideways. It doesn't matter as a composition.

[0081] The substrate heating chamber 15 may be heated by using, for example, a resistance heating element. Heating may be achieved by thermal conduction or thermal radiation from a medium such as a gas. For example, a GRT A (Gas Rapid Thermal Anneal), LRTA (Lamp Ra RTA (Rapid Thermal Anneal) Anneal) can be used. LRTA is compatible with halogen lamps, metal halide lamps, and lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp The object to be treated is heated by the radiation of light (electromagnetic waves) emitted from a lamp such as a lamp. A is a method of performing a heat treatment using a high-temperature gas, such as an inert gas.

[0082] For example, the substrate heating chamber 15 may have the configuration shown in FIG. The substrate heating chamber 15 includes a substrate holder 42 with an embedded substrate heater 44. The gas supply source 56, the vacuum pump 58 and the vacuum pump 59 are connected via Instead of a heating mechanism using a substrate heater, an LRTA was installed opposite the substrate holder. In this case, a reflector may be provided on the substrate holder 42 to efficiently transfer heat to the substrate. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is , which is connected to an RF power supply 50 via a matching box 52 and is disposed opposite the substrate holder 42. 68 will be established.

[0083] The back pressure of the film forming chamber 10 and the substrate heating chamber 15 is 1×10-4 Pa or less, preferably 3 x10 -5 Pa or less, more preferably 1×10 -5 Pa or less.

[0084] In addition, the partial pressure of the gas with m / z=18 in the film formation chamber 10 and the substrate heating chamber 15 is 3×10 - 5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less is.

[0085] In addition, the partial pressure of the gas with m / z=28 in the film formation chamber 10 and the substrate heating chamber 15 is 3×10 - 5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less is.

[0086] In addition, the partial pressure of the gas with m / z=44 in the film formation chamber 10 and the substrate heating chamber 15 is 3×10 - 5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less is.

[0087] The film-forming chamber 10 and the substrate heating chamber 15 have a leak rate of 3×10 -6 Pa·m 3 / s Less than 1 × 10 -6 Pa·m 3 / s or less.

[0088] In addition, the film forming chamber 10 and the substrate heating chamber 15 have a leak rate of 1.0 m / z=18. x10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m3 / s or less.

[0089] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a leak rate of 1.0 m / z=28. x10 -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less.

[0090] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a leak rate of 3.0 m / z=44 gas. x10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less.

[0091] The leak rate depends on external and internal leaks. External leaks occur due to small holes or seals. An internal leak is when gas flows in from outside the vacuum system due to a valve malfunction or other reasons. This is caused by leaks from valves and other partitions, or by gas released from internal components. In order to keep the above figure or less, it is necessary to take measures against both external and internal leaks. There is.

[0092] For example, it is advisable to seal the opening and closing parts of the deposition chamber with a metal gasket. , using a metal material coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have a higher adhesion than O-rings and can reduce external leakage. In addition, the impurities of metal materials coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using this dynamic action, the release of gas containing impurities from the metal gasket is suppressed, and the internal This can reduce internal leakage.

[0093] The materials that make up the film deposition equipment are aluminum, chromium, Titanium, zirconium, nickel or vanadium is used. Also, the above materials can be used in combination with iron, quartz, or other materials. It may also be used by coating an alloy material containing iron, chromium and nickel. The alloy material containing KEL is rigid, heat-resistant, and suitable for processing. If the surface roughness of the component is reduced by polishing or other methods to reduce the area, the released gas can be reduced. It can be reduced.

[0094] Alternatively, the components of the film forming apparatus may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like. That's fine.

[0095] It is preferable that the members of the film forming apparatus are made of metal materials only, for example, quartz. When installing a viewing window, the surface must be coated with iron fluoride or aluminum oxide to suppress gas emissions. It is recommended to coat it thinly with aluminum or chromium oxide.

[0096] If a gas refiner is installed, the length of the piping from the refiner to the deposition chamber must be 5 m or less. Preferably, it should be 1m or less. By keeping the length of the piping 5m or less or 1m or less, The influence of gas released from these can be reduced depending on the length.

[0097] Furthermore, the inside of the film-forming gas piping is coated with iron fluoride, aluminum oxide, chromium oxide, etc. It is recommended to use metal piping that is covered with a protective film. The above-mentioned piping is, for example, Therefore, the amount of impurities released is small, and the amount of impurities mixed into the deposition gas can be reduced. It is recommended to use high performance ultra-small metal gasket fittings (UPG fittings) for the fittings. By using only metallic materials for the piping, the amount of emitted gas is reduced compared to when resin or other materials are used. This is preferable because it can reduce the influence of noise and external leakage.

[0098] The adsorbed substances present in the film formation chamber do not affect the pressure in the film formation chamber while they are adsorbed. Gas is released when exhausting. Therefore, there is no correlation between leak rate and exhaust speed, but the exhaust capacity Using a high-speed pump, remove as much of the adsorbed matter as possible from the deposition chamber and evacuate it in advance. It is important to keep the temperature within the film formation chamber. The film formation chamber may be heated to promote the desorption of adsorbed substances. Heating can increase the desorption rate of adsorbed substances by about 10 times. At this time, the adsorbed matter is removed while supplying an inert gas. This can further increase the desorption rate of water and other substances that are difficult to desorb by exhausting alone. In addition, by heating the supplied inert gas to the same temperature as the heating temperature of the film formation chamber, the adsorbed matter The desorption rate can be further increased. Here, it is preferable to use a rare gas as the inert gas. Depending on the type of film to be formed, oxygen or the like may be used instead of the inert gas. For example, when forming an oxide film, it is preferable to use oxygen, which is the main component of the oxide. There are also.

[0099] Alternatively, an inert gas such as a heated rare gas or oxygen gas may be supplied to the film formation chamber. It is preferable to increase the pressure inside the film formation chamber and then evacuate the chamber again after a certain period of time has elapsed. By supplying a gas containing the above gas, it becomes easier for adsorbed substances to be desorbed from the film-forming chamber. It is effective to repeat the treatment 2 to 30 times, preferably 5 to 15 times. Specifically, the temperature is 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower. By supplying inert gas or oxygen, the pressure in the deposition chamber can be increased to 0.1 Pa or more. The pressure should be 0 kPa or less, 1 Pa or more but not more than 1 kPa, or 5 Pa or more but not more than 100 Pa. The retention period should be between 1 minute and 300 minutes, or between 5 minutes and 120 minutes. The deposition chamber is evacuated for a period of 5 minutes to 300 minutes, or 10 minutes to 120 minutes.

[0100] Furthermore, the desorption rate of the adsorbed substances can be further increased by forming a dummy film. The substrate is preferably made of a material that emits less gas, for example, the same material as the substrate 100 described later. The dummy film formation may be performed simultaneously with heating of the film formation chamber.

[0101] Figure 1(B) shows a film formation apparatus with a different configuration from that shown in Figure 1(A). chamber 22a, the substrate heating chamber 25, the film forming chamber 20a, the film forming chamber 20b, and the load lock chamber 22 The load lock chamber 22a is connected to the substrate heating chamber 25, and the substrate heating chamber 25 is The film forming chamber 20a is connected to the film forming chamber 20b, and the film forming chamber 20b is connected to the load lock. The connecting parts between the chambers are provided with gate valves, and each chamber is independently connected. The film forming chamber 20a and the film forming chamber 20b can be maintained in a vacuum state by using the vacuum chamber 20a. The film forming chambers 10a, 10b and 10c have the same configuration as those in (A). The plate heating chamber 25 has the same structure as the substrate heating chamber 15 shown in FIG. 1(A). The substrate is transported only in one direction, as indicated by the arrow, and the entrance and exit are different. Unlike multi-chamber film forming equipment, it does not have a transfer chamber, so the installation area can be made smaller. The numbers of film-forming chambers, load-lock chambers, and substrate heating chambers are not limited to the above numbers. For example, the film forming chamber 20b may be It may be omitted, or a second substrate heating chamber or a third film forming chamber connected to the film forming chamber 20b may be provided. It is okay to do so.

[0102] By forming an oxide semiconductor film using the above film formation apparatus, impurities in the oxide semiconductor film can be prevented. Furthermore, by using the above film formation apparatus, a film in contact with the oxide semiconductor film can be formed. By forming the oxide semiconductor film, impurities are prevented from being mixed into the oxide semiconductor film from a film in contact with the oxide semiconductor film. This can suppress the following.

[0103] Next, a method for forming an oxide semiconductor film with low concentrations of hydrogen, nitrogen, and carbon, which are impurities, will be described. explain.

[0104] The oxide semiconductor film is grown at a substrate heating temperature of 100° C. or higher and 600° C. or lower, preferably 150° C. or higher. Film formation is performed in an oxygen gas atmosphere at 550°C or less, more preferably 200°C to 500°C. The thickness of the oxide semiconductor film is 1 nm to 40 nm, preferably 3 nm to 20 nm. The higher the substrate heating temperature during film formation, the lower the impurity concentration of the resulting oxide semiconductor film. In addition, the atomic arrangement in the oxide semiconductor film is well-ordered and highly densified, and the film becomes a polycrystalline film or CAAC-OS films can be easily formed. Furthermore, film formation in an oxygen gas atmosphere also Since no extra atoms such as rare gases are included, polycrystalline or CAAC-OS films are formed. However, a mixed atmosphere of oxygen gas and rare gas may be used, in which case the oxygen gas The proportion of is 30% by volume or more, preferably 50% by volume or more, and more preferably 80% by volume or more. Note that the thinner the oxide semiconductor film, the more the short-channel effect of the transistor is reduced. However, if the thickness is too thin, the influence of interface scattering becomes strong, which may result in a decrease in field-effect mobility. There is a saying.

[0105] The oxide semiconductor film is formed at a deposition pressure of 0.8 Pa or less, preferably 0.4 Pa or less. The distance between the nozzle and the substrate is set to 40 mm or less, preferably 25 mm or less, during film formation. By forming the oxide semiconductor film under such conditions, the sputtered particles and other sputtered particles, gas, or In other words, the frequency of collisions between the target and the ions can be reduced depending on the deposition pressure. The distance between the substrate and the sputtering gas is made smaller than the mean free path of the sputtered particles, gas, or ions. This can reduce impurities that are incorporated into the film.

[0106] For example, the mean free path at a pressure of 0.4 Pa and a temperature of 25°C (absolute temperature of 298 K) The hydrogen molecule (H2) is 48.7 mm, the helium atom (He) is 57.9 mm, and the water molecule ( H2O) is 31.3 mm, ethane molecule (CH4) is 13.2 mm, neon atom (Ne) 42.3mm, nitrogen molecules (N2) 23.2mm, carbon monoxide molecules (CO) 16.0m m, oxygen molecule (O2) 26.4 mm, argon atom (Ar) 28.3 mm, carbon dioxide The elementary molecule (CO2) is 10.9 mm, the krypton atom (Kr) is 13.4 mm, and the xenon atom The electron (Xe) is 9.6 mm. If the pressure is doubled, the mean free path will be halved. Therefore, if the absolute temperature doubles, the mean free path doubles.

[0107] The mean free path is determined by pressure, temperature, and the diameter of the atom or molecule. If is constant, the larger the diameter of the atom or molecule, the shorter the mean free path. The diameter of each atom or molecule is 0.218 nm for H2, 0.200 nm for He, and 0.200 nm for H2O. is 0.272nm, CH4 is 0.419nm, Ne is 0.234nm, N2 is 0.316 nm, CO is 0.380 nm, O2 is 0.296 nm, Ar is 0.286 nm, CO2 is 0.460nm, Kr is 0.415nm, and Xe is 0.491nm.

[0108] Therefore, the larger the diameter of an atom or molecule, the shorter the mean free path and the more electrons in the film. When incorporated, the large diameter of the atoms or molecules inhibits the growth of crystalline regions. Therefore, for example, atoms and molecules with diameters larger than that of Ar are likely to become impurities. do.

[0109] Here, when CO2 is added between the layers of In-Ga-Zn-O crystal, the crystal structure can be maintained. We evaluated the properties of the nuclei by classical molecular dynamics calculations.

[0110] Figure 30 is a schematic diagram of an In-Ga-Zn-O crystal, and CO2 is added to the layer indicated by the arrow in Figure 30. The amount of CO2 added was 0.07% (5%) of the total atoms in the In-Ga-Zn-O crystal. .19×10 19 pieces / cm 3 ), 0.15% (1.04 × 10 20 pieces / cm 3 ), 0.2 2% (1.65 × 10 20 pieces / cm 3 ), 0.30% (2.08 × 10 20 pieces / cm 3 ) , 0.37% (2.60 × 10 20 pieces / cm 3 ), 0.44% (3.11 × 10 20 pieces / cm 3 ), 0.52% (3.63 × 10 20 pieces / cm 3), 0.59% (4.15 × 10 20 pieces / cm 3 ) or 0.67% (4.67 × 10 20 pieces / cm 3 ) as a percentage.

[0111] The calculation was performed using Materials Explorer 5.0 manufactured by Fujitsu Ltd. The temperature is 298K, the pressure is 1 atmosphere, the time step is 0.2fs, and the number of steps is 5 million. did.

[0112] As a result, when the CO2 addition rate was 0.07% to 0.52%, the In-Ga-Zn- The O crystal was maintained, and when the CO2 addition rate was 0.59% to 0.67%, the In-Ga -Zn-O crystals could not be maintained.

[0113] In other words, to obtain In-Ga-Zn-O crystals, all atoms of the In-Ga-Zn-O crystals must be It is clear that the ratio of CO2 to CO2 needs to be 0.52% or less or 0.59% or less.

[0114] Next, a heat treatment is performed. The heat treatment is performed in a reduced pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. The temperature is 250°C or higher and 650°C or lower, preferably 300°C or higher and 600°C or lower. By the heat treatment, the impurity concentration in the oxide semiconductor film can be reduced. The oxidizing atmosphere is oxygen, ozone, nitrous oxide, etc. The atmosphere contains 10 ppm or more of oxidizing gases such as oxygen.

[0115] As the heat treatment mentioned above, after heat treatment in a reduced pressure atmosphere or an inert atmosphere, the temperature is maintained. It is preferable to switch to an oxidizing atmosphere while maintaining the temperature, and then further heat treatment. When heat treatment is performed in a nitrogen or inert atmosphere, the impurity concentration in the oxide semiconductor film is reduced. However, oxygen vacancies are also generated at the same time. The amount of oxidation can be reduced by heat treatment in an oxidizing atmosphere.

[0116] The oxide semiconductor film is heated by heating the substrate during film formation and by heat treatment after film formation. It is possible to reduce the concentration of impurities.

[0117] By using the above-described film formation apparatus, an oxide semiconductor film with few impurities can be obtained. An oxide semiconductor film containing few impurities has a low carrier density and high crystallinity. It has excellent semiconductor properties, and therefore, when used in transistors, it is highly reliable. can be done.

[0118] Specifically, the hydrogen concentration in the oxide semiconductor film was measured by SIMS to be 5×10 19 atom s / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1× 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Below Below.

[0119] The nitrogen concentration in the oxide semiconductor film was measured by SIMS. 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5 × 10, more preferably17 atoms / cm 3 The following do.

[0120] The carbon concentration in the oxide semiconductor film was measured by SIMS. 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following do.

[0121] In addition, the oxide semiconductor film was analyzed by thermal desorption spectroscopy (TDS). Gas with m / z=2 (e.g., hydrogen molecule) analyzed by ion spectroscopy Gas with m / z=18, gas with m / z=28 and gas with m / z=44 The amount of emission is 1×10 19 pieces / cm 3 Less than 1 × 10 18 pieces / cm 3 Below Below.

[0122] For the method of measuring the amount of released oxygen atoms using TDS analysis, see the section on measuring the amount of released oxygen atoms below. Please refer to the established method.

[0123] Next, a transistor using an oxide semiconductor film formed using the above-described film formation apparatus will be described. 3 to 8 will be used to explain this.

[0124] The transistors shown in FIGS. 3 to 6 have excellent productivity due to the small number of photolithography steps. The transistors shown in FIGS. 3 to 6 are used in display devices with relatively large transistor sizes. It is often used in places such as

[0125] First, the structure of the transistor shown in Figure 3 will be described. Figure 3(A) shows the structure of the transistor. 3(B) is a cross-sectional view corresponding to the dashed line AB shown in FIG.

[0126] The transistor shown in FIG. 3B includes a base insulating film 102 provided over a substrate 100 and a base insulating film 103 provided over a substrate 100. an oxide semiconductor film 106 provided over the insulating film 102; a pair of electrodes 116 provided in contact with at least a portion of the oxide semiconductor film 106; A gate insulating film 112 is provided to cover the semiconductor film 106 and the pair of electrodes 116. a gate electrode 104 provided to overlap with the oxide semiconductor film 106 with the insulating film 112 interposed therebetween; , has.

[0127] Here, the oxide semiconductor film 106 is an oxide semiconductor film having a low impurity concentration, which is described in this embodiment. A membrane may be applied.

[0128] The oxide semiconductor film 106 has a thickness of 1 nm to 50 nm. In particular, for transistors with a channel length of 30 nm or less, By setting the thickness of the compound semiconductor film 106 to about 5 nm, the short channel effect can be suppressed and a stable It has excellent electrical properties.

[0129] The oxide semiconductor film 106 preferably contains at least In and Zn. The compound semiconductor film 106 contains In and Zn, as well as other elements that reduce the variation in the electrical characteristics of the transistor. It is preferable to include Ga, Sn, Hf or Al to reduce the resistance.

[0130] Alternatively, the oxide semiconductor film 106 may contain, in addition to In and Zn, a material that improves the electrical characteristics of the transistor. To reduce variability, lanthanides La, Ce, Pr, Nd, Sm, Eu, and G may contain one or more elements selected from the group consisting of d, Tb, Dy, Ho, Er, Tm, Yb and Lu. stomach.

[0131] The oxide semiconductor film 106 is made of, for example, an In—Zn—O-based material, which is an oxide of a binary metal. , Sn-Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O based materials, Sn-Mg- O-based materials, In-Mg-O-based materials, In-Ga-O-based materials, and ternary metal oxides n-Ga-Zn-O based materials, In-Al-Zn-O based materials, In-Sn-Zn-O based materials , Sn-Ga-Zn-O based materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials Materials, In-Hf-Zn-O based materials, In-La-Zn-O based materials, In-Ce-Zn- O-based materials, In-Pr-Zn-O-based materials, In-Nd-Zn-O-based materials, In-Sm-Z nO-based materials, In-Eu-Zn-O-based materials, In-Gd-Zn-O-based materials, In-Tb -Zn-O based materials, In-Dy-Zn-O based materials, In-Ho-Zn-O based materials, In- Er-Zn-O based materials, In-Tm-Zn-O based materials, In-Yb-Zn-O based materials, I n-Lu-Zn-O system materials, and In-Sn-Ga-Zn-O system materials, which are oxides of quaternary metals materials, In-Hf-Ga-Zn-O materials, In-Al-Ga-Zn-O materials, In-S n-Al-Zn-O material, In-Sn-Hf-Zn-O material, In-Hf-Al-Z nO-based materials can be used.

[0132] For example, an In-Ga-Zn-O-based material is a material having In, Ga, and Zn as its main components. It means oxide, and the ratio of In, Ga, and Zn does not matter.

[0133] For example, transistors using In-Sn-Zn-O materials can easily achieve high field efficiency. Specifically, the field effect mobility of the transistor is 31 cm 2 / Vs or later Top, 40cm 2 / Vs or more, 60cm 2 / Vs or more, 80cm 2 / Vs or more or 100 cm 2 / Vs or more. Note that materials other than In-Sn-Zn-O based materials (e.g. Even in the case of In-Ga-Zn-O-based materials, the field-effect mobility can be increased by reducing the defect density. It can be done.

[0134] When an In—Zn—O-based material is used for the oxide semiconductor film 106, the atomic ratio is In / Z n=0.5 or more and 50 or less, preferably In / Zn=1 or more and 20 or less, more preferably I n / Zn = 1.5 to 15. By setting the atomic ratio of Zn in the above range, The field effect mobility of the transistor can be improved. When Zn:O=X:Y:Z, it is preferable that Z>1.5X+Y.

[0135] The oxide semiconductor film 106 is formed of a material having the chemical formula InMO3(ZnO) m Material expressed as (m>0) Here, M is selected from Zn, Ga, Al, Mn, Sn, Hf and Co. represents one or more selected metal elements. For example, M may be Ga, Ga and Al, Alternatively, Ga and Mn or Ga and Co may be used.

[0136] The oxide semiconductor film 106 has a band gap of 2 A material having a refractive index of 0.5 eV or more, preferably 2.8 eV or more, and more preferably 3.0 eV or more is selected. Select.

[0137] Note that alkali metals, alkaline earth metals, and the like are reduced in the oxide semiconductor film 106. The oxide semiconductor film 106 preferably has an extremely low impurity concentration. When the above-mentioned impurities are present, recombination occurs within the band gap due to the levels formed by the impurities. As a result, the off-state current of the transistor increases.

[0138] The alkali metal concentration in the oxide semiconductor film 106 was measured by SIMS. Degrees are 5 x 10 16 atoms / cm 3 Less than 1 × 10 16 atoms / cm 3 or less, more preferably 1 × 10 15 atoms / cm 3 Similarly, lithium The concentration is 5 x 10 15 atoms / cm 3 Less than 1 × 10 15 atoms / c m 3 Similarly, the potassium concentration is 5 x 10 15 atoms / cm 3 Below, I prefer Or 1 x 10 15 atoms / cm 3 The following applies.

[0139] The off-state current of the transistor can be reduced by using the oxide semiconductor film 106 described above. Specifically, for example, when the channel length is 3 μm and the channel width is 1 μm, The off-state current of the -18 Below A, 1×10-21 A or less, or 1 x 10 -24 A It can be as follows:

[0140] The oxide semiconductor film 106 is non-single-crystal. In particular, it is preferable that the oxide semiconductor film 106 has crystallinity. For example, A crystalline film or a CAAC-OS film is used.

[0141] An example of a crystal structure contained in a CAAC-OS film will be described in detail with reference to FIGS. 14 to 17. 14 to 17, the upward direction is the c-axis direction, and The plane perpendicular to the direction is the ab plane. When simply referring to the upper half and the lower half, the ab plane is used as the boundary. In Figure 14, the circled O represents a tetrahedral O. The double circled O indicates a three-coordinate O.

[0142] Figure 14(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as 4) adjacent to the In atom. The structure shown has a metal atom and a nearby oxygen atom. The structure shown in Figure 14(A) is an octahedral structure, but it can be easily For simplicity, the structure is shown in a plan view. There are three O atoms in each group, each with four coordinates. The small group shown in Figure 14(A) has a zero charge.

[0143] Figure 14(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom. The structure shown has a tetracoordinated O atom and two tetracoordinated O atoms adjacent to Ga. Both exist on the ab plane. There is one each in the upper and lower halves of Figure 14(B). In addition, since In also has a five-coordinate structure, it can take the structure shown in Figure 14(B). The small group shown in FIG. 14(B) has a charge of 0.

[0144] FIG. 14(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 14(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in Figure 14(C), there are three 4-coordinate O atoms in the upper half and one 4-coordinate O atom in the lower half. There may be four-coordinated O. The small group shown in Figure 14(C) has a zero charge.

[0145] FIG. 14(D) shows a structure having one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 14(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 14(D) has a charge of +1.

[0146] Figure 14(E) shows a small group containing two Zn atoms. The upper half of Figure 14(E) shows a small group containing one Zn atom. The small group shown in Figure 14(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0147] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0148] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In have three neighboring In atoms downward, and the three O atoms in the lower half Each O has three adjacent In atoms in the upward direction. Each O in the upper half has one adjacent Ga in the downward direction, and each O in the lower half has one adjacent Ga in the upward direction. The O atom in the upper half of the 4-coordinate Zn shown in Figure 14(C) has one adjacent Ga atom. The three O's in the lower half each have three neighboring Zn's in the upward direction. Similarly, the number of tetrahedral O atoms above a metal atom and the number of neighboring metal atoms below that O are Similarly, the number of tetrahedral O atoms below the metal atom and the number of adjacent metal atoms above the O atoms are The number of atoms is equal. Since O is tetracoordinated, the number of neighboring metal atoms below is equal to the number of neighboring metal atoms above. The sum of the number of contact metal atoms is 4. Therefore, the number of tetrahedral O atoms above the metal atoms is When the sum of the number of tetracoordinated O atoms below another metal atom is 4, Small groups of species can bond together. For example, six-coordinated metal atoms (In or S) n) is bonded through the tetracoordinate O in the lower half, there are three tetracoordinate O, so It bonds to either a metal atom with a coordinated coordinate (Ga or In) or a metal atom with a coordinated coordinate (Zn) This will happen.

[0149] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinated oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0150] Figure 15(A) shows a model of the middle group that constitutes the layer structure of the In-Sn-Zn-O material. Figure 15(B) shows a large group consisting of three medium groups. 5(C) shows the atomic arrangement when the layer structure of FIG. 15(B) is observed from the c-axis direction.

[0151] In FIG. 15(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the circle indicates that there are three tetrahedral O atoms in the upper and lower halves of Sn. Similarly, in FIG. 15(A), the upper and lower halves of In are Each has one tetracoordinate O atom, which is shown as a circled 1. Similarly, in Figure 15 In (A), there is one tetracoordinate O in the bottom half and three tetracoordinate O in the top half. Zn with one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. This shows that:

[0152] In FIG. 15(A), the middle group that constitutes the layer structure of the In-Sn-Zn-O based material is From the top, Sn has three tetrahedral O atoms in the upper half and three in the lower half, and Sn has one tetrahedral O atom in each half. The In atoms bond to the In atoms in the upper and lower halves of the molecule, and the In atoms bond to the In atoms in the upper half of the molecule. It bonds to the Zn, and three tetracoordinate O atoms are attached to the top via one tetracoordinate O atom in the lower half of the Zn. In is bonded to the In in the upper and lower halves, and the In is bonded to the Z It bonds to a small group consisting of n2 atoms, and through one tetracoordinate O in the lower half of this small group. The structure is such that three tetracoordinated O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple medium groups combine to form large groups.

[0153] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6 67, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, the layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. The structure that takes on a charge of -1 is as follows: As shown in Figure 14(E), there is a small group containing two Zn atoms. For example, Sn If there is one small group containing two Zn atoms for every one containing one Zn atom, the charges will cancel out. Therefore, the total charge of the layer structure can be set to zero.

[0154] Specifically, the large group shown in Figure 15(B) is repeated to form In-Sn-Zn -O-based material crystals (In2SnZn3O8) can be obtained. The layer structure of the Sn-Zn-O material is In2SnZnO6(ZnO) m (m is a natural number.) It can be expressed by the following composition formula:

[0155] In addition to these, there are also other materials such as In-Sn-Ga-Zn-O, which are oxides of quaternary metals, Ternary metal oxides, such as In-Ga-Zn-O and In-Al-Zn-O materials, Sn-Ga-Zn-O based materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials materials, In-Hf-Zn-O based materials, In-La-Zn-O based materials, In-Ce-Zn- O-based materials, In-Pr-Zn-O-based materials, In-Nd-Zn-O-based materials, In-Sm-Z nO-based materials, In-Eu-Zn-O-based materials, In-Gd-Zn-O-based materials, In-Tb -Zn-O based materials, In-Dy-Zn-O based materials, In-Ho-Zn-O based materials, In- Er-Zn-O based materials, In-Tm-Zn-O based materials, In-Yb-Zn-O based materials, I n-Lu-Zn-O based materials, In-Zn-O based materials, which are binary metal oxides, Sn- Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O based materials, Sn-Mg-O based materials The same applies to the case where an In-Mg-O based material or an In-Ga-O based material is used.

[0156] For example, in Figure 16(A), the layer structure of the In-Ga-Zn-O material is shown. A model diagram is shown.

[0157] In FIG. 16(A), the middle group, which is made up of a layer structure of In-Ga-Zn-O-based materials, From the top, In has three tetrahedral O atoms in the upper half and three in the lower half, and one tetrahedral O atom on top. It bonds to the Zn in the bottom half, and the tetracoordinate O is bonded to the Zn via the three tetracoordinate O atoms in the bottom half. One Ga atom is bonded to the upper half and one to the lower half, and one tetracoordinate O atom is bonded to the lower half of the Ga atom. The structure is such that three tetracoordinate O atoms are bonded to the In atoms in the upper and lower halves via the Multiple medium groups combine to form large groups.

[0158] Figure 16(B) shows a large group consisting of three medium groups. 16(B) shows the atomic arrangement when the layer structure of FIG. 16(B) is observed from the c-axis direction.

[0159] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are Since the valence numbers are +3, +2, and +3 respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge is always 0.

[0160] The middle group, which is made up of the layer structure of In-Ga-Zn-O based materials, is shown in Figure 16(A). The combination of middle groups with different arrangements of In, Ga, and Zn is not limited to the same middle group. Large groups are also possible.

[0161] Specifically, the large group shown in Figure 16(B) is repeated to form In-Ga-Zn The crystals of the In-Ga-Zn-O based material can be obtained. The structure is InGaO3(ZnO) n (n is a natural number.)

[0162] In the case of n=1 (InGaZnO4), for example, the crystal structure shown in FIG. 17(A) can be obtained. In the crystal structure shown in FIG. 17(A), as explained in FIG. 14(B), Ga and Since Ga and In are pentacoordinated, structures in which Ga is replaced by In are also possible.

[0163] In the case of n=2 (InGaZn2O5), for example, the crystal structure shown in FIG. 17(B) In the crystal structure shown in FIG. 17(B), as explained in FIG. 14(B), Since Ga and In are five-coordinate, a structure in which Ga is replaced by In is also possible.

[0164] Here, in the large group of InGaZnO4 shown in FIG. 16(B), carbon atoms (C) The change in the crystalline state when one cation is introduced was evaluated using first-principles calculations.

[0165] The calculations were carried out using the first-principles calculation software CASTEP manufactured by Accelrys. The pseudopotential was ultrasoft, and the cutoff energy was 300 eV. .

[0166] FIG. 31(A) shows the position where C is introduced into the InGaZnO4 large group. 31(B) shows the structure of the InGaZnO4 large group after introducing C and optimizing the structure. It is in a crystalline state.

[0167] As shown in Figure 31(B), when C is introduced, C bonds with O and the originally bonded Ga The distance between the O atoms has increased.

[0168] In other words, it was found that the presence of C in In-Ga-Zn-O based materials makes it difficult to maintain the crystal structure. Light.

[0169] Next, in the large group of InGaZnO4, one carbon dioxide molecule (CO2) was introduced. The change in the crystalline state when the SiO2 solution was added was evaluated using first-principles calculations.

[0170] The calculations were carried out using the first-principles calculation software CASTEP manufactured by Accelrys. The pseudopotential was ultrasoft, and the cutoff energy was 300 eV. .

[0171] FIG. 39(A) shows the position where CO2 is introduced in the large group of InGaZnO4. The crystalline states of Figures 39(B), 39(C) and 39(D) are InGaZn In the large group of O4, the optimum structure when CO2 is introduced at the position shown in Figure 39(A) Here, Figure 39(D) is closest to the optimal structure, followed by Figure 39(E). (C) and Figure 39(B) are closer to the optimal structure.

[0172] In Figure 39(B), CO2 replaces part of the InGaZnO4 large group. Then, as shown in Figure 39(C), the spacing between the InGaZnO4 layers expands near CO2, and then As shown in FIG. 39(D), CO2 separates and the spaces between the InGaZnO4 layers expand. He said.

[0173] In other words, if CO2 is present in In-Ga-Zn-O based materials, it becomes difficult to maintain the crystalline structure. You can see that.

[0174] Hereinafter, oxide semiconductors usable for transistors in a semiconductor device according to one embodiment of the present invention will be described. The crystalline state of the body membrane will now be described.

[0175] To evaluate the crystalline state, X-ray diffraction (XRD) of the oxide semiconductor film was performed. The XRD analysis was performed using an X-ray diffraction (XRD) system manufactured by Bruker AXS. Measurement was carried out using the D8 ADVANCE instrument by the out-of-plane method.

[0176] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0177] First, a dehydrogenated quartz substrate was prepared.

[0178] Next, an In-Sn-Zn-O film was formed on the quartz substrate to a thickness of 100 nm.

[0179] The In-Sn-Zn-O film was formed by sputtering in an oxygen gas atmosphere at a power of 100 The film was formed as W(DC). The target was In:Sn:Zn=1:1:1 [atomic ratio] The substrate heating temperature during film formation was room temperature (heating The temperature was either 200°C or 300°C. The sample thus prepared was designated as Sample A.

[0180] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen gas atmosphere for one hour, and then in an oxygen gas atmosphere without lowering the temperature. The sample was then heated for another hour in the atmosphere. did.

[0181] Figure 28 shows the XRD results for sample A and sample B. In sample A, peaks derived from crystals were observed. However, in sample B, 2θ was around 35 deg and 37 deg to 38 deg. A peak derived from the crystal was observed.

[0182] That is, by performing heat treatment on the sample at a temperature of 650° C., a crystalline oxide semiconductor film was obtained. It can be seen that

[0183] There are no major limitations on the substrate 100, but it should at least have heat resistance to the extent that it can withstand subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, sapphire substrates A plate or the like may be used as the substrate 100. Also, single crystals such as silicon and silicon carbide may be used. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates can also be applied. It is preferable to use any of these substrates on which semiconductor elements are provided as the substrate 100 .

[0184] A flexible substrate may also be used as the substrate 100. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 100. A release layer may be provided between the non-flexible substrate and the transistor.

[0185] The base insulating film 102 is made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon oxide. Aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, iridium oxide tritium oxide, lanthanum oxide, cesium oxide, tantalum oxide, and magnesium oxide The above may be selected and used as a single layer or a laminate.

[0186] It is preferable that the base insulating film 102 has sufficient flatness. Specifically, the average surface roughness (R a) is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. By setting Ra to the above-mentioned value or less, the oxide semiconductor film 10 The crystal region is easily formed in the region 6. Ra is defined in JIS B0601. It is a three-dimensional extension of the centerline average roughness that can be applied to surfaces. It can be expressed as "the average of the absolute values ​​of the deviations from the specified surface to the target surface" and is defined by Equation 1.

[0187]

number

[0188] In Equation 1, S0 is the measurement plane (coordinates (x1, y1) (x1, y2) (x2, y 1) The area of ​​the rectangular region defined by the four points (x2, y2), and Z0 is the average of the measurement surface. Ra refers to the height measured by an atomic force microscope (AFM). It can be evaluated using the cope.

[0189] Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or more and 15 atomic % or less , silicon is in the range of 25 atomic % to 35 atomic % and hydrogen is in the range of 0 atomic % to 10 atomic % Silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. For example, oxygen is 5 atomic % or more and 30 atomic % or less, and nitrogen is 20 atomic % or more and 55 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 10 atomic % or more and 25 atomic % or less. However, the above range is based on the Rutherford method. Rutherford Backscattering Spectroscopy (RBS) rometry) and Hydrogen Forward Scattering (HFS) This is measured using Scattering Spectrometry (SCST). The composition of the constituent elements has a value in which the total does not exceed 100 atomic %.

[0190] The base insulating film 102 is preferably an insulating film that releases oxygen by heat treatment.

[0191] "Oxygen is released by heat treatment" means that the amount of oxygen converted to oxygen atoms in TDS analysis is The emission amount is 1.0×10 18 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 This means that the above is the case.

[0192] Here, the method for measuring the amount of released oxygen using TDS analysis will be explained below.

[0193] The total amount of released gas during TDS analysis is proportional to the integral value of the ion intensity of the released gas. The total amount of released gas can then be calculated by comparing this integral value with that of a standard sample.

[0194] For example, the TDS analysis results of a silicon wafer containing a specified density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) is calculated using Equation 2. Here, all of the gases detected at mass number 32 obtained by TDS analysis are acids. It is assumed to be derived from an elementary molecule. There is another molecule with a mass number of 32, CH3OH, but it may exist. The possibility is low and is not considered here. The abundance ratio of oxygen atoms and oxygen molecules containing oxygen atoms with mass number 18 in nature is The rate is so small that it is not taken into consideration.

[0195]

number

[0196] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the insulating film is analyzed by TDS. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released from the insulating film is determined by the electron A thermal desorption analyzer EMD-WA1000S / W manufactured by Kagaku Co., Ltd. was used as a standard sample. 1×10 16 atoms / cm 3 The measurements were carried out using a silicon wafer containing hydrogen atoms.

[0197] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0198] In addition, NO2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0199] In the above structure, the film that releases oxygen by heat treatment is silicon oxide (S iO X (X>2)) or silicon oxide (SiO X (X>2) It means that the number of oxygen atoms per unit volume is more than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per volume was measured by Rutherford backscattering spectroscopy. This is the value.

[0200] Oxygen is supplied from the base insulating film 102 to the oxide semiconductor film 106, The interface state density between the insulating film 106 and the underlying insulating film 102 can be reduced. Due to the action of the oxide semiconductor film 106, carriers are trapped at the interface between the oxide semiconductor film 106 and the base insulating film 102. This can prevent the transistor from being damaged, thereby providing a highly reliable transistor.

[0201] Furthermore, charge may be generated due to oxygen vacancies in the oxide semiconductor film 106. The oxygen vacancies in the compound semiconductor film 106 act as donors and emit electrons as carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. The insulating film 102 supplies oxygen sufficiently to the oxide semiconductor film 106, and the oxide semiconductor film 106 is preferably The excessive oxygen content in the conductive film 106 causes the threshold voltage to shift in the negative direction. This can reduce oxygen vacancies in the oxide semiconductor film 106, which are a cause of the diffusion.

[0202] The excess oxygen is mainly oxygen present between the lattices of the oxide semiconductor film 106, and the oxygen concentration is 1 x10 16 atoms / cm 3 Over 2×10 20 atoms / cm 3 The range is as follows: By setting the concentration of oxygen present between lattices of the oxide semiconductor film 106 within the above range, the crystal is not distorted. This is preferable because it does not cause cracks or the like and does not cause the crystal regions to collapse.

[0203] The pair of electrodes 116 is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, T and W, and their nitrides, oxides and alloys, in a single layer or laminated form. Alternatively, an oxide or oxynitride containing at least In and Zn may be used. For example, an In-Ga-Zn-ON material may be used.

[0204] The gate insulating film 112 is formed by the same method and with the same material as the base insulating film 102. That's fine.

[0205] The gate electrode 104 is formed by the same method and with the same material as the pair of electrodes 116. That's fine.

[0206] Next, the structure of the transistor shown in FIG. 4 will be described. 4(B) is a cross-sectional view corresponding to the dashed dotted line AB shown in FIG.

[0207] The transistor shown in FIG. 4B includes a base insulating film 102 provided over a substrate 100 and a base insulating film 103 provided over a substrate 100. A pair of electrodes 216 provided on the insulating film 102, and a pair of electrodes 216 The oxide semiconductor film 2 is provided in contact with at least a portion of the electrode 216 and the base insulating film 102. 06, and a gate insulating film provided to cover the pair of electrodes 216 and the oxide semiconductor film 206. 212, a gate insulating film 212 provided to overlap with the oxide semiconductor film 206 with the gate insulating film 212 interposed therebetween. and a ground electrode 204.

[0208] The pair of electrodes 216, the oxide semiconductor film 206, the gate insulating film 212, and the gate electrode 204 are the pair of electrodes 116, the oxide semiconductor film 106, the gate insulating film 112, and the The insulating film 104 may be formed by the same method and using the same material as the gate electrode 104.

[0209] Next, the structure of the transistor shown in FIG. 5 will be described. 5(B) is a cross-sectional view corresponding to the dashed dotted line AB shown in FIG.

[0210] The transistor shown in FIG. 5B includes a gate electrode 304 provided over the substrate 100 and a gate A gate insulating film 312 is provided to cover the gate electrode 304, and a gate insulating film 312 is provided to cover the gate electrode 304. an oxide semiconductor film 306 provided to overlap with the gate electrode 304; a pair of electrodes 316 provided in contact with at least a part of the oxide semiconductor film 306; The oxide semiconductor film 306 and the pair of electrodes 316 are covered with a protective insulating film 3 It is preferable to provide 18.

[0211] The pair of electrodes 316, the oxide semiconductor film 306, the gate insulating film 312, and the gate electrode 304 are the pair of electrodes 116, the oxide semiconductor film 106, the gate insulating film 112, and the The insulating film 104 may be formed by the same method and using the same material as the gate electrode 104.

[0212] The protective insulating film 318 is formed by the same method and using the same material as the base insulating film 102. That's fine.

[0213] Next, the structure of the transistor shown in FIG. 6 will be described. 6(B) is a cross-sectional view corresponding to the dashed dotted line AB shown in FIG.

[0214] The transistor shown in FIG. 6B includes a gate electrode 304 provided over the substrate 100 and a gate A gate insulating film 312 is provided to cover the gate electrode 304, and a A pair of electrodes 416 and a gate insulator are provided on the pair of electrodes 416. and an oxide semiconductor film 406 at least partly in contact with the insulating film 312. In addition, when a protective insulating film 418 is provided to cover the pair of electrodes 416 and the oxide semiconductor film 406, preferable.

[0215] Note that the pair of electrodes 416, the oxide semiconductor film 406, and the protective insulating film 418 are each formed in the same The pair of electrodes 116, the oxide semiconductor film 106, and the protective insulating film 318 are formed in the same manner and in the same manner. The material may be used.

[0216] The transistors shown in FIGS. 7 and 8 are more efficient than the transistors shown in FIGS. Although the process is somewhat complicated, it has excellent properties due to its small parasitic capacitance and the fact that short channel effects are unlikely to occur. This structure is suitable for fine transistors that require specific electrical characteristics.

[0217] Next, the structure of the transistor shown in FIG. 7 will be described. 7(B) is a cross-sectional view corresponding to the dashed dotted line AB shown in FIG.

[0218] The transistor shown in FIG. 7B includes a base insulating film 502 provided over the substrate 100 and a base insulating film 503 provided over the substrate 100. A protective film 520 provided around the insulating film 502, and a base insulating film 502 and the protective film 520 an oxide semiconductor film 5 including a high-resistance region 506a and a low-resistance region 506b provided thereon; 506, a gate insulating film 512 provided over the oxide semiconductor film 506, and a gate insulating film 51 a gate electrode 504 overlapping with the oxide semiconductor film 506 with the gate electrode 2 interposed therebetween; a sidewall insulating film 524 provided in contact with a side surface of the oxide semiconductor film 504; a pair of electrodes 516 provided in contact with at least a portion of the oxide semiconductor film 506; A protective insulating film is formed to cover the gate electrode 504, the sidewall insulating film 524, and the pair of electrodes 516. It is preferable to provide a protective insulating film 518. It is preferable to provide a wiring 522 in contact with the pair of electrodes 516 .

[0219] The pair of electrodes 516, the gate insulating film 512, the protective insulating film 518, and the gate electrode 50 4 respectively include a pair of electrodes 116, a gate insulating film 112, a protective insulating film 318, and a gate The electrode 104 may be provided using the same method and material as the electrode 104 .

[0220] The oxide semiconductor film 506 is formed by using the gate electrode 504 as a mask and the gate insulating film 512 impurities having a function of reducing the resistance of the oxide semiconductor film are added through the high-resistance region 5 The impurity may be phosphorus. After the addition of impurities, the temperature is increased to 250°C or higher and 650°C or lower. It is preferable to perform the heat treatment at a temperature of 1000. When the impurity is added by ion implantation, Compared with the case where hydrogen is added by ion doping, the amount of hydrogen mixed into the oxide semiconductor film is small. However, this does not exclude the ion doping method.

[0221] The oxide semiconductor film 506 is formed by using the gate electrode 504 and the sidewall insulating film 524 as a mask. The gate insulating film 512 is formed of an impurity having a function of reducing the resistance of the oxide semiconductor film. may be added to form the high resistance region 506a and the low resistance region 506b. In this case, the region overlapping with the sidewall insulating film 524 is not the low resistance region 506b but the high resistance region 506c. 506a (see FIG. 7(C)).

[0222] Note that by adding impurities through the gate insulating film 512, the oxide semiconductor film 506 However, the damage caused by adding impurities to the gate insulating film can be reduced. Impurities may be injected without going through 512.

[0223] The base insulating film 502 is formed by the same method and using the same material as the base insulating film 102. The insulating film may be processed to provide a groove.

[0224] The protective film 520 is formed by depositing an insulating film so as to fill the grooves formed in the base insulating film 502. Then, chemical mechanical polishing (CMP) is performed. The thin film may be formed by a thin film shaping process.

[0225] The protective film 520 may be silicon oxynitride, silicon nitride, aluminum oxide, or aluminum nitride. , hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cesium oxide One or more of aluminum, tantalum oxide and magnesium oxide are selected and used in a single layer or laminated layer. That's fine.

[0226] The protective film 520 is heated at a temperature of 250°C or higher and 450°C or lower, preferably 150°C or higher and 800°C or lower. It is preferable that the film has a property of not allowing oxygen to pass through even after heat treatment for, for example, one hour in a temperature range. I wish.

[0227] Due to the above-mentioned properties, when the protective film 520 is provided around the base insulating film 502, In this case, oxygen released from the base insulating film 502 by heat treatment flows out of the transistor. In this way, oxygen is held in the base insulating film 502, , preventing a decrease in the field effect mobility of the transistor and reducing the variation in the threshold voltage; Furthermore, reliability can be improved.

[0228] However, a structure in which the protective film 520 is not provided may also be adopted.

[0229] The sidewall insulating film 524 is formed by providing an insulating film covering the gate electrode 504 and then etching the insulating film. The sidewall insulation is formed by etching. Highly anisotropic etching is used. The film 524 is formed in a self-aligned manner by performing a highly anisotropic etching process on the insulating film. For example, it is preferable to use a dry etching method. The etching gases used are, for example, trifluoromethane, octafluorocyclobutane, Examples of etching gases include fluorine-containing gases such as fluorine, tetrafluoromethane, etc. A rare gas or hydrogen may be added. Dry etching is a method of applying a high frequency voltage to a substrate. It is preferable to use a reactive ion etching method (RIE method).

[0230] The wiring 522 may be provided by the same method and using the same material as the gate electrode 104. good.

[0231] Next, the structure of the transistor shown in FIG. 8 will be described. 8(B) is a cross-sectional view corresponding to the dashed dotted line AB shown in FIG.

[0232] The transistor shown in FIG. 8B includes a base insulating film 602 provided over the substrate 100 and a base insulating film 603 provided over the substrate 100. A pair of electrodes 616 provided in the grooves of the insulating film 602, and a pair of electrodes 616 and a base insulating film 602 are formed on the insulating film 602. An oxide semiconductor having a high resistance region 606a and a low resistance region 606b formed on the electrode 616. A conductive film 606, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate insulating film a gate electrode 604 overlapping with the oxide semiconductor film 606 with an insulating film 612 interposed therebetween; A protective insulating film 618 is formed to cover the gate insulating film 612 and the gate electrode 604. In addition, the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film It is preferable to provide wiring 622 in contact with the pair of electrodes 616 through openings provided in 606. It's nice.

[0233] Note that the gate insulating film 612, the protective insulating film 618, the oxide semiconductor film 606, the wiring 622, and the The gate electrode 604 is formed of the gate insulating film 112, the protective insulating film 318, and the oxide semiconductor The film 506, the wiring 522 and the gate electrode 104 are constructed using the same method and materials. That's fine.

[0234] The base insulating film 602 is formed by the same method and using the same material as the base insulating film 102. The insulating film may be processed to provide a groove.

[0235] The pair of electrodes 616 are made of a conductive film so as to fill the grooves formed in the base insulating film 602. The insulating film may be formed by forming a film and then performing CMP processing.

[0236] The field-effect mobility of a transistor will be described below with reference to FIGS.

[0237] The field-effect mobility of transistors, not limited to oxide semiconductors, is often lower than originally intended for various reasons. The measured field-effect mobility is lower than the expected field-effect mobility. These include defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using the Vinson model, the field effect mobility assuming there are no defects inside the semiconductor is calculated as follows: Derived theoretically.

[0238] Let μ0 be the field-effect mobility of the original transistor, and let us consider the existence of some potential barrier in the semiconductor. The measured field-effect mobility μ when assuming the existence of (grain boundaries, etc.) is expressed by Equation 3. .

[0239]

number

[0240] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In the Levinson model, it is assumed that the height E of the potential barrier comes from defects. is determined and is expressed by Equation 4.

[0241]

number

[0242] where e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the The dielectric constant, n, is the carrier density per unit area of ​​the channel, C ox is the gate per unit area Insulating film capacitance, V gs is the gate voltage, and t is the channel thickness. In the case of the following semiconductor layers, the thickness of the channel may be the same as the thickness of the semiconductor layer.

[0243] Drain current I in the linear region ds is expressed by Equation 5.

[0244]

number

[0245] Here, L is the channel length and W is the channel width, and here, L and W are set to 10 μm. Also, V ds is the drain voltage.

[0246] Taking the logarithm of both sides of Equation 5 gives Equation 6.

[0247]

number

[0248] The right side of Equation 6 is V gs Since it is a function of ds / V gs ), the horizontal axis is 1 / V gs The defect density N can be calculated from the slope of the line on the graph obtained by plotting the measured values ​​as That is, the V gs -I ds The characteristic gives the defect density N in the semiconductor.

[0249] The defect density N in a semiconductor depends on the substrate temperature during semiconductor deposition. In-Sn-Zn with a ratio of n and Zn of In:Sn:Zn=1:1:1 [atomic ratio] When an oxide semiconductor film is formed using an -O target, the defect density in the oxide semiconductor N is 1 × 10 12 / cm 2 It will be about that amount.

[0250] Based on the defect density N in the oxide semiconductor described above, calculations can be made using Equation 3 and Equation 4. , the field effect mobility μ of the original transistor is 120 cm 2 / Vs. Therefore, An ideal oxide semiconductor with no defects in the oxide semiconductor or at the interface with the gate insulating film in contact with the oxide semiconductor. The field effect mobility μ of a suitable transistor is 120 cm 2 However, the defect In many oxide semiconductors, the field-effect mobility μ of a transistor is 30 cm 2 / Vs .

[0251] Even if there are no defects inside the semiconductor, the transistors may be scattered by the interface between the channel and the gate insulating film. The transport properties of the transistor are affected. The current at a distance x from the gate insulating film interface is The field effect mobility μ1 is expressed by Equation 7.

[0252]

number

[0253] where D is the electric field strength due to the gate electrode, B is a constant, and l is the depth at which the effect of interface scattering occurs. B and l can be obtained by measuring the electrical characteristics of the transistor. From actual measurements of the electrical characteristics of transistors using compound semiconductors, B = 4.75 × 10 7 cm / s, l=10nm. When D increases, that is, V gsWhen the value of σ increases, the second It can be seen that the field effect mobility μ1 decreases as the term increases.

[0254] An ideal oxide semiconductor with no defects in the oxide semiconductor and at the interface with the gate insulating film The results of calculating the field-effect mobility μ2 of such a transistor are shown in Figure 18. Using the Sentaurus Device manufactured by Nopsys, the band gap of oxide semiconductors The dielectric constant was set to 15, the electron affinity to 4.7 eV, the dielectric constant to 15, and the thickness to 15 nm. Furthermore, the work function of the gate is set to 5.5 eV, and the work functions of the source and drain are set to 4.6 eV. The thickness of the gate insulating film was set to 100 nm and the relative dielectric constant was set to 4.1. The length and width of the channel are both 10 μm. ds was set to 0.1V.

[0255] As shown in Figure 18, V gs is around 1V, the field effect mobility μ2 is 100cm 2 / Vs Although it has more peaks than V gs As the temperature increases, the effect of interface scattering increases and the It can be seen that the field effect mobility μ2 decreases.

[0256] The calculation results for miniaturizing such an ideal transistor are shown in Figures 19 to 20. This is shown in Figure 21. Note that the calculations are based on the assumption that the transistor has the structure shown in Figure 7.

[0257] Here, the resistivity of the low resistance region 506b is set to 2×10 -3 Ωcm, and the width of the gate electrode 504 is set to 3 The width of the sidewall insulating film 524 is 5 nm, and the channel width is 40 nm. For convenience, the region is referred to as a high resistance region 506a. It is assumed to be an intrinsic semiconductor.

[0258] The calculation was performed using the Sentaurus Device manufactured by Synopsys. (B) I ds (solid line) and field-effect mobility μ (dotted line) V gs It is a dependency. ds is V ds is set to 1V, and the field-effect mobility μ is V ds of The calculation is based on a voltage of 0.1 V. Here, the gate insulating film is assumed to be 15 nm thick. 9(A), 10nm is shown in Fig. 19(B), and 5nm is shown in Fig. 19(C). Each is shown.

[0259] From Figure 19, the thinner the gate insulating film, the lower the gs is -3V to 0V The drain current I ds On the other hand, the peak of the field-effect mobility μ value and ON state (here V gs indicates the range from 0V to 3V.) ds There is no noticeable change in V gs is around 1V and I ds is a semiconductor device This exceeds the 10 μA required for devices such as mori.

[0260] Similarly, calculations are performed for the transistor shown in FIG. The transistor to be fabricated is an oxide semiconductor having a high resistance region 507a and a low resistance region 507b. The transistor shown in FIG. 7B differs from the transistor shown in FIG. 7B in that it has a conductor film 507. 7C, the oxide semiconductor film 524 overlaps with the sidewall insulating film 524. The region 07 is included in the high resistance region 507a. The offset region is a transistor having a width of It is also called the set length (Loff) (see Figure 7(A)). For convenience, Loff is the same on the left and right. The width is the same.

[0261] In the transistor shown in FIG. 7(C), Loff is set to 5 nm, and the drain current I d s (solid line) and field-effect mobility μ (dotted line) gs The dependency is shown in Figure 20. d s is V ds is set to 1V, and the field-effect mobility μ is V ds The calculation is based on 0.1V. Here, the case where the thickness of the gate insulating film is 15 nm is shown in FIG. 20(A), and the case where it is 10 nm is shown in FIG. FIG. 20(B) shows the case where the thickness is set to 5 nm, and FIG. 20(C) shows the case where the thickness is set to 5 nm.

[0262] Also, FIG. 21 shows that Loff is set to 15 nm from the structure of the transistor shown in FIG. 7(C). The drain current I ds (solid line) and field-effect mobility μ (dotted line) gs dependence In addition, I ds is V ds is set to 1V, and the field-effect mobility μ is V ds is set to 0.1V Here, the calculation is performed with the gate insulating film thickness set to 15 nm as shown in Figure 21(A). The case where the thickness is 10 nm is shown in FIG. 21(B), and the case where the thickness is 5 nm is shown in FIG. 21(C). .

[0263] From the calculation results shown in Figures 20 and 21, similar to Figure 19, it can be seen that the gate insulating film is thin. The lower the voltage, the more the off-state (Vgs The drain voltage at Flow I ds On the other hand, the peak value of the field-effect mobility μ and the on-state (here, V gs but The drain current I ds It can be seen that there is no noticeable change in .

[0264] The peak of the field-effect mobility μ is 80 cm in FIG. 2 / Vs, but Fig. 20 So 60cm 2 / Vs, 40cm in Figure 21 2 As the degree of / Vs and Loff increase, In addition, the I ds It can be seen that the same tendency also occurs. On the other hand, in the on state, I ds decreases with increasing offset length Loff, but I ds The decrease in V is much slower than that in V. gs but At around 1V, I ds It can be seen that this exceeds the 10 μA required for memory, etc.

[0265] Next, the electrical characteristics of a transistor including an oxide semiconductor will be described.

[0266] FIG. 22 shows a top view and a cross section of the fabricated transistors (samples 1 and 2). 22(A) is a top view of the transistor. FIG. 2 is a cross-sectional view corresponding to the dashed line AB in FIG.

[0267] The transistor shown in FIG. 22B includes a base insulating film 702 provided over a substrate 700 and a The oxide semiconductor film 706 provided over the base insulating film 702 and the oxide semiconductor film 706 The pair of electrodes 716, the oxide semiconductor film 706, and the gate electrodes 716 are formed on the oxide semiconductor film 706. a gate insulating film 712 overlapping with the oxide semiconductor film 706 with the gate insulating film 712 interposed therebetween; The gate insulating film 712 and the gate electrode 704 an interlayer insulating film 718 covering the pair of electrodes 71 6, and a protective insulating film covering the interlayer insulating film 718 and the wiring 722. 728 will be established.

[0268] The substrate 700 is a glass substrate, the base insulating film 702 is a silicon oxide film, and the oxide The semiconductor film 706 is an In—Sn—Zn—O film, and the pair of electrodes 716 is a tungsten film. a silicon oxide film as the gate insulating film 712; and a nitrogen film as the gate electrode 704. The interlayer insulating film 718 is a silicon oxynitride film. The laminated structure of the conductor film and the polyimide film is made of titanium film, aluminum film, The titanium film is formed in this order as a laminated structure, and a polyimide film is formed as a protective insulating film 728. Each was used.

[0269] In the transistor having the structure shown in FIG. 22A, the gate electrode 704 and the pair of electrodes The width of the overlap with the oxide semiconductor film 706 is referred to as Lov. The protrusion of pole 716 is called dW.

[0270] A method for manufacturing the transistors (samples 1 and 2) having the structure shown in FIG. 22B will be described below. do.

[0271] First, the surface of the substrate 700 was subjected to plasma treatment in an argon gas atmosphere. The treatment was carried out using a sputtering device, with a bias power of 200 W (RF) applied to the substrate 700 side. The mixture was added and left for 3 minutes.

[0272] Next, while maintaining the vacuum state, a silicon oxide film, which is the base insulating film 702, is deposited to a thickness of 300 nm. The film was deposited to a thickness of 1000 nm.

[0273] The silicon oxide film was formed using a sputtering device in an oxygen gas atmosphere at a power of 1500W (R The target was a quartz target. The temperature was set to 100°C.

[0274] Next, the surface of the base insulating film 702 is subjected to CMP processing to be flattened to approximately Ra=0.2 nm.

[0275] Next, an In-Sn-Zn-O film, which is an oxide semiconductor film, was formed to a thickness of 15 nm.

[0276] The In-Sn-Zn-O film was prepared using a sputtering system with a volume ratio of argon to oxygen of 2:3. The film was deposited in a mixed atmosphere of In:Sn An In-Sn-Zn-O target with an atomic ratio of Zn = 1:1:1 was used. The substrate heating temperature during film formation was set to 200°C.

[0277] Next, only sample 2 was subjected to heat treatment at a temperature of 650°C. The heat treatment was first carried out in a nitrogen gas atmosphere. The sample was then heated for 1 hour in an oxygen gas atmosphere while maintaining the temperature. Heat treatment was carried out.

[0278] Next, the oxide semiconductor film is processed by a photolithography process to form an oxide semiconductor film 70. 6 was formed.

[0279] Next, a tungsten film was formed to a thickness of 50 nm.

[0280] The tungsten film was formed using a sputtering device in an argon gas atmosphere at a power of 1000W. The substrate heating temperature during film formation was 200°C.

[0281] Next, the tungsten film is processed by a photolithography process to form a pair of electrodes 716. Formed.

[0282] Next, a silicon oxide film serving as a gate insulating film 712 was formed to a thickness of 100 nm. The relative dielectric constant of the silicon oxide film was set to 3.8.

[0283] The silicon oxide film, which is the gate insulating film 712, was formed in the same manner as the base insulating film 702. .

[0284] Next, a tantalum nitride film and a tungsten film were deposited in this order at 15 nm and 13 nm, respectively. The film was deposited to a thickness of 5 nm.

[0285] The tantalum nitride film was formed using a sputtering device in a mixed atmosphere of argon and nitrogen at a ratio of 5:1. The film was deposited at a power of 1000 W (DC). The substrate was not heated during the deposition.

[0286] The tungsten film was formed using a sputtering device in an argon gas atmosphere at a power of 4000W. The substrate heating temperature during film formation was 200°C.

[0287] Next, the tantalum nitride film and the tungsten film are processed by a photolithography process. Then, a gate electrode 704 was formed.

[0288] Next, a silicon oxynitride film that will become the interlayer insulating film 718 was formed to a thickness of 300 nm.

[0289] The silicon oxynitride film that becomes the interlayer insulating film 718 is formed by using a PCVD apparatus with monosilane: hypochlorous acid. The film was formed in a mixed atmosphere of nitrogen dioxide and silicon dioxide = 1:200 with a power of 35 W (RF). The substrate heating temperature was set to 325°C.

[0290] Next, a silicon oxynitride film that will become the interlayer insulating film 718 is applied by a photolithography process. I worked on it.

[0291] Next, a photosensitive polyimide film was formed to a thickness of 1500 nm to become the interlayer insulating film 718 .

[0292] Next, the film used in the photolithography process of the silicon oxynitride film that will become the interlayer insulating film 718 is The photosensitive polyimide that will become the interlayer insulating film 718 is exposed to light using a photomask, and then developed. Next, a heat treatment is performed to harden the photosensitive polyimide film, and then it is combined with the silicon oxynitride film. The heat treatment was carried out in a nitrogen gas atmosphere at a temperature of 300° C. I went there by degrees.

[0293] Next, a titanium film, an aluminum film, and a titanium film were deposited in this order at 50 nm and 10 The films were deposited to thicknesses of 0 nm and 5 nm.

[0294] The titanium film was formed using a sputtering device in an argon gas atmosphere with a power of 100 The film was deposited at 0 W (DC). The substrate was not heated during film deposition.

[0295] The aluminum film was formed using a sputtering device in an argon gas atmosphere at a power of 1000W. The film was deposited as DC. The substrate was not heated during the deposition.

[0296] Next, the titanium film, the aluminum film, and the titanium film are processed by a photolithography process. Thus, a wiring 722 was formed.

[0297] Next, a photosensitive polyimide film serving as a protective insulating film 728 was formed to a thickness of 1500 nm.

[0298] Next, a photosensitive polyimide film is formed using the photomask used in the photolithography process for the wiring 722. The film is exposed to light and then developed to form an opening in the protective insulating film 728 that exposes the wiring 722. did.

[0299] Next, a heat treatment was carried out to harden the photosensitive polyimide film. The heat treatment was carried out in the same manner as the heat treatment for the photosensitive polyimide film used for the film 718 .

[0300] Through the above steps, a transistor having the structure shown in FIG. 22B was manufactured.

[0301] Next, the electrical characteristics of the transistor having the structure shown in FIG. 22B were evaluated.

[0302] V in the transistor with the structure shown in FIG. gs -I ds The characteristics of sample 1 were measured. The results are shown in Figure 23(A) and the results for Sample 2 are shown in Figure 23(B). The transistor has a channel length L of 3 μm, a channel width W of 10 μm, and Lov of 3 μm on each side. m (total 6 μm), dW is 3 μm on each side (total 6 μm). ds is 10V Ta.

[0303] In addition, when Sample 1 is compared with Sample 2, the oxide semiconductor film is formed by heat treatment. The inventors believe that this is due to the heat treatment. This is thought to be because the impurity concentration in the oxide semiconductor film was reduced. a heat treatment performed after the formation of the oxide semiconductor film to reduce the impurity concentration in the oxide semiconductor film; As a result, the field-effect mobility of the transistor can be brought closer to the ideal field-effect mobility. I know it's coming.

[0304] In this way, by performing heat treatment after the oxide semiconductor film is formed, impurities in the oxide semiconductor film can be removed. It can be seen that the concentration of the impurity is reduced, resulting in an increase in the field effect mobility of the transistor.

[0305] Next, a BT test was carried out on Sample 1 and Sample 2. The BT test will be described below.

[0306] First, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds Characteristics Measurements were carried out. ds indicates the drain voltage (potential difference between the drain and source). , the substrate temperature is 150°C, and V ds Next, the voltage applied to the gate insulating film was set to 0.1V. V so that the electric field strength is 2MV / cm gs 20 V was applied to the Next, V gs Next, the substrate temperature was set to 25°C, and V ds is set to 10V, and the transformer Jista's V gs -I ds This measurement was called the Plus BT test.

[0307] Similarly, first set the substrate temperature to 25°C, and then V ds is set to 10V, and the V of the transistor gs -I d s Next, the substrate temperature was set to 150°C, and V dswas set to 0.1V. , V so that the electric field strength applied to the gate insulating film is -2MV / cm gs -20V to Then, V gs Next, the substrate temperature was set to 25°C. S, V ds is set to 10V, and the V of the transistor gs -I ds Measurement was carried out. It is called the BT test.

[0308] The results of the positive BT test for sample 1 are shown in Figure 24(A), and the results of the negative BT test are shown in Figure 24(B). The results of the positive BT test for sample 2 are shown in Figure 25(A), and the results of the negative BT test for sample 2 are shown in Figure 25(B). The results are shown in Figure 25(B). The figure also shows the V before and after the BT test. gs -I ds Variation in characteristics Arrows are added for clarity.

[0309] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test are as follows: The positive and negative BT tests for sample 2 were 1.80V and -0.42V. The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively.

[0310] Samples 1 and 2 showed little change in threshold voltage before and after the BT test, demonstrating high reliability. It can be seen that this is a high-performance transistor.

[0311] Next, the relationship between the substrate temperature and the electrical characteristics of the transistor of Sample 2 was evaluated.

[0312] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and Lov was set to 3 μm on one side (total 6 μm), and dW was set to 0 μm. dswas set to 10V. The substrate temperatures were -40°C, -25°C, 25°C, 75°C, 125°C and 150°C.

[0313] Figure 26(A) shows the relationship between the substrate temperature and the threshold voltage, and Figure 26(B) shows the relationship between the substrate temperature and the field effect transition. The relationship between the mobility is shown.

[0314] From FIG. 26(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was from -40°C (0.38V) to 150°C (-1.08V).

[0315] Furthermore, it can be seen from FIG. 26(B) that the higher the substrate temperature, the lower the field effect mobility. The temperature range is -40°C (37.4cm 2 / Vs) ~ 150℃ (33.4cm 2 / Vs ) was.

[0316] As such, it can be seen that Sample 2 has small fluctuations in electrical characteristics within the above-mentioned temperature range. .

[0317] It is clear that the above-described transistor has high field-effect mobility and high reliability.

[0318] Similarly, a transistor that can be used in a semiconductor device according to one embodiment of the present invention has a channel width of 1 The off-state current per μm was evaluated.

[0319] The sample was prepared in the same manner as sample 2. The transistor used for the measurement had an L of 3 μm. , W is 10 cm, Lov is 2 μm, and dW is 0 μm.

[0320] Figure 27 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, the value obtained by multiplying the reciprocal of the substrate temperature by 1000 (1000 / T) is the horizontal axis.

[0321] The following briefly explains how to measure the off-state current of a transistor. The transistor that becomes this state is called the first transistor.

[0322] The drain of the first transistor is connected to the floating gate FG. The gate FG is connected to the gate of the second transistor.

[0323] First, the first transistor is turned off, and then a charge is applied to the floating gate FG. A constant drain voltage is applied to the second transistor.

[0324] At this time, the charge on the floating gate FG gradually leaks through the first transistor. When the charge on the floating gate FG is released, the source potential of the second transistor becomes The amount of change in the source potential over time is used to determine the leakage current from the first transistor. The amount of charge can be estimated and the off-current can be measured.

[0325] As shown in Figure 27, the fabricated transistor had a channel width of 1 The off-state current per μm is 2×10 -21 A / μm (2zA / μm).

[0326] As described above, it is found that the off-state current of the fabricated transistor is extremely small.

[0327] As described above, by using an oxide semiconductor film with few impurities, a highly reliable transistor can be obtained. You can get a transistor.

[0328] Furthermore, a transistor with excellent electrical characteristics can be obtained.

[0329] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0330] (Embodiment 2) In this embodiment, a liquid crystal display device manufactured using the transistor described in Embodiment 1 Note that in this embodiment, a transistor according to one embodiment of the present invention is used in a liquid crystal display device. Although an example of applying the EL( The transistor according to one aspect of the present invention is used in a display device. Those skilled in the art can easily come up with the idea of ​​applying the above-mentioned method.

[0331] Figure 9 shows a circuit diagram of an active matrix driving liquid crystal display device. Source lines SL_1 to SL_a, gate lines GL_1 to GL_b, and and a plurality of pixels 2200. The pixel 2200 includes a transistor 2230 and a capacitor 2220 and a liquid crystal element 2210. These pixels 2200 are arranged in a matrix. The pixel portion of the liquid crystal display device is formed by these lines. In this case, they are referred to as source lines SL or gate lines GL.

[0332] The transistor described in Embodiment 1 can be used as the transistor 2230. By using a transistor according to one embodiment of the present invention, a display with high display quality and high reliability can be obtained. A display device can be obtained.

[0333] The gate line GL is connected to the gate of the transistor 2230, and the source line SL is connected to the gate of the transistor 2231. The drain of transistor 2230 is connected to the source of capacitor 2220. The capacitor electrode is connected to one of the pixel electrodes of the liquid crystal element 2210. The other capacitor electrode and the other pixel electrode of the liquid crystal element 2210 are connected to a common electrode. The common electrode may be provided in the same layer and made of the same material as the gate line GL.

[0334] The gate lines GL are connected to a gate drive circuit. The transistor may include the transistor shown in FIG.

[0335] The source lines SL are connected to a source driver circuit. The transistor may include the transistor shown in FIG.

[0336] Either or both of the gate drive circuit and the source drive circuit may be implemented using a separately prepared substrate. Formed on a board and then processed by COG (Chip On Glass), wire bonding, or T Even if you connect using methods such as AB (Tape Automated Bonding), good.

[0337] In addition, since transistors are easily damaged by static electricity, it is preferable to provide a protection circuit. It is preferable that the protection circuit is configured using a non-linear element.

[0338] When a potential is applied to the gate line GL so that it is equal to or higher than the threshold voltage of the transistor 2230, The charge supplied from the source line SL becomes the drain current of the transistor 2230. After charging one row, the transistor 2230 in that row is turned off, and no voltage is applied from the source line SL. The stored charge can maintain the required voltage. Then the capacitors in the next row Then, the process moves to charging the capacitor 2220. In this manner, the capacitors in rows 1 to b are charged.

[0339] Note that the transistor 2230 has a low off-state current and therefore is The charge held in 20 is difficult to escape, making it possible to reduce the capacitance of capacitor 2220 Therefore, the power consumption required for charging can be reduced.

[0340] As described above, by using a transistor according to one embodiment of the present invention, power consumption can be reduced. Therefore, a liquid crystal display device with high display quality and high reliability can be obtained.

[0341] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0342] (Embodiment 3) In this embodiment, the transistor described in Embodiment 1 is used to fabricate a memory cell which is a semiconductor device. An example of fabricating a rib will be described.

[0343] A typical example of volatile memory is a memory element that selects transistors to form a capacitor. DRAM (Dynamic Random Access Memory) stores information by storing electrical charges in the Access Memory, which uses circuits such as flip-flops to store memory contents. There is SRAM (Static Random Access Memory).

[0344] The transistor described in Embodiment 1 can be applied to some of the transistors included in the memory. This can be done.

[0345] For example, a memory cell included in a semiconductor device to which the transistor described in Embodiment 1 is applied An example of this will be described with reference to FIG.

[0346] 10A shows a cross-sectional view of the memory cell. The transistor 3340 is formed on a substrate 3100. A base insulating film 3102 is provided, and a protective film 312 is provided around the base insulating film 3102. 0, and a high resistance region 3106a and a high resistance region 3106b provided on the base insulating film 3102 and the protective film 3120. and an oxide semiconductor film 3106 having a low-resistance region 3106b. a gate insulating film 3112 provided thereon and an oxide semiconductor film The gate electrode 3104 is provided so as to overlap with the gate electrode 3106, and the gate electrode 3104 is provided so as to contact with the side surface of the gate electrode 3104. and a pair of electrodes 311 in contact with at least the oxide semiconductor film 3106. 6 and has.

[0347] Here, a substrate 3100, an insulating base film 3102, a protective film 3120, an oxide semiconductor film 3106 , a gate insulating film 3112, a gate electrode 3104, a sidewall insulating film 3124, and a pair of electrodes 3 116 are the substrate 100, the base insulating film 502, the protective film 520, and the oxide semiconductor film 50 6, a gate insulating film 512, a gate electrode 504, a sidewall insulating film 524, and a pair of electrodes 516 It may be provided by the same method and using the same materials as those in the first embodiment.

[0348] The transistor 3340 is covered with an interlayer insulating film 3 328 and an electrode 3326 provided on the interlayer insulating film 3328. One of the electrodes 3116, the interlayer insulating film 3328, and the electrode 3326 form a capacitor. 3330. The figure shows a parallel plate type capacitor, but it can be used to increase the capacitance. A stacked or trench capacitor may be used for this purpose. The insulating film 518 may be formed by a method and using a material similar to that of the protective insulating film 518. The electrodes 3326 may be provided by the same method and using the same materials as the pair of electrodes 516 .

[0349] Furthermore, the transistor 3340 is provided to cover the interlayer insulating film 3328 and the electrode 3326. and a layer insulating film 3118 formed on the layer insulating film 3118 and the layer insulating film 3328. and a wiring 3122 that connects to the other of the pair of electrodes 3116 through the opening. Although not shown, a protective film is provided to cover the interlayer insulating film 3118 and the wiring 3122. By providing the protective film, the surface conduction of the interlayer insulating film 3118 can be prevented. This can reduce the minute leakage current that occurs due to the gate insulating film, thereby reducing the off-state current of the transistor. The wiring 3122 may be provided in the same manner and with the same material as the wiring 522. stomach.

[0350] FIG. 10B is a circuit diagram of the memory cell shown in FIG. 10A. a capacitor C connected to one of the source and drain of the transistor Tr; The capacitor C has one of the source and drain of the transistor Tr. The other side is grounded. The gate of the transistor Tr is connected to the word line WL. Either the source or the drain of the transistor Tr is connected to the bit line BL. The transistor Tr is connected to the sense amplifier SAmp. 3340, and capacitor C corresponds to capacitor 3330.

[0351] The change in the potential held in the capacitor C over time is caused by the off-current of the transistor Tr, as shown in Figure 1. It is known that the voltage gradually decreases as shown in Fig. 0(C). Over time, the applied potential decreases to VA, which is the limit point at which data1 can be read. This period is called the retention period T_1. In other words, in the case of a binary DRAM, during the retention period T_1, A refresh operation must be performed.

[0352] Here, by applying the transistor 3340 to the transistor Tr, the transistor Since the off-current of Tr can be made extremely small, the hold period T_1 can be extended. In other words, it is possible to take a longer interval between refresh operations, so that the memory cells Power consumption can be reduced. In addition, the high reliability of the transistor Tr ensures high reliability. Therefore, a memory cell with high performance can be obtained.

[0353] For example, if the off-state current is 1×10 -18 Below A, 1×10 -21 A or less, preferably 1×10 -24 If a memory cell is configured with transistors that are less than A, the interval between refresh operations can be from several tens of seconds to several decades.

[0354] As described above, by using a transistor according to one embodiment of the present invention, high reliability can be achieved. Therefore, a semiconductor device with low power consumption can be obtained.

[0355] Next, a memory cell constituting a semiconductor device to which the transistor shown in Embodiment 1 is applied will be described. An example different from that shown in FIG. 10 will be described with reference to FIG.

[0356] 11A shows a cross-sectional view of the memory cell. a base insulating film 3382 formed on the first resistor region 3381; 3384a, a second resistive region 3384b, and a third resistive region 3384c. a semiconductor film 3384, a gate insulating film 3386 provided on the semiconductor film 3384, and a gate insulating film A gate electrode 3392 is provided so as to overlap the first resistance region 3384a via a film 3386. and a sidewall insulating film 3394 in contact with the side surface of the gate electrode 3392. 84, a first resistance region 3384a, a second resistance region 3384b, a third resistance region The resistance decreases in the order of the first resistance region 3384a to the gate electrode 33. When a voltage higher than the threshold voltage of the transistor 3350 is applied to 92, a channel is formed. Although not shown, a pair of electrodes may be provided in contact with the third resistance region 3384c.

[0357] The transistor 3350 may be formed using a semiconductor film other than an oxide semiconductor film, for example, polycrystalline silicon. Group 14 elements such as films, single crystal silicon films, polycrystalline germanium films, and single crystal germanium films A transistor using a semiconductor film having an oxide layer may be used. A transistor using a compound semiconductor film may also be used.

[0358] An interlayer insulating film 3396 is provided in contact with the transistor 3350. The insulating film 3396 is also the surface on which the transistor 3340 is formed. The surface is made as flat as possible. Specifically, the surface of the interlayer insulating film 3396 has a Ra of 1 nm. It is preferably 0.3 nm or less, and more preferably 0.1 nm or less.

[0359] The interlayer insulating film 3396 may have a single layer structure or a stacked layer structure. The layer in contact with the insulating film is preferably an insulating film that releases oxygen by heat treatment.

[0360] The transistor 3340 is provided on the interlayer insulating film 3396. One of the pair of electrodes 3116 of the transistor 3350 is connected to the gate electrode 3116 of the transistor 3350. 392. In addition, the pair of electrodes 3116 of the transistor 3340 The capacitor 3330 is formed by one of the electrodes, an interlayer insulating film 3328, and an electrode 3326. Although the figure shows a parallel plate type capacitor, a star type is used to increase the capacitance. Block or trench type capacitors may be used.

[0361] FIG. 11B is a circuit diagram of the memory cell shown in FIG. 11A. A transistor Tr_1, a transistor Tr_2, a capacitor C, a capacitor C, a transistor The floating resistors connected to the drain of transistor Tr_1 and the gate of transistor Tr_2 The gate of the transistor Tr_1 is connected to the gate line GL_1. The source of the transistor Tr_1 is connected to the source line SL_1, and the transistor Tr_ The source of transistor 2 is connected to source line SL_2, and the drain of transistor Tr_2 is connected to drain line Connect to DL_2. Also, the side of capacitor C that is not connected to the floating gate FG is It is connected to the capacitance line CL. The transistor Tr_1 corresponds to the transistor 3340. , transistor Tr_2 corresponds to transistor 3350, and capacitor C corresponds to Equivalent to Ta3330.

[0362] Note that the memory cell shown in this embodiment mode changes the transistor in response to the potential of the floating gate FG. This utilizes the fact that the threshold voltage of the transistor Tr_2 varies. For example, C) is the potential V of the capacitance wiring CL CL and the drain current I flowing through transistor Tr_2 ds This is a diagram explaining the relationship with _2.

[0363] Here, the floating gate FG adjusts the potential via the transistor Tr_1. For example, the potential of the source line SL_1 is set to VDD. The potential of L_1 is set to a potential equal to or higher than the threshold voltage Vth of transistor Tr_1 plus VDD. By doing so, the potential of the floating gate FG can be set to HIGH. By setting the potential of the gate line GL_1 to be equal to or lower than the threshold voltage Vth of the transistor Tr_1, The potential of the floating gate FG can be set to LOW.

[0364] Therefore, V shown with FG=LOW CL -I ds _2 curve and FG=HIGH V CL -I ds You can get either of the two curves. That is, when FG=LOW, V CL I at 0V ds Since _2 is small, the data is 0. Also, when FG=HIGH, V CL I at 0V ds Since _2 is larger, it becomes data 1. In this way, It can be memorized.

[0365] Here, by applying the transistor 3340 to the transistor Tr_1, the transistor Since the off-current of the transistor Tr_1 can be made extremely small, the flow shown in FIG. The charge stored in the gate FG is accidentally leaked through the transistor Tr_1. This reduces the need for data access, making it possible to retain data for a long period of time. In addition, since the field effect mobility of the transistor Tr_1 is high, the memory cell can be operated at high speed. This can be done.

[0366] As described above, by using a transistor according to one embodiment of the present invention, reliability can be improved. Therefore, a semiconductor device that is low in power consumption and capable of high-speed operation can be obtained.

[0367] This embodiment may be used in combination with other embodiment modes.

[0368] (Fourth embodiment) At least the transistor described in Embodiment 1 and the semiconductor device described in Embodiment 3 It also forms a CPU (Central Processing Unit) It is possible.

[0369] FIG. 12(A) is a block diagram showing a specific configuration of the CPU. The PU is provided on a substrate 1190 with an arithmetic logic unit (ALU). nit) 1191, ALU controller 1192, instruction decoder 1193 , interrupt controller 1194, timing controller 1195, register 11 96, Register Controller 1197, Bus Interface (Bus I / F) 119 8. Rewritable ROM1199 and ROM interface (ROM I / F) The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 12(A) is merely an example of a simplified configuration. Actual CPUs have a wide variety of configurations depending on their applications.

[0370] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0371] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0372] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generator generates the clock signal CLK2. Supply to the circuit.

[0373] In the CPU shown in FIG. 12A, the semiconductor device of the third embodiment is provided in the register 1196. It is being done.

[0374] In the CPU shown in FIG. 12A, the register controller 1197 controls the ALU 1191 The holding operation in register 1196 is selected according to the instruction from register 1196. In the semiconductor device of 196, data is held by a phase inversion element or a capacitor. Select whether to hold data by a phase inversion element. In this case, the power supply voltage is supplied to the semiconductor device in the register 1196. When data is to be held, the data is rewritten to the capacitor and the register 119 is The supply of power supply voltage to the semiconductor device in the power supply circuit 6 can be stopped.

[0375] Regarding power supply shutdown, as shown in FIG. 12(B) or FIG. 12(C), A switching element is connected between nodes to which the power supply potential VDD or VSS is applied. The circuits shown in FIGS. 12(B) and 12(C) are explained below. Make it clear.

[0376] 12B and 12C show a switch for controlling the supply of a power supply potential to a semiconductor device. The switching element includes a memory circuit including the transistor with extremely low off-state current described in Embodiment 1. An example of the path configuration is shown below.

[0377] The memory device shown in FIG. 12B includes a switching element 1141 and a semiconductor device 1142. Specifically, each of the semiconductor devices 114 The semiconductor device described in Embodiment 3 can be used for the semiconductor device group 1143. Each semiconductor device 1142 has a high-level The power supply potential VDD of the semiconductor device group 1143 is supplied to the semiconductor device group 1143. In this semiconductor device 1142, the potential of the signal IN and the potential of the low-level power supply potential VSS are It is given.

[0378] In FIG. 12B, the transistor shown in Embodiment 1 is used as the switching element 1141. The transistor is controlled by a signal SigA applied to its gate. The switching is controlled by the

[0379] In FIG. 12B, the switching element 1141 has only one transistor. However, the present invention is not limited to this configuration, and a plurality of transistors may be included. In the case where the switching element 1141 has a plurality of transistors that function as switching elements, In this case, the plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0380] 12C shows the semiconductor devices 1142 included in the semiconductor device group 1143. A low-level power supply potential VSS is supplied to the 11 shows an example of a memory device. A switching element 1141 enables a semiconductor device group 1143. Controlling the supply of a low-level power supply potential VSS to each of the semiconductor devices 1142 It is possible.

[0381] A switch is provided between a group of semiconductor devices and a node to which a power supply potential VDD or a power supply potential VSS is applied. When a switching element is installed to temporarily stop CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, which reduces power consumption. For example, a user of a personal computer may input information into an input device such as a keyboard. The CPU can be stopped while the It is possible.

[0382] In addition, the transistor described in Embodiment 1 and the semiconductor device described in Embodiment 3 may be used. This makes it possible to obtain a CPU that is capable of high-speed operation with low power consumption.

[0383] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0384] This embodiment may be used in combination with other embodiment modes.

[0385] (Embodiment 5) In this embodiment mode, examples of electronic devices to which Embodiments 1 to 4 can be applied will be described. This article explains:

[0386] 13A shows a portable information terminal. The portable information terminal has a housing 4300 and a button 4301. , a microphone 4302, a display unit 4303, a speaker 4304, and a camera 430 5 and has the function of a mobile phone.

[0387] 13B shows a display. The display includes a housing 4310 and a display portion 431 1 and

[0388] FIG. 13C shows a digital still camera. The digital still camera is provided with a housing 4320. , a button 4321 , a microphone 4322 , and a display unit 4323 .

[0389] By using a transistor according to one embodiment of the present invention, it is possible to obtain a high-quality, low-power transistor. You can get a child device.

[0390] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Example]

[0391] In this example, the pressure and leak current in the film formation chamber of a sputtering apparatus to which one embodiment of the present invention is applied are measured. Shows the crate.

[0392] The deposition chamber has a volume of 1.40 m 3 The turbomolecular pump and cryotrap are parallel A roughing vacuum pump is also provided as an auxiliary pump.

[0393] After opening the film formation chamber to the atmosphere, the chamber was evacuated for 6 hours using a turbomolecular pump.

[0394] Next, the total pressure in the deposition chamber was 5×10 -4 When Pa is reached, start the cryotrap. Then, chamber baking was performed at 400°C for 12 hours.

[0395] Next, in the film-forming chamber, a dummy film was deposited until the film was 10 μm thick (integrated power consumption was 50 kWh). The dummy film was formed at a substrate temperature of 250°C and a film forming pressure of 0.3 Pa. The deposition power was 9 kW (AC), and the deposition gas was argon at 50 sccm and oxygen at 50 The test was performed for 920 seconds per substrate at a target-substrate distance of 150 mm. -The film was formed using In-Ga-Zn-O ternary ions with an atomic ratio of In:Ga:Zn=1:1:1. Get was used.

[0396] In this way, the total pressure in the deposition chamber after sufficient removal of impurities was 2.16 × 10 -5 P a, the partial pressure of the gas with m / z = 2 is 8.63 × 10 -6 Pa, m / z = 18 The partial pressure is 8.43 x 10 -6 Pa, the partial pressure of the gas at m / z = 28 is 1.66 × 10 -5 P a, the partial pressure of a gas with m / z = 40 (such as argon atoms) is 3.87 × 10 -7 Pa and The partial pressure of the gas with m / z = 44 is 5.33 × 10 -6 It was Pa.

[0397] Figure 29 shows the total pressure in the deposition chamber and the partial pressure of each gas. The white circle indicates the total pressure, and the black circle indicates the m / z= The partial pressure of the gas at m / z=2 is shown by the white triangles, and the partial pressure of the gas at m / z=18 is shown by the black triangles. The partial pressure of the gas at m / z=8, the white squares are the partial pressure of the gas at m / z=40, and the black squares are the partial pressure of the gas at m / z=4 The partial pressure of the gas is 4. In addition, Fig. 29 shows the pressures in the film formation chamber and the vacuum pump exhaust. The relationship between the pressure and the time from the time of stopping is shown. The measurement was carried out using a Qulee CGM-051 mass meter (also called Q-mass).

[0398] The leak rate for the entire deposition chamber was estimated from the pressures obtained in this way: 9.84 × 10 - 6 Pa·m 3 / s, m / z = 2 gas is 3.24 × 10 -6 Pa·m 3 / s, m / z = 18 is 4.46 × 10 -9 Pa·m 3 / s, m / z=28 is 7. 74×10 -6 Pa·m 3 / s, m / z = 40 gas is 8.72 × 10 -8 Pa·m 3 / s, m / z = 44 gas is 7.89 × 10 -7 Pa·m 3 / s.

[0399] The leak rate is the ratio of the pressure in the deposition chamber to the time after the vacuum pump has stopped. Specifically, the pressures at 1 minute after the vacuum pump was stopped and the pressure at 15 The difference between each pressure at the time of 1 minute was divided by the time and multiplied by the volume of the deposition chamber to obtain the leak rate. [Example]

[0400] In this embodiment, the film formation chamber of the sputtering apparatus shown in Example 1 is further equipped with a This is achieved by supplying an inert gas such as a heated noble gas to remove any impurities present. This example shows a process in which the pressure in the deposition chamber is increased and the deposition chamber is evacuated again after a certain time has passed.

[0401] Specifically, argon gas at a temperature of 70°C was introduced into the film-forming chamber so that the pressure was 20 Pa. After supplying for 1 hour, the vacuum pump was evacuated for 10 minutes. Repeated 0 times.

[0402] In this way, the total pressure in the deposition chamber after further removing impurities was 1.34 × 10 -5 P a, the partial pressure of the gas with m / z = 2 is 7.58 × 10 -6Pa, m / z = 18 The partial pressure is 5.79 x 10 -6 Pa, the partial pressure of the gas at m / z = 28 is 8.40 × 10 -6 P a, the partial pressure of the gas at m / z = 40 is 1 × 10 -7 Pa or less (below the lower limit of measurement) and m / The partial pressure of the gas at z=44 is 1×10 -7 Pa or less (below the lower limit of measurement).

[0403] FIG. 37 shows the relationship between the total pressure in the film formation chamber and the time elapsed since the evacuation by the vacuum pump was stopped. Each pressure was measured using a quadrupole mass spectrometer, Qulee CGM-051, manufactured by ULVAC, Inc. The measurement was performed using a probe M-11 manufactured by ULVAC, Inc.

[0404] The leak rate for the entire deposition chamber was estimated to be 6.94 × 10 -6 Pa·m 3 / s, m / z = 2 gas is 3.13 × 10 -6 Pa·m 3 / s, m / z= 18 is 3.20 x 10 -9 Pa·m 3 / s, m / z=28 gas is 3.1 2×10 -6 Pa·m 3 / s, m / z = 40 gas is 7.27 × 10 -8 Pa·m 3 / s, m / z = 44 gas is 3.20 × 10 -7 Pa·m 3 / s.

[0405] The leak rate is determined based on the relationship between the pressure in the deposition chamber and the time elapsed since the vacuum pump stopped evacuation. Specifically, the total pressure was calculated from the total pressure at 1 minute after the vacuum pump exhaust was stopped and the total pressure at 15 minutes. The difference between the total pressure at the time of the leak and the total pressure at the time of the leak was divided by time and multiplied by the volume of the deposition chamber to obtain the leak rate.

[0406] Table 1 shows a comparison of the pressures and leak rates between Example 1 and Example 2.

[0407] [Table 1]

[0408] As shown above, the pressure in the deposition chamber is increased by supplying heated argon gas, and a constant After the time has passed, the film formation chamber is evacuated again to remove impurities from the film formation chamber. As a result, the release of impurities was reduced and the pressures in the deposition chamber were It can be seen that the force and the respective leak rate are reduced. [Example]

[0409] In this example, the sample was formed using the film formation chamber of the sputtering apparatus shown in Example 1. TDS analysis, SIMS and XRD analysis were performed.

[0410] The sample was prepared by depositing an In-Ga-Zn-O film with a thickness of 100 nm on a glass substrate. Made.

[0411] The conditions for forming the In-Ga-Zn-O film are as follows:

[0412] The substrate temperature was 250°C, the deposition pressure was 0.3 Pa, the deposition power was 9 kW (AC), and the deposition gas was Argon was supplied at 50 sccm and oxygen at 50 sccm, and the target-substrate distance was set at 150 The atomic ratio of In:Ga:Zn was 1:1:1. The -O target was used.

[0413] First, a TDS analysis was performed.

[0414] The TDS analysis was performed using a thermal desorption analyzer EMD-WA1000S manufactured by Electronic Science Corporation. / W was used.

[0415] The TDS analysis results of the sample are shown in Figure 32. Here, Figure 32(A) shows the gas with m / z=18. ion intensity of the gas with m / z=28, and Fig. 32(C) shows the m The solid line in Figure 32 indicates the ion intensity of the gas with / z=44. The dotted line indicates the ion intensity when the film is heated at 350°C for 1 hour in a nitrogen gas atmosphere after deposition. Then, the sample was treated in an oxidizing atmosphere (80% by volume of nitrogen gas, 20% by volume of oxygen gas) for 1 The ionic strength when heat treatment was performed for 2 hours is shown.

[0416] From the obtained ionic strength, it was found that the In-Ga-Zn-O film can be formed by heat treatment after film formation. The amount of gas released is m / z=18, m / z=28, and m / z=44. It can be seen that the

[0417] Next, SIMS was performed on the sample.

[0418] For the SIMS, an IMS 7fR manufactured by CAMECA was used.

[0419] FIG. 33 shows the hydrogen depth profile measured by SIMS.

[0420] FIG. 34 shows the carbon depth profile obtained by SIMS.

[0421] FIG. 35 shows the depth profile of nitrogen measured by SIMS.

[0422] 33 to 35, the solid line indicates the depth profile without heat treatment, and the dots indicate the depth profile without heat treatment. After the wire is formed, it is heat-treated in a nitrogen gas atmosphere at 450°C for 1 hour, and then oxidized. Data when heat treatment was performed for 1 hour in an atmosphere (nitrogen 80% by volume, oxygen 20% by volume) The pulse profile is shown.

[0423] From the obtained depth profile, it was found that the In-Ga-Zn-O film was heat-treated after deposition. It can be seen that the concentrations of hydrogen, carbon, and nitrogen decrease as a result.

[0424] Next, XRD analysis of the sample was carried out.

[0425] For the XRD analysis, a Bruker AXS X-ray diffractometer D8 ADVANCE was used. The measurements were performed using the out-of-plane method.

[0426] FIG. 36 shows the XRD results of the In—Ga—Zn—O film.

[0427] In FIG. 36, the solid line indicates the XRD result without heat treatment, and the dotted line indicates the result of nitrogen gas after film formation. The sample was then heated in an oxidizing atmosphere (80% nitrogen) at 450°C for 1 hour. % by volume and 20% by volume of oxygen for 1 hour.

[0428] In FIG. 36, it can be seen that all samples have multiple crystalline peaks. It can be seen that the intensity of the characteristic peak increases when a heat treatment is performed after film formation.

[0429] In-Ga-Zn-O film formed using the film formation chamber of the sputtering apparatus shown in Example 1 It can be seen that the impurity concentration is low and there are crystalline regions. [Explanation of symbols]

[0430] 10 Deposition chamber 10a Deposition chamber 10b Deposition chamber 10c Deposition chamber 11 Substrate supply room 12a Load lock chamber 12b Load lock chamber 13 Transport Room 14 Cassette port 15 Substrate heating chamber 20a Deposition chamber 20b Deposition chamber 22a Load lock chamber 22b Load lock chamber 25 Substrate heating chamber 32 Target 34 Target holder 42 PCB holder 44 Substrate heater 46 Shutter axis 48 Shutter plate 50 RF power supply 52 Matching box 54 Refiner 55 Mass flow controller 56 Gas supply source 57 Gas heating mechanism 58 Vacuum Pump 59 Vacuum Pump 68 Counter electrode 100 boards 102 Undercoat insulating film 104 gate electrode 106 Oxide semiconductor film 112 Gate insulating film 116 Pair of Electrodes 204 gate electrode 206 Oxide semiconductor film 212 Gate insulating film 216 Pair of Electrodes 304 Gate electrode 306 Oxide semiconductor film 312 Gate insulating film 316 Pair of electrodes 318 Protective insulating film 406 Oxide semiconductor film 416 Pair of Electrodes 418 Protective insulating film 502 Undercoat insulating film 504 gate electrode 506 Oxide semiconductor film 506a High resistance area 506b Low resistance region 507 Oxide semiconductor film 507a High resistance area 507b Low resistance region 512 Gate insulating film 516 Pair of electrodes 518 Protective insulating film 520 Protective film 522 Wiring 524 Sidewall insulating film 602 Undercoat insulating film 604 Gate electrode 606 Oxide semiconductor film 606a High resistance area 606b Low resistance region 612 Gate insulating film 616 Pair of electrodes 618 Protective insulating film 622 Wiring 700 boards 702 Undercoat insulating film 704 gate electrode 706 Oxide semiconductor film 712 Gate insulating film 716 Pair of Electrodes 718 Interlayer insulating film 722 Wiring 728 Protective insulating film 1141 Switching element 1142 Semiconductor devices 1143 Semiconductor Devices 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 pixels 2210 Liquid crystal element 2220 capacitor 2230 transistor 3100 board 3102 Undercoat insulating film 3104 Gate electrode 3106 Oxide semiconductor film 3106a High resistance area 3106b Low resistance region 3112 Gate insulating film 3116 Pair of electrodes 3118 Interlayer insulating film 3120 Protective film 3122 Wiring 3124 Sidewall insulating film 3326 Electrode 3328 Interlayer insulating film 3330 capacitor 3340 transistor 3350 transistor 3382 Undercoat insulating film 3384 Semiconductor film 3384a Resistance Area 3384b Resistance Area 3384c resistance area 3386 Gate insulating film 3392 Gate electrode 3394 Sidewall insulating film 3396 Interlayer insulating film 4300 chassis 4301 Button 4302 Microphone 4303 Display section 4304 Speaker 4305 Camera 4310 chassis 4311 Display section 4320 chassis 4321 Button 4322 Microphone 4323 Display Department

Claims

[Claim 1] having a memory cell, The memory cell includes a transistor and a capacitor, One of the source and the drain of the transistor is electrically connected to a bit line; the other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor; a gate electrode of the transistor is electrically connected to a word line; the transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer has crystals oriented such that the c-axis is perpendicular to a surface of the oxide semiconductor layer, The memory device wherein, after a potential is applied to one electrode of the capacitor by turning on the transistor, the charge applied to the capacitor is held by turning off the transistor.

Images