Method for manufacturing wiring board
By forming via holes through the selective removal of post materials using a dissolving liquid, the method addresses void formation and shape stability issues, resulting in high-precision and efficient manufacturing of wiring boards with stable via holes.
Patent Information
- Application Number
- JP2024021406
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-15
- Publication Date
- 2025-08-27
AI Technical Summary
The existing method for manufacturing wiring boards faces issues with void formation and insufficient shape stability of fine holes due to the insulating layer covering post materials, leading to potential defects.
A method involving the formation of a first conductor layer with conductor pads, application of a photosensitive resin post material, and subsequent removal of the post material using a dissolving liquid to create via holes, followed by filling with conductors, ensuring precise and stable via hole formation.
This approach enables the efficient production of wiring boards with insulating layers having fine holes with improved shape stability and reduced manufacturing steps, enhancing yield and precision.
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Figure 2025125377000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]
[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board including a first conductor layer having conductor pads, and an insulating layer laminated on the first conductor layer, the insulating layer having holes for exposing the conductor pads and having conductors formed in the holes. The holes are manufactured by forming post materials on the conductor pads, laminating an insulating layer to cover the post materials, and then removing the post materials. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73514 Summary of the Invention [Problem to be solved by the invention]
[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, an insulating layer is formed to cover the first conductor layer together with the post material, and therefore, when forming a fine hole, there is a risk of voids being formed between the post material and the insulating layer, and the shape stability of the hole may be insufficient. [Means for solving the problem]
[0005] The method for manufacturing a wiring board of the present invention includes forming a first conductor layer including a conductor pad on a first insulating layer, forming a post material on the conductor pad using a photosensitive resin, forming a second insulating layer on the first insulating layer so as to cover the first conductor layer and only a portion of the side surface of the post material, removing the post material from the second insulating layer using a dissolving liquid that dissolves the post material, thereby forming a via hole in the second insulating layer so that the conductor pad is exposed from the second insulating layer, and filling the via hole with a conductor so as to contact the conductor pad, thereby forming a via conductor.
[0006] According to the embodiment of the present invention, a wiring board having an insulating layer including fine holes with excellent shape stability can be efficiently manufactured. [Brief explanation of the drawings]
[0007] [Figure 1] 1 is a cross-sectional view partially illustrating an example of a wiring substrate manufactured by a manufacturing method according to an embodiment of the present invention. [Figure 2A] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2B] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2C] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2D] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2E] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION
[0008] A wiring board according to one embodiment of the present invention will be described with reference to the drawings. The drawings are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention. A wiring board 1, which is an example of a wiring board manufactured by a manufacturing method according to one embodiment, is a wiring board including a laminated structure formed of multiple conductor layers and insulating layers stacked alternately. Opposing conductor layers sandwiching an insulating layer are electrically connected by via conductors that penetrate the insulating layer in the thickness direction. The number of conductor layers and insulating layers included in the manufactured wiring board is not limited and can be selected as appropriate. The laminated structure of the wiring board is also not limited.
[0009] FIG. 1 shows a cross-sectional view of a portion of a wiring board 1, which is an example of a wiring board according to this embodiment. The wiring board 1 of the illustrated example includes an insulating layer 10 (first insulating layer), a conductor layer 11 (first conductor layer) formed on the insulating layer 10, an insulating layer 12 (second insulating layer) formed on the insulating layer 10 and the conductor layer 11, and a via conductor 21 connecting the conductor layer 11 to a conductor layer 13 (second conductor layer) facing the conductor layer 11 across the insulating layer 12. The conductor layer 11 includes a conductor pattern including conductor pads 11p. FIG. 1 shows four via conductors 21 formed on the conductor pads 11p along the thickness direction of the wiring board 1. The via conductors 21 are composed of a metal film layer 22 and a plating film layer 23 on the metal film layer 22.
[0010] In the description of the wiring board 1 of this embodiment, in relation to the insulating layer 10 and the conductor layer 11, the conductor layer 11 side, i.e., the upper side on the paper, is referred to as the "upper side" or simply "top," and the insulating layer 10 side is referred to as the "lower side" or simply "bottom." For example, the upper surface of the insulating layer 10 refers to the first surface 10F of the insulating layer 10.
[0011] The wiring board 1 is merely one example of the wiring board of this embodiment. Although four via conductors 21 are shown in Fig. 1, the number of via conductors 21 is not limited. The via conductors 21 of the wiring board 1 of this embodiment can be formed in any desired number and at any desired position depending on the conductor patterns included in the upper and lower conductor layers to which they are connected.
[0012] The insulating layers 10 and 12 may be formed using an insulating resin material such as epoxy resin or phenolic resin. The insulating layers 10 and 12 may contain any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). The insulating layers 10 and 12 may further contain an inorganic filler such as silica. The number of conductor layers and insulating layers formed below the insulating layer 10 and above the conductor layer 13 in the wiring substrate 1 is not limited. The insulating layer 10 may be a single layer, or it may be a build-up layer having a laminated structure, i.e., two or more insulating layers and one or more conductor layers sandwiched between these insulating layers. If the insulating layer 10 is a build-up layer, the insulating layer within the build-up layer may include via conductors connecting the conductor layers on both sides of each insulating layer.
[0013] The conductors constituting the conductor layers 11 and 13 and the via conductor 21 may be any conductive metal, such as copper or nickel. Preferably, the conductor layers 11 and 13 and the via conductor 21 are made of copper. In the example of FIG. 1, the via conductor 21 has a two-layer structure including a metal film layer 22 (preferably a sputtered film layer or an electroless plated film layer) and a plated film layer 23 (preferably an electrolytic plated film layer). Although the conductor layer 11 is shown as a single-layer structure in FIG. 1 for ease of viewing, it may have a multi-layer structure of two or more layers. Like the via conductor 21, the conductor layer 11 may be formed from a metal film layer and a plated film layer. The conductor layer 11 may have a three-layer structure including a metal foil such as copper foil, a metal film layer (e.g., a copper sputtered film or an electroless copper plated film), and an electrolytic plated film layer (e.g., an electrolytic copper plated film). The conductor layer 13 is formed integrally with the via conductor 21. Therefore, the conductor layer 13 can be formed from the same metal film layer and plating film layer as the via conductors 21. The conductor layers 11 and 13 are patterned to have a predetermined conductor pattern.
[0014] The via conductors 21 that penetrate the insulating layer 12 in the thickness direction are formed by filling through holes 12a that penetrate the insulating layer 12 with a conductor. The through holes 12a are formed so that the aspect ratio of the via conductors 21 (height h from the upper surface 11F of the lower conductive layer 11 to which the via conductor 21 is connected to the lower surface 13B of the upper conductive layer 13 / diameter d of the via conductor 21 on the upper surface 11F of the lower conductive layer 11 to which the via conductor 21 is connected) is, for example, 0.5 or more and 5 or less. The height h of the via conductors 21 is, for example, 5 μm or more and 25 μm or less.
[0015] The via diameter d of the via conductor 21 (the diameter of the via conductor 21 on the upper surface 11F of the lower conductor layer 11 to which the via conductor 21 is connected) is approximately 1 μm or more and approximately 20 μm or less. Although the term "diameter" is used, the planar shape of the via conductor 21 is not necessarily limited to a circle. The via conductor 21 can be formed in any planar shape. "Diameter" means the distance between the longest two points on the periphery of the via conductor 21 in a horizontal cross section. Furthermore, here, "planar shape" means the shape of the object when viewed parallel to the thickness direction of the wiring board 1, i.e., the shape of the object in a planar view.
[0016] The via conductors 21 can be formed so that the angle between the side surface 21a of the via conductor 21 and the top surface 11F of the conductor layer 11 is 90° or more and 115° or less. By forming the via conductors 21 in a shape with such a tapered angle, the via conductors 21 can be formed at a fine pitch even if the via conductors 21 have a relatively high aspect ratio. Preferably, the via conductors 21 can be formed so that the via diameter d is approximately the same from the lower end contacting the conductor layer 11 to the upper end contacting the conductor layer 13. Finer via conductors 21 can be arranged at a higher density. For example, the minimum distance between adjacent via conductors 21 can be set to 20 μm or less. In such a case, through holes 12a for forming the via conductors 21 are formed in the insulating layer 12 at a fine pitch. Therefore, the insulating layer 12 may contain an inorganic filler such as fine particles of silica (SiO2), alumina, or mullite, but it may be preferable that the insulating layer 12 does not contain an inorganic filler so that small diameter through holes 12a can be easily formed.
[0017] Next, a method for manufacturing a wiring board according to an embodiment will be specifically described with reference to FIGS. 2A to 2E, using wiring board 1 of FIG. 1 as an example.
[0018] As shown in FIG. 2A , post materials 31 are formed on the upper surface 11F of the conductor layer 11 at positions where via conductors 21 are to be formed. Specifically, first, a conductor layer 11 including a predetermined conductor pattern including conductor pads 11p is formed on the insulating layer 10 by any method. The conductor layer 11 may be formed, for example, by a semi-additive method. In this case, after a seed metal film (not shown) is formed on the entire surface of the insulating layer 10 by electroless plating or the like, a plating resist (not shown) having openings in predetermined locations is formed, and an electrolytically plated film is formed in the openings. The conductor layer 11 including the electrolytically plated film is formed. Thereafter, the plating resist is removed, and unnecessary portions of the seed metal film are removed by etching. However, the conductor layer 11 may also be formed by a full-additive method or a subtractive method. The conductor layer 11 may include wiring such as signal lines and power supply lines.
[0019] Next, a post material 31 made of a photosensitive resin is formed on the upper surface 11F of the conductor pad 11p of the conductor layer 11. For example, a UV-curable photosensitive resin is layered on the insulating layer 10 and the conductor layer 11 to form a photosensitive resin layer. The post material 31 is formed by exposure and development using an exposure mask (not shown) that exposes the formation position of the post material 31, i.e., the position where the via conductor 21 (see FIG. 1) is to be formed. Preferably, the post material 31 is formed to have approximately the same diameter from its lower end contacting the conductor layer 11 to its upper end opposite the lower end. The post material 31 may be formed so that the angle formed between the side surface of the post material 31 and the upper surface 11F of the conductor layer 11 is 90° or more and 115° or less. The height of the post material 31 from the upper surface 11F of the conductor layer 11 to its upper end is greater than the height h from the lower end to the upper end of the via conductor 21 (see FIG. 1) to be formed.
[0020] As the photosensitive resin, for example, a photosensitive resist such as a photosensitive acrylic resin, a photosensitive polyimide resin, a photosensitive polybenzoxazole resin, a photosensitive phenol resin, a photosensitive epoxy resin, a photosensitive cycloolefin resin, or a photosensitive benzocyclobutene resin can be suitably used.
[0021] 2B, an insulating layer 12 is formed on the insulating layer 10 to cover the upper surface 11F and side surfaces of the conductor layer 11 and at least a portion of the side surfaces of the post material 31. In the method for manufacturing a wiring board according to the embodiment, the insulating layer 12 is formed to a thickness that covers only a portion of the side surfaces of the post material 31. The end surface of the upper end of the post material 31 is not covered by the insulating layer 12. That is, the insulating layer 12 is formed so that the upper surface 12F of the insulating layer 12 is lower than the end surface of the upper end of the post material 31. Here, the height from the upper surface 11F of the conductor layer 11 to the upper surface 12F of the insulating layer 12 is approximately equal to the height h from the lower end to the upper end of the via conductor 21 (see FIG. 1) to be formed.
[0022] The insulating layer 12 is formed by applying and curing a fluid interlayer material. For example, an epoxy resin or the like can be suitably used as such an interlayer material. By using a fluid interlayer material, even when via conductors 21 with a relatively high aspect ratio are arranged at a fine pitch, i.e., when high-aspect-ratio post materials 31 are formed at high density on the conductor layer 11, the spaces between the post materials 31, the side surfaces of the post materials 31, and the top surface 11F and side surfaces of the conductor layer 11 that are not covered by the post materials 31 can be well covered with the interlayer material without forming voids between the post materials 31 and the side surfaces.
[0023] In the method for manufacturing a wiring board according to the embodiment, upper surface 12F of insulating layer 12 is formed to be lower than the end face of the upper end of post material 31. Because insulating layer 12 does not cover post material 31, a step such as polishing is not required to expose the end face of the upper end of post material 31 from insulating layer 12. This reduces the number of steps in manufacturing wiring board 1, and therefore can improve the manufacturing yield of wiring boards.
[0024] Next, as shown in FIG. 2C , the post material 31 is removed so that the upper surface 11F of the conductor pad 11p is exposed from the insulating layer 12. For example, the end face of the upper end of the post material 31 is brought into contact with a dissolving liquid. This dissolves at least a portion of the post material 31. The partially dissolved post material 31 is removed from the insulating layer 12. A via hole (through hole 12a) is formed in the insulating layer 12. For example, a permanganic acid solution or the like can be used as the dissolving liquid. A permanganic acid solution or the like can dissolve the polymer resin of the post material 31, so that the post material 31 can be removed from the insulating layer 12. Note that the post material 31 does not need to be completely dissolved by the dissolving liquid; it is sufficient that the post material 31 is dissolved to an extent that it can be removed from the insulating layer 12.
[0025] In the wiring board manufacturing method of the embodiment, since the insulating layer 12 is formed using a fluid interlayer material, it is believed that problems such as poor flow of resin material between adjacent post materials 31 are unlikely to occur. It is believed that even small-diameter via holes (through holes 12a) can be formed with high precision. Furthermore, it is believed that the use of a fluid interlayer material can achieve good flatness on the surface of the interlayer material after lamination. Since the insulating layer 12 is formed to a thickness that does not cover the upper end of the post material 31, after lamination of the insulating layer 12, the post material 31 can be directly subjected to a dissolving process using a dissolving liquid. It is believed that via holes (through holes 12a) can be manufactured efficiently with few steps.
[0026] In the wiring board manufacturing method of the embodiment, the via hole (through hole 12a) is formed by removing the post material 31 from the insulating layer 12. Therefore, the via hole (through hole 12a) can be formed in a desired shape by appropriately selecting the shape of the post material 31 and forming the post material 31. For example, the via hole (through hole 12a) may be formed with approximately the same diameter from the conductor layer 11 side to the top surface 12F side of the insulating layer 12, as shown in FIG. 2C , or may be formed so that the angle formed between the side surface of the through hole 12a and the top surface 11F of the conductor layer 11 is 90° or more and 115° or less. It is believed that finer via holes (through holes 12a) can be formed with high precision compared to a through hole formation process using laser processing, which forms tapered through holes. The hole diameter of the via hole (through hole 12a) on the conductor layer 11 side is equal to the via diameter d of the via conductor 21 (the diameter of the via conductor 21 on the upper surface 11F of the lower conductor layer 11 to which the via conductor 21 is connected), and is approximately 1 μm or more and approximately 20 μm or less.
[0027] 2D , a metal film layer 22 is formed on the upper surface 11F of the conductor pad 11p exposed from the insulating layer 12 and on the surface of the insulating layer 12 by electroless plating, sputtering, or the like. Preferably, the metal film layer 22 is a sputtering film formed by sputtering. The metal film layer 22 covers the upper surface 12F of the insulating layer 12, the inner wall surface of the through hole 12a, and the bottom surface of the through hole 12a formed by the upper surface 11F of the conductor pad 11p exposed from the insulating layer 12.
[0028] Next, as shown in FIG. 2E, via conductors 21 and a conductor layer 13 are formed. A resist (not shown) is applied onto the metal film layer 22 to form a resist layer (not shown) with a predetermined pattern. Subsequently, a plating film layer 23 is formed by electrolytic plating in the areas not covered by the resist layer. The resist layer is then removed, and the metal film layer 22 exposed by the removal is then removed by an etching process. As a result, the plating film layer 23 is filled into the through hole 12a to form the via conductor 21, and the conductor layer 13 is formed on the upper surface 12F of the insulating layer 12.
[0029] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to the drawings. The conditions and order of the manufacturing method described above may be changed as appropriate. Depending on the structure of the wiring board to be manufactured, some of the steps described above may be omitted, or any other steps may be added in addition to the steps described above. [Explanation of symbols]
[0030] 1. Wiring board 10, 12 Insulation layer 11, 13 Conductor layer 11p contact pad 12a Through hole (via hole) 21 Via conductor 22 Metal film layer 23 Plating film layer 31 Post material
Claims
1. forming a first conductor layer including a conductor pad on the first insulating layer; forming a post material on the conductive pad using a photosensitive resin; forming a second insulating layer on the first insulating layer so as to cover the first conductor layer and only a portion of the side surface of the post material; removing the post material from the second insulating layer using a dissolving liquid that dissolves the post material, thereby forming a via hole in the second insulating layer so that the conductive pad is exposed from the second insulating layer; and filling the via hole with a conductor to form a via conductor so as to contact the conductor pad; A method for manufacturing a wiring board, comprising:
2. 2. The method for manufacturing a wiring board according to claim 1, Forming the second insulating layer includes applying a flowable interlayer material onto the first insulating layer.
3. 2. The method for manufacturing a wiring board according to claim 1, Filling the via holes with conductors includes forming a second conductor layer on the upper surface of the second insulating layer, the second conductor layer being electrically connected to the first conductor layer through the via conductors.
4. 2. The method for manufacturing a wiring board according to claim 1, Forming a post material using the photosensitive resin forming a photosensitive resin layer by stacking a photosensitive resin that is cured by ultraviolet light on the first insulating layer and the conductive pads; irradiating the ultraviolet light onto a portion of the photosensitive resin layer where the post material is to be formed, thereby hardening the photosensitive resin and forming the post material; Contains:
5. 2. The method for manufacturing a wiring board according to claim 1, Forming the post material includes forming the post material so that the diameter is approximately the same from the bottom end of the post material that contacts the conductive pad to the top end opposite the bottom end.
6. 2. The method for manufacturing a wiring board according to claim 1, Forming the post material includes forming the post material so that the angle formed between the side surface of the post material and the top surface of the first conductor layer is 90° or more and 115° or less.
7. 2. The method for manufacturing a wiring board according to claim 1, The via hole is formed so that the via diameter of the via conductor on the first conductor layer side is 1 μm or more and 20 μm or less.
8. 2. The method for manufacturing a wiring board according to claim 1, The via hole is formed so that the aspect ratio of the via conductor is 0.5 or more and 5 or less.
Citation Information
Patent Citations
Printed-wiring board and method for manufacturing the same
JP2017073514A