Bottom surface emitting vertical cavity surface emitting laser

Abstract

To provide a bottom surface emitting vertical cavity surface emitting laser (BSE VCSEL) with a lithographically defined aperture.SOLUTION: The BSE VCSEL may be oxide-free. Two contacts are located above a substrate. An aperture and one or more active regions are located between two DBRs. A first contact is coupled to the substrate and the first DBR, which is below the aperture. A second contact is coupled to the second DBR, which is above the aperture.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001]

[0001] The limitations and drawbacks of conventional bottom-emitting vertical-cavity surface-emitting laser (BSE VCSEL) devices will become apparent to those skilled in the art through a comparison of such approaches with certain aspects of the present methods and systems described in the remainder of this disclosure with reference to the drawings. Summary of the Invention

[0002]

[0002] Systems and methods, as more fully set forth in the claims, provide a BSE VCSEL device having an aperture defined using lithography substantially as illustrated by and / or described in connection with at least one of the figures. [Brief explanation of the drawings]

[0003] [Figure 1]

[0003] FIG. 1 is a diagram of an example single-junction BSE VCSEL having a lithographically defined aperture, in accordance with various example implementations of this disclosure. [Figure 2]

[0004] 1 is a diagram of an example array of two single-junction BSE VCSELs with lithographically defined apertures, in accordance with various example implementations of this disclosure. [Figure 3]

[0005] 1 is a diagram of a first example multi-junction BSE VCSEL having a lithographically defined aperture in accordance with various example implementations of this disclosure. FIG. [Figure 4]

[0006] FIG. 10 is a diagram of a second example multi-junction BSE VCSEL having a lithographically defined aperture in accordance with various example implementations of this disclosure. [Figure 5]

[0007] FIG. 10 is a diagram of a third example multi-junction BSE VCSEL having a lithographically defined aperture in accordance with various example implementations of this disclosure. [Figure 6]

[0008] FIG. 10 is a diagram of a fourth example multi-junction BSE VCSEL having a lithographically defined aperture in accordance with various example implementations of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0004]

[0009] This disclosure describes a bottom-emitting vertical-cavity surface-emitting laser (BSE VCSEL) with a lithographically defined aperture. The system and method provide a BSE VCSEL with a lithographically defined aperture that allows for small emitter spacing.

[0005]

[0010] VCSELs with lithographically defined apertures have better mode content control and reliability. In addition, lithographically defined apertures allow for smaller emitter spacing. The apertures in existing BSE VCSEL devices are sometimes defined by an oxidation process of AlInGaAs. Oxide apertures have the disadvantage of requiring larger emitter spacing in the array due to the added oxidation distance. Therefore, the disclosed BSE VCSELs can have oxide-free apertures.

[0006]

[0011] When the disclosed BSE VCSEL designs include oxide-free apertures, the emitter spacing can be smaller than in conventional oxide-based BSE VCSELs, and therefore there is no need for oxide spacing in the disclosed oxide-free BSE VCSEL designs.

[0007]

[0012] The disclosed BSE VCSEL design allows for precise optical aperture (OA) and mode control. High repeatability of aperture shape and size allows for small apertures. This allows for manufacturability of BSE VCSELs with a minimum aperture (e.g., greater than 0.5 μm). The aperture in a BSE VCSEL may be defined using lithography, allowing for precision down to 10 nm. The aperture may be defined through a tunnel junction (Tj) for gain guiding. Alternatively, the aperture may be defined through an index step for index guiding.

[0008]

[0013] The mode shape and content may be designed and tailored to the optical requirements of the rear side. Various circular or polygonal (e.g., triangular, rectangular, hexagonal) shapes of the OA may be defined using lithography. The placement and number of apertures is design dependent.

[0009]

[0014] Lithographically defined aperture implementations may be applied to both single-junction and multi-junction BSE VCSELs. One or more apertures may be designed and lithographically defined to obtain the desired mode content and divergence angle at the device output. Each aperture may be defined within the tunnel junction layer or through an index step.

[0010]

[0015] The disclosed BSE VCSEL designs can enable improved current spreading compared to top-emitters. The disclosed BSE VCSEL designs can also enable larger apertures that can be manufactured. Such large apertures (e.g., >100 μm) enable higher optical output power. The disclosed BSE VCSEL designs can enable improved reliability due to the absence of an oxide layer. The disclosed BSE VCSEL designs can enable electrical connections on the opposite side from the optical output, which simplifies vertical integration. The disclosed BSE VCSEL designs can enable superior over-temperature performance due to improved heat dissipation.

[0011]

[0016] FIG. 1 illustrates an example single-junction BSE VCSEL with a lithographically defined aperture, according to various example implementations of this disclosure.

[0017] The single-junction BSE VCSEL of Figure 1 comprises a substrate 101, an n-contact 103, an n-distributed Bragg reflector (nDBR) 105, an aperture 107, an active region 1091, a p-DBR 113, and a p-contact 115. The n-contact 103 is bonded to the side of the n-DBR 105. The substrate 101 may be semi-insulating (SI). The substrate 101 may be coated on the bottom side with an anti-reflection (AR) coating 119. The substrate 101 may be coated on the top side with a current spreading layer 117 adjacent to the n-contact 103 and the n-DBR 105. Light is output from the bottom of the BSE VCSEL as shown.

[0012]

[0018] 2 illustrates an example array of two single-junction BSE VCSELs with lithographically defined apertures, according to various example implementations of this disclosure. The array may comprise two or more light emitters.

[0013]

[0019] Each single-junction BSE VCSEL (emitter) in FIG. 2 includes an n-contact 103, an n-DBR 105, an aperture 107, an active region 1091, a p-DBR 113, and a p-contact 115. The n-contact 103 is coupled to the side of the n-DBR 105. The substrate 101 may be semi-insulating. All of the single-junction BSE VCSELs in the array may be mounted on a single substrate 101. The single substrate 101 may be covered on the bottom side with an AR coating 119. The substrate 101 may be covered on the top side with a current spreading layer 117 adjacent to each n-contact 103 and each n-DBR 105. The current spreading layer 117 under each emitter is not electrically coupled to the current spreading layer 117 under every other emitter. Light from all of the BSE VCSELs in the array is output from the bottom of the BSE VCSEL as shown.

[0014]

[0020] FIG. 3 illustrates a first example multi-junction BSE VCSEL having a lithographically defined aperture according to various example implementations of this disclosure.

[0021] The multi-junction BSE VCSEL of FIG. 3 includes a substrate 101, an n-contact 103, an n-DBR 105, an aperture 107, and one or more tunnel junctions (Tjs) 1111-111. m-1 Multiple active regions 1091-109 separated by m The multi-junction BSE VCSEL comprises an n-contact 103, a p-DBR 113, and a p-contact 115. The n-contact 103 is bonded to the side of the n-DBR 105. The substrate 101 may be semi-insulating. The substrate 101 may be covered on the bottom side with an AR coating 119. The substrate 101 may be covered on the top side with a current spreading layer 117 adjacent to the n-contact 103 and the n-DBR 105. Light is output from the bottom of the multi-junction BSE VCSEL as shown.

[0015]

[0022] FIG. 4 illustrates a second example multi-junction BSE VCSEL having a lithographically defined aperture in accordance with various example implementations of this disclosure.

[0023] The multi-junction BSE VCSEL of FIG. 4 includes a substrate 101, an n-contact 103, an n-DBR 105, an aperture 107, and one or more tunnel junctions (Tjs) 1111-111. m-1 Multiple active regions 1091-109 separated by m 4 includes a p-contact 115, a p-DBR 113, and a p-contact 115. The substrate 101 may be semi-insulating. The substrate 101 may be coated on the bottom side with an AR coating 119. The multi-junction BSE VCSEL of FIG. 4 includes an intra-cavity n-contact 103. The substrate 101 in FIG. 4 is directly bonded to the n-DBR 105, and the n-contact 103 is located on top of the n-DBR 105. Light is output from the bottom of the multi-junction BSE VCSEL as shown.

[0016]

[0024] FIG. 5 illustrates a third example multi-junction BSE VCSEL having a lithographically defined aperture in accordance with various example implementations of this disclosure.

[0025] The multi-junction BSE VCSEL of FIG. 5 includes a substrate 101, an n-contact 103, an n-DBR 105, an aperture 107, and one or more tunnel junctions (Tjs) 1111-111. m-1 Multiple active regions 1091-109 separated by m 5, the n-contact 103 is planarized through an n-via 121. A passivation layer 123 isolates the n-contact 103 from the p-contact 115. The substrate 101 may be semi-insulating. The substrate 101 may be covered on the bottom side by an AR coating 119. In the multi-junction BSE VCSEL of FIG. 5, the n-contact 103 is planarized through an n-via 121. A passivation layer 123 isolates the n-contact 103 from the p-contact 115. The substrate 101 may be covered on the top side by a current spreading layer 117 adjacent to the n-via 121 and the n-DBR 105. Light is output from the bottom of the multi-junction BSE VCSEL as shown.

[0017]

[0026] FIG. 6 illustrates a fourth example multi-junction BSE VCSEL having a lithographically defined aperture in accordance with various example implementations of this disclosure.

[0027] The multi-junction BSE VCSEL of FIG. 6 includes a substrate 101, a first n-contact 1031, a second n-contact 1032, a first n-DBR 1051, a second n-DBR 1052, an aperture 107, and a plurality of active regions 1091-109. m and multiple tunnel junctions (Tjs) 1111~111 m6. Each tunnel junction converts electrons into holes to create a p-region between the tunnel junction and the active region. The substrate 101 may be semi-insulating. The substrate 101 may be covered on the bottom side by an AR coating 119. In the multi-junction BSE VCSEL of FIG. 6, a first n-contact 1031 is coupled to the side of the first n-DBR 1051 below the aperture 107, and a second n-contact 1032 is coupled to the top surface of the second n-DBR 1052 above the aperture 107. The substrate 101 may be covered on the top side by a current spreading layer 117 adjacent to the first n-contact 103 and the first n-DBR 105. Light is output from the bottom of the multi-junction BSE VCSEL as shown.

[0018]

[0028] As used herein, the terms "circuits" and "circuitry" refer to physical electronic components (i.e., hardware) as well as any software and / or firmware ("code") that may comprise, be executed by, or otherwise be associated with hardware. As used herein, for example, a particular processor and memory may include a first "circuit" when executing a first one or more lines of code, and a second "circuit" when executing a second one or more lines of code. As used herein, "and / or" means any one or more of the items in the list connected by "and / or." By way of example, "x and / or y" means any element of the triplet {(x), (y), (x, y)}. As another example, "x, y, and / or z" means any element of the seven-element set {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}. As used herein, the term "exemplary" means serving as a non-limiting example, instance, or illustration. As used herein, the terms "e.g.," and "for example" start from a list of one or more non-limiting examples, instances, or illustrations. As used herein, circuitry is "operable" to perform a function whenever the circuitry includes the necessary hardware and code (if either is necessary) to perform the function, regardless of whether the function's capabilities are disabled or not enabled (e.g., by user-configurable settings, factory trims, etc.). As used herein, the term "based on" means "based at least in part on." For example, "x based on y" means that "x" is based at least in part on "y" (and may also be based on, for example, z).

[0019]

[0029] While the present method and / or system has been described with reference to certain implementations, those skilled in the art will recognize that various changes may be made and equivalents may be substituted without departing from the scope of the present method and / or system. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from the scope of the present disclosure. Therefore, the present method and / or system is not limited to the particular implementations disclosed, but it is intended that the present method and / or system will include all implementations that fall within the scope of the appended claims. [Explanation of symbols]

[0020] 101 Substrate 103 n contact 1031 first n contact 1032 second n contact 105 nDBR 1051 First nDBR 1052 Second nDBR 107 Aperture 109 Active region 1091 active area 1092 active area 109 m active area 111 Tunnel Junction 1111 tunnel junction 111 m-1 tunnel junction 111 m tunnel junction 113 pDBR 115p contacts 117 Current Diffusion Layer 119 AR coating 121 n-via 123 Passivation Layer

Claims

1. 1. A system comprising a first bottom-emitting vertical-cavity surface-emitting laser (BSE VCSEL), the first BSE VCSEL comprising: a substrate operable to output an optical signal from a bottom side; A first contact; a first distributed Bragg reflector (DBR) operably coupled to the top side of the substrate and to the first contact; a first aperture directly coupled to a top side of the first DBR, the first aperture being defined using lithography; a first active region directly coupled to a top side of the first aperture; a second DBR operatively coupled to a top side of the first active region; a second contact directly coupled to the top surface side of the second DBR; A system comprising:

2. The system of claim 1 , wherein the substrate is semi-insulating.

3. 10. The system of claim 1, wherein the substrate is covered on the bottom side with an anti-reflective coating.

4. The system of claim 1 , wherein the substrate is covered on the top side by a current spreading layer.

5. 10. The system of claim 1, the first contact is an n-contact; the second contact is a p-contact; system.

6. 10. The system of claim 1, the first DBR is an nDBR; the second DBR is a pDBR; system.

7. 10. The system of claim 1, the first contact is an n-contact; the second contact is an n-contact; system.

8. 10. The system of claim 1, the first DBR is an nDBR; the first BSE VCSEL comprises a tunnel junction above the first active region; the second DBR is an nDBR; the second DBR is directly coupled to the tunnel junction; system.

9. 10. The system of claim 1, comprising a second BSE VCSEL, the second BSE VCSEL comprising: a third contact operably coupled to a top side of the substrate; a third DBR operably coupled to the top side of the substrate; a second aperture directly coupled to the top surface side of the third DBR; a second active region directly coupled to the top side of the second aperture; a fourth DBR operatively coupled to a top side of the second active region; and a fourth contact directly coupled to the top surface side of the fourth DBR; A system comprising:

10. 10. The system of claim 9, wherein the substrate is covered on the top side by a current spreading layer, and the current spreading layer under the first DBR is separated from the current spreading layer under the third DBR.

11. 10. The system of claim 1, the first BSE VCSEL comprises a plurality of active regions; the plurality of active regions comprises the first active region; the active regions are separated by tunnel junctions; system.

12. 10. The system of claim 1, wherein the first contact is directly coupled to a top side of the first DBR.

13. The system of claim 1 , wherein the shape of the aperture is one of a circle and a polygon.

14. 10. The system of claim 1, wherein the aperture is defined for gain guiding through a tunnel junction.

15. 10. The system of claim 1, wherein the aperture is defined for index guiding via an index step.

16. 10. The system of claim 1, wherein the aperture is greater than 0.5 μm.

17. 10. The system of claim 1, the first contact is planarized through a via; the first BSE VCSEL includes a passivation layer isolating the first contact from the second contact; system.

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