Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a technology capable of suppressing poor embedding of a metal layer into depressions within an alloy layer and improving the bond strength between the metal layer and the alloy layer.SOLUTION: A semiconductor device comprises a semiconductor substrate 10, an alloy layer 20 formed on the semiconductor substrate 10 and containing the semiconductor material of the semiconductor substrate 10 as its main component, and a metal layer 30 provided on the alloy layer 20. A plurality of recesses 31 are provided discretely on the surface of the metal layer 30 side within the alloy layer 20, and 90% or more of the plurality of recesses 31 exhibit a mortar-like shape, where the opening width of each recess 31 monotonically decreases as it progresses deeper.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor device in which discrete recesses are provided on the surface of an electrode (corresponding to an alloy layer) provided on a semiconductor chip (corresponding to a semiconductor substrate) to increase the adhesion strength with a first bonding metal (corresponding to a metal layer) provided thereon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 246241 [Non-patent literature]

[0004] [Non-Patent Document 1] “Inert gas bubble formation in magnetron sputtered thin-film CdTe solar cells” Peter Hatton, et al., Proc. Of the royal soc. A, vol 476, issue 2239 Summary of the Invention [Problem to be solved by the invention]

[0005] The technology described in Patent Document 1 utilizes a phenomenon specific to the plating process to form depressions on the surface of the alloy layer. In the plating process, depressions are easily formed by selective etching or corrosion of the agglomerated layer.

[0006] However, in the technology described in Patent Document 1, since the recesses are formed in a plating process, it is difficult to control the opening shape of the recesses, and if the width of the opening of the recess is smaller than the width of the depth of the recess, the metal layer may not be sufficiently embedded in the recesses, resulting in a problem of reduced adhesion strength between the metal layer and the alloy layer.

[0007] Therefore, an object of the present disclosure is to provide a technique that can suppress insufficient filling of a metal layer into a recess in an alloy layer and improve the adhesive strength between the metal layer and the alloy layer. [Means for solving the problem]

[0008] The semiconductor device according to the present disclosure comprises a semiconductor substrate, an alloy layer provided on the semiconductor substrate and containing the semiconductor material of the semiconductor substrate as a main component, and a metal layer provided on the alloy layer, wherein a plurality of recesses are discretely provided on the surface of the alloy layer facing the metal layer, and 90% or more of the plurality of recesses are funnel-shaped, with the opening width of each recess monotonically decreasing as the recess progresses deeper. [Effects of the Invention]

[0009] According to the present disclosure, the opening width of each recess monotonically decreases as it goes deeper, which can suppress insufficient filling of the metal layer into the recess of the alloy layer, thereby improving the adhesion strength between the metal layer and the alloy layer. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] 2 is a schematic cross-sectional view of a contact region of the semiconductor device according to the embodiment; [Figure 4] 10 is a diagram showing a cross-sectional TEM image of a contact region of the semiconductor device according to the embodiment. FIG. [Figure 5]FIG. 4(b) is an enlarged view of a part of FIG. 4(a) with dimensions indicated. [Figure 6] 1A and 1B show elemental maps of Si (a) and Ar (b). [Figure 7] FIG. 1 shows EDX spectra of Si and Ar. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Embodiment> DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following describes embodiments with reference to the accompanying drawings. Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. In the following description, n and p represent the conductivity types of the semiconductor.

[0012] As shown in FIG. 1, the semiconductor device is a power semiconductor device and includes a semiconductor substrate 10, an alloy layer 20, and a metal layer 30. The alloy layer 20 is provided on the semiconductor substrate 10. The alloy layer 20 contains the semiconductor element of the semiconductor substrate 10 as a main component and has a thickness t1. The metal layer 30 is provided on the alloy layer 20. A plurality of recesses 31 are provided discretely on the surface of the alloy layer 20 facing the metal layer 30. Hereinafter, the "surface of the alloy layer 20 facing the metal layer 30" will also be simply referred to as the "surface of the alloy layer 20."

[0013] Of the multiple recesses 31, 90% or more of the recesses 31 have a cone shape in which the opening width of each recess 31 monotonically decreases with increasing depth. Here, the cross-sectional opening width varies depending on the cut location of the recess 31, and the opening width w2 refers to the widest opening width. Similarly, the cross-sectional depth varies depending on the cut location of the recess 31, and the depth t2 refers to the deepest depth. Note that "monotonically decreasing" refers to a shape in which the width substantially narrows with increasing depth, and may include localized unevenness such as roughness, as long as the boundary portions of the recesses form, on average, a part of an ellipse.

[0014] The semiconductor material of the semiconductor substrate 10 may be a compound containing Si, SiC, or Ga. An n-type layer or a p-type layer selectively activated with a dopant or acceptor may also be present in the semiconductor substrate 10. Furthermore, the alloy layer 20 may be in contact with the n-type layer, the p-type layer, or both, or may be alloyed with the semiconductor material including the n-type layer, the p-type layer, or both.

[0015] The alloy layer 20 may be formed by chemically reacting a pre-alloying metal film 21 (see FIG. 2(a)) deposited by sputtering or chemical vapor deposition (CVD) through heat treatment. In this case, the alloy layer 20 contains, as its main components, a semiconductor element and the constituent elements of the pre-alloying metal film 21. The pre-alloying metal film 21 contains, for example, Ti, Ni, or Co as its main component. The alloy layer 20 preferably has a composition containing at least 20% or more of the semiconductor material of the semiconductor substrate 10. In particular, when the semiconductor material of the semiconductor substrate 10 is Si or SiC, the alloy layer 20 is preferably composed of a silicide. More preferably, the alloy layer 20 may be composed of a silicide containing Ti or Ni.

[0016] The metal layer 30 may be formed by sputtering or CVD. In this case, the metal layer 30 may be composed of Ti, Ni, W, Cu, Al, or an alloy containing any of these. More preferably, the metal layer 30 may be composed of a metal containing TiN or Al as its main component, or a laminated metal of a metal containing TiN as its main component and a metal containing Al as its main component. An upper metal layer 40 (see FIG. 3) composed of a different component from the metal layer 30 may be provided on top of the metal layer 30.

[0017] The recesses 31 are formed discretely on the surface of the alloy layer 20, eroding the alloy layer 20. The thickness t1 of the alloy layer 20 is, for example, 10 nm to 50 nm, and the depth t2 of the recesses 31 is, for example, 5 nm to t1. The opening width w2 of the recesses 31 is, for example, 5 nm to 100 nm. The metal layer 30 is filled inside the recesses 31, and no rough regions are formed in which the atomic density of the elements constituting the alloy layer 20 or the metal layer 30 is less than 99.0 wt% as determined by a common elemental analysis method such as energy dispersive X-ray spectroscopy (EDX). In other words, the atomic density of the elements constituting the alloy layer 20 or the metal layer 30 at the interface between the alloy layer 20 and the metal layer 30 is 99.0 wt% or more. This creates an anchor effect at the interface between the metal layer 30 and the alloy layer 20, increasing adhesion strength.

[0018] On the other hand, since no rough regions with reduced atomic density are formed, the contact resistance does not deteriorate. Furthermore, by controlling the size of the recess 31 to the order of nanometers, it is possible to form a contact region with a width of less than 1.0 μm in a power semiconductor device. By controlling the depth t2 of the recess 31 so that it does not exceed the thickness t1 of the alloy layer 20, only the alloy layer 20 comes into contact with the semiconductor substrate 10, maintaining good ohmic contact.

[0019] Next, a method for manufacturing a semiconductor device will be described. Figures 2(a) to 2(d) are schematic cross-sectional views for explaining the method for manufacturing a semiconductor device according to an embodiment.

[0020] 2(a), a metal containing an inert gas is deposited on a semiconductor substrate 10 by sputtering or CVD to form a metal film 21 before alloying. Next, the metal film 21 formed on the semiconductor substrate 10 is heat-treated to cause a chemical reaction between the semiconductor substrate 10 and the metal film 21, thereby forming an alloy layer 20. At this time, a region 32 with reduced atomic density can be formed on the surface of the alloy layer 20 by using the technique described below.

[0021] As an example, a case where the metal film 21 before alloying is formed by sputtering will be described. Sputtering is generally a film formation method in which a chamber is filled with a certain proportion of inert gas, which is then converted into plasma and bombarded with a target metal, physically breaking the bonds between the atoms of the target metal, ionizing (activating) the metal atoms and depositing them on the semiconductor substrate 10. During this process, the semiconductor substrate 10 contains not only the desired metal ions but also trace amounts of inert gas ions that have been converted into plasma. In conventional manufacturing methods, the content of inert gas ions is low, so that during heat treatment the inert gas ions either volatilize and disappear, or are incorporated into the alloy layer 20 without agglomerating.

[0022] Here, when the concentration of the inert gas contained in the metal film 21 before alloying is increased, a region 32 with reduced atomic density is formed on the surface of the alloy layer 20 after heat treatment, as shown in Figure 2(b). It is known that the region 32 with reduced atomic density has a reduced mass percent concentration of the atoms constituting the alloy layer 20 and a high content of inert gas (see Figures 4 to 7). That is, the inert gas aggregates during heat treatment, forming a coarse region with reduced atomic density.

[0023] Next, as shown in Fig. 2(c), a surface etching process is performed. Specifically, the surface of the alloy layer 20 including the region 32 with reduced atomic density is subjected to a dry etching process or a wet etching process to remove the region 32 with reduced atomic density and form a recessed region having a plurality of recesses 31.

[0024] Next, as shown in Figure 2(d), a metal that will become the metal layer 30 is deposited on the alloy layer 20 including the recessed region to obtain the desired thickness of the metal layer 30, and the metal layer 30 is filled into the recess 31. By forming the recess 31 filled with the metal layer 30, an anchor effect acts, increasing the adhesion strength. Furthermore, by eliminating the region 32 with reduced atomic density, it is possible to suppress the deterioration of contact resistance.

[0025] The phenomenon in which the inert gas contained in the metal film 21 aggregates upon heat treatment to form a region 32 with reduced atomic density is generally known and is described, for example, in Non-Patent Document 1. When this phenomenon is applied to a semiconductor device, it is preferable that the region 32 with reduced atomic density can be controlled to a desired width, depth, density, and position. If the region 32 with reduced atomic density is too wide, it may occupy the entire contact region of the power semiconductor device, resulting in a thin thickness t1 of the alloy layer 20.

[0026] Furthermore, if the depth of the region 32 with reduced atomic density is too deep, good ohmic contact cannot be obtained due to contact between the metal layer 30 and the semiconductor substrate 10, and the contact resistance increases. Furthermore, if the occupancy rate of the region 32 with reduced atomic density is too high, the thickness t1 of the alloy layer 20 becomes thin, as in the case where the opening width w2 of the recess 31 is widened.

[0027] Furthermore, if the region 32 with reduced atomic density is not formed on the surface of the alloy layer 20 but is formed inside the alloy layer 20, the depression 31 will not be formed by the surface etching process. Therefore, it is important to control the region 32 with reduced atomic density to a desired width, depth, density, and position.

[0028] Next, a method for controlling the region 32 with reduced atomic density will be described. As described above, the region 32 with reduced atomic density is formed by the aggregation of the inert gas. In other words, it is necessary to control the amount of inert gas contained in the metal film 21 before alloying. In sputtering, the amount of inert gas taken in can be controlled by adjusting the pressure in the chamber, adjusting the plasma density, adjusting the voltage required to attract active species to the semiconductor substrate 10, and the like.

[0029] The pressure inside the chamber is adjusted by the flow rate of the inert gas, for example, in the range of 1 sccm to 100 sccm. One of the parameters for adjusting the plasma density is the DC bias, which is adjusted, for example, in the range of 1 kW to 50 kW. The voltage required to attract active species is adjusted by the AC bias, for example, in the range of 1 W to 1 kW. The temperature during film formation is, for example, from room temperature to 500°C. These parameters are adjusted so that the designer can form the cone-shaped depressions 31 whose opening width monotonically decreases with depth. It is preferable that all of the multiple depressions 31 have the above shape, but if 90% or more of the multiple depressions 31 have the above shape, an increase in adhesion strength due to the anchor effect can be expected.

[0030] Furthermore, the thicker the metal film 21 before alloying, the greater the amount of inert gas atoms that aggregate at the interface between the metal film 21 and the semiconductor substrate 10, so a thicker metal film 21 is preferable. On the other hand, if the thickness of the metal film 21 before alloying is too thick, the thickness of the alloy layer 20 tends to increase accordingly. In this case, the alloy layer 20 cannot contact the n-type layer or p-type layer in which the impurities are activated, resulting in increased contact resistance. Therefore, the thickness of the alloy layer 20 is limited, for example, to 30 nm or more and 50 nm or less.

[0031] Furthermore, the heat treatment performed after depositing the pre-alloyed metal film 21 can also be an important parameter. If the heat treatment is performed at a high temperature for a long time, the aggregation of the inert gas accelerates, causing the region 32 with reduced atomic density to become too large. This increases the opening width w2 and depth t2 of the recess 31, preventing the desired shape from being obtained and resulting in a deterioration in contact resistance. The heat treatment conditions are preferably, for example, between 700°C and 900°C, and between 10 and 120 seconds. The control parameters for the heat treatment must also be adjusted so that the designer can obtain the recess 31 desired.

[0032] The metal film 21 before alloying may be deposited by a CVD method. In this case, unlike the sputtering method, an inert gas is not introduced during the deposition of the metal film 21, so it is necessary to introduce the inert gas, for example, by an ion implantation method, after the deposition of the metal film 21. Even if the inert gas is introduced after the deposition of the metal film 21, the inert gas will aggregate due to the heat treatment, and a region 32 with a reduced atomic density will be formed.

[0033] Here, the inert gas is Ar, N, or a rare gas element. The concentration of the inert gas contained at the interface between the metal layer 30 and the alloy layer 20 is preferably equal to or lower than the concentration of the inert gas contained in the bulk of the semiconductor substrate 10.

[0034] Next, the structure of a contact region, which is a part of the semiconductor device, will be described. Fig. 3 is a schematic cross-sectional view of a contact region of a semiconductor device according to an embodiment. The contact region is an emitter contact region or a source contact region.

[0035] As shown in FIG. 3 , the contact region of the semiconductor device is composed of a semiconductor substrate 10, an alloy layer 20, a metal layer 30, an upper metal layer 40, and an interlayer insulating film 50. A plurality of recesses 31 are provided discretely on the surface of the alloy layer 20 facing the metal layer 30. The interlayer insulating film 50 may be a TEOS film, a BPSG film, a thermal oxide film, or a laminated film thereof, and is formed to ensure insulation with the gate electrode (not shown). The bottom width w3 of the contact region is on the submicron order, for example, 0.2 μm to 1.0 μm, and the ratio of the bottom width w3 of the contact region to the thickness of the interlayer insulating film 50, in other words, the ratio of the thickness of the interlayer insulating film 50 to the bottom width w3 of the contact region, is, for example, 1.5 or greater. An n-type layer or a p-type layer may be selectively formed on the semiconductor substrate 10, and the alloy layer 20 is preferably in contact with the n-type layer or the p-type layer.

[0036] 4A and 4B are diagrams showing cross-sectional TEM images of the contact region of the semiconductor device according to the embodiment. Fig. 4A shows the cross-sectional structure when the surface etching process shown in Fig. 2C is not performed. Fig. 4B shows the cross-sectional structure when the region 32 with reduced atomic density is not formed.

[0037] The cross-sectional TEM image shown in Figure 4 is an atomic number contrast image, and for materials composed of the same elements, the darker the image, the lower the atomic density. When a metal layer 30 is formed without etching under conditions where the inert gas content and heat treatment conditions are adjusted, discrete regions 32 with reduced atomic density are formed, as shown in Figure 4(a). By performing an etching process on the surface of the alloy layer 20 including the regions 32 with reduced atomic density, the regions 32 with reduced atomic density are turned into depressions 31, and the metal layer 30 can be deposited in these depressions to obtain the structure shown in Figure 3.

[0038] On the other hand, if the content of the inert gas contained in the metal film 21 before alloying and the heat treatment conditions are not adjusted sufficiently, a region 32 with reduced atomic density will not be formed, as shown in Figure 4(b), and even if a surface etching process is performed on the alloy layer 20 in this state, a depression 31 will not be formed.

[0039] Figure 5 is an enlarged view of a portion of Figure 4(a) with dimensions indicated. As shown in Figure 5, by adjusting the inert gas elements contained in metal film 21 before alloying and the heat treatment conditions, we have successfully formed a region 32 with reduced atomic density, having an opening width of 35 nm and a depth of 10 nm. Figure 5 shows one example of an embodiment, and it is preferable that the opening width of recess 31 is, for example, 5 nm to 100 nm, and the depth of recess 31 is, for example, 5 nm or more and is equal to or less than thickness t1 of alloy layer 20.

[0040] 6A and 6B are diagrams showing elemental maps of Si (a) and Ar (b). Specifically, Fig. 6A shows an elemental map of Si, and Fig. 6B shows an elemental map of Ar.

[0041] The metal layer 30 does not contain Si as a constituent element, but the alloy layer 20 and the semiconductor substrate 10 contain Si as constituent elements. Therefore, as shown in FIG. 6(a), the metal layer 30 is depicted with a darker contrast in the Si element map. Although the upper metal layer 40 does not contain Si, the EDX spectrum confirms that the contrast is due to the large background noise. The region indicated by the dashed line is a region 32 where the atomic density of Si, a constituent element of the alloy layer 20, is reduced.

[0042] 6(b), the region indicated by the dashed line shows a high Ar atom density. The contrast of the upper metal layer 40 in FIG. 6(b) was also confirmed to be background noise. As will be described later, the contrast of the region 32 with reduced atomic density shows an EDX spectrum peak for Ar that is significantly higher than the background noise. Therefore, this region is a region where the concentrations of the alloy-constituting elements are low and the atomic concentration of the inert gas is high.

[0043] 7A and 7B are diagrams showing EDX spectra of Si and Ar, specifically, Fig. 7A is a diagram showing the EDX spectrum of Si, and Fig. 7B is a diagram showing the spectrum of Ar.

[0044] 7(a) and (b), the thick line is the spectrum of the alloy layer 20 including the region 32 with reduced atomic density, and the thin line is the spectrum of the alloy layer 20 without the region 32 with reduced atomic density. It can be seen that the peak intensity of the semiconductor elements is reduced and that the Ar element is significantly detected.

[0045] Here, the Si atom density in the region 32 where the atom density is reduced is reduced by about 20%. By forming the metal layer 30 after etching the surface of the alloy layer 20, the region 32 where the atom density is reduced becomes a depression 31 filled with the metal layer 30, and no reduction in the atom density as shown in Figures 7(a) and (b) is observed. Therefore, the reduction in the atomic mass percent concentration (wt%) at the interface calculated from the EDX spectrum is considered to be at most less than 1.0%.

[0046] As described above, the semiconductor device according to the embodiment includes a semiconductor substrate 10, an alloy layer 20 provided on the semiconductor substrate 10 and containing the semiconductor material of the semiconductor substrate 10 as a main component, and a metal layer 30 provided on the alloy layer 20. A plurality of recesses 31 are provided discretely on the surface of the alloy layer 20 facing the metal layer 30, and 90% or more of the plurality of recesses 31 have a cone shape in which the opening width of each recess 31 monotonically decreases as the recess 31 advances deeper.

[0047] Therefore, the opening width of each recess 31 decreases monotonically as it goes deeper, which can suppress insufficient embedding of the metal layer 30 into the recess 31 of the alloy layer 20. This can improve the adhesion strength between the metal layer 30 and the alloy layer 20.

[0048] Furthermore, the opening width w2 of each recess 31 is 5 nm or more and 100 nm or less, the thickness t1 of the alloy layer 20 is 30 nm or more, and the depth t2 of each recess 31 is smaller than the thickness t1 of the alloy layer 20. Therefore, the deterioration of the contact resistance can be suppressed.

[0049] Furthermore, the concentration of the inert gas contained in the interface between the metal layer 30 and the alloy layer 20 is equal to or lower than the concentration of the inert gas contained in the bulk of the semiconductor substrate 10. Therefore, by forming an interface that does not contain an inert gas, it is possible to suppress a decrease in adhesion strength.

[0050] The inert gas contained in the interface between the metal layer 30 and the alloy layer 20 and in the bulk of the semiconductor substrate 10 is Ar or N. Therefore, by forming an interface that does not contain an inert gas, it is possible to suppress a decrease in adhesion strength.

[0051] Furthermore, since the atomic density of the elements constituting the alloy layer 20 is 99.0 wt % or more, a dense film is formed at the interface between the metal layer 30 and the alloy layer 20, thereby improving the adhesive strength.

[0052] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0053] Various aspects of the present disclosure are summarized below as appendices.

[0054] (Appendix 1) a semiconductor substrate; an alloy layer provided on the semiconductor substrate and containing the semiconductor material of the semiconductor substrate as a main component; a metal layer provided on the alloy layer, a plurality of recesses are discretely provided on a surface of the alloy layer facing the metal layer, A semiconductor device, wherein 90% or more of the recesses have a cone shape in which the opening width of each recess monotonically decreases as the recess goes deeper.

[0055] (Appendix 2) the opening width of each recess is 5 nm or more and 100 nm or less; The thickness of the alloy layer is 30 nm or more, 2. The semiconductor device of claim 1, wherein the depth of each recess is smaller than the thickness of the alloy layer.

[0056] (Appendix 3) an interlayer insulating film provided on the semiconductor substrate and having a contact region; 3. The semiconductor device according to claim 1, wherein the bottom width of the contact region is 0.2 μm or more and 1.0 μm or less.

[0057] (Appendix 4) 4. The semiconductor device according to claim 3, wherein a ratio of the bottom width of the contact region to a thickness of the interlayer insulating film is 1.5 or more.

[0058] (Appendix 5) 5. The semiconductor device according to claim 1, wherein the concentration of the inert gas contained at the interface between the metal layer and the alloy layer is equal to or lower than the concentration of the inert gas contained in the bulk of the semiconductor substrate.

[0059] (Appendix 6) 6. The semiconductor device according to claim 5, wherein the inert gas contained at the interface between the metal layer and the alloy layer and the inert gas contained in the bulk of the semiconductor substrate is Ar or N2.

[0060] (Appendix 7) 7. The semiconductor device according to claim 1, wherein the atomic density of the elements constituting the alloy layer is 99.0 wt % or more.

[0061] (Appendix 8) The semiconductor device according to any one of claims 1 to 7, wherein the metal layer is made of a metal primarily composed of TiN or Al, or a laminated metal of a metal primarily composed of TiN and a metal primarily composed of Al.

[0062] (Appendix 9) The semiconductor device for power, 9. The semiconductor device according to claim 1, wherein the semiconductor material of the semiconductor substrate is a compound containing Si, SiC, or Ga.

[0063] (Appendix 10) 10. The semiconductor device according to claim 1, wherein the alloy layer is made of a silicide containing Ti or Ni.

[0064] (Appendix 11) A metal film is formed by depositing a metal containing an inert gas on a semiconductor substrate by a sputtering method or a CVD method, forming an alloy layer by subjecting the metal film to a heat treatment; forming a region in which the atomic density of metal atoms or semiconductor atoms containing the inert gas is reduced on a surface of the alloy layer opposite to the semiconductor substrate; etching the surface of the alloy layer to form the region with reduced atomic density into a recessed region having a plurality of recesses; A method for manufacturing a semiconductor device includes depositing a metal to be a metal layer on the alloy layer including the recessed region. [Explanation of symbols]

[0065] 10 semiconductor substrate, 20 alloy layer, 21 metal film, 30 metal layer, 31 recess, 50 interlayer insulating film.

Claims

1. a semiconductor substrate; an alloy layer provided on the semiconductor substrate and containing the semiconductor material of the semiconductor substrate as a main component; a metal layer provided on the alloy layer, a plurality of recesses are discretely provided on a surface of the alloy layer facing the metal layer, A semiconductor device, wherein 90% or more of the plurality of recesses have a cone shape in which the opening width of each recess monotonically decreases as the recess advances.

2. the opening width of each recess is equal to or greater than 5 nm and equal to or less than 100 nm; The thickness of the alloy layer is 30 nm or more, The semiconductor device according to claim 1 , wherein the depth of each of said recesses is smaller than the thickness of said alloy layer.

3. an interlayer insulating film provided on the semiconductor substrate and having a contact region; 2. The semiconductor device according to claim 1, wherein the bottom width of said contact region is not less than 0.2 [mu]m and not more than 1.0 [mu]m.

4. 4. The semiconductor device according to claim 3, wherein a ratio of said bottom width of said contact region to a thickness of said interlayer insulating film is 1.5 or more.

5. 2. The semiconductor device according to claim 1, wherein the concentration of the inert gas contained at the interface between said metal layer and said alloy layer is equal to or lower than the concentration of the inert gas contained in the bulk of said semiconductor substrate.

6. The inert gas contained in the interface between the metal layer and the alloy layer and the inert gas contained in the bulk of the semiconductor substrate is Ar or N 2 6. The semiconductor device according to claim 5, wherein:

7. 2. The semiconductor device according to claim 1, wherein the atomic density of the elements constituting said alloy layer is 99.0 wt % or more.

8. 2. The semiconductor device according to claim 1, wherein said metal layer is made of a metal containing TiN or Al as a main component, or a laminated metal of a metal containing TiN as a main component and a metal containing Al as a main component.

9. The semiconductor device for power, The semiconductor device according to claim 1 , wherein the semiconductor material of the semiconductor substrate is Si, SiC, or a compound containing Ga.

10. 2. The semiconductor device according to claim 1, wherein said alloy layer is made of a silicide containing Ti or Ni.

11. A metal film is formed by depositing a metal containing an inert gas on a semiconductor substrate by a sputtering method or a CVD method; forming an alloy layer by subjecting the metal film to a heat treatment; forming a region in which the atomic density of metal atoms or semiconductor atoms containing the inert gas is reduced on a surface of the alloy layer opposite to the semiconductor substrate; etching the surface of the alloy layer to form the region with reduced atomic density into a recessed region having a plurality of recesses; A method for manufacturing a semiconductor device includes depositing a metal to be a metal layer on the alloy layer including the recessed region.

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