Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a parasitic capacitance around a first pad.SOLUTION: A semiconductor device 1 includes: a first diffusion region of an n type formed in a surface layer portion of a first main surface 3; a second diffusion region of a p type formed in the surface layer portion of the first main surface 3; an insulating layer 23 formed on the first main surface 3 so as to cover the first diffusion region and the second diffusion region; a first pad 9 disposed on the insulating layer 23 and electrically connected to the first diffusion region 17; and a trench parasitic capacitance formation portion 450 formed in the surface layer portion of the first main surface 3 so as to face the first pad 9 with the insulating layer 23 interposed therebetween. The first pad 9 forms a parasitic capacitance CP2 at a location between the insulating layer 23 and the first pad.SELECTED DRAWING: Figure 20A

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Documents 1 and 2 disclose a semiconductor device including a semiconductor substrate and a TVS circuit (Transient Voltage Suppressor circuit) formed on the semiconductor substrate. The TVS circuit is composed of a plurality of diodes including a Zener diode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-190531 [Patent Document 2] Patent Publication No. 2021-057491

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device capable of reducing parasitic capacitance around a first pad.

[0005] According to an embodiment of the present disclosure, there is provided a semiconductor device including: a semiconductor layer of a first conductivity type having a major surface; a first diffusion region of a second conductivity type formed in a surface portion of the major surface; a second diffusion region of the first conductivity type formed in the surface portion of the major surface; an insulating layer formed on the major surface to cover the first diffusion region and the second diffusion region; a first pad disposed on the insulating layer and electrically connected to the first diffusion region; and an internal parasitic capacitance forming portion formed in the surface portion of the semiconductor layer to form an internal parasitic capacitance between an opposing portion of the semiconductor layer facing the first pad across the insulating layer and the major surface or an extended surface flush with the major surface. The internal parasitic capacitance forming portion may include a trench parasitic capacitance forming portion having a first trench formed in the major surface and an inner portion of the insulating layer embedded in the first trench, the trench parasitic capacitance forming portion forming a trench parasitic capacitance between the extended surface of the first trench and the opposing portion formed on a bottom surface of the first trench. The first pad may form a first parasitic capacitance connected in series to the trench parasitic capacitance between itself and an upper portion of the insulating layer formed above the main surface or the extended surface.

[0006] According to an embodiment of the present disclosure, there is provided a semiconductor device including: a semiconductor layer of a first conductivity type having a major surface; a first diffusion region of a second conductivity type formed in a surface layer portion of the major surface; a second diffusion region of the first conductivity type formed in a surface layer portion of the major surface; an insulating layer formed on the major surface to cover the first diffusion region and the second diffusion region; a first pad disposed on the insulating layer and electrically connected to the first diffusion region; and a first trench formed in the major surface, the first trench having a portion of the insulating layer embedded therein. The first pad may form a third parasitic capacitance with an opposing region formed at a bottom surface of the first trench so as to face the first pad across the insulating layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. [Figure 4] FIG. 4 is a plan view showing the layout of the first pads and the second pads. [Figure 5] FIG. 5 is a plan view showing the layout of the first wiring layer. [Figure 6] FIG. 6 is a plan view showing the layout of the chip. [Figure 7] FIG. 7 is an enlarged view of the portion surrounded by the dashed line VII in FIG. [Figure 8A] 8A is a cross-sectional view taken along line VIIIA-VIIIA shown in FIG. [Figure 8B] FIG. 8B is an enlarged view of the portion surrounded by the dashed dotted line VIIIB in FIG. 8A. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is an enlarged view of the portion surrounded by the dashed line X in FIG. [Figure 11] FIG. 11 is an electrical circuit diagram of the semiconductor device. [Figure 12] FIG. 12 is an electrical circuit diagram showing the parasitic capacitance around the first pad. [Figure 13] FIG. 13 is a schematic plan view of a diode chip included in a semiconductor device according to a second embodiment of the present disclosure, and is a view corresponding to FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. [Figure 15] FIG. 15 is an enlarged view of the portion surrounded by the dashed line XV in FIG. [Figure 16] FIG. 16 is a schematic plan view of a diode chip included in a semiconductor device according to a third embodiment of the present disclosure, and is a view corresponding to FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18]FIG. 18 is an enlarged view of the portion surrounded by the dashed line XVIII in FIG. [Figure 19] FIG. 19 is a schematic plan view of a diode chip included in a semiconductor device according to a fourth embodiment of the present disclosure, and is a view corresponding to FIG. [Figure 20A] FIG. 20A is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 20B] FIG. 20B is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21] FIG. 21 is an electric circuit diagram showing parasitic capacitance around the first pad according to the fourth embodiment. [Figure 22] FIG. 22 is a schematic plan view of a chip included in a semiconductor device according to a fifth embodiment of the present disclosure, and corresponds to FIG. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. [Figure 24] FIG. 24 is an electric circuit diagram showing parasitic capacitance around the first pad according to the fifth embodiment. [Figure 25] FIG. 25 is a schematic cross-sectional view of a semiconductor device according to a modification (first modification) of the first embodiment of the present disclosure, and corresponds to FIG. [Figure 26] FIG. 26 is an electric circuit diagram showing parasitic capacitance around the first pad according to the first modification. [Figure 27] FIG. 27 is a schematic cross-sectional view of a semiconductor device according to a modified example (second modified example) of the first embodiment of the present disclosure, and corresponds to FIG. [Figure 28] FIG. 28 is a schematic cross-sectional view of a semiconductor device according to a modification (third modification) of the second embodiment of the present disclosure, and corresponds to FIG. [Figure 29] FIG. 29 is a schematic cross-sectional view of a semiconductor device according to a modification (fourth modification) of the second embodiment of the present disclosure, and corresponds to FIG. [Figure 30] FIG. 30 is a schematic cross-sectional view of a semiconductor device according to a modification (fifth modification) of the second embodiment of the present disclosure, and corresponds to FIG. [Figure 31] FIG. 31 is a schematic cross-sectional view of a semiconductor device according to a modification (sixth modification) of the fifth embodiment of the present disclosure, and corresponds to FIG. [Figure 32] FIG. 32 is a schematic cross-sectional view of a semiconductor device according to a modified example (seventh modified example) of the fifth embodiment of the present disclosure, and corresponds to FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Detailed explanation] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) that is substantially equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a plan view showing the layout of first pads 9 and second pads 11. FIG. 5 is a plan view showing the layout of a first wiring layer 24. FIG. 6 is a plan view showing the layout of a chip 2. FIG. 7 is an enlarged view of a portion surrounded by dashed dotted line VII in FIG. 6. FIG. 8A is a cross-sectional view taken along line VIIIA-VIIIA in FIG. 7. FIG. 8B is an enlarged view of a portion surrounded by dashed dotted line VIIIB in FIG. 8A.

[0013] The semiconductor device 1 includes a chip 2. The chip 2 may also be called a "semiconductor chip," a "diode chip," or the like. The semiconductor device 1 is a small chip component (semiconductor device). In this embodiment, the semiconductor device 1 is made up of an ESD protection chip that protects an electric circuit from ESD (Electro-Static Discharge). The ESD protection chip protects the electric circuit by discharging an applied ESD surge to a power supply wiring or a ground wiring.

[0014] The semiconductor device 1 may be called a "diode," a "TVS diode," a "diode chip," or the like.

[0015] The chip 2 has a first main surface (main surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view. In this embodiment, the first main surface 3 and the second main surface 4 are formed in a square shape (approximately square shape) in a plan view.

[0016] 1, in the circumferential direction of the chip 2 (counterclockwise in FIG. 1) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first to fourth side surfaces 5A to 5D are flat surfaces extending along the vertical direction Z.

[0017] The first to fourth side surfaces 5A to 5D may have a length of 0.1 mm to 2 mm in plan view, and may be 0.1 mm to 0.2 mm, 0.2 mm to 0.3 mm, 0.3 mm to 0.4 mm, 0.4 mm to 0.5 mm, 0.5 mm to 0.6 mm, 0.6 mm to 0.7 mm, 0.7 mm to 0.8 mm, 0.8 mm to 0.9 mm, 0.9 mm to 1 mm, 1 mm to 1.2 mm, 1.2 mm to 1.4 mm, 1.4 mm to 1.6 mm, 1.6 mm to 1.8 mm, or 1.8 mm to 2 mm.

[0018] 2, chip 2 includes a p-type (first conductivity type) semiconductor layer 6. P-type semiconductor layer 6 is exposed from second main surface 4 and first to fourth side surfaces 5A to 5D. Semiconductor layer 6 may also be referred to as a "base region," a "semiconductor region," or the like.

[0019] In this embodiment, the semiconductor layer 6 is made of a p-type semiconductor substrate 7. The p-type impurity concentration of the semiconductor substrate 7 is 1×10 12 cm -3 More than 1×10 14 cm -3 The semiconductor substrate 7 is specifically a silicon substrate. The semiconductor substrate 7 forms the surface layer of the first main surface 3 and the surface layer of the second main surface 4 of the chip 2. The p-type impurity concentration of the semiconductor substrate 7 is 1.0×10 13 cm -3 Over 1.0 x 10 15 cm -3 Since the semiconductor substrate 7 has a relatively low p-type impurity concentration, - The thickness of the semiconductor substrate 7 may be 10 μm or more and 800 μm or less.

[0020] 6, chip 2 has a device formation region 8 in which a diode device is formed in a surface layer portion of first main surface 3, two first pad regions 10 in which first pads 9 are arranged on first main surface 3, and one second pad region 12 in which second pad 11 is arranged on first main surface 3. Device formation region 8, first pad region 10, and second pad region 12 do not overlap one another. In this embodiment, device formation region 8 is a thyristor region 13 in which a thyristor (reverse conducting thyristor) is formed.

[0021] The thyristor region 13 is set in the inner part of the chip 2 at a distance from the periphery (first to fourth side faces 5A to 5D) of the chip 2 in a plan view. The two first pad regions 10 are formed in a region on the first side face 5A side as viewed from the center of the chip 2, extending from the second side face 5B to the fourth side face 5D. The single second pad region 12 is formed in a region on the third side face 5C side as viewed from the center of the chip 2, spaced from both the second side face 5B and the fourth side face 5D. The thyristor region 13 is formed in a region excluding these regions.

[0022] A first area ratio of the planar area of ​​thyristor region 13 to the planar area of ​​first main surface 3 may be 25% or more and 80% or less. It may be 25% or more and 30% or less, 30% or more and 35% or less, 35% or more and 40% or less, 40% or more and 45% or less, 45% or more and 50% or less, 50% or more and 55% or less, 55% or more and 60% or less, 60% or more and 65% or less, 65% or more and 70% or less, 70% or more and 75% or less, or 75% or more and 80% or less. The first area ratio is preferably 40% or more and 70% or less.

[0023] The semiconductor device 1 includes a plurality of thyristor structures 14 in a thyristor region 13. The plurality of thyristor structures 14 are arranged at intervals inward from the periphery of the thyristor region 13. In this embodiment, the plurality of thyristor structures 14 are arranged at intervals in the first direction X and are formed in stripes extending in the second direction Y. That is, in this embodiment, the plurality of thyristor structures 14 are arranged in stripes extending in the second direction Y. It goes without saying that the number of the plurality of thyristor structures 14 is not limited to the number shown in FIG. 6 and may be a greater number (for example, a larger number).

[0024] 7, the plurality of thyristor structures 14 includes a plurality of first thyristor structures 15 and a plurality of second thyristor structures 16. The first thyristor structures 15 extend in lines in the second direction Y. The second thyristor structures 16 extend in lines in the second direction Y. The first thyristor structures 15 and the second thyristor structures 16 are arranged alternately in the first direction X. The plurality of first thyristor structures 15 are arranged in stripes. The plurality of second thyristor structures 16 are arranged in stripes.

[0025] 7 and 8A, first thyristor structure 15 includes a first diffusion region 17 formed in first main surface 3. The n-type impurity concentration of first diffusion region 17 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3The n-type impurity concentration of the first diffusion region 17 is higher than the p-type impurity concentration of the semiconductor substrate 7. The first diffusion region 17 may also be referred to as an "n-type well region." The first diffusion region 17 extends linearly in the second direction Y.

[0026] 8B, first diffusion region 17 has a first width W1 in first direction X. First width W1 is, for example, not less than 5 μm and not more than 20 μm. First depth D1 of bottom portion 17a of first diffusion region 17 is, for example, not less than 1 μm and not more than 5 μm.

[0027] 7 and 8A, the first thyristor structure 15 includes an n-type base region 18 and a p-type emitter region 19 formed in a surface layer portion of the first diffusion region 17. The n-type base region 18 and the p-type emitter region 19 extend linearly in the second direction Y. The p-type emitter region 19 and the n-type base region 18 are formed with a gap therebetween in the first direction X. The n-type base region 18 is disposed on the second side face 5B side of the p-type emitter region 19. The n-type base region 18 is formed with a gap between it and the periphery of the first diffusion region 17 on the second side face 5B side. The p-type emitter region 19 is formed with a gap between it and the periphery of the first diffusion region 17 on the fourth side face 5D side.

[0028] The n-type impurity concentration of the n-type base region 18 is 1.0×10 19 cm -3 Over 1.0 x 10 20 cm -3 The n-type impurity concentration of the n-type base region 18 is higher than the n-type impurity concentration of the first diffusion region 17. The n-type base region 18 may also be referred to as an "n-type high concentration region," a "first base region," a "base region," or the like.

[0029] Referring to FIG. 8B, the n-type base region 18 has a second width W2 in the first direction X. The second width W2 of the n-type base region 18 is, for example, not less than 0.5 μm and not more than 3 μm. The second width W2 is narrower than the first width W1 (W2 <W1)。

[0030] The second depth D2 of the bottom 18a of the n-type base region 18 is, for example, 0.5 μm or more and 2 μm or less. The second depth D2 is shallower than the first depth D1 (D2 < D1).

[0031] Referring to FIGS. 7 and 8A, the n-type impurity concentration of the p-type emitter region 19 is 1.0×10 19 cm -3 or more and 1.0×10 20 cm -3 or less. The p-type impurity concentration of the p-type emitter region 19 is higher than the n-type impurity concentration of the semiconductor substrate 7. The p-type impurity concentration of the p-type emitter region 19 is higher than the p-type impurity concentration of the second diffusion region 20 described below. The p-type emitter region 19 may be referred to as a "p-type high-concentration region", a "first emitter region", an "emitter region", etc.

[0032] Referring to FIG. 8B, the p-type emitter region 19 has a third width W3 in the first direction X. The third width W3 is, for example, 0.5 μm or more and 3 μm or less. The third width W3 is narrower than the first width W1 (W3 < W1). In this form, the third width W3 is equal to the second width W2 (W3 = W2).

[0033] The third depth D3 of the bottom 19a of the p-type emitter region 19 is, for example, 0.5 μm or more and 2 μm or less. The third depth D3 is shallower than the first depth D1 (D3 < D1). In this form, the third depth D3 is equal to the second depth D2 (D3 = D2).

[0034] Referring to FIGS. 7 and 8A, the second thyristor structure 16 includes a second diffusion region 20 formed on the first main surface 3. The p-type impurity concentration of the second diffusion region 20 is 1.0×10 16 cm -3 or more and 1.0×10 18 cm -3 or less. The p-type impurity concentration of the second diffusion region 20 is higher than the p-type impurity concentration of the semiconductor substrate 7. The second diffusion region 20 may be referred to as a "p-type well region". The second diffusion region 20 extends linearly in the second direction Y.

[0035] Referring to FIG. 8B, the second diffusion region 20 has a fourth width W4 in the first direction X. The fourth width W4 is, for example, 5 μm or more and 20 μm or less. In this form, the fourth width W4 is equal to the first width W1 (W4 = W1). The fourth depth D4 of the bottom 20a of the second diffusion region 20 is, for example, 1 μm or more and 5 μm or less. The fourth depth D4 is equal to the first depth D1 (D4 = D1).

[0036] Referring to FIGS. 7 and 8A, the second thyristor structure 16 includes an n-type emitter region 21 and a p-type base region 22 formed in the surface layer portion of the second diffusion region 20. The n-type emitter region 21 and the p-type base region 22 extend linearly in the second direction Y. The p-type base region 22 is formed at an interval from the n-type emitter region 21 in the first direction X. The n-type emitter region 21 is disposed on the second side surface 5B side with respect to the p-type base region 22. The n-type emitter region 21 is formed at an interval from the peripheral edge on the second side surface 5B side of the second diffusion region 20. The p-type base region 22 is formed at an interval from the peripheral edge on the fourth side surface 5D side of the second diffusion region 20.

[0037] The n-type impurity concentration of the n-type emitter region 21 is 1.0×10 19 cm -3 or more and 1.0×10 20 cm -3 or less. The n-type impurity concentration of the n-type emitter region 21 is higher than the n-type impurity concentration of the second diffusion region 20. The n-type emitter region 21 may be referred to as an "n-type high concentration region", a "high concentration region", an "emitter region", etc.

[0038] Referring to FIG. 8B, the n-type emitter region 21 has a fifth width W5 in the first direction X. The fifth width W5 of the n-type emitter region 21 is, for example, 0.5 μm or more and 3 μm or less. The fifth width W5 is narrower than the fourth width W4 (W5 < W4). In this form, the fifth width W5 is equal to the second width W2 (W5 = W2).

[0039] The fifth depth D5 of the bottom 21a of the n-type emitter region 21 is, for example, 0.5 μm or more and 2 μm or less. The fifth depth D5 is shallower than the fourth depth D4 (D5 < D4). In this form, the fifth depth D5 is equal to the second depth D2 (D5 = D2).

[0040] Referring to FIGS. 7 and 8A, the n-type impurity concentration of the p-type base region 22 is 1.0×10 19 cm -3 or more and 1.0×10 20 cm -3 or less. The p-type impurity concentration of the p-type base region 22 is higher than the n-type impurity concentration of the semiconductor substrate 7. The p-type impurity concentration of the p-type base region 22 is higher than the p-type impurity concentration of the second diffusion region 20. The p-type base region 22 may be referred to as a "p-type high-concentration region", a "second base region", a "base region", etc.

[0041] The p-type base region 22 has a sixth width W6 in the first direction X. The sixth width W6 is, for example, 0.5 μm or more and 3 μm or less. The sixth width W6 is narrower than the fourth width W4 (W6 < W4). In this form, the sixth width W6 is equal to the third width W3 (W6 = W3). The sixth width W6 is equal to the fifth width W5 (W6 = W5).

[0042] Referring to FIG. 8B, the sixth depth D6 of the bottom 22a of the p-type base region 22 is, for example, 0.0.5 μm or more and 2 μm or less. The sixth depth D6 is shallower than the fourth depth D4 (D6 < D4). In this form, the sixth depth D6 is equal to the third depth D3 (D6 = D3). The sixth depth D6 is equal to the fifth depth D5 (D6 = D5).

[0043] Referring to FIGS. 2 and 8A, the semiconductor device 1 (chip 2) includes an insulating layer 23 covering the first main surface 3. The insulating layer 23 collectively covers the device formation region 8 (thyristor region 13), the two first pad regions 10 and the one second pad region 12. The insulating layer 23 covers the thyristor structure 14 (the first thyristor structure 15 and the second thyristor structure 16) in the thyristor region 13. The insulating layer 23 may be referred to as an "interlayer insulating film", an "insulating film", an "interlayer film", an "intermediate insulating film", etc.

[0044] In this embodiment, the insulating layer 23 has a stacked wiring structure in which multiple insulating layers and multiple wiring layers are alternately stacked. Each insulating layer 23 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, each insulating layer 23 includes a silicon oxide film.

[0045] The thickness of insulating layer 23 (thickness T230 of upper portion 230 described later (FIG. 8A)) may be 3 μm or more and 30 μm or less. The thickness of insulating layer 23 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, 8 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. The thickness of insulating layer 23 is preferably 5 μm or more and 15 μm or less.

[0046] The insulating layer 23 includes a first wiring layer 24 (FIG. 8A) disposed anywhere above the first main surface 3 via the insulating layer, and a second wiring layer 25 (FIG. 2) disposed above the first wiring layer 24 via the insulating layer. The multiple wirings included in the first wiring layer 24 all have the same height from the first main surface 3. The multiple wirings included in the second wiring layer 25 all have the same height from the first main surface 3. The first wiring layer 24 and the second wiring layer 25 have different heights from the first main surface 3.

[0047] 1 and 4, the semiconductor device 1 includes two first pads (pads) 9 arranged on an insulating layer 23. The first pads 9 are metal pads, and in this embodiment, the first pads 9 are formed from a metal material containing Al (aluminum).

[0048] In this embodiment, the first pad 9 is formed in a circular shape in a plan view. The first pad 9 has a peripheral portion. The first pad 9 may also be referred to as a "first metal," a "first pad," a "first electrode," etc. The first pad 9 is included in the second wiring layer 25.

[0049] 4, the two first pads 9 are arranged in a region on the first side surface 5A side of the thyristor region 13 (see FIG. 6) in a plan view. The two first pads 9 are formed with a gap in the first direction X. That is, the first pads 9 include a first pad 9 on the second side surface 5B side and a first pad 9 on the fourth side surface 5D side. The first pad 9 on the second side surface 5B side is arranged with a narrow gap between it and the second side surface 5B. The first pad 9 on the fourth side surface 5D side is arranged with a narrow gap between it and the fourth side surface 5D.

[0050] When a center line is set that crosses the center position of the chip 2 in the first direction X in the second direction Y, the two first pads 9 are preferably formed in a layout that is line-symmetrical with respect to the center line. The two first pads 9 are preferably the same size.

[0051] 1 and 4, the semiconductor device 1 includes one second pad (pad) 11 disposed on the insulating layer 23. The second pad 11 is a metal pad, and in this embodiment, the second pad 11 is formed of a metal material containing Al (aluminum). The second pad 11 functions as a cathode electrode. In this embodiment, the second pad 11 is formed in a circular shape in a plan view. The second pad 11 may also be referred to as a "second metal," a "second pad," a "second electrode," or the like. The second pad 11 is included in the second wiring layer 25.

[0052] 4, one second pad 11 is arranged in a region on the third side surface 5C side of the thyristor region 13 (FIG. 6) in a plan view. The second pads 11 are arranged at narrow intervals on the third side surface 5C. The second pads 11 are preferably formed in a layout in which the centers of the second pads 11 are located on a center line that crosses the central portion of the chip 2 in the second direction Y. In this embodiment, the second pad 11 has a polygonal shape that is wide in both the first direction X and the second direction Y in a plan view.

[0053] 5, the semiconductor device 1 includes, in the insulating layer 23, a first connection structure 27 that electrically connects the plurality of first thyristor structures 15 (FIG. 7) to the first pad 9, and a second connection structure 28 that electrically connects the plurality of second thyristor structures 16 (FIG. 7) to the second pad 11. In this embodiment, the first connection structure 27 includes a plurality of first connection wirings 55 arranged in a stripe pattern extending in the second direction Y. The plurality of first connection wirings 55 are included in the first wiring layer 24 (FIG. 8A).

[0054] 5 and 8A, the first connection wiring 55 extends in a line in the second direction Y. The first connection wiring 55 is disposed above the first thyristor structure 15. The first connection wiring 55 overlaps the first thyristor structure 15 in a plan view. The first connection wiring 55 is electrically connected to the n-type base region 18 and the p-type emitter region 19 of the first thyristor structure 15 via a first lower via 29 (FIG. 8A).

[0055] An end portion (an end portion on the first end face 5A side) of the first connection wiring 55 reaches a region facing below the first pad 9, and is connected to the first pad 9 in that region via a first upper via 30 (FIG. 5). In other words, the first connection wiring 55 electrically connects the n-type base region 18 (FIG. 8A) and p-type emitter region 19 (FIG. 8A) of the first thyristor structure 15 to the first pad 9.

[0056] The first connection wiring 55 faces only a portion (the portion where the first upper via 30 (FIG. 5) is formed) of the first pad 9. That is, in plan view, most of the first pad 9 does not overlap with the first connection wiring 55. Therefore, the presence of the first connection wiring 55 has almost no effect on the parasitic capacitance between the first pad 9 and the insulating layer 23.

[0057] 5, in this embodiment, the second connection structure 28 includes a plurality of second connection wirings 56 arranged in stripes extending in the second direction Y, and a pad wiring 57 having a shape (a polygonal shape that is wide in both the first direction X and the second direction Y) that matches the shape of the second pad 11 (FIG. 4) in a plan view. The plurality of second connection wirings 56 are drawn out from the pad wiring 57 in the second direction Y. The plurality of second connection wirings 56 and the pad wiring 57 are included in the first wiring layer 24 (FIG. 8A).

[0058] In this embodiment, since the second pad 11 is at the same potential as the second diffusion region 20, no parasitic capacitance is formed between the second pad 11 and the semiconductor substrate 7. Therefore, the second pad region 12 is not a region that forms parasitic capacitance with the second pad 11. Therefore, no particular problem occurs even if the pad wiring 57 is arranged so as to face the second pad 11 in a plan view.

[0059] 5 and 8A, the second connection wiring 56 extends in a line in the second direction Y. The second connection wiring 56 is disposed above the second thyristor structure 16. The second connection wiring 56 overlaps with the second thyristor structure 16 in a plan view.

[0060] The second connection wiring 56 is electrically connected to the n-type emitter region 21 and p-type base region 22 of the second thyristor structure 16 through the second lower via 31 (FIG. 8A). The pad wiring 57 is electrically connected to the second pad 11 through a second upper via (not shown). In this way, the second connection structure 28 electrically connects the n-type emitter region 21 and p-type base region 22 of the second thyristor structure 16 to the second pad 11.

[0061] The p-type emitter region 19 and the first n-type diffusion region 17 form a first pn junction 41 in a surface layer portion of the thyristor region 13. The first pn junction 41 forms a first Zener diode DZ1 in the thyristor region 13.

[0062] The p-type second diffusion region 20 and the n-type emitter region 21 form a second pn junction 42 in the surface layer portion of the thyristor region 13. The second pn junction 42 forms a second Zener diode DZ2 in the thyristor region 13.

[0063] 1 and 2, the semiconductor device 1 includes an upper insulating film 33 on the first main surface 3 that selectively covers the first pad 9 and the second pad 11. The upper insulating film 33 includes a first pad opening 35 that exposes an inner portion of the first pad 9. The first pad opening 35 is formed in a circular shape in a plan view. The upper insulating film 33 covers the periphery of the first pad 9. The inner portion of the first pad 9 is exposed through the first pad opening 35, thereby forming a first electrode surface 38. A connector (e.g., a bonding wire) BW is connected to the first electrode surface 38.

[0064] The upper insulating film 33 includes a second pad opening 36 that exposes the inner portion of the second pad 11. The second pad opening 36 is formed in a circular shape in a plan view. The upper insulating film 33 covers the periphery of the second pad 11. The inner portion of the second pad 11 is exposed through the second pad opening 36, thereby forming a second electrode surface 39. A connecting body BW is connected to the second electrode surface 39.

[0065] The upper insulating film 33 has an outer periphery at a position spaced apart from the first to fourth side surfaces 5A to 5D. The insulating layer 23 is exposed between the outer periphery of the upper insulating film 33 and the first to fourth side surfaces 5A to 5D. The exposed portion of the insulating layer 23 is annular (specifically, quadrangular annular).

[0066] The upper insulating film 33 preferably has a thickness greater than the thickness of the first pad 9 and the thickness of the second pad 11. The thickness of the upper insulating film 33 is preferably less than the thickness of the chip 2.

[0067] The upper insulating film 33 may have a laminated structure including an inorganic insulating film and an organic insulating film laminated in this order from the chip 2 side. The upper insulating film 33 may include at least one of an inorganic insulating film and an organic insulating film, and does not necessarily have to include both an inorganic insulating film and an organic insulating film at the same time. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film preferably includes an insulating material different from that of the insulating layer 23. The organic insulating film preferably includes a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0068] Referring to FIG. 5, a shield ring 37 is formed on the insulating layer 23 around the periphery of the semiconductor device 1. The shield ring 37 is formed in a rectangular ring shape along the first to fourth side surfaces 5A to 5D. In plan view, the thyristor region 13, the first pad region 10, and the second pad region 12 are surrounded by the shield ring 37. The shield ring 37 is, for example, a shield wiring included in the insulating layer 23. When the semiconductor device is cut to separate chips, cracks or chips may occur on the periphery of the chip. If cracks or chips occur on the periphery of the chip, moisture may easily penetrate from the outside. Therefore, in this embodiment, the shield ring 37 is formed in a rectangular ring shape in plan view around the periphery of the insulating layer 23.

[0069] In the thyristor region 13, a laminated parasitic capacitance forming portion (internal parasitic capacitance forming portion) 50 is formed on the first main surface 3.

[0070] Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 6. Fig. 10 is an enlarged view of a portion surrounded by dashed line X in Fig. 9. The stacked parasitic capacitance forming portion 50 will be described with reference to Figs. 6, 9 and 10.

[0071] The stacked parasitic capacitance forming portion 50 has a stacked structure LS1 of an n-type first diffusion layer 51 and a p-type second diffusion layer 52. The stacked structure LS1 (stacked parasitic capacitance forming portion 50) forms a parasitic capacitance between the semiconductor substrate 7 and the first main surface 3.

[0072] In this embodiment, the multilayer structure LS1 is circular in plan view. The multilayer structure LS1 overlaps the first pad 9 in plan view. The periphery of the multilayer structure LS1 is located inward from the periphery of the first pad 9 in plan view. More specifically, the multilayer structure LS1 overlaps the first electrode surface 38 in plan view. The periphery of the multilayer structure LS1 is aligned with the periphery of the first electrode surface 38 in plan view.

[0073] 6 and 9, the first diffusion layer 51 is a lower layer of the stacked structure LS1. The first diffusion layer 51 is formed on the first main surface 3. In this embodiment, the first diffusion layer 51 has a circular shape in a plan view. The periphery of the first diffusion layer 51 is the periphery of the stacked structure LS1. The n-type impurity concentration of the first diffusion layer 51 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 The n-type impurity concentration of the first diffusion layer 51 is higher than the p-type impurity concentration of the semiconductor substrate 7. In this embodiment, the n-type impurity concentration of the first diffusion layer 51 is the same as the n-type impurity concentration of the first diffusion region 17.

[0074] 9, the first diameter (width) DL1 of the first diffusion layer 51 is, for example, not less than 250 μm and not more than 1 mm. The first diameter DL1 is larger than the first width W1 (FIG. 8B) of the first diffusion region 17 (DL1>W1). The first diameter DL1 is larger than the fourth width W4 (FIG. 8B) of the second diffusion region 20 (DL1>W4).

[0075] 10, the seventh depth D7 of the bottom 51a of the first diffusion layer 51 is, for example, not less than 1 μm and not more than 5 μm. In this embodiment, the seventh depth D7 is equal to the first depth D1 (FIG. 8B) of the bottom 17a of the first diffusion region 17 and the fourth depth D4 (FIG. 8B) of the bottom 20a of the second diffusion region 20 (D7=D1=D4). The first diffusion layer 51 may be formed in the same process as the first diffusion region 17.

[0076] 6 and 9, the second diffusion layer 52 is an upper layer of the stacked structure LS1. The second diffusion layer 52 is formed in a surface layer portion of the first diffusion layer 51. In this embodiment, the second diffusion layer 52 is circular in plan view. The second diffusion layer 52 surrounds the lower and lateral sides of the first diffusion layer 51. The p-type impurity concentration of the second diffusion layer 52 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 The p-type impurity concentration of the second diffusion layer 52 is higher than the p-type impurity concentration of the semiconductor substrate 7. In this embodiment, the p-type impurity concentration of the second diffusion layer 52 is the same as the p-type impurity concentration of the second diffusion region 20.

[0077] 10, the periphery of the second diffusion layer 52 is located inward from the periphery of the first diffusion layer 51 (the periphery of the laminated structure LS1). The second diameter (width) DL2 of the second diffusion layer 52 is, for example, not less than 200 μm and not more than 950 mm. The second diameter DL2 is larger than the first width W1 (FIG. 8B) of the first diffusion region 17 (DL2>W1). The second diameter DL2 is larger than the fourth width W4 (FIG. 8B) of the second diffusion region 20 (DL2>W4).

[0078] Referring to FIG. 10, the eighth depth D8 of the bottom 52a of the second diffusion layer 52 is, for example, not less than 0.7 μm and not more than 3 μm. In this form, the eighth depth D8 is shallower than the seventh depth D7 (D8 < D7). The eighth depth D8 is shallower than the first depth D1 of the bottom 17a of the first diffusion region 17 (FIG. 8B) and the fourth depth D4 of the bottom 20a of the second diffusion region 20 (FIG. 8B) (D8 < D1 = D4). The eighth depth D8 is deeper than the third depth D3 of the bottom 19a of the p-type emitter region 19 (FIG. 8B) and the sixth depth D6 of the bottom 22a of the p-type base region 22 (FIG. 8B) (D6 > D3 = D6).

[0079] In the stacked structure LS1, a first stacked parasitic capacitance (internal parasitic capacitance) C1 is formed between the p-type second diffusion layer 52 and the n-type first diffusion layer 51. A second stacked parasitic capacitance (internal parasitic capacitance) C2 is formed between the n-type first diffusion layer 51 and the p-type semiconductor substrate 7.

[0080] Also, since the first pad 9 is at the same potential as the n-type first diffusion region 17, a parasitic capacitance is formed between the first pad 9 and the p-type semiconductor substrate 7. The first pad 9 faces the first pad region 10 across the insulating layer 23 (faces the opposing portion 7a on the surface of the semiconductor substrate 7 that opposes the first pad 9), forming a parasitic capacitance CP1.

[0081] FIG. 11 is an electrical circuit diagram of the semiconductor device 1. The semiconductor device 1 includes a first pad 9, a second pad 11, and a TVS circuit 80. The TVS circuit 80 is composed of a series circuit in which a first parallel circuit 81 and a second parallel circuit 82 are connected in series, and is electrically connected to the first pad 9 and the second pad 11.

[0082] The first parallel circuit 81 includes a plurality of first Zener diodes DZ1 connected in parallel to each other. The cathodes of the plurality of first Zener diodes DZ1 are connected to the first pad 9. The anodes of the plurality of first Zener diodes DZ1 are electrically connected to the second pad 11.

[0083] The second parallel circuit 82 includes a plurality of second Zener diodes DZ2 connected in parallel to one another. The anodes of the plurality of second Zener diodes DZ2 are electrically connected to the first pad 9. The cathodes of the plurality of second Zener diodes DZ2 are electrically connected to the second pad 11.

[0084] The semiconductor device 1 is a bidirectional device that allows current to flow in both directions between the first pad 9 and the second pad 11. That is, when a voltage equal to or greater than a predetermined threshold voltage with the first pad 9 being positive is applied between the first pad 9 and the second pad 11, a current flows from the first pad 9 to the second pad 11 via the first Zener diode DZ1.

[0085] On the other hand, when a voltage equal to or greater than a predetermined threshold voltage with the second pad 11 being positive is applied between the first pad 9 and the second pad 11, a current flows from the second pad 11 to the first pad 9 via the second Zener diode DZ2.

[0086] As described above, in the stacked structure LS1, a first stacked parasitic capacitance C1 is formed between the p-type second diffusion layer 52 and the n-type first diffusion layer 51. A second stacked parasitic capacitance C2 is formed between the n-type first diffusion layer 51 and the p-type semiconductor substrate 7. The first pad 9 faces the first pad region 10 across the insulating layer 23, and forms a parasitic capacitance (first parasitic capacitance, second parasitic capacitance) CP1 with the insulating layer 23. In this embodiment, since the first trench 451 is not formed in the first main surface 3, the total thickness of the insulating layer 23 matches the thickness T230 of the upper portion 230. Therefore, in this embodiment, the parasitic capacitance (first parasitic capacitance) between the first pad 9 and the upper portion 230 and the parasitic capacitance (second parasitic capacitance) between the first pad 9 and the insulating layer 23 are both the parasitic capacitance CP1.

[0087] FIG. 12 is an electric circuit diagram showing the parasitic capacitance around the first pad 9 (the portion between the first pad 9 and the opposing portion 7a of the semiconductor substrate 7 that faces the first pad 9).

[0088] The semiconductor device 1 includes a first pad 9, an opposing portion 7a (FIGS. 9 and 10) of the semiconductor substrate 7 that opposes the first pad 9, and a first pad parasitic capacitance circuit 90. The first pad parasitic capacitance circuit 90 forms a series circuit consisting of a first stacked layer parasitic capacitance C1, a second stacked layer parasitic capacitance C2, and a parasitic capacitance CP1. The combined capacitance CS1 around the first pad 9 is expressed by the following equation (1):

[0089]

number

[0090] In contrast, consider the case where the laminated structure LS1 (laminated parasitic capacitance forming portion 50) is removed. In this case, the combined capacitance CS1* around the first pad 9 coincides with the parasitic capacitance CP1. The combined capacitance CS1 is less than the combined capacitance CS1*. Therefore, by forming the laminated structure LS1 on the first main surface 3, the parasitic capacitance around the first pad 9 can be reduced.

[0091] As described above, according to the first embodiment, a stacked layer structure LS1 having a first diffusion layer 51 and a second diffusion layer 52 is formed on the first main surface 3. A first stacked layer parasitic capacitance C1 is formed between the p-type second diffusion layer 52 and the n-type first diffusion layer 51, and a second stacked layer parasitic capacitance C2 is formed between the n-type first diffusion layer 51 and the semiconductor substrate 7 of the first conductivity type. The first pad 9 faces the first pad region 10 with the insulating layer 23 interposed therebetween, and forms a parasitic capacitance CP1 with the insulating layer 23. The parasitic capacitance CP1 forms a series circuit with the first stacked layer parasitic capacitance C1 and the second stacked layer parasitic capacitance C2. This reduces the parasitic capacitance around the first pad 9 compared to when the stacked layer structure LS1 is not formed on the first main surface 3.

[0092] Furthermore, the seventh depth D7 of the bottom 51a of the first diffusion layer 51 is the same as the first depth D1 of the bottom 17a of the first diffusion region 17. Therefore, the first diffusion layer 51 and the first diffusion region 17 can be formed in the same process. This reduces the number of processes compared to when the first diffusion layer 51 and the first diffusion region 17 are formed separately.

[0093] Fig. 13 is a schematic plan view of a chip 2 included in a semiconductor device 201 according to a second embodiment of the present disclosure, and corresponds to Fig. 6. Fig. 14 is a cross-sectional view taken along line XIV-XIV shown in Fig. 13. Fig. 15 is an enlarged view of a portion surrounded by dashed line XV in Fig. 14. In Figs. 13 to 15, the same reference numerals are used to designate the same components as those described above, and their description will be omitted.

[0094] The semiconductor device 201 differs from the semiconductor device 1 in that the first main surface 3 is provided with an isolation portion 202 that isolates the first pad region 10 from the thyristor region 13 .

[0095] 13, the isolation portion 202 is formed in a strip shape so as to cross between the n-type first diffusion layer 51 of the stacked structure LS1 and the diffusion regions 17, 20 of the thyristor structure 14. In this embodiment, the isolation portion 202 is formed in a line shape on the first main surface 3 along the boundary between the first pad region 10 and the thyristor region 13. The isolation portions 202 corresponding to the two first pad regions 10 are connected to each other.

[0096] In this embodiment, the isolation portion 202 is made of a p-type high concentration region 203. The n-type impurity concentration of the p-type high concentration region 203 is 1.0×10 19 cm -3 Over 1.0 x 10 20 cm -3 The p-type impurity concentration of the p-type high concentration region 203 is higher than the n-type impurity concentration of the semiconductor substrate 7. The p-type impurity concentration of the p-type high concentration region 203 is higher than the p-type impurity concentration of the second diffusion region 20 (FIG. 8A). The p-type impurity concentration of the p-type high concentration region 203 is equal to the p-type impurity concentrations of the p-type emitter region 19 (FIG. 8A) and the p-type base region 22 (FIG. 8A).

[0097] 15, the p-type heavily doped region 203 has a seventh width W7. The seventh width W7 is, for example, not less than 0.5 μm and not more than 3 μm. The seventh width W7 may be equal to the third width W3 (FIG. 8B) of the p-type emitter region 19 and the sixth width W6 (FIG. 8B) of the p-type base region 22 (W7=W3=W6). The seventh width W7 may be wider than the third width W3 and the sixth width W6 (W7>W3=W6), or may be narrower than the third width W3 and the sixth width W6 (W7 <W3=W6)。

[0098] The ninth depth D9 of the p-type heavily doped region 203 is, for example, not less than 0.5 μm and not more than 2 μm. In this embodiment, the ninth depth D9 is equal to the third depth D3 (FIG. 8B) of the p-type emitter region 19 and the sixth depth D6 (FIG. 8B) of the p-type base region 22 (D9=D3=D6).

[0099] Since the p-type high concentration region 203 is formed so as to cross between the n-type first diffusion layer 51 and the n-type first diffusion region 17, interference between the depletion layer extending from the first diffusion region 17 and the depletion layer extending from the first diffusion layer 51 can be prevented.

[0100] The semiconductor device 201 according to the second embodiment of the present disclosure provides the same effects as those described in relation to the first embodiment.

[0101] Furthermore, according to the semiconductor device 201, the p-type high concentration region 203 can prevent interference between the depletion layer spreading from the first diffusion region 17 and the depletion layer spreading from the first diffusion layer 51, so that the parasitic capacitance in the first pad region 10 (the parasitic capacitance in the stacked structure LS1) can be kept even higher, thereby reducing the parasitic capacitance around the first pad 9.

[0102] Fig. 16 is a schematic plan view of a diode chip included in a semiconductor device 301 according to a third embodiment of the present disclosure, and corresponds to Fig. 6. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 16. Fig. 18 is an enlarged view of a portion surrounded by dashed dotted line XVIII in Fig. 17. In Figs. 16 to 18, the same reference symbols are used for components that are the same as those described above, and descriptions thereof will be omitted.

[0103] The semiconductor device 301 differs from the semiconductor device 1 in that the first main surface 3 is provided with an isolation portion 302 that isolates the first pad region 10 from the thyristor region 13 .

[0104] 16, the isolation portion 302 is formed in a strip shape so as to cross between the n-type first diffusion layer 51 of the stacked structure LS1 and the diffusion regions 17, 20 of the thyristor structure 14. In this embodiment, the isolation portion 302 is formed in a line shape along the boundary between the first pad region 10 and the thyristor region 13 on the first main surface 3. The isolation portions 302 corresponding to two first pad regions 10 are connected to each other.

[0105] In this embodiment, the isolation portion 302 includes an isolation trench structure 303. The isolation trench structure 303 includes an isolation trench 304 and an insulator 305 formed on the inner surface of the isolation trench 304. The isolation trench structure 303 insulates the surface portion of the first pad region 10 from the surface portion of the thyristor region 13.

[0106] 18, the insulation trench 304 is formed in the first main surface 3. The insulation trench 304 has a tenth depth D 10 The 10th depth D 10 The second depth D2 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. 10 The tenth depth D of the isolation trench 304 may be deeper than the depths of the diffusion regions 17, 20 of the thyristor structure 14 (first depth D1 (FIG. 8B) and fourth depth D4 (FIG. 8B)). The isolation trench 304 may be formed in a tapered shape in cross section, the width of which decreases toward the bottom surface, which will be described next. 10 is preferably 3 μm or more and 10 μm or less.

[0107] The insulator 305 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulator 305 includes a silicon oxide film.

[0108] Since the insulating trench structure 303 insulates the surface portion of the first pad region 10 from the surface portion of the thyristor region 13, the presence of the insulating trench structure 303 prevents current from flowing between the first pad region 10 and the thyristor region 13, and the current path between the first pad region 10 and the thyristor region 13 is diverted in the vertical direction Z.

[0109] The semiconductor device 301 according to the third embodiment of the present disclosure provides the same effects as those described in relation to the first embodiment.

[0110] Furthermore, according to the semiconductor device 301, the insulating trench structure 303 prevents current from flowing between the first pad region 10 and the thyristor region 13, thereby maintaining the parasitic capacitance in the first pad region 10 (the parasitic capacitance in the stack structure LS1) even higher, thereby reducing the parasitic capacitance around the first pad 9.

[0111] Furthermore, since the insulating trench structure 303 is formed deep, it is possible to further hinder the flow of current between the stacked structure LS1 and the first diffusion region 17. This makes it possible to maintain a higher parasitic capacitance in the first pad region 10 (parasitic capacitance in the stacked structure LS1), thereby further reducing the parasitic capacitance around the first pad 9.

[0112] Fig. 19 is a schematic plan view of a chip 2 included in a semiconductor device 401 according to a fourth embodiment of the present disclosure, and corresponds to Fig. 6. Figs. 20A and 20B are cross-sectional views taken along the line XX-XX shown in Fig. 19. Fig. 21 is an electrical circuit diagram showing parasitic capacitance around a first pad 9 according to the fourth embodiment (the portion between the first pad 9 and an opposing portion 7a of the semiconductor substrate 7 that faces the first pad 9). In Figs. 19 to 21, the same reference numerals are used to designate the same components as those previously described, and their description will be omitted.

[0113] The semiconductor device 401 includes a trench parasitic capacitance forming portion (internal parasitic capacitance forming portion) 450 formed in the first pad region 10. The trench parasitic capacitance forming portion 450 includes a first trench 451 formed in the first main surface 3 and an intra-trench insulating layer 231 buried inside the first trench 451. The intra-trench insulating layer 231 is a part of the insulating layer 23. The semiconductor device 401 differs from the semiconductor device 1 in that the semiconductor device 401 includes the trench parasitic capacitance forming portion 450 instead of the stacked parasitic capacitance forming portion 50.

[0114] The first trench 451 of the trench parasitic capacitance forming portion 450 defines the inner surface (side surface 453 and bottom surface 452 shown in FIGS. 20A and 20B) of the trench parasitic capacitance forming portion 450. In this embodiment, the first trench 451 is cylindrical.

[0115] The side surface 453 of the first trench 451 is a cylindrical surface. In this embodiment, the side surface 453 is perpendicular to the first main surface 3 (extending in the vertical direction Z). The side surface 453 of the first trench 451 is located inward from the periphery of the first pad 9 in plan view. The periphery of the first trench 451 is aligned with the periphery of the first electrode surface 38 in plan view. The side surface 453 may be a tapered surface whose diameter decreases toward the second main surface 4.

[0116] 20A and 20B, side surface 453 of first trench 451 has a third diameter (width) DL3. Third diameter DL3 is, for example, not less than 250 μm and not more than 1 mm. Third diameter DL3 is larger than first width W1 (FIG. 8B) of first diffusion region 17 (DL3>W1). Third diameter DL3 is larger than fourth width W4 (FIG. 8B) of second diffusion region 20 (DL3>W4).

[0117] It is preferable that the bottom surface 452 of the first trench 451 has a portion that extends flat (is a flat surface). It is particularly preferable that the flat portion (flat surface) of the bottom surface 452 of the first trench 451 extends substantially parallel to the first main surface 3. Of course, the bottom surface 452 of the first trench 451 may be curved in an arc shape toward the second main surface 4.

[0118] The first trench 451 has a trench depth DT in the vertical direction Z. The trench depth DT may be 3 μm or more and 30 μm or less. The trench depth DT may have a value belonging to any one of the following ranges: 3 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less. The trench depth DT is more preferably 5 μm or more and 15 μm or less.

[0119] In this embodiment, trench depth DT is deeper than first depth D1 (FIG. 8B) of bottom 17a of first diffusion region 17 and fourth depth D4 (FIG. 8B) of bottom 20a of second diffusion region 20 (DT>D1=D4). In this embodiment, trench depth DT is preferably smaller than third diameter DL3 of side surface 453.

[0120] The intra-trench insulating layer 231 of the trench parasitic capacitance forming portion 450 is located below an extended plane EP of the first main surface 3 (hereinafter simply referred to as "extended plane EP") in the surface layer portion of the first main surface 3 (the region where the first trench 451 is formed). In this specification, the extended plane EP is an imaginary plane that is coplanar with the first main surface 3 above the first trench 451. The intra-trench insulating layer 231 is a part of the insulating layer 23. In other words, the insulating layer 23 includes an upper portion 230 located above the first main surface 3 and the extended plane EP, and the intra-trench insulating layer 231. In this embodiment, the thickness of the intra-trench insulating layer 231 matches the trench depth DT of the first trench 451.

[0121] In this embodiment, the intra-trench insulating layer 231 has a cylindrical shape. The intra-trench insulating layer 231 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the intra-trench insulating layer 231 includes a silicon oxide film.

[0122] In this embodiment, the intra-trench insulating layer 231 overlaps the first pad 9 in plan view. More specifically, the intra-trench insulating layer 231 overlaps the first electrode surface 38 in plan view.

[0123] The first pad 9 faces the first pad region 10 with the insulating layer 23 (the upper portion 230 and the intra-trench insulating layer 231) sandwiched therebetween. The first pad 9 forms a parasitic capacitance (third parasitic capacitance) CP2 ( FIG. 20A ) between the first pad 9 and the opposing portion 7a of the semiconductor substrate 7 that faces the first pad 9. In this embodiment, the total thickness of the insulating layer 23 is the sum of the thickness T230 of the upper portion 230 and the trench depth DT. Since the parasitic capacitance is inversely proportional to the inter-electrode distance, the parasitic capacitance CP2 between the first pad 9 and the insulating layer 23 is reduced compared to a case where the first trench 451 is not formed in the first main surface 3 (compared to the first embodiment). Therefore, by forming the first trench 451 in the first main surface 3 and embedding the intra-trench insulating layer 231 inside the first trench 451, the parasitic capacitance around the first pad 9 can be reduced. In this embodiment, the parasitic capacitance CP2 is the parasitic capacitance between the first pad 9 and the opposing portion 7a formed on the bottom surface 452.

[0124] As described above, according to the fourth embodiment, the trench parasitic capacitance forming portion 450 is formed on the first main surface 3 so as to face the first pad 9 with the insulating layer sandwiched therebetween. The distance between the first pad 9 and the facing portion 7a can be kept larger than when the first trench 451 is not formed on the first main surface 3. Since the parasitic capacitance is inversely proportional to the distance between the electrodes, by keeping the distance between the first pad 9 and the facing portion 7a large, the parasitic capacitance around the first pad 9 can be reduced compared to when the trench parasitic capacitance forming portion 450 is not formed on the first main surface 3.

[0125] 20B, from another perspective, the intra-trench insulating layer 231 forms a parasitic capacitance CP1 (FIG. 20B) between the semiconductor substrate 7 and the extended surface EP. Also, the trench parasitic capacitance forming portion 450 forms a trench parasitic capacitance CT (internal parasitic capacitance, FIG. 20B) between the semiconductor substrate 7 and the extended surface EP. In this case, the parasitic capacitance CP1 forms a series circuit with the trench parasitic capacitance CT.

[0126] 21, a semiconductor device 401 includes a first pad 9, an opposing portion 7a (FIG. 20B) of a semiconductor substrate 7 that opposes the first pad 9, and a first-pad parasitic capacitance circuit 490. The first-pad parasitic capacitance circuit 490 forms a series circuit made up of a trench parasitic capacitance CT and a parasitic capacitance CP1. A combined capacitance CS2 around the first pad 9 is expressed by the following equation (2).

[0127]

number

[0128] In contrast, consider the case where the trench parasitic capacitance forming portion 450 is removed. In this case, the combined capacitance CS2* is equal to the parasitic capacitance CP1. The combined capacitance CS2 is less than the combined capacitance CS2*. Therefore, by forming the trench parasitic capacitance forming portion 450 on the first main surface 3, the parasitic capacitance around the first pad 9 can be reduced.

[0129] Fig. 22 is a schematic plan view of a chip 2 included in a semiconductor device 501 according to a fifth embodiment of the present disclosure, and is a view corresponding to Fig. 6. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in Fig. 22. Fig. 24 is an electrical circuit diagram showing parasitic capacitance around a first pad 9 according to the fifth embodiment. In Figs. 22 to 24, the same reference symbols are used for components that are the same as those described above, and descriptions thereof will be omitted.

[0130] The semiconductor device 501 includes a stacked parasitic capacitance forming portion (internal parasitic capacitance forming portion) 550 in addition to the trench parasitic capacitance forming portion 450. The semiconductor device 501 differs from the semiconductor device 401 according to the fourth embodiment in that it includes the stacked parasitic capacitance forming portion 550.

[0131] The stacked parasitic capacitance forming portion 550 has a stacked structure LS2 of an n-type first diffusion layer 551 and a p-type second diffusion layer 552. The stacked structure LS2 (stacked parasitic capacitance forming portion 550) forms a parasitic capacitance between the semiconductor substrate 7 and the bottom surface 452 of the first trench 451.

[0132] In this embodiment, the stacked structure LS2 is circular in plan view. The periphery of the stacked structure LS2 is located inward from the periphery of the bottom surface 452 of the first trench 451 in plan view, with a gap therebetween. In this embodiment, the periphery of the stacked structure LS2 is located inward from the periphery of the first electrode surface 38 in plan view.

[0133] The stacked structure LS2 differs from the stacked structure LS1 in that it is formed on the bottom surface 452 of the first trench 451 and that the peripheral portion of the stacked structure LS2 is located inward from the peripheral edge of the first electrode surface 38 in plan view. In other respects, the stacked structure LS2 is common to the stacked structure LS1.

[0134] The first diffusion layer 551 is a lower layer of the stacked structure LS2. The periphery of the first diffusion layer 551 is the periphery of the stacked structure LS2. The n-type impurity concentration of the first diffusion layer 551 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 The n-type impurity concentration of the first diffusion layer 551 is higher than the p-type impurity concentration of the semiconductor substrate 7. In this embodiment, the n-type impurity concentration of the first diffusion layer 551 is the same as the n-type impurity concentration of the first diffusion region 17.

[0135] The fourth diameter (width) DL4 of the first diffusion layer 551 is smaller than the third diameter DL3 of the first trench 451 (DL4 < DL3). The fourth diameter DL4 is larger than the first width W1 (FIG. 8B) of the first diffusion region 17 (DL4 > W1). The fourth diameter DL4 is larger than the fourth width W4 (FIG. 8B) of the second diffusion region 20 (DL4 > W4). The depth of the bottom 551a of the first diffusion layer 551 is the same as the seventh depth D7 (FIG. 8B) of the bottom 51a of the first diffusion layer 51.

[0136] The second diffusion layer 552 is the upper layer of the stacked structure LS2. The lower and side portions of the second diffusion layer 552 are surrounded by the second diffusion layer 552. The p-type impurity concentration of the second diffusion layer 552 is 1.0 × 10 16 cm -3 or more and 1.0 × 10 18 cm -3 or less. The p-type impurity concentration of the second diffusion layer 552 is higher than the p-type impurity concentration of the semiconductor substrate 7. In this form, the p-type impurity concentration of the second diffusion layer 552 is the same as the p-type impurity concentration of the second diffusion region 20.

[0137] The periphery of the second diffusion layer 552 is located inward of the periphery of the first diffusion layer 551 (the periphery of the stacked structure LS2). The fifth diameter (width) DL5 of the second diffusion layer 552 is smaller than the fourth diameter (width) DL4 of the first diffusion layer 551 (DL5 < DL4). The fifth diameter DL5 of the second diffusion layer 552 is smaller than the third diameter DL3 of the first trench 451 (DL5 < DL3). The fifth diameter DL5 is larger than the first width W1 (FIG. 8B) of the first diffusion region 17 (DL5 > W1). The fifth diameter DL5 is larger than the fourth width W4 (FIG. 8B) of the second diffusion region 20 (DL5 > W4). The depth of the bottom 552a of the second diffusion layer 552 is the same as the eighth depth D8 (FIG. 8B) of the bottom 51a of the first diffusion layer 51.

[0138] In the stacked structure LS2, a first stacked parasitic capacitance C1 is formed between the p-type second diffusion layer 552 and the n-type first diffusion layer 551. A second stacked parasitic capacitance C2 is formed between the n-type first diffusion layer 551 and the p-type semiconductor substrate 7. The first pad 9 faces the first pad region 10 across the insulating layer 23 (facing a facing portion 7a on the surface of the semiconductor substrate 7 that faces the first pad 9), forming a parasitic capacitance CP2.

[0139] 24, a semiconductor device 501 includes a first pad 9, an opposing portion 7a (FIG. 23) of a semiconductor substrate 7 that opposes the first pad 9, and a first pad parasitic capacitance circuit 590. The first pad parasitic capacitance circuit 590 forms a series circuit consisting of a first stacked layer parasitic capacitance C1, a second stacked layer parasitic capacitance C2, and a parasitic capacitance CP2. A combined capacitance CS3 around the first pad 9 is expressed by the following equation (3):

[0140]

number

[0141] In contrast, consider the case where the stacked layer structure LS2 (stacked parasitic capacitance forming portion 550) is removed from the bottom surface 242 of the first trench 241 (i.e., the case of the fourth embodiment). In this case, the combined capacitance CS3* coincides with the combined capacitance CS3. The combined capacitance CS3 is less than the combined capacitance CS3*. Therefore, by forming the stacked layer structure LS2 on the first main surface 3, the parasitic capacitance around the first pad 9 can be further reduced.

[0142] The semiconductor device 501 according to the fifth embodiment of the present disclosure provides the same effects as those described in relation to the fourth embodiment.

[0143] Furthermore, according to the semiconductor device 501, in the first pad region 10, a stacked layer structure LS2 having a first diffusion layer 551 and a second diffusion layer 552 is formed on the bottom surface 452 of the first trench 451. A first stacked layer parasitic capacitance C1 is formed between the p-type second diffusion layer 552 and the n-type first diffusion layer 551, and a second stacked layer parasitic capacitance C2 is formed between the n-type first diffusion layer 551 and the semiconductor substrate 7 of the first conductivity type. The first pad 9 faces the first pad region 10 across the insulating layer 23 and forms a parasitic capacitance CP2. The parasitic capacitance CP2 forms a series circuit with the first stacked layer parasitic capacitance C1 and the second stacked layer parasitic capacitance C2. This reduces the parasitic capacitance around the first pad 9 compared to the fourth embodiment.

[0144] Furthermore, the semiconductor device 501 according to the fifth embodiment of the present disclosure provides the same effects as those described in relation to the first embodiment.

[0145] Furthermore, according to the semiconductor device 501 according to the fifth embodiment of the present disclosure, in the first pad region 10, a trench parasitic capacitance forming portion 450 is formed in the first main surface 3. A larger distance can be maintained between the first pad 9 and the facing portion 7a compared to when the first trench 451 is not formed in the first main surface 3. Since parasitic capacitance is inversely proportional to the distance between electrodes, by maintaining a larger distance between the first pad 9 and the facing portion 7a, the parasitic capacitance around the first pad 9 can be reduced compared to the first embodiment.

[0146] Although several embodiments of the present disclosure have been described above, the present disclosure can be embodied in other forms.

[0147] 25, in the semiconductor device 1 according to the first embodiment, the stacked layer structure LS1 of the stacked parasitic capacitance forming portion 50 may be a multi-layer structure having more than two layers. In the example of FIG. 25, the stacked layer structure LS1 is a four-layer structure. In the example of FIG. 25, the stacked layer structure LS1 includes a first diffusion layer 51, a second diffusion layer 52, an n-type third diffusion layer 53 formed in a surface layer portion of the second diffusion layer 52, and a p-type fourth diffusion layer 54 formed in a surface layer portion of the third diffusion layer 53.

[0148] The third diffusion layer 53 is an intermediate layer of the stacked structure LS1. In this embodiment, the third diffusion layer 53 is circular in plan view. The third diffusion layer 53 surrounds the lower and lateral sides of the second diffusion layer 52. The n-type impurity concentration of the third diffusion layer 53 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 The n-type impurity concentration of the third diffusion layer 53 may be the same as the n-type impurity concentration of the first diffusion layer 51. The n-type impurity concentration of the third diffusion layer 53 may be higher than the n-type impurity concentration of the first diffusion layer 51, or may be lower than the n-type impurity concentration of the first diffusion layer 51.

[0149] The fourth diffusion layer 54 is the uppermost layer of the stacked structure LS1. In this embodiment, the fourth diffusion layer 54 is circular in plan view. The fourth diffusion layer 54 surrounds the lower and lateral sides of the first diffusion layer 51. The p-type impurity concentration of the fourth diffusion layer 54 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 The p-type impurity concentration of the fourth diffusion layer 54 may be higher than the n-type impurity concentration of the second diffusion layer 52, or may be lower than the n-type impurity concentration of the second diffusion layer 52.

[0150] 25, a first stacked layer parasitic capacitance C1 is formed between the p-type second diffusion layer 52 and the n-type first diffusion layer 51. A second stacked layer parasitic capacitance C2 is formed between the n-type first diffusion layer 51 and the p-type semiconductor substrate 7. A third stacked layer parasitic capacitance (internal parasitic capacitance) C3 is formed between the p-type fourth diffusion layer 54 and the n-type third diffusion layer 53. A fourth stacked layer parasitic capacitance (internal parasitic capacitance) C4 is formed between the n-type third diffusion layer 53 and the p-type second diffusion layer 52. The first pad 9 faces the first pad region 10 with the insulating layer 23 interposed therebetween, and forms a parasitic capacitance CP1.

[0151] 26, the semiconductor device 1 includes a first pad 9, an opposing portion 7a (FIG. 25) of the semiconductor substrate 7 that opposes the first pad 9, and a first-pad parasitic capacitance circuit 190. The first-pad parasitic capacitance circuit 190 forms a series circuit consisting of a third stacked layer parasitic capacitance C3, a fourth stacked layer parasitic capacitance C4, a first stacked layer parasitic capacitance C1, a second stacked layer parasitic capacitance C2, and a parasitic capacitance CP1. A combined capacitance CS4 around the first pad 9 is expressed by the following equation (4):

[0152] CS4=C1×C2×C3×C4 / (CP1×C1×C2×C3+CP1×C1×C2×C4+CP1×C1×C3×C4+CP1×C2×C3×C4+C1×C2×C3×C4)×CP1...Formula (4)

[0153] Therefore, by making the laminated structure LS1 a multi-layer structure of three or more layers, the parasitic capacitance around the first pad 9 can be further reduced.

[0154] The modified example (first modified example) shown in FIGS. 25 and 26 may be applied to the stacked parasitic capacitance forming portion 550 (stacked structure LS2) of the fourth and fifth embodiments.

[0155] The stacked structures LS1 and LS2 are not limited to four-layer stacked structures. The stacked structures LS1 and LS2 may be three-layer structures without the fourth diffusion layer 54. Furthermore, the stacked structures LS1 and LS2 may further include an n-type fifth diffusion layer formed on the surface layer of the fourth diffusion layer 54, and may be five or more layer stacked structures.

[0156] The modified example (first modified example) shown in FIGS. 25 and 26 may be combined with any of the embodiments (including the modified examples) except for the first, fourth, and fifth embodiments.

[0157] 27, in the semiconductor device 1 according to the first embodiment, the bottom of the first diffusion layer 51 and the bottom of the second diffusion layer 52 may not be flat but may have a downwardly convex curved surface. The bottom of the first diffusion layer 51 and the bottom of the second diffusion layer 52 may have a downwardly convex spherical surface. The center of the bottom of the first diffusion layer 51 and the bottom of the second diffusion layer 52 may be the deepest part.

[0158] In this case, the contact area between the first diffusion layer 51 and the second diffusion layer 52 can be increased compared to when the bottoms of the first diffusion layer 51 and the second diffusion layer 52 are flat, thereby increasing the parasitic capacitance of the stacked structure LS1 and further reducing the parasitic capacitance around the first pad 9.

[0159] The modified example (second modified example) shown in FIG. 27 may be combined with any embodiment (including the modified example) except for the first embodiment.

[0160] As shown in FIG. 28, the depth of the p-type heavily doped region 203 (the eleventh depth D 11 ) may be deeper than the third depth D3 of the p-type emitter region 19 (FIG. 8B) and the sixth depth D6 of the p-type base region 22 (FIG. 8B). 11 >D3=D6). 11th depth D 11 may be deeper than the first depth D1 (FIG. 8B) of the first diffusion region 17 and the fourth depth D4 (FIG. 8B) of the second diffusion region 20 (D 11 >D1=D4). 11th depth D 11 However, it may be deeper than the seventh depth D7 (FIG. 10) of the bottom 51a of the first diffusion layer 51 (D 11 >D7). The modified example shown in FIG. 28 (third modified example) may be combined with any of the embodiments (including the modified examples) except for the second embodiment.

[0161] 29, the p-type high concentration region 203 may not be in contact with the first diffusion layer 51 (stacked structure LS1) but may be formed at a distance from the periphery of the first diffusion layer 51 (stacked structure LS1). The modification example (fourth modification example) shown in FIG. 29 may be combined with any embodiment (including the modification examples) other than the second embodiment.

[0162] 30, when the first thyristor structure 15 (i.e., the n-type first diffusion region 17 (FIG. 8A)) is adjacent to the stacked parasitic capacitance formation portion 50 (stacked structure LS1), the p-type high concentration region 203 may be in contact with the first thyristor structure 15 (first diffusion region 17 (FIG. 8A)). In the example of FIG. 30, the p-type high concentration region 203 is in contact with both the first diffusion layer 51 (stacked structure LS1) and the first thyristor structure 15 (first diffusion region 17 (FIG. 8A)). The modification example (fifth modification example) shown in FIG. 30 may be combined with any embodiment (including the modifications) other than the second embodiment.

[0163] 31, the p-type high concentration region 203 (isolation portion 202) according to the second embodiment may be applied to the semiconductor device 501 according to the fifth embodiment. In this case, the p-type high concentration region 203 is formed in the bottom surface 452 of the first trench 451. The modification example (sixth modification example) shown in FIG. 31 may be combined with any embodiment (including the modification examples) other than the second embodiment.

[0164] 32, the insulating trench structure 303 (isolation portion 302) according to the third embodiment may be applied to the semiconductor device 501 according to the fifth embodiment. In this case, the insulating trench structure 303 is formed on the bottom surface 452 of the first trench 451. The modification example (seventh modification example) shown in FIG. 32 may be combined with any of the embodiments (including the modifications) except for the second embodiment.

[0165] Furthermore, the semiconductor layer 6 does not have to be formed only by the semiconductor substrate 7, but may be a laminated structure of the semiconductor substrate 7 and a semiconductor layer (for example, an epitaxial layer). In this case, the first thyristor structure 15, the second thyristor structure 16, the laminated parasitic capacitance forming portions 50 and 550, the trench parasitic capacitance forming portion 450, etc. may be formed in the semiconductor layer (for example, an epitaxial layer).

[0166] In the above-described embodiments, examples have been described in which the first conductivity type is p-type and the second conductivity type is n-type, but the first conductivity type may be n-type and the second conductivity type may be p-type. A specific configuration in this case can be obtained by replacing p-type regions with n-type regions and n-type regions with p-type regions in the above description and accompanying drawings.

[0167] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0168] The following additional features can be extracted from the description of this specification and the drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments.

[0169] [Appendix A-1] a first conductivity type semiconductor layer (6) having a main surface (3); a first diffusion region (17) of a second conductivity type formed in a surface layer portion of the main surface (3); a second diffusion region (20) of the first conductivity type formed in a surface layer portion of the main surface (3); an insulating layer (23) formed on the main surface (3) so as to cover the first diffusion region (17) and the second diffusion region (20); a first pad (9) disposed on the insulating layer (23) and electrically connected to the first diffusion region (17); an internal parasitic capacitance forming portion (50, 450, 550) formed in a surface layer portion of the semiconductor layer (6) and forming internal parasitic capacitances (C1, C2, C3, C4, CT) between an opposing portion (7a) of the semiconductor layer (6) opposing the first pad (9) across the insulating layer (23) and the main surface (3) or an extension surface (EP) flush with the main surface (3); A semiconductor device (1, 201, 301, 401, 501) in which the first pad (9) forms a first parasitic capacitance (CP1) connected in series to the internal parasitic capacitances (C1, C2, C3, C4, CT) between the first pad (9) and an upper portion (230) of the insulating layer (23) formed above the main surface (3) or the extended surface (EP).

[0170] The first pad (9) is at the same potential as the first diffusion region (17) of the second conductivity type, so that a parasitic capacitance is formed between the first pad (9) and the semiconductor layer (6) of the first conductivity type.

[0171] According to this configuration, an internal parasitic capacitance-forming portion (50, 450, 550) is formed in the surface layer portion of the semiconductor layer (6). The internal parasitic capacitance-forming portion (50, 450, 550) forms internal parasitic capacitances (C1, C2, C3, C4, CT) between the opposing portion (7a) and the main surface (3) or the extended surface (EP). Then, a first parasitic capacitance (CP1) connected in series to the internal parasitic capacitances (C1, C2, C3, C4, CT) is formed between the first pad (9) and the upper portion (230). This reduces the parasitic capacitance around the first pad (9) (parasitic capacitance in the portion between the first pad and the opposing portion) compared to when the internal parasitic capacitance-forming portion (50, 450, 550) is not formed in the surface layer portion of the semiconductor layer (6).

[0172] [Appendix A-2] A semiconductor device (1, 201, 301, 501) according to Appendix A-1, wherein the internal parasitic capacitance forming portion (50, 450, 550) has a stacked structure (LS1, LS2) of a first diffusion layer (51, 551) of a second conductivity type formed on a surface layer portion of the semiconductor layer (6) so as to face the first pad (9) across the insulating layer (23), and a second diffusion layer (52, 552) of the first conductivity type formed on a surface layer portion of the first diffusion layer (51, 551), and includes a stacked parasitic capacitance forming portion (50, 550) that forms stacked parasitic capacitances (C1, C2, C3, C4) between the semiconductor layer (6) and the surface of the stacked structure (LS1, LS2).

[0173] According to this configuration, a stacked structure (LS1, LS2) having a first diffusion layer (51, 551) and a second diffusion layer (52, 552) is formed in a surface layer portion of the semiconductor layer (6). A stacked parasitic capacitance (first stacked parasitic capacitance (CL1)) is formed between the second diffusion layer (52, 552) of the first conductivity type and the first diffusion layer (51, 551) of the second conductivity type, and a stacked parasitic capacitance (second stacked parasitic capacitance (CL2)) is formed between the first diffusion layer 51 of the second conductivity type and the semiconductor layer (6) of the first conductivity type. Then, a first parasitic capacitance (CP1) connected in series to these stacked parasitic capacitances (C1, C2, C3, C4) is formed between the first pad (9) and the upper portion (230). This reduces the parasitic capacitance around the first pad (9) (the parasitic capacitance in the area between the first pad and the opposing portion) compared to when the laminated structure (LS1, LS2) is not formed on the surface layer of the semiconductor layer (6).

[0174] [Appendix A-3] The semiconductor device (1, 201, 301, 501) according to Appendix A-2, wherein the first diffusion layer (51, 551) is formed on the main surface (3).

[0175] [Appendix A-4] The semiconductor device (1, 201, 301, 501) according to Appendix A-2 or Appendix A-3, wherein a depth (D8) of a bottom (52a, 552a) of the second diffusion layer (52, 552) is shallower than a bottom (51a, 551a) of the first diffusion layer (51, 551).

[0176] [Appendix A-5] A semiconductor device (1, 201, 301, 501) according to any one of Appendices A-2 to A-4, wherein a depth (D7) of a bottom (51a, 551a) of the first diffusion layer (51, 551) is equal to a depth (D1) of a bottom (17a) of the first diffusion region (17).

[0177] [Appendix A-6] The semiconductor device (1, 201, 301, 501) according to any one of Appendices A-2 to A-5, wherein a depth (D8) of a bottom (52a, 552a) of the second diffusion layer (52, 552) is shallower than a bottom (17a) of the first diffusion region (17).

[0178] [Appendix A-7] A semiconductor device (1, 201, 301, 501) according to any one of Appendices A-2 to A-6, further comprising a separation portion (202, 302) formed between the first diffusion region (17) and the first diffusion layer (51, 551) and separating the first diffusion region (17) from the first diffusion layer (51, 551).

[0179] [Appendix A-8] The semiconductor device (1, 201, 301, 401, 501) according to Appendix A-7, wherein the separation portion (202, 302) includes a high concentration region (203) of the first conductivity type having a higher concentration of the first conductivity type impurity than the semiconductor layer (6).

[0180] [Appendix A-9] The semiconductor device (1, 201, 301, 501) according to Appendix A-8, wherein the first conductivity type impurity concentration of the high concentration region (203) is higher than the first conductivity type impurity concentration of the second diffusion region (20).

[0181] [Appendix A-10] A semiconductor device (1, 201, 301, 501) described in Appendix A-7, wherein the isolation portion includes an insulating trench structure (303) including an insulating trench (304) formed in a surface portion of the semiconductor layer (6) and an insulator (305) embedded in the insulating trench (304).

[0182] [Appendix A-11] The depth (D 10 ) is deeper than a bottom (51a, 551a) of the first diffusion layer (51, 551).

[0183] [Appendix A-12] A semiconductor device (1, 201, 301, 501) according to any one of Appendices A-2 to A-11, wherein the stacked structure (LS1, LS2) further includes a third diffusion layer (53) of a second conductivity type formed on a surface portion of the second diffusion layer (52, 552).

[0184] [Appendix A-13] The first pad (9) has an electrode surface (38) on which a connecting body (W) can be placed, A semiconductor device (1, 201, 301, 501) according to any one of Appendix A-2 to Appendix A-12, wherein, in a planar view, the stacked parasitic capacitance forming portion (50, 550) overlaps the electrode surface (38) via the insulating layer (23).

[0185] [Appendix A-14] The semiconductor device (1, 201, 301, 501) according to any one of Appendices A-1 to A-13, wherein the semiconductor layer (6) is a semiconductor substrate (7).

[0186] [Appendix A-15] a first conductivity type semiconductor layer (6) having a main surface (3); a first diffusion region (17) of a second conductivity type formed in a surface layer portion of the main surface (3); a second diffusion region (20) of the first conductivity type formed in a surface layer portion of the main surface (3); an insulating layer (23) formed on the main surface (3) so as to cover the first diffusion region (17) and the second diffusion region (20); a first pad (9) disposed on the insulating layer (23) and electrically connected to the first diffusion region (17); a laminated parasitic capacitance forming portion (50, 550) having a laminated structure (LS1, LS2) of a first diffusion layer (51, 551) of a second conductivity type formed in a surface layer portion of the semiconductor layer (6) so as to face the first pad (9) with the insulating layer (23) interposed therebetween, and a second diffusion layer (52, 552) of the first conductivity type formed in a surface layer portion of the first diffusion layer (51, 551), and forming laminated parasitic capacitances (C1, C2, C3, C4) between the semiconductor layer (6) and the surface of the laminated structure (LS1, LS2); A semiconductor device (1, 201, 301, 501) in which the first pad (9) forms a second parasitic capacitance (CP1, CP2) connected in series to the stacked parasitic capacitance (C1, C2, C3, C4) between the first pad (9) and the insulating layer (23).

[0187] The first pad (9) is at the same potential as the first diffusion region (17) of the second conductivity type, so that a parasitic capacitance is formed between the first pad (9) and the semiconductor layer (6) of the first conductivity type.

[0188] According to this configuration, a stacked structure (LS1, LS2) having a first diffusion layer (51, 551) and a second diffusion layer (52, 552) is formed on a surface layer portion of the semiconductor layer (6). A stacked parasitic capacitance (first stacked parasitic capacitance (CL1)) is formed between the second diffusion layer (52, 552) of the first conductivity type and the first diffusion layer (51, 551) of the second conductivity type, and a stacked parasitic capacitance (second stacked parasitic capacitance (CL2)) is formed between the first diffusion layer 51 of the second conductivity type and the semiconductor layer (6) of the first conductivity type. Then, a second parasitic capacitance connected in series to the stacked parasitic capacitances (C1, C2, C3, C4) is formed between the first pad (9) and the insulating layer (23). This reduces the parasitic capacitance around the first pad (9) (parasitic capacitance between the first pad and the opposing portion) compared to when the stacked structures (LS1, LS2) are not formed on the surface layer portion of the semiconductor layer (6).

[0189] [Appendix B-1] a first conductivity type semiconductor layer (6) having a main surface (3); a first diffusion region (17) of a second conductivity type formed in a surface layer portion of the main surface (3); a second diffusion region (20) of the first conductivity type formed in a surface layer portion of the main surface (3); an insulating layer (23) formed on the main surface (3) so as to cover the first diffusion region (17) and the second diffusion region (20); a first pad (9) disposed on the insulating layer (23) and electrically connected to the first diffusion region (17); an internal parasitic capacitance forming portion (450, 550) formed in a surface layer portion of the semiconductor layer (6) and forming internal parasitic capacitances (C1, C2, C3, C4, CT) between an opposing portion (7a) of the semiconductor layer (6) opposing the first pad (9) across the insulating layer (23) and the main surface (3) or an extension surface (EP) flush with the main surface (3); the internal parasitic capacitance forming portion (450, 550) is a trench parasitic capacitance forming portion (450) having a first trench (451) formed in the main surface (3) and an intra-trench insulating layer (231) of the insulating layer (23) embedded inside the first trench (451), and includes a trench parasitic capacitance forming portion (450) that forms a trench parasitic capacitance (CT) between the extension surface (EP) of the first trench (451) and the facing portion (7a) formed on a bottom surface (452) of the first trench (451); A semiconductor device (401, 501) in which the first pad (9) forms a first parasitic capacitance (CP1) connected in series to the trench parasitic capacitance (CT) between the first pad (9) and an upper portion (230) of the insulating layer (23) formed above the main surface (3) or the extended surface (EP).

[0190] According to this configuration, a trench parasitic capacitance forming portion (450) is formed in the surface layer portion of the semiconductor layer (6). The trench parasitic capacitance forming portion (450) forms a trench parasitic capacitance (CT) between the facing portion (7a) and the main surface (3) or the extended surface (EP). Then, a first parasitic capacitance (CP1) connected in series to the trench parasitic capacitance (CT) is formed between the first pad (9) and the upper portion (230). This reduces the parasitic capacitance around the first pad (9) (the parasitic capacitance in the portion between the first pad and the facing portion) compared to when the trench parasitic capacitance forming portion (450) is not formed in the surface layer portion of the semiconductor layer (6).

[0191] [Appendix B-2] The semiconductor device (401, 501) according to Appendix B-1, wherein the bottom surface (452) of the first trench (451) is a flat surface parallel to the main surface (3).

[0192] [Appendix B-3] A semiconductor device (401, 501) according to Appendix B-1 or Appendix B-2, wherein a depth (DT) of the bottom surface (452) of the first trench (451) is deeper than a bottom (17a) of the first diffusion region (17).

[0193] [Appendix B-4] The first pad (9) has an electrode surface (38) on which a connecting body (W) can be placed, A semiconductor device (401, 501) according to any one of Appendices B-1 to B-3, wherein, in a planar view, the trench parasitic capacitance forming portion (450) overlaps the electrode surface (38) via the insulating layer (23).

[0194] [Appendix B-5] The semiconductor device (501) according to any one of Appendices B-1 to B-4, wherein the internal parasitic capacitance forming portion (450, 550) further includes a stacked parasitic capacitance forming portion (550) having a stacked structure (LS2) of a first diffusion layer (51, 551) of a second conductivity type formed in a surface layer portion of the semiconductor layer (6) so as to face the first pad (9) across the insulating layer (23), and a second diffusion layer (52, 552) of the first conductivity type formed in a surface layer portion of the first diffusion layer (51, 551), and forming stacked parasitic capacitances (C1, C2, C3, C4) between the semiconductor layer (6) and the surface of the stacked structure (LS2).

[0195] [Appendix B-6] The semiconductor device (501) according to Appendix B-5, wherein a depth (D8) of a bottom (52a, 552a) of the second diffusion layer (52, 552) is shallower than a depth (D8) of a bottom (51a, 551a) of the first diffusion layer (51, 551).

[0196] [Appendix B-7] A semiconductor device (501) according to Appendix B-5 or Appendix B-6, wherein a depth (D7) of a bottom (51a, 551a) of the first diffusion layer (51, 551) is equal to a depth (D1) of a bottom (17a) of the first diffusion region (17).

[0197] [Appendix B-8] The semiconductor device (501) according to any one of Appendices B-5 to B-7, wherein a depth (D8) of a bottom (52a, 552a) of the second diffusion layer (52, 552) is shallower than a bottom (17a) of the first diffusion region (17).

[0198] [Appendix B-9] A semiconductor device (501) according to Appendices B-5 to B-8, further comprising a separation portion (202, 302) formed between the first diffusion layer (51, 551) and the periphery of the bottom surface (452) of the first trench (451), separating the first diffusion region (17) from the first diffusion layer (51, 551).

[0199] [Appendix B-10] The semiconductor device (501) according to Appendix B-9, wherein the separation portion (202, 302) includes a high concentration region (203) of the first conductivity type having a higher concentration of the first conductivity type impurity than the semiconductor layer (6).

[0200] [Appendix B-11] The semiconductor device (501) according to Appendix B-10, wherein the first conductivity type impurity concentration of the high concentration region (203) is higher than the first conductivity type impurity concentration of the second diffusion region (20).

[0201] [Appendix B-12] A semiconductor device (501) according to Appendix B-9, wherein the isolation portion includes an insulating trench structure (303) including an insulating trench (304) formed on the bottom surface (452) of the first trench (451) and an insulator (305) embedded in the insulating trench (304).

[0202] [Appendix B-13] The depth (D 10 ) is deeper than the bottom (51a, 551a) of the first diffusion layer (51, 551).

[0203] [Appendix B-14] The semiconductor device (401, 501) according to any one of Appendices B-1 to B-13, wherein the semiconductor layer (6) is a semiconductor substrate (7).

[0204] [Appendix B-15] a first conductivity type semiconductor layer (6) having a main surface (3); a first diffusion region (17) of a second conductivity type formed in a surface layer portion of the main surface (3); a second diffusion region (20) of the first conductivity type formed in a surface layer portion of the main surface (3); an insulating layer (23) formed on the main surface (3) so as to cover the first diffusion region (17) and the second diffusion region (20); a first pad (9) disposed on the insulating layer (23) and electrically connected to the first diffusion region (17); a first trench (451) formed on the main surface (3) so as to face the first pad with the insulating layer therebetween, the first trench (451) having a portion (231) of the insulating layer buried therein; A semiconductor device (401, 501) in which the first pad (9) forms a third parasitic capacitance (CP2) between the first pad (9) and an opposing region (7a) formed on the bottom surface (452) of the first trench (451) so as to face the first pad (9) across the insulating layer (23).

[0205] According to this configuration, a trench parasitic capacitance forming portion (450) is formed in the surface layer portion of the semiconductor layer (6). Compared to when the first trench (451) is not formed in the first main surface (3), the distance between the first pad (9) and the opposing portion (7a) can be kept larger. Since the parasitic capacitance (CP3) is inversely proportional to the distance between the electrodes, by keeping the distance between the first pad (9) and the opposing portion (7a) large, the parasitic capacitance around the first pad (9) can be reduced. [Explanation of symbols]

[0206] 1: Semiconductor device 2: Tip 3: First main surface (main surface) 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: Semiconductor layer 7: Semiconductor substrate 7a: Opposing part 8:Device formation area 9: First pad 10: First pad area 11: Second pad 12: Second pad area 13: Thyristor area 14: Thyristor structure 15: First thyristor structure 16: Second thyristor structure 17: First diffusion region 17a: Bottom 18: n-type base region 18a: Bottom 19: p-type emitter region 19a: Bottom 20: Second diffusion region 20a: bottom 21: n-type emitter region 21a: Bottom 22: p-type base region 22a: Bottom 23: Insulating layer 230: Upper part 24: 1st wiring layer 25: 2nd wiring layer 27: First connection structure 28: Second connection structure 29: 1st bottom via 30: 1st upper via 31: Second bottom via 33: Upper insulating film 35: First pad opening 36: Second pad opening 37: Shield ring 38: 1st electrode surface 39:Second electrode surface 41: 1st pn junction 42: 2nd pn junction 50: Stacked parasitic capacitance forming portion (internal parasitic capacitance forming portion) 51: First diffusion layer 51a: Bottom 52: Second diffusion layer 52a: bottom 53: Third diffusion layer 54: Fourth diffusion layer 55: First connection wiring 56: Second connection wiring 57: Pad wiring 80:TVS circuit 81: 1st parallel circuit 82: 2nd parallel circuit 90: First pad parasitic capacitance circuit 190: First pad parasitic capacitance circuit 201: Semiconductor device 202: Separation section 203: p-type high concentration region 230: Upper part 231: Trench insulation layer (part) 301: Semiconductor device 302: Separation part 303: Insulated trench structure 304: Insulation trench 305: Insulator 401: Semiconductor device 450: Trench parasitic capacitance forming portion (internal parasitic capacitance forming portion) 451: First Trench 452: Bottom 453: Side 490: First pad parasitic capacitance circuit 501: Semiconductor device 550: Stacked parasitic capacitance forming portion (internal parasitic capacitance forming portion) 551: First diffusion layer 551a: Bottom 552: Second diffusion layer 552a: Bottom 590: First pad parasitic capacitance circuit BW: Connector C1: First layer parasitic capacitance (internal parasitic capacitance) C2: Second layer parasitic capacitance (internal parasitic capacitance) C3: Third layer parasitic capacitance (internal parasitic capacitance) C4: 4th layer parasitic capacitance (internal parasitic capacitance) CP1: Parasitic capacitance (first parasitic capacitance, second parasitic capacitance) CP2: Parasitic capacitance (third parasitic capacitance) CT: Trench parasitic capacitance (internal parasitic capacitance) D1: First depth D2: Second depth D3: Third depth D4: 4th depth D5: 5th depth D6: 6th depth D7: 7th depth D8: 8th depth D9: 9th depth D 10 :10th depth D 11 :11th depth DL1: First diameter DL2: Second diameter DL3: 3rd diameter DL4: 4th diameter DL5: 5th diameter DT: Trench depth DZ1: First Zener diode DZ2: Second Zener diode EP: Extension surface LS1: Laminated structure LS2: Laminated structure T230: Thickness W1: 1st width W2: Second width W3: 3rd width W4: 4th width W5: 5th width W6: 6th width W7: 7th width X: 1st direction Y: Second direction Z: Vertical direction

Claims

1. a first conductivity type semiconductor layer having a major surface; a first diffusion region of a second conductivity type formed in a surface layer portion of the main surface; a second diffusion region of the first conductivity type formed in a surface layer portion of the main surface; an insulating layer formed on the main surface so as to cover the first diffusion region and the second diffusion region; a first pad disposed on the insulating layer and electrically connected to the first diffusion region; an internal parasitic capacitance forming portion formed in a surface layer portion of the semiconductor layer, which forms an internal parasitic capacitance between an opposing portion of the semiconductor layer that faces the first pad across the insulating layer and the main surface or an extended surface that is flush with the main surface; the internal parasitic capacitance forming portion is a trench parasitic capacitance forming portion having a first trench formed in the main surface and an inner trench portion of the insulating layer embedded inside the first trench, and includes a trench parasitic capacitance forming portion that forms a trench parasitic capacitance between the extension surface in the first trench and the opposing portion formed on a bottom surface of the first trench, a first parasitic capacitance connected in series to the trench parasitic capacitance between the first pad and an upper portion of the insulating layer formed above the main surface or the extended surface;

2. The semiconductor device according to claim 1 , wherein the bottom surface of the first trench is a flat surface parallel to the main surface.

3. The semiconductor device according to claim 1 , wherein the depth of the bottom surface of the first trench is deeper than the bottom of the first diffusion region.

4. the first pad has an electrode surface on which a connector can be placed, 2. The semiconductor device according to claim 1, wherein said trench parasitic capacitance forming portion overlaps said electrode surface via said insulating layer in plan view.

5. 5. The semiconductor device according to claim 1, wherein the internal parasitic capacitance forming portion has a stacked structure including a first diffusion layer of a second conductivity type formed in a surface layer portion of the semiconductor layer so as to face the first pad across the insulating layer, and a second diffusion layer of the first conductivity type formed in the surface layer portion of the first diffusion layer, and further includes a stacked parasitic capacitance forming portion that forms a stacked parasitic capacitance between the semiconductor layer and the surface of the stacked structure.

6. 6. The semiconductor device according to claim 5, wherein the depth of the bottom of said second diffusion layer is shallower than the depth of the bottom of said first diffusion layer.

7. 6. The semiconductor device according to claim 5, wherein the depth of the bottom of said first diffusion layer is equal to the depth of the bottom of said first diffusion region.

8. 6. The semiconductor device according to claim 5, wherein the depth of the bottom of said second diffusion layer is shallower than the depth of the bottom of said first diffusion region.

9. 6. The semiconductor device according to claim 5, further comprising an isolation portion formed between said first diffusion layer and a periphery of said bottom surface of said first trench, said isolation portion isolating said first diffusion region from said first diffusion layer.

10. 10. The semiconductor device according to claim 9, wherein said isolation portion includes a high concentration region of the first conductivity type having a higher concentration of first conductivity type impurities than said semiconductor layer.

11. 11. The semiconductor device according to claim 10, wherein a first conductivity type impurity concentration of said high concentration region is higher than a first conductivity type impurity concentration of said second diffusion region.

12. 10. The semiconductor device according to claim 9, wherein the isolation portion includes an insulating trench structure including an insulating trench formed in the bottom surface of the first trench and an insulating film buried in the insulating trench.

13. The semiconductor device according to claim 12 , wherein the depth of the bottom of said insulating trench structure is deeper than the depth of the bottom of said first diffusion layer.

14. 3. The semiconductor device according to claim 1, wherein the semiconductor layer is a semiconductor substrate.

15. a first conductivity type semiconductor layer having a major surface; a first diffusion region of a second conductivity type formed in a surface layer portion of the main surface; a second diffusion region of the first conductivity type formed in a surface layer portion of the main surface; an insulating layer formed on the main surface so as to cover the first diffusion region and the second diffusion region; a first pad disposed on the insulating layer and electrically connected to the first diffusion region; a first trench formed in the main surface, the first trench having a portion of the insulating layer buried therein; The semiconductor device, wherein the first pad forms a third parasitic capacitance with an opposing region formed at the bottom surface of the first trench so as to face the first pad with the insulating layer interposed therebetween.

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