Power conversion device and gate drive circuit therefor

Abstract

To suppress malfunction of an upper arm power semiconductor element even when disturbance noise occurs.SOLUTION: A power conversion device 11 includes: an upper arm IGBT 13 provided between a main DC power source Vdc and an output-terminal Pout; a gate short-circuit MOSFET 17 provided between a first gate terminal 13G related to the upper arm IGBT 13 and the output terminal Pout and in which a first parasitic capacitance Cgs is provided in parallel; a first zener diode DZ1 provided between a second gate terminal 17G related to the gate-short-circuit MOSFET 17 and the output-terminal Pout; a first diode D1 provided between the main DC power source Vdc and the first zener diode DZ1 and in which a second parasitic capacitance Cd1 is provided in parallel; and a second diode D2 provided close to the first diode D1 and configured to irradiate the first diode D1 with light.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a gate drive circuit for a power conversion device and a power conversion device. [Background technology]

[0002] A power conversion device (inverter device) has the function of converting DC power into AC power using power semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). Operating an inverter device requires a gate drive circuit to turn the power semiconductor elements on and off.

[0003] Patent Document 1 discloses an invention relating to a gate drive circuit for a power conversion device in which a gate short-circuiting MOSFET is provided between the gate and emitter of an upper arm IGBT, and in a level shift circuit that converts a low-voltage side signal into a drive signal for the upper arm IGBT, the circuit configuration is such that a voltage drop occurs across a resistor on the high-voltage side by turning a current source on and off, and the gate drive circuit is equipped with a means for pulsing the transmission signal. According to the gate drive circuit of the power conversion device disclosed in Patent Document 1, when the inverter device and the gate drive circuit are integrated, power consumption and manufacturing costs can be reduced. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 11-313488 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the gate drive circuit of the power conversion device according to Patent Document 1, when the upper arm IGBT (upper arm power semiconductor element) is in the off state due to the on operation of the gate short-circuiting MOSFET (gate short-circuiting semiconductor element), the gate short-circuiting semiconductor element may be turned off by external noise or the like, which may result in a malfunction of the upper arm power semiconductor element (transition from the off state to the on state).

[0006] The present invention has been made to solve the above-mentioned problems, and aims to provide a gate drive circuit for a power conversion device that can suppress malfunction of an upper arm power semiconductor element even when disturbance noise or the like occurs, and the power conversion device. [Means for solving the problem]

[0007] In order to solve the above problem, the gate drive circuit of the power conversion device according to the present invention comprises: A gate drive circuit of a power conversion device that converts DC power into AC power and outputs the AC power, an upper arm power semiconductor element (13) provided between a main DC power supply (Vdc) and an output terminal (Pout); a gate short-circuiting semiconductor element (17) provided between a first gate terminal (13G) of the upper arm power semiconductor element (13) and the output terminal (Pout), and having a first parasitic capacitance (Cgs) arranged in parallel therewith; a first Zener diode (DZ1) provided between a second gate terminal (17G) of the gate short-circuiting semiconductor element (17) and the output terminal (Pout); a first diode (D1) provided between the main DC power supply (Vdc) and the first Zener diode (DZ1), and having a second parasitic capacitance (Cd1) arranged in parallel therewith; a second diode (D2) provided adjacent to the first diode (D1) and irradiating light onto the first diode (D1); the first Zener diode (DZ1) and the first diode (D1) are connected in series via a relay point (18) that has approximately the same potential as the second gate terminal (17G); An upper arm control signal is input to the first gate terminal (13G), and a gate short circuit control signal is input to the second gate terminal (17G), The main DC power supply (Vdc), the output terminal (Pout), the upper arm power semiconductor element (13), the gate short-circuiting semiconductor element (17), the first Zener diode (DZ1), and the first diode (D1) belong to a common high-voltage wiring system, while the second diode (D2) belongs to a low-voltage wiring system that is electrically independent from the high-voltage wiring system. This is its most important feature.

[0008] According to the present invention, even when disturbances such as noise occur, malfunction of the upper arm power semiconductor element can be suppressed. Problems, configurations, and effects other than those described above will be described in detail in the following embodiments. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic configuration diagram of a power conversion device according to a comparative example. [Figure 2A] FIG. 10 is a time chart illustrating the operation of a power conversion device according to a comparative example. [Figure 2B] FIG. 10 is a time chart illustrating the operation of a power conversion device according to a comparative example. [Figure 3] 1 is a schematic configuration diagram of a power conversion device according to an embodiment of the present invention. [Figure 4A] 3 is a time chart illustrating the operation of the power conversion device according to the embodiment of the present invention. FIG. [Figure 4B] 3 is a time chart illustrating the operation of the power conversion device according to the embodiment of the present invention. FIG. [Figure 5] FIG. 10 is a partial configuration diagram showing the periphery of a first diode in a power conversion device according to a modified example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A gate drive circuit for a power conversion device and a power conversion device according to embodiments of the present invention will be described in detail with reference to the appropriate drawings. In the description of the gate drive circuit of the power conversion device and the power conversion device according to the embodiment of the present invention, components having common functions are given common reference numerals, and duplicated descriptions thereof will be omitted as a general rule.

[0011] [Power conversion device 10 according to comparative example] First, a power conversion device 10 according to a comparative example will be described with reference to Fig. 1. Fig. 1 is a schematic configuration diagram of the power conversion device 10 according to the comparative example.

[0012] As shown in FIG. 1, the power conversion device 10 according to the comparative example has a function of converting DC power supplied from a high-voltage main DC power supply Vdc (for example, but not limited to, 600 V) into AC power and outputting it to an output terminal Pout.

[0013] To achieve these functions, the power conversion device 10 according to the comparative example is configured to include a main DC power supply Vdc, an output terminal Pout, an upper arm IGBT 13 (Q1), a lower arm IGBT 15 (Q2), a gate short-circuiting MOSFET 17 (M1), a first Zener diode DZ1, a first diode D1, a second Zener diode DZ2, and a MOSFET 19 (M2), as shown in FIG.

[0014] The upper arm IGBT 13 (Q1) is an N-channel IGBT provided between the main DC power supply Vdc and the output terminal Pout. The upper arm IGBT 13 (Q1) has a collector terminal C connected to the positive electrode of the main DC power supply Vdc and an emitter terminal E connected to the output terminal Pout. A first freewheeling diode D3 is connected in anti-parallel to the upper arm IGBT 13 (Q1). An upper arm control signal is input to a first gate terminal 13G (hereinafter sometimes abbreviated as "first gate terminal 13G") associated with the upper arm IGBT 13 (Q1). This controls the switching operation of the upper arm IGBT 13 (Q1).

[0015] The gate short-circuiting MOSFET 17(M1) is an N-channel MOSFET provided between the first gate terminal 13G and the output terminal Pout. The gate short-circuiting MOSFET 17(M1) has a drain terminal D connected to the gate terminal G of the upper arm IGBT 13(Q1) and a source terminal S connected to the output terminal Pout. A gate short-circuiting control signal is input to a second gate terminal 17G (hereinafter sometimes abbreviated as "second gate terminal 17G") of the gate short-circuiting MOSFET 17(M1) via a MOSFET 19(M2). This controls the switching operation of the gate short-circuiting MOSFET 17(M1).

[0016] A first Zener diode DZ1 is provided between the second gate terminal 17G and the output terminal Pout. The first Zener diode DZ1 has a cathode terminal K connected to the second gate terminal 17G and an anode terminal A connected to the output terminal Pout.

[0017] Between the second gate terminal 17G and the output terminal Pout, a first parasitic capacitance Cgs is provided in parallel with a first Zener diode DZ1. Here, the first parasitic capacitance Cgs exhibits a capacitance value that combines the parasitic capacitance occurring between the second gate terminal 17G and the source terminal S and the parasitic capacitance occurring between the cathode terminal K and the anode terminal A of the first Zener diode DZ1.

[0018] The first diode D1 is provided between the second gate terminal 17G and the main DC power supply Vdc. The first diode D1 is a high-voltage diode that has a withstand voltage characteristic exceeding the voltage of the main DC voltage Vdc. The first diode D1 has a cathode terminal K connected to the positive electrode of the main DC power supply Vdc and an anode terminal A connected to a relay point 18 that has approximately the same potential as the second gate terminal 17G. In other words, the first Zener diode DZ1 and the first diode D1 are connected in series via the relay point 18 that has approximately the same potential as the second gate terminal 17G.

[0019] A second parasitic capacitance Cd1 is provided in parallel with the first diode D1 between the relay point 18 (second gate terminal 17G) and the main DC power supply Vdc. The second parasitic capacitance Cd1 has a value according to the parasitic capacitance occurring between the cathode terminal K and the anode terminal A of the first diode D1.

[0020] The second Zener diode DZ2 is provided between the first gate terminal 13G and the output terminal Pout. The second Zener diode DZ2 has a cathode terminal K connected to the first gate terminal 13G and an anode terminal A connected to the output terminal Pout.

[0021] The lower arm IGBT 15(Q2) is an N-channel IGBT provided between the output terminal Pout and the ground terminal GND. The lower arm IGBT 15(Q2) has a collector terminal C connected to the output terminal Pout and an emitter terminal E connected to the ground terminal GND. A second freewheeling diode D4 is connected in anti-parallel to the lower arm IGBT 15(Q2). A lower arm control signal is input to a third gate terminal 15G (hereinafter sometimes abbreviated as "third gate terminal 15G") associated with the lower arm IGBT 15(Q2). This controls the switching operation of the lower arm IGBT 15(Q2).

[0022] The MOSFET 19 (M2) is an N-channel MOSFET provided between the relay point 18 (second gate terminal 17G) and the ground terminal GND. The MOSFET 19 (M2) has a drain terminal D connected to the relay point 18 (second gate terminal 17G) and a source terminal S connected to the ground terminal GND. A gate short-circuit control signal is input to a fourth gate terminal 19G (hereinafter sometimes abbreviated as "fourth gate terminal 19G") associated with the MOSFET 19 (M2). This controls the switching operation of the MOSFET 19 (M2).

[0023] [Operation of the power conversion device 10 according to the comparative example] Next, the operation of the power conversion device 10 according to the comparative example will be described with reference to Figs. 2A and 2B. Figs. 2A and 2B are time charts used to explain the operation of the power conversion device 10 according to the comparative example. In Fig. 2A, the horizontal axis represents time, and the vertical axis represents L-level / H-level logic. In Fig. 2B, the horizontal axis represents time, and the vertical axis represents voltage. There may be a time delay in the voltage according to Fig. 2B compared to the logic according to Fig. 2A.

[0024] As shown in FIG. 2A, the upper arm control signal is a signal that is input to the first gate terminal 13G of the upper arm IGBT 13 (Q1) and controls the switching operation of the upper arm IGBT 13 (Q1). 2A, the gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19 (M2) and is a signal for controlling the switching operation of the gate short-circuiting MOSFET 17 (M1) via the switching operation of the MOSFET 19 (M2). The gate short-circuiting MOSFET 17 (M1) has a function of turning off the upper arm IGBT 13 (Q1) that is in the on state.

[0025] The MOSFET 19 (M2) has a function of turning off the gate short-circuiting MOSFET 17 (M1) by extracting the charge (first parasitic capacitance Cgs) stored between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) through a switching operation in accordance with the gate short-circuiting control signal. As a result, when the upper arm IGBT 13 (Q1) is in the on state, the MOSFET 19 (M2) operates to turn off the gate short-circuiting MOSFET 17 (M1).

[0026] To achieve this function, the waveform of the gate short-circuit control signal is synchronized in time series with the waveform of the upper arm control signal and has a common polarity value. Note that being synchronized in time series and having a common polarity value means that the gate short-circuit control signal is at L level when the upper arm control signal is L, and at H level when the upper arm control signal is H, as shown in Figure 2A.

[0027] The waveform of the voltage across the second gate terminal 17G-S of the gate short-circuiting MOSFET 17(M1) is synchronized in time series with the waveform of the gate short-circuiting control signal and exhibits an inverted value. Note that being synchronized in time series with and exhibiting an inverted value means that, as shown in Fig. 2A, the voltage across the second gate terminal 17G-S is at H level (the gate short-circuiting MOSFET 17(M1) is off) during a period when the gate short-circuiting control signal is at L level, and the voltage across the second gate terminal 17G-S is at L level (the gate short-circuiting MOSFET 17(M1) is on) during a period when the gate short-circuiting control signal is at H level.

[0028] Furthermore, the waveform of the voltage across the first gate terminals 13G-S of the upper arm IGBT 13(Q1) is synchronized in time series with the waveform of the upper arm control signal and has a common polarity value. Note that being synchronized in time series and having a common polarity value means that, as shown in Fig. 2A, the voltage across the first gate terminals 13G-E is at an L level (the upper arm IGBT 13(Q1) is off) during a period when the upper arm control signal is at an L level, and the voltage across the first gate terminals 13G-E is at an H level (the upper arm IGBT 13(Q1) is on) during a period when the upper arm control signal is at an H level.

[0029] 2A, to turn on the upper arm IGBT 13 (Q1), an H-level gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19 (M2), and an H-level upper arm control signal is input to the first gate terminal 13G of the upper arm IGBT 13 (Q1). The H-level gate short-circuit control signal and the upper arm control signal are input to the fourth gate terminal 19G and the first gate terminal 13G, respectively, in synchronization with each other. A lower arm control signal of L level is input to the third gate terminal 15G of the lower arm IGBT 15(Q2) in time synchronization with the upper arm control signal of H level, thereby turning the lower arm IGBT 15(Q2) off.

[0030] When an H-level gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19(M2), the MOSFET 19(M2) is turned on. This lowers the potential of the relay node 18 connected to the drain terminal D of the MOSFET 19(M2), causing the charge (first parasitic capacitance Cgs) stored between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17(M1) to be extracted. As a result, the voltage between the second gate terminal 17G and the source S converges to the L level (see FIG. 2A). As a result, the gate short-circuiting MOSFET 17 (M1) is turned off.

[0031] When the gate short-circuiting MOSFET 17 (M1) is in the off state, if an H-level upper-arm control signal is input to the first gate terminal 13G of the upper-arm IGBT 13 (Q1), the voltage between the first gate terminal 13G and the emitter E of the upper-arm IGBT 13 (Q1) is inverted to the H level, and the upper-arm IGBT 13 (Q1) is turned on (see FIG. 2A). As a result, a predetermined output voltage Va related to the main DC power supply Vdc is supplied to the output terminal Pout.

[0032] 2A, to turn off the upper arm IGBT 13 (Q1), an L-level gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19 (M2), and an L-level upper arm control signal is input to the first gate terminal 13G of the upper arm IGBT 13 (Q1). The L-level gate short-circuit control signal and the upper arm control signal are input to the fourth gate terminal 19G and the first gate terminal 13G, respectively, in synchronization with each other. A lower arm control signal of H level is input to the third gate terminal 15G of the lower arm IGBT 15(Q2) in time synchronization with the upper arm control signal of L level, thereby turning on the lower arm IGBT 15(Q2).

[0033] 2B, assume that an L-level upper-arm control signal is input to the first gate terminal 13G of the upper-arm IGBT 13 (Q1). Then, at the same time t1, the collector C-emitter E voltage of the upper-arm IGBT 13 (Q1) inverts from L to H, and the upper-arm IGBT 13 (Q1) enters an OFF state. As a result, from time t1 to time t4, the voltage between the emitter E of the upper arm IGBT 13 (Q1) and the ground terminal GND (the potential of the output terminal Pout) drops approximately linearly from the predetermined output voltage Va to the ground potential. After time t1, the voltage between the first gate terminal 13G and the emitter E of the upper arm IGBT 13 (Q1) begins to rise substantially linearly.

[0034] Between times t1 and t3, the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) (the potential at the relay point 18) rises approximately linearly from the ground potential to the DZ1 clamp voltage Vdz1 in accordance with the capacitive voltage division between the first parasitic capacitance Cgs and the second parasitic capacitance Cd1.

[0035] At time t2, when the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) (the potential at the relay point 18) exceeds the M1 threshold voltage VthM1, the voltage between the drain D and the source S of the gate short-circuiting MOSFET 17 (M1) is inverted from the H level to the L level, and the gate short-circuiting MOSFET 17 (M1) is turned on. As a result, after time t2, the voltage between the first gate terminal 13G and the emitter E of the upper arm IGBT 13 (Q1) drops substantially linearly until it reaches the ground potential. This is because the drain D and source S of the gate short-circuiting MOSFET 17 (M1) become conductive, thereby short-circuiting the first gate terminal 13G and the emitter E of the upper arm IGBT 13 (Q1).

[0036] At time t3, when the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) (potential at the relay point 18) reaches the DZ1 clamp voltage Vdz1, from time t3 onwards, the voltage between the second gate terminal 17G and the source S (potential at the relay point 18) is clamped and fixed to the DZ1 clamp voltage Vdz1.

[0037] At time t4, when the voltage between the emitter E of the upper arm IGBT 13 (Q1) and the ground terminal GND (the potential of the output terminal Pout) reaches the ground potential, the voltage between the second gate terminal 17G of the gate short-circuiting MOSFET 17 (M1) and the source S (the potential of the relay point 18) decreases approximately linearly until it reaches the ground potential from time t4 to t6. This phenomenon is due to the release of charge from the first parasitic capacitance Cgs due to disturbance noise, leakage from peripheral elements, etc.

[0038] At time t5, when the voltage between the second gate terminal 17G and the source S (the potential at the relay point 18) falls below the M1 threshold voltage VthM1, the voltage between the drain D and the source S of the gate short-circuiting MOSFET 17 (M1) inverts from the L level to the H level, and the gate short-circuiting MOSFET 17 (M1) falls into the OFF state.

[0039] At time t7, when the gate short-circuiting MOSFET 17 (M1) is in the off state, if the voltage between the first gate terminal 13G and the emitter E of the upper arm IGBT 13 (Q1) exceeds the Q1 threshold voltage VthQ1 due to the influence of external noise, etc., the voltage between the collector C and the emitter E of the upper arm IGBT 13 (Q1) inverts from the H level to the L level, causing the upper arm IGBT 13 (Q1) to malfunction (transition from the off state to the on state).

[0040] In short, in the power conversion device 10 according to the comparative example, when the upper arm IGBT 13 (Q1) is in the off state due to the on operation of the gate short-circuiting MOSFET 17 (M1), the gate short-circuiting MOSFET 17 (M1) may be turned off due to disturbance noise or the like, which may result in a malfunction of the upper arm IGBT 13 (Q1) (transition from the off state to the on state).

[0041] [Power conversion device 11 according to the embodiment] Next, a power conversion device 11 according to an embodiment will be described with reference to Fig. 3. Fig. 3 is a schematic configuration diagram of the power conversion device 11 according to the embodiment.

[0042] The power conversion device 11 according to the embodiment, like the power conversion device 10 according to the comparative example, has the function of converting DC power supplied from a high-voltage main DC power supply Vdc (e.g., 600 V) into AC power and outputting it to an output terminal Pout.

[0043] To achieve these functions, the power conversion device 11 according to the embodiment is configured to include a high-voltage main DC power supply Vdc, an output terminal Pout, an upper arm IGBT 13 (Q1), a lower arm IGBT 15 (Q2), a gate short-circuiting MOSFET 17 (M1), a first Zener diode DZ1, a first diode D1, a second Zener diode DZ2, and a MOSFET 19 (M2). These components, including the high-voltage main DC power supply Vdc, belong to a common high-voltage wiring system.

[0044] The power conversion device 11 according to the embodiment includes components having functions in common with the power conversion device 10 according to the comparative example. Therefore, in the following, we will basically avoid redundant explanations of the components having the common functions and focus on the differences from the power conversion device 10 according to the comparative example.

[0045] As shown in FIG. 3, the power conversion device 11 according to the embodiment includes a second diode D2 that is provided in the vicinity of the first diode D1 and irradiates the first diode D1 with infrared light. The second diode D2 has a cathode terminal K and an anode terminal A connected to a current source I0. The current source I0 is a DC power supply with a relatively low voltage (not particularly limited, but for example, about 10 to 20 V). The current source I0 serves to pass a current Id2 of a predetermined magnitude through the second diode D2. The second diode D2 and the current source I0 belong to a low-voltage wiring system that is electrically independent from the high-voltage wiring system that includes the high-voltage main DC power supply Vdc.

[0046] [Operation of the power conversion device 11 according to the embodiment] Next, the operation of the power conversion device 11 according to the embodiment will be described with reference to Fig. 4A and Fig. 4B. Fig. 4A and Fig. 4B are time charts used to explain the operation of the power conversion device 11 according to the embodiment. In Fig. 4A, the horizontal axis represents time, and the vertical axis represents L-level / H-level logic. In Fig. 4B, the horizontal axis represents time, and the vertical axis represents voltage and current. There may be a time delay between the logic according to Fig. 4A and the voltage and current according to Fig. 4B.

[0047] As shown in FIG. 4A, the upper arm control signal is a signal that is input to the first gate terminal 13G of the upper arm IGBT 13 (Q1) and controls the switching operation of the upper arm IGBT 13 (Q1). 4A, the gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19 (M2) and is a signal for controlling the switching operation of the gate short-circuiting MOSFET 17 (M1) via the switching operation of the MOSFET 19 (M2). The gate short-circuiting MOSFET 17 (M1) has a function of turning off the upper arm IGBT 13 (Q1) that is in the on state.

[0048] The MOSFET 19 (M2) has a function of turning off the gate short-circuiting MOSFET 17 (M1) by extracting the charge (first parasitic capacitance Cgs) stored between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) through a switching operation in accordance with the gate short-circuiting control signal. As a result, when the upper arm IGBT 13 (Q1) is in the on state, the MOSFET 19 (M2) operates to turn off the gate short-circuiting MOSFET 17 (M1).

[0049] To achieve this function, the waveform of the gate short-circuit control signal is synchronized in time series with the waveform of the upper arm control signal and has a common polarity value. Note that being synchronized in time series and having a common polarity value means that the gate short-circuit control signal is at L level when the upper arm control signal is L, and at H level when the upper arm control signal is H, as shown in Figure 4A.

[0050] The waveform of the voltage across the second gate terminal 17G-S of the gate short-circuiting MOSFET 17(M1) is synchronized in time series with the waveform of the gate short-circuiting control signal and exhibits an inverted value. Note that being synchronized in time series with and exhibiting an inverted value means that, as shown in Fig. 4A , the voltage across the second gate terminal 17G-S is at H level (the gate short-circuiting MOSFET 17(M1) is off) during a period when the gate short-circuiting control signal is at L level, and the voltage across the second gate terminal 17G-S is at L level (the gate short-circuiting MOSFET 17(M1) is on) during a period when the gate short-circuiting control signal is at H level.

[0051] Furthermore, the waveform of the voltage across the first gate terminals 13G-S of the upper arm IGBT 13(Q1) is synchronized in time series with the waveform of the upper arm control signal and has a common polarity value. Note that being synchronized in time series and having a common polarity value means that, as shown in Fig. 4A, the voltage across the first gate terminals 13G-E is at an L level (the upper arm IGBT 13(Q1) is off) during a period when the upper arm control signal is at an L level, and the voltage across the first gate terminals 13G-E is at an H level (the upper arm IGBT 13(Q1) is on) during a period when the upper arm control signal is at an H level.

[0052] 4A, to turn on the upper arm IGBT 13 (Q1), an H-level gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19 (M2), and an H-level upper arm control signal is input to the first gate terminal 13G of the upper arm IGBT 13 (Q1). The H-level gate short-circuit control signal and the upper arm control signal are input to the fourth gate terminal 19G and the first gate terminal 13G, respectively, in synchronization with each other. A lower arm control signal of L level is input to the third gate terminal 15G of the lower arm IGBT 15(Q2) in time synchronization with the upper arm control signal of H level, thereby turning the lower arm IGBT 15(Q2) off.

[0053] When an H-level gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19(M2), the MOSFET 19(M2) is turned on. This causes the potential of the relay point 18 connected to the drain terminal D of the MOSFET 19(M2) to drop, causing the charge (first parasitic capacitance Cgs) stored between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17(M1) to be extracted. As a result, the voltage between the second gate terminal 17G and the source S converges to the L level (see FIG. 4A). As a result, the gate short-circuiting MOSFET 17 (M1) is turned off.

[0054] When the gate short-circuiting MOSFET 17 (M1) is in the off state, if an H-level upper-arm control signal is input to the first gate terminal 13G of the upper-arm IGBT 13 (Q1), the voltage between the first gate terminal 13G and the emitter E of the upper-arm IGBT 13 (Q1) is inverted to the H level, and the upper-arm IGBT 13 (Q1) is turned on (see FIG. 4A). As a result, a predetermined output voltage Va related to the main DC power supply Vdc is supplied to the output terminal Pout.

[0055] On the other hand, to turn off the upper arm IGBT 13 (Q1), as shown in Fig. 4A, an L-level gate short-circuit control signal is input to the fourth gate terminal 19G of the MOSFET 19 (M2), and an L-level upper arm control signal is input to the first gate terminal 13G of the upper arm IGBT 13 (Q1). The L-level gate short-circuit control signal and the upper arm control signal are input to the fourth gate terminal 19G and the first gate terminal 13G, respectively, in synchronization with each other. A lower arm control signal of H level is input to the third gate terminal 15G of the lower arm IGBT 15(Q2) in time synchronization with the upper arm control signal of L level, thereby turning on the lower arm IGBT 15(Q2).

[0056] 4B, assume that an L-level upper-arm control signal is input to the first gate terminal 13G of the upper-arm IGBT 13(Q1). Then, at the same time t11, the collector C-emitter E voltage of the upper-arm IGBT 13(Q1) inverts from L to H, and the upper-arm IGBT 13(Q1) enters an OFF state. As a result, from time t11 to time t14, the voltage between the emitter E of the upper arm IGBT 13 (Q1) and the ground terminal GND (the potential of the output terminal Pout) drops approximately linearly from the predetermined output voltage Va to the ground potential. After time t11, the voltage between the first gate terminal 13G and the emitter E of the upper arm IGBT 13 (Q1) begins to rise substantially linearly.

[0057] Between times t11 and t12, the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) (the potential at the relay point 18) rises approximately linearly from the ground potential to the DZ1 clamp voltage Vdz1 in accordance with the capacitive voltage division between the first parasitic capacitance Cgs and the second parasitic capacitance Cd1.

[0058] At time t12, when the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) (the potential at the relay point 18) exceeds the M1 threshold voltage VthM1, the voltage between the drain D and the source S of the gate short-circuiting MOSFET 17 (M1) is inverted from the H level to the L level, and the gate short-circuiting MOSFET 17 (M1) is turned on.

[0059] As a result, after time t12, the voltage between the first gate terminal 13G and the emitter E of the upper arm IGBT 13 (Q1) drops substantially linearly until it reaches the ground potential. This is because the drain D and source S of the gate short-circuiting MOSFET 17 (M1) become conductive, and therefore the first gate terminal 13G and the emitter E of the upper arm IGBT 13 (Q1) are short-circuited.

[0060] At time t12, the current source I0 is turned on, causing a current Id2 to flow through the second diode D2. As a result, the second diode D2, which is provided adjacent to the first diode D1, irradiates the first diode D1 with infrared light. Then, at the same time t12, a photocurrent Id1, which has increased due to the infrared light received by the second diode D2, flows through the first diode D1. The magnitude of the photocurrent Id1 may be appropriately set by adjusting the magnitude of the current Id2 related to the second diode D2, taking into consideration the need to accurately maintain the on state of the gate short-circuiting MOSFET 17 (M1) even when external noise or the like occurs.

[0061] This photocurrent Id1 operates to charge the first parasitic capacitance Cgs by flowing to the second gate terminal 17G of the gate short-circuiting MOSFET 17 (M1) via the relay point 18. This allows the photocurrent Id1 to further increase the amount of charge stored at the relay point 18 (second gate terminal 17G) in combination with the capacitive voltage division between the first parasitic capacitance Cgs and the second parasitic capacitance Cd1 (see the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) from time t12 to t13). This makes it possible to accurately maintain the on state of the gate short-circuiting MOSFET 17 (M1), thereby preventing the gate short-circuiting MOSFET 17 (M1) from being turned off due to disturbance noise or the like, and thereby suppressing malfunction (transition from the off state to the on state) of the upper arm IGBT 13 (Q1), thereby significantly improving the reliability of the operation of the upper arm IGBT 13 (Q1).

[0062] At time t13, when the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) (potential at the relay point 18) reaches the DZ1 clamp voltage Vdz1, from that time onwards, the voltage between the second gate terminal 17G and the source S (potential at the relay point 18) is clamped and held at the DZ1 clamp voltage Vdz1. Here, the phenomenon in which the photocurrent Id1 charges the relay point 18 (second gate terminal 17G) acts to further enhance the function of clamping and holding the potential of the relay point 18 at the DZ1 clamp voltage Vdz1.

[0063] At time t14, the voltage between the emitter E of the upper arm IGBT 13 (Q1) and the ground terminal GND (the potential of the output terminal Pout) reaches the ground potential. However, after time t14, the voltage between the second gate terminal 17G and the source S of the gate short-circuiting MOSFET 17 (M1) (the potential at the relay point 18) does not decrease toward the ground potential. This is because, even if charge is released from the first parasitic capacitance Cgs due to disturbance noise, leakage from peripheral elements, or the like, the photocurrent Id1 charges the relay point 18 (second gate terminal 17G) beyond the released charge.

[0064] [Power conversion device 11 according to a modified example] Next, a power conversion device 11 according to a modified example of the present invention will be described with reference to FIG. FIG. 5 is a partial configuration diagram showing the periphery of the first diode D1 in a power conversion device 11 according to a modified example of the present invention. 5, a power conversion device 11 according to a modification of the present invention includes a plurality of second diodes D2 provided to surround the first diode D1. The plurality of second diodes D2 may be connected in series or in parallel with each other. According to the power conversion device 11 of the modified example of the present invention, the magnitude of the photocurrent Id1 flowing through the first diode D1 can be adjusted appropriately, thereby significantly improving the effect of suppressing malfunction (transition from the off state to the on state) of the upper arm IGBT 13 (Q1).

[0065] [Configuration and Function of the Gate Drive Circuit of the Power Conversion Device 11 According to the Present Invention] The gate drive circuit (1) of the power conversion device 11 according to the present invention is a gate drive circuit of the power conversion device 11 that converts DC power into AC power and outputs the AC power, and includes: an upper-arm power semiconductor element 13 (Q1) provided between a main DC power supply Vdc and an output terminal Pout; a gate short-circuiting semiconductor element 17 (M1) provided between a first gate terminal 13G of the upper-arm power semiconductor element 13 (Q1) and the output terminal Pout and having a first parasitic capacitance Cgs juxtaposed thereto; a first Zener diode DZ1 provided between a second gate terminal 17G of the gate short-circuiting semiconductor element 17 (M1) and the output terminal Pout; a first diode D1 provided between the main DC power supply Vdc and the first Zener diode DZ1 and having a second parasitic capacitance Cd1 juxtaposed thereto; and a second diode D2 provided adjacent to the first diode D1 and irradiating the first diode D1 with infrared light. The first Zener diode DZ1 and the first diode D1 are connected in series via a relay point 18 that has approximately the same potential as the second gate terminal 17G, an upper arm control signal is input to the first gate terminal 13G, while a gate short-circuit control signal is input to the second gate terminal 17G, and the main DC power supply Vdc and the output terminal Pout, the upper arm power semiconductor element 13 (Q1), the gate short-circuiting semiconductor element 17 (M1), the first Zener diode DZ1, and the first diode D1 belong to a common high-voltage wiring system, while the second diode D2 belongs to a low-voltage wiring system that is electrically independent from the high-voltage wiring system.

[0066] According to the gate drive circuit (1) of the power conversion device 11 of the present invention, even when disturbance noise or the like occurs, it is possible to suppress malfunction of the upper arm power semiconductor element 13 (Q1).

[0067] The gate drive circuit (2) of the power conversion device 11 according to the present invention may be the gate drive circuit (1) of the power conversion device 11, further comprising a second Zener diode DZ2 provided between the first gate terminal 13G and the output terminal Pout, wherein the first Zener diode DZ1 has a cathode terminal K connected to the relay point 18 and an anode terminal A connected to the output terminal Pout, the first diode D1 has a cathode terminal K connected to the positive electrode of the main DC power supply Vdc and an anode terminal A connected to the relay point 18, the second diode D2 has a cathode terminal K and an anode terminal A connected to the current source I0, and the second Zener diode DZ2 has a cathode terminal K connected to the first gate terminal 13G and an anode terminal A connected to the output terminal Pout.

[0068] According to the gate drive circuit (2) of the power conversion device 11 of the present invention, similar to the gate drive circuit (1) of the power conversion device 11 of the present invention, even when disturbance noise or the like occurs, it is possible to suppress malfunction of the upper arm power semiconductor element 13 (Q1).

[0069] The gate drive circuit (3) of the power conversion device 11 according to the present invention may be the gate drive circuit (2) of the power conversion device 11, and may have a configuration in which the upper arm power semiconductor element 13 (Q1) is an N-channel upper arm IGBT 13 (Q1) having a collector terminal C connected to the positive electrode of the main DC power supply Vdc and an emitter terminal E connected to the output terminal Pout, a first free wheel diode D3 is connected in anti-parallel to the upper arm IGBT 13 (Q1), and the gate short-circuiting semiconductor element 17 (M1) is an N-channel gate short-circuiting MOSFET 17 (M1) having a drain terminal D connected to the first gate terminal 13G and a source terminal S connected to the output terminal Pout.

[0070] According to the gate drive circuit (3) of the power conversion device 11 of the present invention, even when disturbance noise or the like occurs, it is possible to suppress malfunction of the upper arm IGBT 13 (Q1).

[0071] The gate drive circuit (4) of the power conversion device 11 according to the present invention may be the gate drive circuit (2) or (3) of the power conversion device 11, and may have a configuration in which a plurality of second diodes D2 are provided so as to surround the first diode D1 (see the modified example shown in FIG. 5).

[0072] The gate drive circuit (4) of the power conversion device 11 according to the present invention makes it possible to appropriately adjust the magnitude of the photocurrent Id1 flowing through the first diode D1, thereby significantly improving the effect of suppressing malfunction (transition from the off state to the on state) of the upper arm IGBT 13 (Q1) compared to the gate drive circuits (2) or (3) of the power conversion device 11.

[0073] On the other hand, a power conversion device 11 (5) according to the present invention is a power conversion device 11 that converts DC power into AC power and outputs it, and includes: an upper-arm power semiconductor element 13 (Q1) provided between a main DC power supply Vdc and an output terminal Pout; a lower-arm power semiconductor element 15 (Q2) provided between the output terminal Pout and a ground terminal GND; a gate short-circuiting semiconductor element 17 (M1) provided between a first gate terminal 13G of the upper-arm power semiconductor element 13 (Q1) and the output terminal Pout and having a first parasitic capacitance Cgs juxtaposed thereto; a first Zener diode DZ1 provided between a second gate terminal 17G of the gate short-circuiting semiconductor element 17 (M1) and the output terminal Pout; a first diode D1 provided between the main DC power supply Vdc and the first Zener diode DZ1 and having a second parasitic capacitance Cd1 juxtaposed thereto; and a second diode D2 provided adjacent to the first diode D1 and irradiating the first diode D1 with infrared light. The first Zener diode DZ1 and the first diode D1 are connected in series via a relay point 18 that has approximately the same potential as the second gate terminal 17G, and an upper arm control signal is input to the first gate terminal 13G, and a lower arm control signal is input to the third gate terminal 15G associated with the lower arm power semiconductor element 15 (Q2), while a gate short-circuit control signal is input to the second gate terminal 17G, and the main DC power supply Vdc and the output terminal Pout, the upper arm power semiconductor element 13 (Q1), the gate short-circuiting semiconductor element 17 (M1), the first Zener diode DZ1, and the first diode D1 belong to a common high-voltage wiring system, while the second diode D2 belongs to a low-voltage wiring system that is electrically independent from the high-voltage wiring system.

[0074] According to the power conversion device 11(5) of the present invention, even when disturbance noise or the like occurs, it is possible to suppress malfunction of the upper arm power semiconductor element 13(Q1).

[0075] A power conversion device 11(6) according to the present invention may be the power conversion device 11(5), further including a second Zener diode DZ2 provided between the first gate terminal 13G and the output terminal Pout, wherein the first Zener diode DZ1 has a cathode terminal K connected to the relay point 18 and an anode terminal A connected to the output terminal Pout, the first diode D1 has a cathode terminal K connected to the positive electrode of the main DC power supply Vdc and an anode terminal A connected to the relay point 18, the second diode D2 has a cathode terminal K and an anode terminal A connected to the current source I0, and the second Zener diode DZ2 has a cathode terminal K connected to the first gate terminal 13G and an anode terminal A connected to the output terminal Pout.

[0076] According to the power conversion device 11(6) of the present invention, similarly to the power conversion device 11(5) of the present invention, even when disturbance noise or the like occurs, it is possible to suppress malfunction of the upper arm power semiconductor element 13(Q1).

[0077] A power conversion device 11(7) according to the present invention may be the power conversion device 11(5), in which the upper-arm power semiconductor element 13(Q1) is an N-channel upper-arm IGBT 13(Q1) having a collector terminal C connected to the positive electrode of the main DC power supply Vdc and an emitter terminal E connected to the output terminal Pout, and a first free wheel diode D3 is connected in anti-parallel to the upper-arm IGBT 13(Q1), the lower-arm power semiconductor element 15(Q2) is an N-channel lower-arm IGBT 15(Q2) having a collector terminal C connected to the output terminal Pout and an emitter terminal E connected to the ground terminal GND, and a second free wheel diode D4 is connected in anti-parallel to the lower-arm IGBT 15(Q2), and the gate-shorting semiconductor element 17(M1) is an N-channel gate-shorting MOSFET 17(M1) having a drain terminal D connected to the first gate terminal 13G and a source terminal S connected to the output terminal Pout.

[0078] According to the power conversion device 11(7) of the present invention, even when disturbance noise or the like occurs, it is possible to suppress malfunction of the upper arm IGBT 13(Q1).

[0079] A power conversion device 11(8) according to a modification of the present invention (see FIG. 5) may be the power conversion device 11(7) in which a plurality of second diodes D2 are provided to surround the first diode D1.

[0080] According to the power conversion device 11(8) of the present invention, the magnitude of the photocurrent Id1 flowing through the first diode D1 can be appropriately adjusted, and as a result, the effect of suppressing malfunction (transition from the off state to the on state) of the upper arm IGBT 13(Q1) can be significantly improved compared to the power conversion device 11(7).

[0081] The power conversion device 11 (9) according to the present invention is the power conversion device 11 (7) or (8), and may be configured such that the main DC power supply Vdc and the output terminal Pout, the upper arm IGBT 13 (Q1), the first freewheeling diode D3, the lower arm IGBT 15 (Q2), the second freewheeling diode D4, the gate short-circuiting MOSFET 17 (M1), the first Zener diode DZ1, the first diode D1, and the second diode D2 are mounted on a single semiconductor chip.

[0082] According to the power conversion device 11 (9) of the present invention, even when disturbance noise or the like occurs, in addition to the effect of suppressing malfunction (transition from the off state to the on state) of the upper arm IGBT 13 (Q1), it is possible to obtain a power conversion device 11 that has excellent space efficiency and can be expected to achieve cost reduction.

[0083] The present invention is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments have been described in detail to facilitate understanding of the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0084] For example, in the explanation of the embodiment based on FIG. 4B, an embodiment was explained in which "at time t12, the current source I0 is turned on, causing a current Id2 to flow through the second diode D2. As a result, the second diode D2, which is provided close to the first diode D1, irradiates the first diode D1 with infrared light. Then, at the same time t12, a photocurrent Id1, which has increased as a result of receiving the infrared light related to the second diode D2, flows through the first diode D1." However, the present invention is not limited to this example. Instead of time t12 when the gate short-circuiting MOSFET 17 (M1) is turned on, at time t11 when the upper arm IGBT 13 (Q1) is turned off, a configuration may be adopted in which the current source I0 is turned on to cause a current Id2 to flow through the second diode D2. In this case, the above embodiment can be replaced with the following embodiment: "At time t11, the current source I0 is turned on, causing a current Id2 to flow through the second diode D2. As a result, the second diode D2, which is provided close to the first diode D1, irradiates the first diode D1 with infrared light. Then, at the same time t11, a photocurrent Id1, which has increased as a result of receiving the infrared light related to the second diode D2, flows through the first diode D1."

[0085] In the power conversion device 11 according to the present invention, the main DC power supply Vdc and the output terminal Pout, the upper-arm power semiconductor element 13, the gate short-circuiting semiconductor element 17, the first Zener diode DZ1, and the first diode D1 belong to a common high-voltage wiring system, while the second diode D2 belongs to a low-voltage wiring system that is electrically independent from the high-voltage wiring system. To achieve this, a configuration may be adopted in which the multiple elements belonging to the high-voltage wiring system and the elements belonging to the low-voltage wiring system are each formed separately on a common SOI substrate. With this configuration, it is possible to expect the effect of manufacturing a compact power conversion device 11 at low cost.

[0086] Finally, in the embodiments and modifications of the present invention, the control lines and information lines shown are those that are considered necessary for explanation, and do not necessarily show all the control lines and information lines on the product. [Explanation of symbols]

[0087] 11 Power conversion device 13 Upper arm IGBT (upper arm power semiconductor element) 13G First gate terminal 15 Lower arm IGBT (lower arm power semiconductor element) 15G 3rd gate terminal 17 Gate short MOSFET (Gate short semiconductor device) 17G Second gate terminal 18 Relay Point 19 MOSFET 19G 4th gate terminal Cgs 1st parasitic capacitance Cd1 2nd parasitic capacitance D1 First diode D2 Second diode D3 First freewheeling diode D4 Second freewheeling diode DZ1 First Zener diode DZ2 Second Zener diode GND Grounding terminal I0 current source Id1 Photocurrent Pout output terminal Vdc Main DC power supply

Claims

1. A gate drive circuit of a power conversion device that converts DC power into AC power and outputs the AC power, an upper arm power semiconductor element (13) provided between a main DC power supply (Vdc) and an output terminal (Pout); a gate short-circuiting semiconductor element (17) provided between a first gate terminal (13G) of the upper arm power semiconductor element (13) and the output terminal (Pout), and having a first parasitic capacitance (Cgs) arranged in parallel therewith; a first Zener diode (DZ1) provided between a second gate terminal (17G) of the gate short-circuiting semiconductor element (17) and the output terminal (Pout); a first diode (D1) provided between the main DC power supply (Vdc) and the first Zener diode (DZ1), and having a second parasitic capacitance (Cd1) arranged in parallel therewith; a second diode (D2) provided adjacent to the first diode (D1) and irradiating light onto the first diode (D1); the first Zener diode (DZ1) and the first diode (D1) are connected in series via a relay point (18) having substantially the same potential as the second gate terminal (17G); An upper arm control signal is input to the first gate terminal (13G), while a gate short-circuit control signal is input to the second gate terminal (17G), The main DC power supply (Vdc), the output terminal (Pout), the upper arm power semiconductor element (13), the gate short-circuiting semiconductor element (17), the first Zener diode (DZ1), and the first diode (D1) belong to a common high-voltage wiring system, while the second diode (D2) belongs to a low-voltage wiring system that is electrically independent from the high-voltage wiring system. A gate drive circuit for a power conversion device.

2. 2. The gate drive circuit of the power conversion device according to claim 1, The device further includes a second Zener diode (DZ2) provided between the first gate terminal (13G) and the output terminal (Pout), The first Zener diode (DZ1) has a cathode terminal (K) connected to the relay point (18) and an anode terminal (A) connected to the output terminal (Pout), The first diode (D1) has a cathode terminal (K) connected to the positive electrode of the main DC power supply (Vdc) and an anode terminal (A) connected to the relay point (18), The second diode (D2) has a cathode terminal (K) and an anode terminal (A) connected to a current source (I0), The second Zener diode (DZ2) has a cathode terminal (K) connected to the first gate terminal (13G) and an anode terminal (A) connected to the output terminal (Pout). A gate drive circuit for a power conversion device.

3. 3. The gate drive circuit of the power conversion device according to claim 2, The upper arm power semiconductor element (13) is an N-channel upper arm IGBT (13) having a collector terminal (C) connected to the positive electrode of the main DC power supply (Vdc) and an emitter terminal (E) connected to the output terminal (Pout), A first free wheel diode (D3) is connected in anti-parallel to the upper arm IGBT (13), The gate short-circuiting semiconductor element (17) is an N-channel gate short-circuiting MOSFET (17) having a drain terminal (D) connected to the first gate terminal (13G) and a source terminal (S) connected to the output terminal (Pout). A gate drive circuit for a power conversion device.

4. 4. The gate drive circuit of the power conversion device according to claim 2 or 3, The second diode (D2) is provided in plurality so as to surround the first diode (D1). A gate drive circuit for a power conversion device.

5. A power conversion device (11) that converts DC power into AC power and outputs the AC power, an upper arm power semiconductor element (13) provided between a main DC power supply (Vdc) and an output terminal (Pout); a lower arm power semiconductor element (15) provided between the output terminal (Pout) and a ground terminal (GND); a gate short-circuiting semiconductor element (17) provided between a first gate terminal (13G) of the upper arm power semiconductor element (13) and the output terminal (Pout), and having a first parasitic capacitance (Cgs) arranged in parallel therewith; a first Zener diode (DZ1) provided between a second gate terminal (17G) of the gate short-circuiting semiconductor element (17) and the output terminal (Pout); a first diode (D1) provided between the main DC power supply (Vdc) and the first Zener diode (DZ1), and having a second parasitic capacitance (Cd1) arranged in parallel therewith; a second diode (D2) provided adjacent to the first diode (D1) and irradiating light onto the first diode (D1); the first Zener diode (DZ1) and the first diode (D1) are connected in series via a relay point (18) having substantially the same potential as the second gate terminal (17G); An upper arm control signal is input to the first gate terminal (13G), and a lower arm control signal is input to a third gate terminal (15G) associated with the lower arm power semiconductor element (15), while a gate short-circuit control signal is input to the second gate terminal (17G), The main DC power supply (Vdc), the output terminal (Pout), the upper arm power semiconductor element (13), the gate short-circuiting semiconductor element (17), the first Zener diode (DZ1), and the first diode (D1) belong to a common high-voltage wiring system, while the second diode (D2) belongs to a low-voltage wiring system that is electrically independent from the high-voltage wiring system. A power conversion device characterized by:

6. The power conversion device (11) according to claim 5, The device further includes a second Zener diode (DZ2) provided between the first gate terminal (13G) and the output terminal (Pout), The first Zener diode (DZ1) has a cathode terminal (K) connected to the relay point (18) and an anode terminal (A) connected to the output terminal (Pout), The first diode (D1) has a cathode terminal (K) connected to the positive electrode of the main DC power supply (Vdc) and an anode terminal (A) connected to the relay point (18), The second Zener diode (DZ2) has a cathode terminal (K) connected to the first gate terminal (13G) and an anode terminal (A) connected to the output terminal (Pout), The second diode (D2) has a cathode terminal (K) and an anode terminal (A) connected to a current source (I0). A power conversion device characterized by:

7. The power conversion device (11) according to claim 5, The upper arm power semiconductor element (13) is an N-channel upper arm IGBT (13) having a collector terminal (C) connected to the positive electrode of the main DC power supply (Vdc) and an emitter terminal (E) connected to the output terminal (Pout), A first free wheel diode (D3) is connected in anti-parallel to the upper arm IGBT (13), The lower arm power semiconductor element (15) is an N-channel lower arm IGBT (15) having a collector terminal (C) connected to the output terminal (Pout) and an emitter terminal (E) connected to the ground terminal (GND), A second free wheel diode (D4) is connected in anti-parallel to the lower arm IGBT (15), The gate short-circuiting semiconductor element (17) is an N-channel gate short-circuiting MOSFET (17) having a drain terminal (D) connected to the first gate terminal (13G) and a source terminal (S) connected to the output terminal (Pout). A power conversion device characterized by:

8. The power conversion device (11) according to claim 7, The second diode (D2) is provided in plurality so as to surround the first diode (D1). A power conversion device characterized by:

9. The power conversion device (11) according to claim 7 or 8, The main DC power supply (Vdc), the output terminal (Pout), the upper arm IGBT (13), the first freewheeling diode (D3), the lower arm IGBT (15), the second freewheeling diode (D4), the gate short-circuiting MOSFET (17), the first Zener diode (DZ1), the first diode (D1), and the second diode (D2) are mounted on one semiconductor chip. A power conversion device characterized by:

Images