Layout method

Abstract

To provide a novel circuit layout method.SOLUTION: In a circuit including a first terminal, a second terminal, a third terminal, a fourth terminal, a first wire, and a second wire, a layout method includes the steps of: generating a layout for connecting between the first terminal and the third terminal using the first wire; generating a layout for connecting between the second terminal and the fourth terminal using the second wire; calculating a first wiring resistance of the first wire; calculating a second wiring resistance of the second wire; and generating automatically a layout of the first wire and the second wire of the circuit so that the first wiring resistance and the second wiring resistance become equal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a system for managing circuit layouts using a computer device. One aspect of the present invention relates to a layout method for automatically generating a circuit layout. Another aspect of the present invention relates to a layout method for automatically placing a circuit layout on a substrate for evaluating semiconductor elements. Another aspect of the present invention relates to a circuit block generation method for automatically generating a layout using multiple circuits as circuit blocks for evaluating variations in manufacturing equipment. Another aspect of the present invention relates to a learning model that learns variation information of manufacturing equipment that manufactures semiconductor elements. Another aspect of the present invention relates to a management system in which the learning model places the layout of the circuit blocks on a substrate depending on the types of circuits included in the circuit blocks.

[0002] The above-mentioned circuits include functional circuits that are provided with functions by multiple semiconductor elements, and TEGs (Test Element Groups). Therefore, even when a TEG is described in this specification, it can be replaced with a functional circuit or a circuit.

[0003] In this specification and elsewhere, a semiconductor element refers to an element that can function by utilizing semiconductor characteristics. Examples of semiconductor elements include transistors, diodes, light-emitting elements, and light-receiving elements. Another example of a semiconductor element is a passive element formed by a conductive film such as a capacitor, resistor, or inductor, or an insulating film. Another example of a semiconductor element is a semiconductor device including a circuit having a semiconductor element or a passive element. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed toward process miniaturization. One of the reasons for this process miniaturization is the demand for semiconductor devices to consume less power by operating at lower voltages and to operate at higher frequencies. Semiconductor devices are composed of various semiconductor elements, and variations in the characteristics of the semiconductor elements can narrow the operating range of the semiconductor device and reduce its reliability. In particular, in the development of new processes associated with miniaturization, it is important to accurately evaluate the variations in characteristics between substrates and within a substrate. Furthermore, in analog circuits, the variations in the characteristics of semiconductor elements have a significant impact on circuit operation. Therefore, characteristic evaluation using TEGs is important in the development of new processes, and TEG designs that can accurately evaluate the variations in characteristics within a substrate are required.

[0005] Note that inter-substrate variation refers to the range of variation in semiconductor elements for each substrate. Intra-substrate variation refers to the range of variation in multiple semiconductor elements formed within a substrate. Note that in this specification, intra-substrate variation may also be referred to as intra-plane variation. Furthermore, variations in semiconductor elements that are affected by variations in manufacturing equipment include electrical characteristics, shape, and reliability.

[0006] Patent Document 1 discloses a layout method for a semiconductor integrated circuit. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-65056 Summary of the Invention [Problem to be solved by the invention]

[0008] Developing a semiconductor device requires process design, device design, and circuit design. For example, when forming a semiconductor device, the semiconductor device is formed by combining multiple manufacturing processes. A problem with semiconductor devices is that the electrical characteristics of the semiconductor device change if the order of the manufacturing processes is changed. Furthermore, even if the same process is used, the electrical characteristics of the semiconductor device change if the manufacturing equipment or process conditions are changed.

[0009] Even when the same process conditions are set for different manufacturing equipment with the same process and function, semiconductor devices formed with the same equipment can exhibit different electrical characteristics depending on the state of the manufacturing equipment. The state of the manufacturing equipment, for example, refers to the difference in variability between the substrate immediately after maintenance on the manufacturing equipment and the substrate processed after multiple processes using the manufacturing equipment. Therefore, there is a problem in that variability in the manufacturing equipment affects the variability of the semiconductor devices. Therefore, to evaluate the variability of semiconductor devices, it is necessary to be able to independently extract the state of each manufacturing equipment used to form the semiconductor devices.

[0010] To achieve this, there is a need to prepare TEGs to evaluate the variations in each manufacturing equipment. Another issue is that the information required for each design differs depending on the process, device, or circuit. Furthermore, if the placement of TEGs within a substrate does not take into account variations within the substrate (within the surface) caused by the manufacturing equipment, there is a problem in that the necessary information cannot be obtained even when the TEG is evaluated.

[0011] In recent years, semiconductor elements are primarily formed using a stacking process. Therefore, TEG design has the problem of design errors occurring due to manual TEG layout work. This has led to a demand for efficient layout design using EDA (Electronic Design Automation) tools and automatic layout. However, to accurately evaluate the variability of manufacturing equipment from the variability of semiconductor elements as described above, knowledge of processes, devices, and circuits is also required. Automatic layout, which simply places and connects components, has the problem of making it difficult to accurately evaluate the variability of semiconductor elements.

[0012] In view of the above problems, an object of one embodiment of the present invention is to provide a management system for managing circuit layouts using a computer device. Another object of one embodiment of the present invention is to provide a layout method for automatically generating a circuit layout. Another object of one embodiment of the present invention is to provide a layout method for automatically arranging a circuit layout on a substrate for evaluating semiconductor elements. Another object of one embodiment of the present invention is to provide a circuit block generation method for automatically generating a layout using a plurality of circuits as circuit blocks for evaluating variations in a manufacturing device. Another object of one embodiment of the present invention is to provide a learning model for learning variation information of a manufacturing device that manufactures semiconductor elements. Another object of one embodiment of the present invention is to provide a management system in which a learning model arranges the layout of circuit blocks on a substrate depending on the type of circuits included in the circuit blocks.

[0013] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0014] The management system according to one aspect of the present invention functions as a TEG management system, which automatically generates a TEG layout using a program stored in a storage device.

[0015] One aspect of the present invention is a layout method for a circuit (TEG) having a first terminal, a second terminal, a third terminal, a fourth terminal, a first wiring, and a second wiring, comprising the steps of: generating a layout that connects the first terminal and the third terminal using the first wiring; generating a layout that connects the second terminal and the fourth terminal using the second wiring; calculating a first wiring resistance of the first wiring; calculating a second wiring resistance of the second wiring; and automatically generating the layout of the first wiring and the second wiring of the circuit so that the first wiring resistance and the second wiring resistance are equal.

[0016] Preferably, the first and second terminals are measurement terminals, and the third and fourth terminals are terminals of a semiconductor element included in the circuit.

[0017] In the above configuration, the circuit preferably includes a third wiring, and the layout method preferably further includes the steps of generating a layout that connects the first terminal and the third terminal using the third wiring including a contact; calculating a third wiring resistance of the third wiring; changing the magnitude of the first wiring resistance by changing the layout of the shape or position of the first wiring so that the first wiring resistance is equal to the third wiring resistance; and automatically generating the layout of the first wiring and third wiring of the circuit so that the first wiring resistance is equal to the third wiring resistance.

[0018] One aspect of the present invention is a management system for automatically placing a layout of a TEG block on a substrate. The management system preferably includes a learning model, and the learning model learns measurement data including an in-plane distribution of a manufacturing apparatus used to form semiconductor elements included in the TEG, and a layout of the TEG generated using a layout method is provided to the learning model, and the learning model automatically places the TEG layout on the substrate. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a management system for managing circuit layouts using a computer device can be provided. According to one embodiment of the present invention, a layout method for automatically generating a circuit layout can be provided. According to another embodiment of the present invention, a layout method for automatically placing a circuit layout on a substrate for evaluating a semiconductor element can be provided. According to another embodiment of the present invention, a circuit block generation method for automatically generating a layout using a plurality of circuits as circuit blocks for evaluating variations in a manufacturing device can be provided. According to another embodiment of the present invention, a learning model for learning variation information of a manufacturing device for manufacturing a semiconductor element can be provided. According to another embodiment of the present invention, a management system for placing a circuit block layout on a substrate based on the type of circuit included in the circuit block by the learning model can be provided.

[0020] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a diagram illustrating a computer device included in the TEG management system. [Figure 2] FIG. 2 is a flowchart illustrating the TEG management system. [Figure 3] FIG. 3 is a diagram illustrating the TEG setting screen. [Figure 4] FIG. 4 is a diagram illustrating a display screen of a TEG map. [Figure 5] FIG. 5 is a flowchart illustrating a method for generating a TEG layout. [Figure 6] FIG. 6 is a flowchart illustrating a method for generating a TEG layout. [Figure 7] 7A and 7B are diagrams illustrating the layout of a TEG. [Figure 8] 8A and 8B are diagrams for explaining the layout of the TEG. [Figure 9] FIG. 9 is a flowchart illustrating a method for arranging TEG blocks. [Figure 10] Fig. 10A is a diagram illustrating a learning model for learning the in-plane distribution of devices, and Fig. 10B is a diagram illustrating a learning model capable of arranging TEG blocks. [Figure 11] FIG. 11 is a diagram for explaining a method for generating a measurement recipe from a TEG block map. [Figure 12] FIG. 12 is a diagram illustrating the TEG management system. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0024] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0025] It should be noted that the ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and are not intended to limit the number.

[0026] (Embodiment) In this embodiment, a layout method for automatically generating a layout of a TEG using a computer device and a management system for managing the placement of the layout of a circuit generated on a substrate will be described.

[0027] First, the TEG will be described. The TEG is used when developing semiconductor elements (or circuits) formed on a substrate and managing manufacturing equipment. In other words, the TEG is an evaluation element (or evaluation circuit) for detecting problems in the manufacturing process or the design process. As an example, it is known that a transistor, which is one type of semiconductor element, is formed through multiple manufacturing processes. Examples of manufacturing processes for forming the shape of a transistor include a film formation process and a processing process. The processing process further includes a patterning process, an etching process, and the like. In addition, the manufacturing process of a transistor also includes an impurity addition process, a heat treatment process, and the like, but descriptions of these processes will be omitted in one embodiment of the present invention.

[0028] For example, film formation processes include a semiconductor film formation process, an insulating film formation process, and a conductive film formation process. Processing processes include a patterning process for transferring the shape of a semiconductor film, an insulating film, or a conductive film, and a processing process for processing the patterned film to the size of the pattern. Semiconductor elements are formed into transistor shapes by repeating film formation processes and processing processes. However, semiconductor films, insulating films, and conductive films each have variations in film thickness or film quality due to the film formation equipment used in the film formation process.

[0029] Since the semiconductor film forms the channel of a transistor, uniformity in the film thickness and film quality within the substrate affects the variation in the electrical characteristics of multiple transistors formed on the same substrate. Furthermore, the film thickness and film quality of the insulating film formed between the semiconductor film and the conductive film affect the electrical characteristics of the transistor. Furthermore, the conductive film is preferably a highly conductive film because it forms the gate, source, and drain of the transistor. Furthermore, different processing processes are required depending on the film quality to shape the semiconductor film, insulating film, and conductive film. Therefore, multiple manufacturing processes are required to form a transistor. Each manufacturing process involves processing variations in the manufacturing equipment. One aspect of the present invention is a layout method for generating layouts of multiple TEGs for accurately evaluating the variation in the electrical characteristics of transistors and generating a layout of a TEG block having the multiple TEGs.

[0030] As an example, a layout of a TEG having a transistor will be described. The TEG includes a layout of first to fourth terminals, a transistor, and first to fourth wirings. The first to fourth terminals correspond to measurement terminals. Note that the number of measurement terminals can be changed depending on the semiconductor element or circuit to be evaluated. As a different example, in the case of a layout having a capacitance, the first terminal and the second terminal correspond to measurement terminals.

[0031] Here, an example will be described in which the semiconductor element of the TEG is a transistor. To correctly evaluate the electrical characteristics of a transistor, the gate, drain, and source of the transistor must be electrically connected to a measuring instrument via the first to third terminals. If the transistor has a back gate, the back gate is electrically connected to a measuring instrument via the fourth terminal.

[0032] For example, the TEG has a layout in which the first terminal is connected to one of the source and drain of a transistor via a first wiring, the second terminal is connected to the other of the source and drain of the transistor via a second wiring, and the third terminal is connected to the gate of the transistor via a third wiring. In addition, if the TEG has a back gate, the layout has a fourth terminal connected to the back gate of the transistor via a fourth wiring.

[0033] To accurately evaluate the electrical characteristics of a transistor, it is preferable to apply the correct voltage or current, which is the measurement condition, to each terminal of the transistor. Therefore, in this embodiment, the description focuses on the wiring between the measurement terminal and the terminal of the semiconductor element. Note that each of the wiring has a wiring resistance.

[0034] For example, if the semiconductor element is a transistor, the source and drain are terminals through which current flows, while the gate and backgate are terminals through which current does not flow. Note that even terminals through which no current flows may be evaluated for short circuits between terminals due to shape defects or leakage current through an insulating film. Therefore, it is preferable to treat the gate or backgate in the same way as a terminal through which current flows.

[0035] As transistor design rules become finer, there is a demand for finer wiring design rules as well. However, the thinner the wiring, the higher the wiring resistance. Therefore, the magnitude of wiring resistance has a significant impact on the evaluation of the electrical characteristics of transistors formed using the miniaturization process.

[0036] For example, when the wiring resistance increases, a voltage drop occurs due to the wiring resistance, and a voltage different from the voltage applied to the measurement terminal is applied to the source or drain of the transistor. If the wiring resistances of the first wiring and the second wiring are different, it is difficult to distinguish whether the current measurement results are affected by transistor variations or by the voltage drop due to the wiring resistance. Furthermore, if measurements show different electrical characteristics when the source and drain of the transistor are swapped, it is difficult to distinguish whether the problem is caused by the transistor or by the wiring resistance of the first or second wiring.

[0037] Therefore, it is preferable to lay out the first wiring and the second wiring so that the wiring resistance of the first wiring and the second wiring is equal. By making the wiring resistance of the first wiring and the second wiring equal, the electrical characteristics of a semiconductor element including a transistor can be correctly evaluated. Therefore, by evaluating the TEG, manufacturing or design issues can be easily identified. It is also preferable to lay out the third wiring and the fourth wiring so that the wiring resistance of the third wiring and the fourth wiring is equal.

[0038] A TEG management system according to one embodiment of the present invention automatically generates a TEG layout using a TEG generation program stored in a storage device. The layout method in the TEG management system combines multiple resistor blocks to connect measurement terminals to terminals of semiconductor elements. When the semiconductor element is a transistor, the transistor has one terminal (source or drain), the other terminal (source or drain), and a gate terminal.

[0039] The TEG generation program includes a step of generating a layout that connects a first terminal and one of a source or drain terminal of a transistor via a first wiring, and a step of generating a layout that connects a second terminal and the other of a source or drain terminal of the transistor via a second wiring.

[0040] The first wiring and the second wiring have a layout of a first wiring block and a layout of a second wiring block. In one embodiment of the present invention, the first resistance value is calculated from the layout of the first wiring block, and the second resistance value is calculated from the layout of the second wiring block. Therefore, the layout of the first wiring block and the layout of the second wiring block forming the first wiring can be treated as a first wiring resistance obtained by adding the first resistance value and the second resistance value. Furthermore, the layout of the first wiring block and the layout of the second wiring block forming the second wiring can be treated as a second wiring resistance obtained by adding the first resistance value and the second resistance value.

[0041] The TEG generation program automatically generates a TEG layout so that the first wiring resistance and the second wiring resistance are equal. By creating a layout in which the first wiring resistance is equal to the second wiring resistance, the influence of the wiring resistance of the TEG on the electrical characteristics can be reduced. The first wiring resistance and the second wiring resistance can be set to specified resistance values. As an example, the impedance of the first wiring resistance and the second wiring resistance can be set to 50 ohms.

[0042] As described above, the layout method using the TEG generation program can be applied to the layout generation of TEGs for evaluating various semiconductor elements. For example, when evaluating a transistor, it is preferable to provide multiple TEGs for evaluating the transistor. Examples of TEGs for managing the electrical characteristics of a transistor include a resistive TEG for managing the resistance value of the semiconductor film of the transistor, a capacitive TEG for managing the thickness and quality of the insulating film, a resistive TEG for managing the resistance value of a conductive film used in the source, drain, or gate of the transistor, a contact TEG for connecting different conductive layers, and a TEG with different channel lengths or channel widths of the transistor. The TEG generation program can generate a layout using the multiple types of TEGs described above as TEG blocks.

[0043] The TEG block can further include layouts for analytical TEGs, such as a TDS evaluation TEG for evaluating film quality using thermal desorption spectroscopy (TDS) and a SIMS evaluation TEG for evaluating film quality using secondary ion mass spectrometry (SIMS). Evaluations using the TEG block can easily identify the causes of variations in the electrical characteristics of transistors and identify issues in the manufacturing process and design process.

[0044] However, the TEG blocks must be placed in appropriate positions and in appropriate numbers within the substrate to evaluate variations within the substrate. Variations within the substrate are affected by the manufacturing equipment used in each manufacturing process. Therefore, the TEG management system preferably has a learning model for placing an appropriate number of TEG blocks in appropriate positions within the substrate. The learning model can learn the in-plane distribution of the manufacturing equipment used to form the TEG. By providing the learning model with TEGs or TEG blocks generated using a layout method, the learning model can automatically place TEGs on the substrate. Furthermore, the TEG management system can generate a measurement recipe for measuring the electrical characteristics of the TEGs automatically placed on the substrate.

[0045] Next, a layout method for automatically generating a circuit layout and a management system for managing the placement of the circuit layout generated on a board will be described with reference to FIGS.

[0046] FIG. 1 is a diagram illustrating a computer device included in a TEG management system. The computer device 10 includes a processor 11, a storage device 12, a graphics processing unit (GPU) 14, an input / output device 15, and a storage device 16. The input / output device 15 includes a display device, a touch panel, a keyboard, a mouse, and the like. The storage device 16 includes an EDA program 31, a TEG generation program 32, a TEG map generation program 33, a learning model 34, and a database 35. Each of the above programs can perform calculations and other operations for the TEG management system using the processor 11 and the GPU 14. The processor 11 or the GPU 14 can use the storage device 12 as a cache memory. The database 35 includes TEG information 35a, coordinate information 35b, characteristic information 35c, and process information 35d.

[0047] The TEG information 35a stores basic layout information of feasible transistors and process management elements (for example, capacitance TEGs, resistance TEGs, resistance TEGs such as Kelvin connection, sheet resistance TEGs, contact TEGs, coverage and short TEGs, open and short TEGs, and analysis TEGs). It can also include circuit TEGs (ring oscillator circuits, shift register circuits, combinational circuits) for evaluating basic circuit operations. It is preferable that each piece of TEG information 35a is stored with measurement terminal information and information on the size of the TEG associated with each other.

[0048] The structure, layout, and process information of a new transistor can be registered as the TEG information 35a. When registering a new transistor structure, it is preferable to associate and store design rules related to the new transistor.

[0049] As the coordinate information 35b, the size of the board, the shape of the board (rectangular or circular), the mountable area, the number of TEG blocks to be mounted, and the like can be stored.

[0050] Previously measured data, etc., are stored as characteristic information 35c. The learning model can learn about the in-plane variation of each manufacturing device used in the manufacturing process using the measurement data included in characteristic information 35c.

[0051] The process information 35d may be process information that can be used for semiconductor elements and circuits. The process information 35d is preferably associated with the characteristic information 35c.

[0052] The EDA program 31 is software for supporting design work such as the layout of semiconductor elements and circuits. The TEG management system generates the layout of the target TEG by instructing the EDA program 31. Note that the TEG management system, which is one aspect of the present invention, may be included in the EDA program 31. Including the TEG management system in the EDA program 31 makes it easier to automatically generate the layout of the TEG.

[0053] The TEG generation program 32 can automatically generate a TEG layout using the TEG information 35a, coordinate information 35b, and process information 35d. The TEG generation program 32 may instruct the EDA program 31 to generate the TEG layout. The TEG generation program 32 will be described in detail with reference to FIGS. 5 to 8.

[0054] The TEG map generation program 33 automatically places the TEG automatically generated by the TEG generation program 32 on a specified substrate, and automatically generates a TEG map. The TEG map generation program 33 can also generate a measurement recipe. The TEG map generation program 33 will be described in detail with reference to FIG. 4 or FIG. 9.

[0055] The learning model 34 has a neural network, and learns the measurement data included in the characteristic information 35c using the GPU 14. By providing the learning model 34 with layout information of the generated TEG or TEG block, the learning model 34 can generate and output a TEG block map suitable for determining the contents of the TEG or TEG block and evaluating the manufacturing process.

[0056] 2 is a flowchart illustrating the TEG management system. The TEG management system can be divided into a TEG setting method SA01, a TEG generation method SA02, and a TEG map generation method SA03.

[0057] First, the TEG setting method SA01 will be described. Step S01 is a step for setting the board. In the board setting, the shape of the board, coordinate selection, and board size can be set.

[0058] Step S02 is a step for selecting a transistor structure.

[0059] Step S03 is a step for selecting a process evaluation TEG. The process evaluation TEG includes a capacitance TEG, a resistance TEG, a contact TEG, and an analysis TEG.

[0060] Step S04 is a step for selecting process information. The process information can be selected from process information 35d stored in the database 35. As an example, the process information 35d stores a process for forming a transistor. Note that new process information can be added to the process information 35d. Examples of process information will be described in detail with reference to FIG. 3.

[0061] Next, a TEG generation method SA02 will be described. Step S05 is a step of generating layouts of multiple TEGs related to selected transistors. The TEG generation program 32 automatically generates the TEG layout by instructing the EDA program 31 on the selected transistor structure and the process evaluation TEG related to the selected transistor structure. The layout generation method will be described in detail with reference to FIGS. 5 to 8.

[0062] Step S06 is a step for generating a TEG block. The TEG block can be assigned a TEG block name by treating the multiple TEGs generated in step S05 as one TEG block. The TEG map generation program 33 can generate a TEG block layout by automatically arranging multiple TEGs. Alternatively, the user may specify the position of the TEGs in the TEG block layout. Note that the TEG block name can be a TEG block name that has already been registered. Alternatively, a new TEG block name can be assigned.

[0063] Step S07 is a step of placing the TEG block on the substrate using the learning model 34. The learning model 34 is trained using data on the in-plane distribution (electrical, film thickness, film quality, etc.) of the manufacturing equipment that is already stored in the database 35. Therefore, by providing the TEG block to the learning model as inference data, the learning model can determine at which position on the substrate the TEG block should be placed to grasp the in-plane distribution on the substrate, and output that position.

[0064] Next, the TEG map generation method SA03 will be described. Step S08 is a step of generating a TEG block list. The TEG block list is a method of listing TEGs included in a TEG block as a single unit. The types of TEGs included in a TEG block are generated as a TEG list.

[0065] Step S09 is a step of displaying the TEG block map and TEG block list on a GUI (Graphical User Interface). The GUI displays the TEG block list and TEG block map, and also displays the TEG list and TEG map included in the TEG block. When either the TEG block list or the TEG list is selected, the selected TEG block or TEG is highlighted. This makes it possible to show where the TEG is located within the substrate. A measurement recipe can be generated from the TEG map and TEG list displayed on the GUI.

[0066] 3 is a diagram illustrating a TEG setting screen 40. The TEG setting screen 40 has a substrate setting 41, a TEG block setting 42, process information 43, and a TEG generation button 45.

[0067] The board setting 41 includes a board shape selection field 41a, a coordinate selection field 41b, and a board size selection field 41c. The board shape selection field 41a allows the user to select, for example, either "rectangle" or "circle" as the board shape. The coordinate selection field 41b allows the user to select "automatic" or "manual." Coordinate selection refers to selecting whether the TEG block, described below, is to be automatically placed by the TEG map generation program 33 or to be manually placed at an arbitrary position. The board size selection field 41c allows the user to select the size of the board on which the TEG is to be placed. Note that while FIG. 3 shows an example in which "8 inches" is selected, one embodiment of the present invention is not limited to this, and the user can select from multiple options.

[0068] The TEG block setting 42 includes a TEG block name registration field 42a, a transistor structure selection field 42b, and a process evaluation TEG selection field 42c. The TEG block name registration field 42a allows the user to select either "New" or "Registered" for the TEG block name. If a registered TEG block name is selected, the information of the already registered TEG block can be read. The user can add or delete information to or from the TEG block associated with the registered TEG block name, and register the information of the TEG block under a different name.

[0069] The transistor structure selection field 42b allows the user to select a transistor structure. While FIG. 3 shows an example in which "Type_A," "Type_B," or "Type_C" can be selected, the number of selectable transistor structures and the options are not limited to these. The transistor structure is associated with process information 43, which will be described later.

[0070] The process evaluation TEG selection field 42c allows the user to select a TEG that can independently evaluate the manufacturing process for forming the transistor selected in the transistor structure selection field 42b. Examples of process evaluation TEGs include a "capacitor TEG (C)," a "resistance TEG (R)," a "contact TEG (Cn)," and an "analysis TEG (A)."

[0071] Although not shown in detail in Figure 3, as an example, if you select "Resistor TEG (R)" in the process evaluation TEG selection field 42c, you can generate a TEG layout by selecting the process evaluation TEG in detail from among resistor TEG, Kelvin-connected resistor TEG, sheet resistance TEG, contact TEG, coverage and short TEG, and open and short TEG.

[0072] As an example, the resistor TEG will be described in more detail. Resistor TEGs include a TEG for managing the resistance of a semiconductor layer used in a transistor, a TEG for managing the resistance of a conductive film used in the gate of a transistor, a TEG for managing the conductive film used in the source or drain of a transistor, a TEG for managing the resistance of a conductive film used in the back gate of a transistor, and a TEG for managing the contact resistance for connecting the respective conductive films.

[0073] The TEG generation program 32 can automatically generate the layout of the TEG selected in the process evaluation TEG selection field 42c. It is preferable that the process evaluation TEG to be generated can be arbitrarily selected.

[0074] The process information 43 has a process name registration field 43a and a process list field 43b. The process name registration field 43a allows a user to "newly" register a process name (FileName). Alternatively, a user can select a process name that has already been "registered." If a registered process name is selected, a process list related to the already registered process name can be displayed in the process list field 43b. If a transistor structure is selected in the transistor structure selection field 42b, the process name associated with the selected transistor structure can be displayed. The displayed process list allows users to add or delete processes, and the process list can be saved with a new process name assigned.

[0075] In FIG. 3, for example, the process list field 43b displays a process list for the transistor Type_A selected in the transistor structure selection field 42b. The process list includes items such as a number, a process type, an equipment, element 1, and element 2. The number indicates the order of the process, and the process type indicates a film formation process (inorganic film formation, semiconductor film formation, conductive film formation, etc.) or a processing process (etching process, CMP (Chemical Mechanical Polishing) process, etc.). The equipment is associated with the manufacturing equipment used in each manufacturing process. Furthermore, element 1 and element 2 can each be assigned information about which component of a semiconductor device the process type forms. For example, element 1 indicates a transistor component (channel, gate film, gate electrode, source or drain (SD electrode), etc.), and element 2 indicates a capacitance component (electrode 1, electrode 2, capacitance film). Note that process types can be added or deleted as needed.

[0076] As an example of a process list, we will use process list number "2" as an example. Number "2" is associated with "semiconductor film deposition" as the process type, "device M2" as the device, "channel" as element 1, and "-" as element 2. To explain in detail, this indicates that device M2 is used in the semiconductor film deposition process, and the semiconductor film functions as a channel. Note that explanations of the other manufacturing processes in the process list will be omitted.

[0077] The TEG generation button 45 has a function of causing the TEG generation program 32 to automatically generate a layout of a TEG of the type selected in the TEG block setting 42. When "Auto" is selected in the coordinate selection selection field 41b, the TEG generation program 32 can automatically arrange the layout positions of multiple TEGs and store the automatically arranged multiple TEGs under a specified TEG block name. When "Manual" is selected in the coordinate selection selection field 41b, the layout positions of multiple TEGs can be freely arranged and stored under a specified TEG block name. Note that, although FIG. 3 shows an example in which the TEG generation button 45 is labeled "Create," one aspect of the present invention is not limited to this.

[0078] When generating a layout of a TEG, the TEG generation program 32 preferably generates a plurality of transistor TEGs for evaluating the dependency on the channel length and channel width of the transistor.

[0079] 4 is a diagram illustrating a display screen of a TEG map. A TEG map 50 has a TEG block display area 51 and a substrate map display area 52.

[0080] The TEG block display area 51 has a TEG block name selection field 51a, a TEG list 51b, and a TEG map 51c. The TEG block name selection field 51a allows the user to select a registered TEG block. The TEG list 51b has the TEG number No., TEG name TName, X coordinate, and Y coordinate. FIG. 4 shows, as an example, an example in which the TEG map 51c has an area in which 10 TEGs can be placed in the X direction and 10 TEGs in the Y direction. The TEG map 51c shows the area of ​​the selected TEG block. The TEG block name BName is preferably registered in the database 35.

[0081] In Fig. 4, TEGs included in the TEG block selected in the selection field 51a for the TEG block name BName are displayed in the TEG list 51b. Fig. 4 shows an example in which the TEG list 51b includes transistor-related TEGs (TEG_T1, TEG_T2, TEG_T3), resistor-related TEGs (TEG_R1), capacitor-related TEGs (TEG_C1, TEG_C2), and an analysis TEG (TEG_A1). Each TEG is associated with a position coordinate on the TEG map.

[0082] Next, the TEG map 51c will be described. In the TEG map 51c, TEGs related to transistors are displayed as "T", TEGs related to resistors are displayed as "R", TEGs related to capacitance are displayed as "C", and TEGs for analysis are displayed as "A". If there is sufficient display area on the screen, it is preferable to display more detailed information. As an example, when displaying TEG_T1, it is more preferable to display it as "T1" rather than "T".

[0083] Next, a description will be given of the board map display area 52. The board map display area 52 has a TEG block list 52a, a TEG block map 52b, and a mapping execution button 55.

[0084] The TEG block list 52a is a list for registering TEG blocks to be placed on a board. The Add button 54 is used to register a new TEG block name BName in the TEG block list 52a. For TEG blocks registered in the TEG block list 52a, it is possible to select using a check box whether or not to layout them on a board.

[0085] The TEG block map 52b displays the layout area of ​​the TEG block using the selection field 41a for the board shape set in the board setting 41. FIG. 4 shows an example in which a circular board is selected. Therefore, the area 53b within the range 53a inside the circle is the layout area of ​​the TEG block. Note that the area 53c indicates the layout prohibited area of ​​the TEG block.

[0086] The mapping execution button 55 can layout the selected TEG blocks registered in the TEG block list 52a in the layoutable area (area 53b) on the board. While FIG. 4 shows an example in which the mapping execution button 55 displays "Mapping," this is not a limitation of the present invention. The TEG map generation program 33 determines the placement of TEG blocks using a learning model that has learned the in-plane variations of the manufacturing equipment. The learning model can place TEG blocks in positions where the in-plane variations of the manufacturing equipment are likely to appear.

[0087] 4 is an example of an arrangement of five types of TEG blocks registered in the TEG block list 52a. In an area 53d where the TEG blocks are arranged, a number corresponding to the TEG block is displayed.

[0088] As an example, if the TEG block name BName is block name Block_1, area 53d displays "1", if the block name is Block_2, area 53d displays "2", if the block name is Block_3, area 53d displays "3", if the block name is Block_4, area 53d displays "4", and if the block name is Block_5, area 53d displays "5".

[0089] 5 is a flowchart illustrating a TEG layout generation method, and is a flowchart illustrating the details of step S05 in the flowchart shown in FIG.

[0090] Step S11 is a step of referencing the TEG list generated by the TEG block setting 42. In this step, if there is a TEG for which a layout has not been generated, the process proceeds to step S12, and if the TEG layout of the TEG list has already been generated, the process proceeds to step S06 shown in FIG.

[0091] Step S12 is a step for determining whether the semiconductor element of the TEG to be laid out is a transistor. If the semiconductor element is a transistor, the process proceeds to step S14, and if it is not a transistor, the process proceeds to step S13.

[0092] Step S13 is a step for determining whether the semiconductor device requires four measurement terminals. As an example, four measurement terminals are required to measure a Kelvin-connected resistor TEG. If four measurement terminals are required, proceed to step S14; otherwise, proceed to step S15.

[0093] Step S14 is a step of arranging four measurement terminals on the TEG, followed by step S16.

[0094] Step S15 is a step of arranging the required number of measurement terminals on the TEG, followed by step S16.

[0095] Step S16 is a step of loading layout information of the semiconductor elements held by the TEG from the TEG information 35a, followed by step S17.

[0096] Step S17 is a step for acquiring terminal information from the layout information of the loaded semiconductor element. As an example, if the semiconductor element is a transistor, layout information such as the gate electrode, source electrode, drain electrode, and back gate electrode can be acquired. As a different example, if the semiconductor element is a resistor or capacitor, layout information such as electrode 1 and electrode 2 can be acquired. Next, the process proceeds to step S18.

[0097] Step S18 is a step of connecting each measurement terminal to a terminal of the semiconductor element by wiring. The details of this step will be described in detail with reference to FIG. 6. The layout of the TEG is completed by connecting each measurement terminal to a terminal of the semiconductor element by wiring. Next, the process proceeds to step S11. Steps S12 to S18 are repeated until there are no more TEGs for which a layout has not been generated.

[0098] 6 is a flowchart illustrating a method for generating a TEG layout, and is a flowchart illustrating the details of step S18 in the flowchart shown in FIG.

[0099] Step S21 is a step for calculating the distance between the coordinates of the four measurement terminals (PD1, PD2, PD3, PD4) and the coordinates of the terminals (Pa, Pb, Pc) of the semiconductor element. Next, the process proceeds to step S22.

[0100] Step S22 is a step for determining the terminal of the semiconductor element to which the measurement terminal is connected. As an example, the distance d1 between measurement terminal PD1 and terminal Pa of the semiconductor element, the distance d2 between measurement terminal PD2 and terminal Pb of the semiconductor element, and the distance d3 between measurement terminal PD3 and terminal Pc of the semiconductor element are calculated. The terminal of the semiconductor element that is closest to each measurement terminal is selected as the connection target for that measurement terminal. Next, the process proceeds to step S23.

[0101] Step S23 is a step for determining whether the terminals Pa, Pb, and Pc of the semiconductor element are generated in the same manufacturing process. As an example, if the terminals Pa, Pb, and Pc of the semiconductor element are generated in the same manufacturing process, the process proceeds to step S24. If at least one of the terminals Pa, Pb, and Pc of the semiconductor element is generated in a different manufacturing process, the process proceeds to step S26.

[0102] Step S24 is a step for determining whether the distances d1, d2, and d3 between the respective terminals are the same (or approximately the same). If the distances between the respective terminals are the same (or approximately the same), the process proceeds to step S25. If the distances between the respective terminals are different, the process proceeds to step S26.

[0103] Step S25 is a step of connecting the measurement terminals and the terminals of the semiconductor element using the wiring block R. As an example, the TEG generation program 32 connects the measurement terminal PD1 and the terminal Pa of the semiconductor element using the wiring block R, connects the measurement terminal PD2 and the terminal Pb of the semiconductor element using the wiring block R, and connects the measurement terminal PD3 and the terminal Pc of the semiconductor element using the wiring block R.

[0104] The wiring layout can be formed using multiple wiring blocks R. As an example, the measurement terminal PD1 can be connected to the terminal Pa of the semiconductor element using wiring formed by wiring blocks R(1) and R(2). The measurement terminal PD2 can be connected to the terminal Pb of the semiconductor element using wiring formed by wiring blocks R(1) and R(2). The measurement terminal PD3 can be connected to the terminal Pc of the semiconductor element using wiring formed by wiring blocks R(1) and R(2).

[0105] The resistance value of the wiring block R(1) relative to the shape and distance may be the same (or approximately the same) as that of the wiring block R(2), or may be different. However, it is preferable that the magnitude of the wiring resistance of the wiring formed by the wiring block R(1) and the wiring block R(2) is the same (or approximately the same). Once the layout in which each measurement terminal is connected to the terminal of the semiconductor element using the wiring formed by the wiring block R is completed, proceed to step S11.

[0106] Step S26 is a step of connecting the measurement terminal and the terminal of the semiconductor element using the wiring block R and the contact block Cn. As an example, the TEG generation program 32 connects the measurement terminal PD1 and the terminal Pa of the semiconductor element using the wiring 1, connects the measurement terminal PD2 and the terminal Pb of the semiconductor element using the wiring 2, and connects the measurement terminal PD3 and the terminal Pc of the semiconductor element using the wiring 3.

[0107] Next, step S27 will be described. Step S27 is, as an example, a step of provisionally calculating the magnitude of the wiring resistance of wire 1 at distance d1, wire 2 at distance d2, and wire 3 at distance d3. Note that wire 1, wire 2, or wire 3 may each include a contact block Cn. The magnitude of each wiring resistance is provisionally calculated, and the wire with the maximum wiring resistance is detected, and the resistance component of that wire is set to the wiring resistance RLmax. Next, the process proceeds to step S28. Note that contact block Cn has a contact resistance.

[0108] Step S28 is a step of correcting the wiring blocks R of the other wirings so that the wiring resistance of the other wirings becomes equal to the wiring resistance RLmax. The correction of the wiring blocks R can be adjusted by adjusting the number of wiring blocks R(1) to R(n). Alternatively, the correction can be performed by varying the size of the wiring blocks R to create wiring blocks Ra whose wiring resistance becomes equal to the wiring resistance RLmax. Furthermore, the magnitude of the contact resistance can be corrected by changing the number of contacts that the contact block Cn has.

[0109] As an example, when the wiring resistance RL(1) of wiring 1 is wiring resistance RLmax, it is preferable that the wiring resistances RL(2) and RL(3) are each the same (or approximately the same) as the wiring resistance RL(1).

[0110] A case will be described in which the wiring 1 is composed of a wiring block R(1), a contact block Cn(1), and a wiring block R(2), and the magnitude of the wiring resistance of the wiring 1 is the wiring resistance RL(1).

[0111] When the wiring 2 is formed by the wiring block R(1) and the wiring block R(3), the wiring block R(3) is selected so that the wiring resistance RL(2) of the wiring 2 is the same (or approximately the same) as the wiring resistance RL(1). The size of the wiring block R(3) is preferably selected so that it is the same (or approximately the same) as the contact block Cn(1) and the wiring block R(2).

[0112] When the wiring 3 is formed by the wiring block R(1), the contact block Cn(2), and the wiring block Ra(1), the magnitude of the contact resistance of the contact block Cn(2) is corrected so that the magnitude of the wiring resistance RL(3) of the wiring 3 is the same (or approximately the same) as the magnitude of the wiring resistance RL(1), and the wiring block Ra(1) with the corrected size of the wiring block R(1) is selected. After the layout is completed in which each measurement terminal is connected to the terminal of each semiconductor element using the wirings 1 to 3, the process proceeds to step S11.

[0113] 7A and 7B are diagrams illustrating the layout of a TEG, which is generated according to the flowcharts described in FIGS.

[0114] 7A is an example of a layout of a TEG having transistors as semiconductor elements. FIG. 7A shows an example in which the TEG has a TEG region 61 and a marker TM. The TEG region 61 has measurement terminals PD1 to PD4, a transistor 62, wiring 63, wiring 64, and wiring 65. The wiring 63 has wiring blocks R(1) and R(2). The wiring 64 has wiring blocks R(1) and R(2). The wiring 65 has wiring blocks R(3) and R(4). The transistor 62 has terminals Pa, Pb, and Pc. The transistor has a semiconductor film Pos, which is connected to terminal Pa via contact block Cn1 and to terminal Pb via contact block Cn2.

[0115] Each measurement terminal has its own center coordinate as its reference point. As an example, measurement terminal PD1 has a reference point PD1a (x1, y1). Measurement terminal PD2 has a reference point PD2a (x2, y2). Measurement terminal PD3 has a reference point PD3a (x3, y3). Measurement terminal PD4 has a reference point PD4a (x4, y4). The marker TM corresponds to the reference point that defines the position of the TEG region 61. Therefore, the positions of each of measurement terminals PD1 to PD4 are determined with the center of marker TM (x0, y0) as the origin.

[0116] Next, the connection between the measurement terminals and the terminals of the semiconductor element will be described. As an example, the measurement terminal PD1 is connected to the terminal Pa of the transistor via the wiring 63. The measurement terminal PD2 is connected to the terminal Pb of the transistor via the wiring 64. The measurement terminal PD3 is connected to the terminal Pc of the transistor via the wiring 65. It is preferable that the wiring resistance of the wiring 63 is the same (or approximately the same) as the wiring resistance of the wiring 64. In FIG. 7A, the wiring 63 and the wiring 64 are configured by the wiring block R(1) and the wiring block R(2), respectively. Therefore, the wiring 63 and the wiring 64 are laid out so that the magnitude of the wiring resistance is the same (or approximately the same).

[0117] The wiring resistance of wiring 63 is preferably the same (or approximately the same) as the wiring resistance of wiring 65. Wiring 63 is composed of wiring blocks R(1) and R(2), while wiring 65 is composed of wiring blocks R(3) and R(4). Therefore, it is preferable to determine the shapes and magnitude of the wiring resistance of wiring blocks R(3) and R(4) so ​​that the combined resistance of wiring blocks R(3) and R(4) is equal to the combined resistance of wiring blocks R(1) and R(2). Furthermore, wiring 65 may further include a contact block.

[0118] 7B is a layout of a TEG having a capacitor as a semiconductor element. As an example, the TEG has a TEG region 61 and a marker TM. The TEG region 61 has a measurement terminal PD1, a measurement terminal PD2, a capacitor 66, a wiring 67, and a wiring 68. The wiring 67 has a wiring block R(5), a contact block Cn2, and a wiring block R(6). The wiring 67 has a wiring block Ra(5) and a wiring block R(7). The capacitor 66 has an electrode Pd and an electrode Pe.

[0119] The measurement terminal PD1 is connected to the capacitor electrode Pd via a wiring 67. The measurement terminal PD2 is connected to the capacitor electrode Pe via a wiring 68. The wiring resistance of the wiring 67 is preferably the same as (or approximately the same as) the wiring resistance of the wiring 68. The wiring 67 has a contact block Cn2, and may have a higher wiring resistance than the wiring 68. Therefore, it is preferable to select a wiring block for the wiring 68 so that the magnitude of the wiring resistance of the wiring 67 is the same as (or approximately the same as) that of the wiring 67. The resistance value of the wiring block Ra(5) can be increased by increasing the distance therebetween compared to the wiring block R(5). The wiring block R(7) can be configured to have a different resistance value from the wiring block R(6).

[0120] 8A and 8B are diagrams illustrating the layout of a TEG. FIG. 8A differs from FIG. 7A in that it includes wiring 63a and wiring 64a. FIG. 8B is a diagram illustrating wiring 63a in detail. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations thereof will be omitted.

[0121] As shown in FIG. 8B, the wiring 63a is a wiring block whose processable wiring width is limited to wiring width dc1 and whose spacing between wirings is limited to wiring spacing dc2. This wiring block can be automatically selected when a CMP process is selected as the conductive film processing process. When a CMP process is selected as the processing process, the wiring width dc1 and wiring spacing dc2 may be limited by the processing accuracy of the manufacturing equipment. As an example, the wiring resistance of wiring 63a is the combined resistance of wiring 63a1, wiring 63a2, and wiring 63a3. Note that while FIG. 8B shows an example in which wiring 63a is composed of three wirings, it is preferable to select the number of wirings for wiring 63a appropriately depending on the desired wiring resistance. The description of wiring 63a can be referenced, so a detailed description of wiring 64a will be omitted.

[0122] 9 is a flowchart illustrating a method for arranging TEG blocks, which corresponds to step S07 in FIG.

[0123] The TEG map generation program 33 can arrange TEG blocks on a substrate using a learning model 34. The learning model 34 is preferably trained using measurement data of the in-plane distribution (electrical, film thickness, film quality, etc.) of an existing manufacturing device. As an example, the TEG blocks selected from the TEG block list shown in FIG. 4 are provided to the learning model as inference data. The learning model 34 can arrange the TEG blocks at positions suitable for grasping the in-plane distribution of the semiconductor element. Therefore, the TEG map generation program 33 can output information on the arrangement of the TEG blocks as a TEG map data file, and can further display it on a display device.

[0124] Next, the flowchart shown in Fig. 9 will be described in detail. Step S31 is a step for determining whether "automatic" has been selected in the coordinate selection selection field 41b. If "automatic" has been selected, the process proceeds to step S32. Note that, if "manual" has been selected in the coordinate selection selection field 41b, the process proceeds to step S35. Note that, in step S35, the arrangement and number of TEG blocks can be manually specified to generate the TEG block map 52b.

[0125] Step S32 is a step in which TEG blocks are automatically placed on the substrate using the learning model. The TEG block list is provided to the learning model as inference data. The learning model can place TEG blocks at positions that allow appropriate extraction of the in-plane distribution of the manufacturing equipment. Next, proceed to step S33.

[0126] Step S33 is a step for checking whether the placed TEG blocks need to be rearranged. More specifically, the TEG blocks placed by the learning model are displayed on the display device as a TEG block map 52b by the TEG map generation program 33. As an example, the TEG block map 52b in FIG. 4 shows an example in which TEG blocks are displayed on the TEG block map 52b. If rearrangement is required, the process proceeds to step S32; if rearrangement is not required, the process proceeds to step S34. If rearrangement is required, the TEG block map 52b can be rearranged using the mapping execution button 55. It is also preferable that the number of TEG blocks for each rearrangement can be specified.

[0127] Step S34 is a step in which the TEG block map 52b is completed. Completion of the TEG block map 52b indicates that the position information of the TEG blocks arranged in the TEG block map 52b, the TEG block list, and the like have been stored in a file. It also indicates that the position information of the TEG blocks arranged in the TEG block map 52b, the TEG block list, and the like can be reused.

[0128] FIG. 10A is a diagram illustrating a learning model 34 that learns the in-plane distribution of devices.

[0129] As an example, the learning model 34 has neural networks 71 and 72. The neural network 71 has an input layer 71a, a hidden layer 71b, and a hidden layer 71c. Note that multiple hidden layers 71b can be provided. The neural network 72 functions as a fully connected layer. The input layer 71a has neurons X1 through Xn, the hidden layer 71b has neurons Y1 through Yn, and the hidden layer 71c has neurons Z1 through Zn. Note that n is a positive integer greater than 2.

[0130] Measurement data of the manufacturing equipment is provided to the neural network 71 as training data. The measurement data includes the in-plane distribution of each manufacturing equipment. It is preferable that each measurement data provided as training data is data measured according to all coordinates included in the TEG block map 52b. Neurons included in the neural network 71 learn the measurement data as training data.

[0131] Therefore, the neural network 71 outputs a feature vector based on the type of TEG formed in the manufacturing process and the measurement data of the TEG. Therefore, the learning model 34 can be rephrased as a multimodal learning model. Therefore, the feature vector output by the neural network 71 is not limited to one. It is possible to output multiple feature vectors. Below, we will explain the case where the neural network 71 outputs multiple feature vectors.

[0132] The neural network 72 is provided with multiple feature vectors generated by the neural network 71. Therefore, it is preferable that the neural network 72 has a fully connected layer that can handle multimodal inputs. By having a fully connected layer, the neural network 72 can collectively handle multiple feature vectors output by the neural network 71.

[0133] The output of each fully connected layer can use an activation function such as a sigmoid function, a step function, or a ramp function (ReLU: Rectifield Linear Unit). A nonlinear activation function can be effectively used to convert multiple different training data into feature vectors. Therefore, the neural network 72 can learn measurement data including the in-plane distribution of TEGs formed by a manufacturing process, which is provided as training data.

[0134] Fig. 10B is a diagram illustrating a learning model 34a in which a TEG block can be arranged. The learning model 34a shown in Fig. 10B differs from the learning model shown in Fig. 10A in that it further includes an input layer 11a. Note that neural network 71 and neural network 72 are learning models that have trained on measurement data of a TEG formed in a manufacturing process.

[0135] The input layer 11a corresponds to an input interface for providing the trained neural network 71 with TEG blocks to be arranged in the TEG block map 52b as inference data. The input layer 11a can be used to provide inference data of a number different from the number of inputs of the input layer 71a of the trained neural network 71. The inference data indicates multiple TEG blocks included in the TEG block list (e.g., Block_1, Block_2 to Block_n in FIG. 10B). Note that the TEG block includes multiple TEGs. Note that the TEGs included in each TEG block may all be different types of TEGs, or some of them may be different types of TEGs. Each TEG is associated with a manufacturing device for producing a semiconductor device by process information 43.

[0136] Therefore, when the trained learning model 34a is given multiple TEG blocks included in the TEG block list, it can arrange the TEG blocks in the TEG block map 52b. The learning model 34a can arrange each TEG block in an appropriate position that can reproduce the in-plane distribution of the TEG formed by the manufacturing process. Furthermore, the learning model 34a can arrange a number of TEG blocks that can reproduce the effect of the in-plane distribution of the TEG formed by the manufacturing process on the semiconductor element.

[0137] FIG. 11 is a diagram illustrating a method for generating a measurement recipe from a TEG block map 52b. FIG. 11 differs from FIG. 4 in that it includes a generate button 56. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations will be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0138] The TEG map generation program 33 can generate a measurement recipe from the generated TEG block map 52b. As an example, when the selection box 56a displayed in the TEG block list 52a is selected, the number "1" is selected. By selecting the number "1", the TEG list constituting the TEG block is expanded, and at the same time, the frame of the area 56b in which the block name Block_1 is arranged is highlighted. Note that "1" is displayed in the area 56b in which the block name Block_1 is arranged. Furthermore, when the TEG name TName "TEG_T1" is selected from the expanded TEG list, the background of the area 56b is highlighted (hatched in FIG. 11). Note that in the TEG map 51c, it is preferable that the background of the area in which the selected TEG name TName "TEG_T1" is arranged is highlighted.

[0139] As described above, a measurement recipe is generated by pressing the Generate button 56 after the measurement target has been selected. The measurement recipe is generated by associating the target TEG name (TName) with coordinate information. The measurement recipe can be saved in a file. Alternatively, the measurement recipe can be sent to the measuring instrument. Although FIG. 11 shows an example in which the Generate button 56 displays "Make," one aspect of the present invention is not limited to this.

[0140] Figure 12 is a diagram illustrating a TEG management system different from that shown in Figure 1. In the configuration of the invention described below, the same parts as those in Figure 1 or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0141] The computer device 10 has a communication circuit 17. The input / output device 15 is connected to a display device 21, a touch sensor 22, a keyboard 23, a mouse controller 24, etc. The data server 80 has a processor 81, a GPU 82, a storage device 83, and a communication circuit 87. The communication circuit 17 can be connected to multiple other remote computers 10a and the data server 80 via a network. The multiple other remote computers 10a or the data server 80 may be installed in Japan or elsewhere.

[0142] Here, the network includes a local area network (LAN) and the Internet. The network can use either or both of wired and wireless communication. When wireless communication is used in the network, various communication methods can be used, such as short-range communication methods such as Wi-Fi (registered trademark) and Bluetooth (registered trademark), as well as communication methods conforming to the third generation mobile communication system (3G), LTE (sometimes called 3.9G), fourth generation mobile communication system (4G), or fifth generation mobile communication system (5G).

[0143] The TEG management system can use the TEG information 35a, coordinate information 35b, characteristic information 35c, and process information 35d stored in another remote computer 10a or a data server 80 via a network.

[0144] The TEG management system can also be used by a remote computer 10a via a network. Alternatively, the TEG management system can be operated on the computer device 10 by using the TEG management system stored in a storage device of the data server 80 or the remote computer 10a. The remote computer 10a may be a portable information terminal, or a portable terminal such as a tablet computer or a notebook computer. In the case of a portable information terminal or a portable terminal, communication can be performed using wireless communication.

[0145] According to one embodiment of the present invention, a management system for managing a TEG layout using a computer device can be provided. According to another embodiment of the present invention, a layout method for automatically generating a TEG layout in which wiring resistance between terminals and measurement terminals of a semiconductor element is equal can be provided. According to another embodiment of the present invention, a layout method for automatically placing a TEG on a substrate for evaluating variations in electrical characteristics of semiconductor elements can be provided. According to another embodiment of the present invention, a TEG block generation method for automatically generating a TEG block on a substrate for evaluating in-plane variations of each manufacturing equipment can be provided. According to another embodiment of the present invention, a learning model for learning in-plane variation information of a manufacturing equipment for manufacturing semiconductor elements can be provided. According to another embodiment of the present invention, a management system for arranging a layout of TEG blocks on a substrate based on the type of circuit included in the TEG block by the learning model can be provided.

[0146] This embodiment can be carried out by combining parts thereof as appropriate. [Explanation of symbols]

[0147] : Cn2: contact block, dc1: wiring width, dc2: wiring spacing, PD1: measurement terminal, PD1a: reference point, PD2: measurement terminal, PD2a: reference point, PD3: measurement terminal, PD3a: reference point, PD4: measurement terminal, PD4a: reference point, X1: neuron, Y1: neuron, Z1: neuron, 10: computer device, 10a: remote computer, 11: processor, 11a: input layer, 12: storage device, 14: GPU, 15: input / output device, 16: storage device, 17: communication circuit, 21: display device, 22: Touch sensor, 23: Keyboard, 31: EDA program, 32: TEG generation program, 33: TEG map generation program, 34: Learning model, 34a: Learning model, 35: Database, 35a: TEG information, 35b: Coordinate information, 35c: Characteristics information, 35d: Process information, 40: TEG setting screen, 41: Board setting, 41a: Board shape selection field, 41b: Coordinate selection field, 41c: Board size selection field, 42: TEG block setting, 42a: TEG block name registration field, 42b: Transaction Register structure selection field, 42c: Process evaluation TEG selection field, 43: Process information, 43a: Process name registration field, 43b: Process list field, 45: TEG generation button, 50: TEG map, 51: TEG block display area, 51a: TEG block name selection field, 51b: TEG list, 51c: TEG map, 52: Board map display area, 52a: TEG block list, 52b: TEG block map, 53a: Range inside the circle, 53b: Area, 53c: Area, 53d: Area, 54: Add button, 55: Map Ping execution button, 56: Generate button, 56a: Selection box, 56b: Area, 61: TEG area, 62: Transistor, 63: Wiring, 63a: Wiring, 63a1: Wiring, 63a2: Wiring, 63a3: Wiring, 64: Wiring, 64a: Wiring, 65: Wiring, 66: Capacitance, 67: Wiring, 68: Wiring, 71: Neural network, 71a: Input layer, 71b: Hidden layer, 71c: Hidden layer, 72: Neural network, 80: Data server, 81: Processor, 82: GPU, 83: Storage device, 87: Communication circuit

Claims

1. A layout method for a circuit having a transistor, a first measurement terminal, a second measurement terminal, a first wiring, and a second wiring, the method comprising: the first wiring has a function of connecting the first measurement terminal and one of the source and the drain of the transistor, the second wiring has a function of connecting the second measurement terminal and the other of the source and the drain of the transistor, calculating a wiring resistance of the first wiring; calculating a wiring resistance of the second wiring; and automatically generating a layout of the first wiring and the second wiring in the circuit so that the wiring resistance of the first wiring and the wiring resistance of the second wiring are equal.

2. A layout method for a circuit having a transistor, a first measurement terminal, a second measurement terminal, a third measurement terminal, a first wiring, a second wiring, and a third wiring, the method comprising: the first wiring has a function of connecting the first measurement terminal and one of the source and the drain of the transistor, the second wiring has a function of connecting the second measurement terminal and the other of the source and the drain of the transistor, the third wiring has a function of connecting the third measurement terminal and a gate of the transistor, calculating a wiring resistance of the first wiring; calculating a wiring resistance of the second wiring; calculating a wiring resistance of the third wiring; a step of automatically generating a layout of the first wiring, the second wiring, and the third wiring in the circuit so that the wiring resistance of the first wiring, the wiring resistance of the second wiring, and the wiring resistance of the third wiring are equal.

Images