Display and method for manufacturing the same

Abstract

To provide a display with simplified processes.SOLUTION: A display includes: a substrate; a first insulating layer arranged on the substrate; a first electrode arranged on the first insulating layer; a second insulating layer formed on the first insulating layer and the first electrode along the bend of the first insulating layer and the first electrode; a second electrode formed on the second insulating layer; a light emitting structure arranged on the second electrode; and a third electrode arranged on the light emitting structure.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] With the development of information technology, the importance of display devices, which are a connection medium between users and information, is increasing, and accordingly, the use of display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs) is increasing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 2021-0042515 (KR10-2021-0042515A) [Patent Document 2] U.S. Patent Application Publication No. 2023 / 0042515 (US2023 / 0042515A) [Patent Document 3] Korean Patent Publication No. 2021-0155399 (KR10-2021-0155399A)

[0004] Recently, head-mounted display devices (HMDs) have been developed. HMDs are display devices worn by users in the form of glasses or a helmet, and realize virtual reality (VR) or augmented reality (AR), in which a focus is formed at a close distance in front of the eyes. High-resolution panels are used in head-mounted display devices, which require pixels suitable for high-resolution panels. Summary of the Invention [Problem to be solved by the invention]

[0005] It is an object of the present invention to provide a display device with a simplified process. Another object of the present invention is to provide a method for manufacturing a display device. [Means for solving the problem]

[0006] In order to achieve one object of the present invention, a display device according to an embodiment of the present invention includes a substrate, a first insulating layer disposed on the substrate, a first electrode disposed on the first insulating layer, a second insulating layer formed on the first insulating layer and the first electrode along the bending of the first insulating layer and the first electrode, a second electrode formed on the second insulating layer, a light-emitting structure disposed on the second electrode, and a third electrode disposed on the light-emitting structure.

[0007] In one embodiment, the second insulating layer includes a first opening exposing at least a portion of the first electrode, and the second electrode can be in direct contact with the first electrode.

[0008] In one embodiment, the display device further includes a third insulating layer including a second opening that exposes at least a portion of the second electrode, and the third insulating layer can be disposed on an area of ​​the second electrode that is in direct contact with the first electrode.

[0009] In one embodiment, the substrate includes a display region in which first to third sub-pixels are arranged, and the thickness of the second insulating layer formed on a portion of the first electrode may be different from each other in at least two of the first to third sub-pixels.

[0010] In one embodiment, the second insulating layer includes a 2-1 insulating layer and a 2-2 insulating layer, and each of the 2-1 insulating layer and the 2-2 insulating layer can be selectively disposed on the portion of the first electrode.

[0011] In one embodiment, the display device may further include a third insulating layer including a second opening that exposes at least a portion of the second electrode, and a sacrificial layer disposed between the second electrode and the third insulating layer.

[0012] In one embodiment, the sacrificial layer may include a conductive material.

[0013] In one embodiment, the sacrificial layer may have an undercut structure between the second electrode and the third insulating layer.

[0014] In one embodiment, the light emitting structure can output white light.

[0015] In order to achieve one object of the present invention, a display device according to an embodiment of the present invention may include a substrate, a first insulating layer disposed on the substrate, a first electrode disposed on the first insulating layer, a second insulating layer formed on the first insulating layer and the first electrode and in direct contact with the first electrode, a second electrode formed on the second insulating layer, a light-emitting structure disposed on the second electrode, and a third electrode disposed on the light-emitting structure.

[0016] In one embodiment, the display device further includes a third insulating layer including a second opening that exposes at least a portion of the second electrode, and the third insulating layer can be disposed on an area of ​​the second electrode that is in direct contact with the first electrode.

[0017] In one embodiment, the substrate includes a display region in which first to third sub-pixels are arranged, and the thickness of the second insulating layer formed on a portion of the first electrode may be different from each other in at least two of the first to third sub-pixels.

[0018] In one embodiment, the second insulating layer includes a 2-1 insulating layer and a 2-2 insulating layer, and each of the 2-1 insulating layer and the 2-2 insulating layer can be selectively disposed on the portion of the first electrode.

[0019] In one embodiment, the display device may include a third insulating layer including a second opening exposing at least a portion of the second electrode, and disposed between the second electrode and the third insulating layer.

[0020] In one embodiment, the sacrificial layer may include a conductive material.

[0021] In one embodiment, the sacrificial layer may have an undercut structure between the second electrode and the third insulating layer.

[0022] In one embodiment, the light emitting structure can output white light. [Effects of the Invention]

[0023] The display device according to the embodiment of the present invention can simplify the manufacturing process by eliminating the step of planarizing the identification layer.

[0024] In the display device according to the embodiment of the present invention, the anode electrode is directly connected to the reflective electrode without a via, thereby simplifying the manufacturing process.

[0025] The display device according to the embodiment of the present invention can protect the anode electrode by including a sacrificial layer.

[0026] However, the effects of the present invention are not limited to the above-mentioned effects, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a block diagram illustrating an embodiment of a display device. [Figure 2] FIG. 2 is a block diagram illustrating an embodiment of one of the subpixels of FIG. 1. [Figure 3] FIG. 2 is a plan view showing an embodiment of the display panel of FIG. [Figure 4]FIG. 4 is an exploded perspective view showing a part of the display panel of FIG. [Figure 5] FIG. 5 is a plan view showing an embodiment of one of the pixels of FIG. 4. [Figure 6] FIG. 6 is a cross-sectional view taken along line II' in FIG. 5. [Figure 7] 7 is a table showing examples of thicknesses of the discrimination layer in FIG. 6. [Figure 8] FIG. 8 is a cross-sectional view showing CASE 6 in FIG. 7. [Figure 9] 7 is a cross-sectional view showing an embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG. 6. FIG. [Figure 10] 7 is a cross-sectional view showing another embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG. 6. FIG. [Figure 11] 7 is a cross-sectional view showing still another embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG. 6. FIG. [Figure 12] 5 is a plan view showing another embodiment of one of the pixels of FIG. 4. FIG. [Figure 13] 5 is a plan view showing yet another embodiment of any one of the pixels of FIG. 4. FIG. [Figure 14] FIG. 7 is a cross-sectional view showing an example of the shape of the first lens in FIG. 6. [Figure 15] FIG. 7 is a cross-sectional view showing an example of the shape of the first lens in FIG. 6. [Figure 16] FIG. 7 is a cross-sectional view showing an example of the shape of the first lens in FIG. 6. [Figure 17] 3 is a cross-sectional view showing a part of first to third sub-pixels of a display device according to an embodiment of the present invention. [Figure 18] 1 is a flowchart illustrating a method for manufacturing a display device according to an embodiment of the present invention. [Figure 19] FIG. 20 is a diagram showing the step S200 in FIG. 18. [Figure 20] FIG. 20 is a diagram showing the step S300 in FIG. 18. [Figure 21] FIG. 20 is a diagram showing the step S400 in FIG. 18. [Figure 22]FIG. 20 is a diagram showing the step S500 in FIG. 18. [Figure 23] FIG. 20 is a diagram showing the step S600 in FIG. 18. [Figure 24] 5A to 5C are diagrams illustrating a process of forming a first identification layer and a second identification layer according to a manufacturing method of a display device according to an embodiment of the present invention. [Figure 25] 5A to 5C are diagrams illustrating a process of forming a first identification layer and a second identification layer according to a manufacturing method of a display device according to an embodiment of the present invention. [Figure 26] 5A to 5C are diagrams illustrating a process of forming a first identification layer and a second identification layer according to a manufacturing method of a display device according to an embodiment of the present invention. [Figure 27] 5A to 5C are diagrams illustrating a process of forming a first identification layer and a second identification layer according to a manufacturing method of a display device according to an embodiment of the present invention. [Figure 28] 5A to 5C are diagrams illustrating a process of forming a first identification layer and a second identification layer according to a manufacturing method of a display device according to an embodiment of the present invention. [Figure 29] 5A to 5C are diagrams illustrating a process of forming a sacrificial layer according to a method of manufacturing a display device according to an embodiment of the present invention; [Figure 30] 5A to 5C are diagrams illustrating a process of forming a sacrificial layer according to a method of manufacturing a display device according to an embodiment of the present invention; [Figure 31] 4A to 4C are diagrams illustrating a process of forming a sacrificial layer according to a method of manufacturing a display device according to an embodiment of the present invention; [Figure 32] FIG. 1 is a block diagram illustrating an embodiment of a display system. [Figure 33] FIG. 33 is a perspective view showing an application example of the display system of FIG. [Figure 34] FIG. 34 shows a head-mounted display device worn by the user of FIG. 33. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operation of the present invention will be described, and description of other parts will be omitted so as not to obscure the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. The embodiments described herein are merely provided to provide a detailed description sufficient to enable those skilled in the art to easily implement the technical concept of the present invention.

[0029] Throughout the specification, when a moiety is referred to as being "connected" to another moiety, this includes not only "directly connected" but also "indirectly connected" via an intervening element. The terms used herein are intended to describe specific embodiments and are not intended to limit the present invention. Throughout the specification, when a moiety is referred to as "comprising" a certain element, this does not mean that it excludes other elements, but that it can further include other elements, unless otherwise specified. The terms "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, and one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of the relevant elements.

[0030] Here, terms such as "first," "second," etc. may be used to describe various components, but such components are not limited to such terms. Such terms are used to distinguish one component from another. Therefore, a first component can be referred to as a second component within the scope of what is disclosed herein.

[0031] Spatially relative terms such as "below," "above," and the like may be used for descriptive purposes to describe the relationship of one element or feature to another, as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacture, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings were inverted, an element depicted as being "below" another element or feature would then be oriented "above" that other element or feature. Thus, in one embodiment, the term "below" can encompass both above and below. Moreover, a device may be otherwise oriented (e.g., rotated 90 degrees or at another orientation), and the spatially relative terms used herein should be interpreted accordingly.

[0032] Various embodiments are described with reference to drawings that illustrate idealized embodiments. It is to be understood that variations in shape due, for example, to tolerances and / or manufacturing techniques, may occur. Therefore, the embodiments disclosed herein should not be construed as limited to the particular shapes illustrated, but should also be construed to include variations in shapes that result, for example, from manufacturing. Thus, the shapes illustrated in the drawings may not represent the actual shapes of regions of a device, and the embodiments are not limited thereto.

[0033] FIG. 1 is a block diagram showing an embodiment of a display device. Referring to FIG. 1, a display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0034] The display panel 110 includes sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 via first to m-th gate lines GL1 to GLm. The sub-pixels SP may be connected to the data driver 130 via first to n-th data lines DL1 to DLn.

[0035] Each of the subpixels SP may include at least one light-emitting element configured to generate light. This allows each of the subpixels SP to generate light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more of the subpixels SP may constitute one pixel PXL. For example, as shown in FIG. 1, three subpixels may constitute one pixel PXL.

[0036] The gate driver 120 is connected to the sub-pixels SP arranged in the row direction via the first to m-th gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m-th gate lines GL1 to GLm in response to gate control signals GCS. In this embodiment, the gate control signals GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting gate signals in synchronization with the timing at which a data signal is applied, etc.

[0037] In an embodiment, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver may operate under the control of the controller 150.

[0038] The gate driver 120 may be arranged on one side of the display panel 110. However, embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and such drivers may be arranged on one side of the display panel 110 and on the other side of the display panel 110 opposite the one side. In this manner, the gate driver 120 may be arranged around the periphery of the display panel 110 in various forms depending on the embodiment.

[0039] The data driver 130 is connected to the sub-pixels SP arranged in a column direction via first to n-th data lines DL1 to DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0040] The data driver 130 can apply data signals having gray scale voltages corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using voltages from the voltage generator 140. When gate signals are applied to the first to m-th gate lines GL1 to GLm, the data signals corresponding to the image data DATA can be applied to the data lines DL1 to DLm. This allows the corresponding sub-pixels SP to generate light corresponding to the data signals. This allows an image to be displayed on the display panel 110.

[0041] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0042] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to the components of the display device 100. For example, the voltage generator 140 can be configured to receive an input voltage from outside the display device 100, adjust the received voltage, and regulate the adjusted voltage to generate the plurality of voltages.

[0043] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first and second power supply voltages VDD and VSS may be provided to the subpixels SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS may have a voltage level lower than the first power supply voltage VDD. In another embodiment, the first power supply voltage VDD or the second power supply voltage VSS may be provided by a device external to the display device 100.

[0044] Additionally, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the subpixel SP. For example, during a sensing operation for sensing electrical characteristics of the transistors and / or light emitting elements of the subpixel SP, a predetermined reference voltage may be applied to the first to n-th data lines DL1 to DLn, and the voltage generator 140 may generate such a reference voltage.

[0045] The controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG from the outside and a control signal CTRL for controlling the display of the input image data IMG. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0046] The controller 150 can convert the input image data IMG to be compatible with the display device 100 or the display panel 110 and output the image data DATA. In an embodiment, the controller 150 can align the input image data IMG to be compatible with the row-based sub-pixels SP and output the image data DATA.

[0047] Two or more of the data driver 130, the voltage generator 140, and the controller 150 may be implemented in a single integrated circuit. As shown in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In such a case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally separate components within a single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a separate component from the driver integrated circuit DIC.

[0048] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense a temperature around the display device 100 and generate temperature data TEP representing the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0049] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In some embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may adjust the data signal and the first and second power supply voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0050] Fig. 2 is a block diagram showing an embodiment of any one of the subpixels in Fig. 1. Fig. 2 exemplarily shows a subpixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and j-th column (j is an integer greater than or equal to 1 and less than or equal to n) of the subpixels SP in Fig. 1.

[0051] Referring to FIG. 2, the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0052] The light emitting element LD is connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN, where the first power supply voltage node VDDN is a node that transfers the first power supply voltage VDD of FIG. 1, and the second power supply voltage node VSSN is a node that transfers the second power supply voltage VSS of FIG. 1.

[0053] The anode electrode AE ​​of the light emitting element LD may be connected to a first power supply voltage node VDDN via the sub-pixel circuit SPC, and the cathode electrode CE of the light emitting element LD may be connected to a second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0054] The sub-pixel circuit SPC may be connected to the ith gate line GLi among the first to mth gate lines GL1 to GLm in Fig. 1, the ith light-emitting control line ELi among the first to mth light-emitting control lines EL1 to ELm in Fig. 1, and the jth data line DLj among the first to nth data lines DL1 to DLn in Fig. 1. The sub-pixel circuit SPC is configured to control the light-emitting element LD in response to signals received via these signal lines.

[0055] The sub-pixel circuit SPC may operate in response to a gate signal received via an ith gate line GLi. The ith gate line GLi may include one or more sub-gate lines. In an embodiment, as shown in FIG. 2, the ith gate line GLi may include first and second sub-gate lines SGL1 and SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received via the first and second sub-gate lines SGL1 and SGL2. In this way, when the ith gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received via the corresponding sub-gate lines.

[0056] The sub-pixel circuit SPC may operate in response to a light-emitting control signal received via an i-th light-emitting control line ELi. In an embodiment, the i-th light-emitting control line ELi may include one or more sub-light-emitting control lines. When the i-th light-emitting control line ELi includes two or more sub-light-emitting control lines, the sub-pixel circuit SPC may operate in response to a light-emitting control signal received via the corresponding sub-light-emitting control line.

[0057] The sub-pixel circuit SPC may receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of gate signals received via the first and second sub-gate lines SGL1 and SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN via the light-emitting element LD according to the stored voltage in response to an emission control signal received via the ith emission control line ELi. This allows the light-emitting element LD to generate light of a brightness corresponding to the data signal.

[0058] FIG. 3 is a plan view showing an embodiment of the display panel of FIG.

[0059] 3, the embodiment of the display panel 110 (DP) of FIG. 1 may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0060] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0061] When the display panel DP is used as a display screen for a head-mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP may be located very close to the user's eyes. In such cases, a relatively high degree of integration of the sub-pixels SP is required. To increase the integration of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the silicon substrate SUB. A display device 100 (see FIG. 1 ) including the display panel DP formed on the silicon substrate SUB may be called an OLEDoS (OLED on Silicon) display device.

[0062] The sub-pixels SP are arranged in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a penta-tile pattern. TM (PENTILE TM The first direction DR1 may be the row direction, and the second direction DR2 may be the column direction.

[0063] Two or more sub-pixels among the plurality of sub-pixels SP can form one pixel PXL.

[0064] Components for controlling the sub-pixels SP may be arranged in the non-display area NDA on the substrate SUB. For example, wirings connected to the sub-pixels SP, such as the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn in FIG. 1, may be arranged in the non-display area NDA.

[0065] At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 of FIG. 1 may be integrated into the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 of FIG. 1 is implemented in the display panel DP but may be disposed in the non-display area NDA. In another embodiment, the gate driver 120 may be realized as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 may be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0066] Pads PD are disposed in the non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP via wiring. For example, the pads PD may be connected to the sub-pixels SP via first to n-th data lines DL1 to DLn.

[0067] The pads PD may interface the display panel DP with other components of the display device 100 (see FIG. 1). In this embodiment, voltages and signals required for operation of the components included in the display panel DP may be provided from the driver integrated circuit DIC of FIG. 1 via the pads PD. For example, the first to n-th data lines DL1 to DLn may be connected to the driver integrated circuit DIC via the pads PD. For example, the first and second power supply voltages VDD and VSS may be received from the driver integrated circuit DIC via the pads PD. For example, if the gate driver 120 is implemented in the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 via the pads PD.

[0068] In one embodiment, a circuit board may be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film. A driver integrated circuit (DIC) may be mounted on the circuit board and electrically connected to the pads PD.

[0069] In an embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including straight and / or curved sides. For example, the display area DA can have a polygonal, circular, semicircular, elliptical, or other shape.

[0070] In some embodiments, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have an at least partially round (curved) display surface. In some embodiments, the display panel DP may be bendable, foldable, or rollable. In such cases, the display panel DP and / or the substrate SUB may comprise a material having flexible properties.

[0071] Figure 4 is an exploded perspective view showing a portion of the display panel of Figure 3. For clarity and simplicity of explanation, Figure 4 shows only a schematic representation of the portion of the display panel DP corresponding to two of the pixels PXL1 and PXL2 of Figure 3. The portions of the display panel DP corresponding to the remaining pixels can be similarly configured.

[0072] 3 and 4, each of the first and second pixels PXL1 and PXL2 may include first to third sub-pixels SP1, SP2, and SP3. However, embodiments are not limited thereto. For example, each of the first and second pixels PXL1 and PXL2 may include four sub-pixels or two sub-pixels.

[0073] 4, the first to third sub-pixels SP1, SP2, and SP3 are shown as having a rectangular shape and the same size when viewed in a third direction DR3 that intersects with the first and second directions DR1 and DR2. However, the embodiment is not limited thereto. The first to third sub-pixels SP1, SP2, and SP3 may be modified to have various shapes.

[0074] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a sealing layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0075] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. In another embodiment, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0076] A pixel circuit layer PCL is disposed on a substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern disposed between the insulating layers. The conductive pattern of the pixel circuit layer PCL may function as at least a part of a circuit element, wiring, etc. The conductive pattern may include copper, although examples are not limited thereto.

[0077] The circuit elements may include subpixel circuits SPC (see FIG. 2) for the first to third subpixels SP1, SP2, and SP3, respectively. The subpixel circuits SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. In an embodiment, if the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, if the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other in a plane defined by the first and second directions DR1 and DR2. For example, each capacitor may include electrodes spaced apart from each other in the third direction DR3 with an insulating layer sandwiched therebetween.

[0078] The wirings of the pixel circuit layer PCL may include signal lines, such as gate lines, emission control lines, and data lines, connected to the first to third sub-pixels SP1, SP2, and SP3, respectively. The wirings may further include a wiring connected to the first power supply voltage node VDDN of FIG. 2. The wirings may also include a wiring connected to the second power supply voltage node VSSN of FIG. 2.

[0079] The light-emitting element layer LDL can include an anode electrode AE, a pixel-defining film PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0080] The anode electrode AE ​​may be disposed on the pixel circuit layer PCL. The anode electrode AE ​​may be in contact with a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material that can reflect light, but the embodiment is not limited thereto.

[0081] A pixel definition film PDL is disposed on the anode electrode AE. The pixel definition film PDL may include second openings OP2 that expose portions of the anode electrode AE. The second openings OP2 of the pixel definition film PDL can be understood as light-emitting regions corresponding to the first to third sub-pixels SP1 to SP3, respectively.

[0082] In some embodiments, the pixel defining layer PDL may include an inorganic material. In such cases, the pixel defining layer PDL may include multiple stacked inorganic layers. For example, the pixel defining layer PDL may include silicon oxide (SiOx) and silicon nitride (SiNx). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0083] The light emitting structure EMS may be disposed on the anode electrode AE ​​exposed by the second opening OP2 of the pixel defining film PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0084] In an embodiment, the light emitting structure EMS may fill the second opening OP2 of the pixel defining film PDL and be entirely disposed above the pixel defining film PDL. That is, the light emitting structure EMS may extend over the first to third subpixels SP1 to SP3. In such a case, at least a portion of the layers in the light emitting structure EMS may be interrupted or folded (winding in the stacking cross section) at the boundaries between the first to third subpixels SP1 to SP3. However, the embodiment is not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first to third subpixels SP1 to SP3 may be separated from each other, and each of them may be disposed within the second opening OP2 of the pixel defining film PDL.

[0085] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first to third sub-pixels SP1 to SP3. In this manner, the cathode electrode CE may serve as a common electrode for the first to third sub-pixels SP1 to SP3.

[0086] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material so as to have a relatively thin thickness. In some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials, such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0087] Any one of the anode electrodes AE, a portion of the light emitting structure EMS overlapping it, and a portion of the cathode electrode CE overlapping it can be understood to constitute one light emitting element LD (see FIG. 2). That is, each of the light emitting elements of the first to third subpixels SP1 to SP3 may include one anode electrode, a portion of the light emitting structure EMS overlapping it, and a portion of the cathode electrode CE overlapping it. In each of the first to third subpixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported into the light emitting layer of the light emitting structure EMS to form excitons. Light can be generated when the excitons transition from an excited state to a ground state. The brightness of the light can be determined depending on the amount of current flowing through the light emitting layer. The wavelength range of the generated light can be determined depending on the configuration of the light emitting layer.

[0088] An encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In an embodiment, the encapsulation layer TFE can include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic film can include silicon nitride, silicon oxide, silicon oxynitride (SiOxNy), or the like. For example, the organic film may include organic insulating materials such as acrylic resin (including methacrylic resins), epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic and inorganic films of the encapsulation layer TFE are not limited to these.

[0089] To improve the sealing efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include a thin film containing aluminum oxide (AlOx). The thin film containing aluminum oxide may be located on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL. For example, the thickness of the thin film containing aluminum oxide may be 300 to 800 Å.

[0090] The thin film including aluminum oxide may be formed by atomic layer deposition (ALD). However, embodiments are not limited thereto. The encapsulation layer TFE may further include a thin film formed from at least one of various materials suitable for improving encapsulation efficiency.

[0091] The optical function layer OFL is disposed on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0092] The color filter layer CFL is disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter light emitted from the light emitting structures EMS to selectively output light of a wavelength range or color corresponding to each subpixel. The color filter layer CFL includes color filters CF corresponding to the first to third subpixels SP1 to SP3, respectively, and each of these color filters CF can transmit light of the wavelength range corresponding to the subpixel. For example, the color filter corresponding to the first subpixel SP1 can transmit red light, the color filter corresponding to the second subpixel SP2 can transmit green light, and the color filter corresponding to the third subpixel SP3 can transmit blue light. Depending on the light emitted from the light emitting structures EMS of each subpixel, at least some of the color filters CF may be omitted.

[0093] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may improve light output efficiency by outputting light emitted from the light emitting structure EMS to an intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not limited thereto.

[0094] In this embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first and second directions DR1 and DR2 relative to the second opening OP2 of the pixel defining film PDL. Specifically, in the central region of the display area DA, the centers of the color filters and the lenses may be aligned with or overlap with the centers of the second opening OP2 of the pixel defining film PDL when viewed from the third direction DR3. For example, in the central region of the display area DA, the second opening OP2 of the pixel defining film PDL may completely overlap with the color filters of the color filter layer CFL and the lenses of the lens array LA. In a region of the display area DA adjacent to the non-display area NDA, the centers of the color filters and the lenses may be shifted in a planar direction from the center of the second opening OP2 of the pixel defining film PDL when viewed from the third direction DR3. For example, in a region of the display area DA adjacent to the non-display area NDA, the second opening OP2 of the pixel definition layer PDL can partially overlap with a corresponding color filter of the color filter layer CFL and a corresponding lens of the lens array LA. This allows light emitted from the light emitting structure EMS at the center of the display area DA to be efficiently output in a direction normal to the display surface. At the periphery of the display area DA, light emitted from the light emitting structure EMS can be efficiently output in a direction inclined at a predetermined angle with respect to the normal to the display surface.

[0095] The overcoat layer OC may be disposed on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the underlying layers from foreign substances such as dust and moisture. For example, the overcoat layer OC may include at least one of an inorganic insulating film and an organic insulating film. For example, the overcoat layer OC may include epoxy, but examples are not limited thereto. The overcoat layer OC may have a lower refractive index than the lens array LA.

[0096] A cover window CW may be disposed on the overcoat layer OC. The cover window CW is configured to protect layers underneath it. The cover window CW may have a higher refractive index than the overcoat layer OC. The cover window CW may include glass, but examples are not limited thereto. For example, the cover window CW may be encapsulation glass configured to protect components underneath it. In other embodiments, the cover window CW may be omitted.

[0097] Figure 5 is a plan view showing an embodiment of any one of the pixels of Figure 4. For clarity and simplicity, Figure 5 only shows a first pixel PXL1 of the first and second pixels PXL1 and PXL2 of Figure 4. The remaining pixels may be configured similarly to the first pixel PXL1.

[0098] 4 and 5, the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0099] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0100] The first light-emitting region EMA1 may be a region where light is emitted from a portion of the light-emitting structure EMS (see FIG. 4) corresponding to the first sub-pixel SP1. The second light-emitting region EMA2 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 may be a region where light is emitted from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As described with reference to FIG. 4, each light-emitting region can be understood as a second opening OP2 in the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3.

[0101] FIG. 6 is a cross-sectional view taken along line II' in FIG.

[0102] Referring to FIG. 6, a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB are provided.

[0103] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0104] A pixel circuit layer PCL is disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for the first to third subpixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 for the first subpixel SP1, a transistor T_SP2 for the second subpixel SP2, and a transistor T_SP3 for the third subpixel SP3. The transistor T_SP1 for the first subpixel SP1 may be one of the transistors included in the subpixel circuit SPC for the first subpixel SP1 (see FIG. 2 ), the transistor T_SP2 for the second subpixel SP2 may be one of the transistors included in the subpixel circuit SPC for the second subpixel SP2, and the transistor T_SP3 for the third subpixel SP3 may be one of the transistors included in the subpixel circuit SPC for the third subpixel SP3. For clarity and conciseness, FIG. 6 shows only one of the transistors for each subpixel, and omits the remaining circuit elements.

[0105] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0106] The source region SRA and the drain region DRA may be disposed in a substrate SUB. A well WL formed through an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be disposed spaced apart from each other in the well WL. A region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0107] The gate electrode GE may be disposed in the pixel circuit layer PCL, overlapping the channel region between the source region SRA and the drain region DRA. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0108] The pixel circuit layer PCL may include a plurality of layers including an insulating layer and a conductive pattern disposed between the insulating layers, and the conductive pattern may include first and second conductive patterns CP1 and CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connector DRC that penetrates one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connector SRC that penetrates one or more insulating layers.

[0109] The gate electrode GE and the first and second conductive patterns CP1 and CP2 may be connected to other circuit elements and / or wirings, so that the transistor T_SP1 of the first sub-pixel SP1 may be provided as one of the transistors of the first sub-pixel SP1.

[0110] The transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can each be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0111] In this way, the substrate SUB and the pixel circuit layer PCL can include the circuit elements of each of the first to third sub-pixels SP1 to SP3.

[0112] A via layer VIAL is disposed on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and may have a generally flat surface. The via layer VIAL is configured to flatten steps on the pixel circuit layer PCL. The via layer VIAL may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon carbon nitride (SiCN), but examples are not limited thereto.

[0113] The light-emitting element layer LDL is disposed on the via layer VIAL. The light-emitting element layer LDL can include first to third reflective electrodes RE1 to RE3, an identification layer DDL, first to third anode electrodes AE1 to AE3, a pixel defining film PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0114] First to third reflective electrodes RE1 to RE3 are disposed on the via layer VIAL for the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 can be in contact with a circuit element disposed in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0115] The first to third reflective electrodes RE1 to RE3 may function as full mirrors that reflect light emitted from the light emitting structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. In one embodiment, the first to third reflective electrodes RE1 to RE3 may be formed as a multilayer structure of titanium nitride (TiN), aluminum (Al), and titanium (Ti). In this case, the thickness of titanium nitride (TiN) may be 35 to 150 Å, the thickness of aluminum (Al) may be 250 to 1350 Å, and the thickness of titanium (Ti) may be 50 to 150 Å. The materials of the first to third reflective electrodes RE1 to RE3 are not limited to these.

[0116] In an embodiment, a connecting electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode may improve electrical connection characteristics between the corresponding reflective electrode and circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multi-layer structure. The multi-layer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but is not limited thereto. In an embodiment, the reflective electrode may be located between multiple layers of connecting electrodes.

[0117] An identification layer DDL is disposed on the first to third reflective electrodes RE1 to RE3 and the via layer VIAL. The identification layer DDL may be formed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3 along the bends of the via layer VIAL and the first to third reflective electrodes RE1 to RE3. That is, the identification layer DDL may be formed along the bends without a planarization process. This eliminates the need for a planarization process for the identification layer DDL during the manufacturing process of the display device, thereby simplifying the manufacturing process of the display device. The identification layer DDL may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon carbonitride (SiCN). For example, the thickness of the identification layer DDL may be 150 to 3000 Å. However, the material of the identification layer DDL is not limited thereto.

[0118] The first to third reflective electrodes RE1 to RE3 may function as full mirrors, and the cathode electrode CE may function as a half mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS may be amplified by at least partially traveling back and forth between the corresponding reflective electrodes and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE may be understood as a resonance distance for the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0119] Since the light reflected from the first to third reflective electrodes RE1 to RE3 resonates, it is necessary to adjust the distance between the first to third reflective electrodes RE1 to RE3 and the cathode electrode CE (i.e., the resonance distance). The resonance distance can be adjusted by the identification layer DDL. For example, by disposing the identification layer DDL between the first reflective electrode RE1 and the cathode electrode CE, the distance between the first reflective electrode RE1 and the cathode electrode CE can be adjusted.

[0120] In one embodiment, at least two of the first to third sub-pixels SP1 to SP3 may have different resonance distances, which will be described in detail below with reference to Figures 7 and 8. The adjusted resonance distances may allow light to be amplified effectively and efficiently.

[0121] The discrimination layer DDL may include a first opening OP1 exposing at least a portion of each of the first to third reflective electrodes RE1 to RE3. The first to third anode electrodes AE1 to AE3 may be disposed on the first opening OP1 and the discrimination layer DDL. The first to third anode electrodes AE1 to AE3 may have shapes similar to the first to third light-emitting regions EMA1 to EMA3 of FIG. 5 when viewed from the third direction DR3. The first to third anode electrodes AE1 to AE3 may be in direct contact with (i.e., connected to) the first to third reflective electrodes RE1 to RE3 through the first opening OP1. This omits the process of forming vias to connect the first to third anode electrodes AE1 to AE3 to the first to third reflective electrodes RE1 to RE3, thereby simplifying the manufacturing process of the display device.

[0122] In an embodiment, the first to third anode electrodes AE1 to AE3 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). For example, the first to third anode electrodes AE1 to AE3 may have a thickness of 50 to 450 Å. However, the material of the first to third anode electrodes AE1 to AE3 is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0123] A pixel definition film PDL is disposed on a portion of the first to third anode electrodes AE1 to AE3 and the discrimination layer DDL. The pixel definition film PDL may include a second opening OP2 that exposes a portion of each of the first to third anode electrodes AE1 to AE3. The second opening OP2 of the pixel definition film PDL can define the light-emitting regions of the first to third sub-pixels SP1 to SP3. In this way, the pixel definition film PDL is disposed in the non-light-emitting region NEA in FIG. 5 and can define the first to third light-emitting regions EMA1 to EMA3 in FIG. 5.

[0124] In one embodiment, the pixel definition film PDL may be disposed on a region where the first to third anode electrodes AE1 to AE3 are in direct contact with the corresponding first to third reflective electrodes RE1 to RE3, respectively. That is, the pixel definition film PDL may be disposed above the first opening OP1.

[0125] In an embodiment, the pixel definition film PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx). For example, the pixel definition film PDL may include first to third inorganic insulating layers stacked in sequence, and the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. For example, the thickness of the pixel definition film PDL may be less than 450 Å. However, the material of the pixel definition film PDL is not limited thereto. The first to third inorganic insulating layers may have a stepped cross section in a region adjacent to the second opening OP2.

[0126] In this embodiment, the pixel definition film PDL is configured with a plurality of layers, but the present invention is not limited to this. For example, the pixel definition film PDL may be configured with a single layer.

[0127] A separator SPR may be provided in the boundary region BDA between adjacent sub-pixels, in other words, a separator SPR may be provided in each of the boundary regions between the sub-pixels SP in FIG.

[0128] The separator SPR may cause a discontinuity to be formed in the light emitting structure EMS at the boundary region BDA. For example, the separator SPR may cause the light emitting structure EMS to be interrupted or folded (torn in the laminate cross section) at the boundary region BDA.

[0129] The separator SPR may be provided in or on the pixel defining film PDL. The pixel defining film PDL may include one or more trenches TRCH1, TRCH2 as separators SPR in the boundary region BDA. In an embodiment, as shown in FIG. 6, one or more trenches TRCH1, TRCH2 may penetrate the pixel defining film PDL and the identification layer DDL and partially penetrate the via layer VIAL. In another embodiment, one or more trenches TRCH1, TRCH2 may penetrate the pixel defining film PDL and partially penetrate the identification layer DDL. In another embodiment, one or more trenches TRCH1, TRCH2 may at least partially penetrate the identification layer DDL and / or the via layer VIAL, and a portion of the pixel defining film PDL may be disposed within one or more trenches TRCH1, TRCH2.

[0130] 6 shows two trenches TRCH1 and TRCH2 provided in the boundary region BDA. However, the embodiment is not limited thereto. For example, the pixel defining layer PDL may include one trench in the boundary region BDA. Alternatively, the pixel defining layer PDL may include three or more trenches in the boundary region BDA.

[0131] The first and second trenches TRCH1 and TRCH2 may form discontinuous portions, such as a first void VD1 and a second void VD2, in the light emitting structure EMS in the boundary region BDA. Some of the layers stacked in the light emitting structure EMS may be interrupted or folded by the first and second voids VD1 and VD2. For example, at least one charge generation layer included in the light emitting structure EMS may be interrupted by the first and second voids VD1 and VD2. Thus, the first and second trenches TRCH1 and TRCH2 may at least partially separate portions of the light emitting structure EMS included in the first to third sub-pixels SP1 to SP3. The first and second trenches TRCH1 and TRCH2 may have a width in the first direction DR1 of 300 to 1500 Å and a height in the third direction DR3 of 1000 to 8000 Å.

[0132] 6, the first and second voids VD1 and VD2 are shown to be formed in the light emitting structure EMS at the boundary region BDA, but this is merely an example and the embodiment is not limited thereto. For example, a concave valley may be formed in the light emitting structure EMS at the boundary region BDA. The discontinuities formed in the light emitting structure EMS may be variously changed depending on the shapes of the first and second trenches TRCH1 and TRCH2.

[0133] In the embodiment, the light emitting structure EMS may be formed through a process such as vacuum deposition, inkjet printing, etc. In this case, the same material as the light emitting structure EMS may be located on the bottom surface adjacent to the via layer VIAL in the first and second trenches TRCH1 and TRCH2.

[0134] The separator SPR may be provided in various modifications so that the light emitting structure EMS has a discontinuous portion in the boundary region BDA. In some embodiments, an inorganic insulating pattern may be additionally stacked on the pixel defining layer PDL in the boundary region BDA without the first and second trenches TRCH1 and TRCH2. The width of the uppermost inorganic insulating pattern among the additionally stacked inorganic insulating patterns may be greater than the width of the inorganic insulating pattern disposed immediately below it. For example, in the boundary region BDA, first to third inorganic insulating patterns may be sequentially stacked on the pixel defining layer PDL, and the uppermost third inorganic insulating pattern may have a width greater than that of the second inorganic insulating pattern. For example, the pixel defining layer PDL may have a "T"-shaped or "I"-shaped cross section in the boundary region BDA. Depending on the shape of the pixel defining layer PDL, the layers included in the light emitting structure EMS may be at least partially interrupted or folded in the boundary region BDA.

[0135] The light emitting structure EMS may be disposed on the first to third anode electrodes AE1 to AE3 exposed through the second opening OP2 of the pixel defining layer PDL. The light emitting structure EMS may fill the second opening OP2 of the pixel defining layer PDL and be disposed entirely across the first to third subpixels SP1 to SP3. As described above, the light emitting structure EMS may be at least partially interrupted or folded in the boundary region BDA by the separator SPR. This may reduce current flowing from each of the first to third subpixels SP1 to SP3 to its adjacent subpixel through layers included in the light emitting structure EMS during operation of the display panel DP. Therefore, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability. For example, the thickness of the light emitting structure EMS may be 2000 to 9000 Å.

[0136] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may be provided commonly to the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the light emitting structure EMS.

[0137] The first anode electrode AE1, a portion of the light emitting structure EMS overlapping the first anode electrode AE1, and a portion of the cathode electrode CE overlapping the first anode electrode AE1 may constitute a first light emitting element LD1. The second anode electrode AE2, a portion of the light emitting structure EMS overlapping the second anode electrode AE2, and a portion of the cathode electrode CE overlapping the second anode electrode AE2 may constitute a second light emitting element LD2. The third anode electrode AE3, a portion of the light emitting structure EMS overlapping the third anode electrode AE3, and a portion of the cathode electrode CE overlapping the third anode electrode AE3 may constitute a third light emitting element LD3.

[0138] An encapsulation layer TFE is disposed on the cathode electrode CE. The encapsulation layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In one embodiment, the encapsulation layer TFE can include at least one of silicon nitride (SiNx) and a monomer-based material. In one embodiment, the encapsulation layer TFE can be formed as a multi-layer (stacked film) of silicon nitride (SiNx) / monomer-based material / silicon nitride (SiNx). In this case, the thickness of the silicon nitride (SiNx) can be 4000 to 10000 Å, and the thickness of the monomer-based material can be 0.5 to 4.5 μm. However, the material of the encapsulation layer TFE is not limited thereto, and the encapsulation layer TFE does not necessarily have to be formed as a multi-layer.

[0139] An optically functional layer OFL is disposed on the encapsulation layer TFE. In an embodiment, the optically functional layer OFL can be attached to the encapsulation layer TFE via an adhesive layer APL. For example, the optically functional layer OFL can be manufactured separately and attached to the encapsulation layer TFE via an adhesive layer APL. The adhesive layer APL can further perform the function of protecting underlying layers, including the encapsulation layer TFE.

[0140] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may transmit light of different wavelength ranges. For example, the first to third color filters CF1 to CF3 may transmit red, green, and blue light, respectively. For example, the thickness of the first to third color filters CF1 to CF3 may be 6,000 to 22,000 Å.

[0141] In one embodiment, the first to third color filters CF1 to CF3 may partially overlap each other in the border area BDA. In another embodiment, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0142] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. For example, the first to third lenses LS1 to LS3 may have a thickness of 10,000 to 30,000 Å. The first to third lenses LS1 to LS3 can improve light output efficiency by outputting the light emitted from the first to third light-emitting elements LD1 to LD3, respectively, along intended paths.

[0143] FIG. 7 is a table showing examples of thicknesses of the discrimination layer in FIG. 6, and FIG. 8 is a cross-sectional view showing CASE 6 in FIG.

[0144] For ease of explanation, Figure 8 omits components other than the via layer VIAL, the first to third reflective electrodes RE1 to RE3, the first and second discrimination layers DDL1, DDL2, the pixel defining film PDL, the first to third anode electrodes AE1 to AE3, the light-emitting structure EMS, and the cathode electrode CE.

[0145] 7 and 8, the discrimination layers DDL formed on the portions PP of the first to third reflective electrodes RE1 to RE3 may have different thicknesses in at least two of the first to third sub-pixels SP1 to SP3. The resonance distances of the sub-pixels SP1 to SP3 may be different. Therefore, it is necessary to adjust the resonance distances of the sub-pixels SP1 to SP3 by varying the thickness of the discrimination layers DDL for each of the sub-pixels SP1 to SP3. The thicknesses of the discrimination layers DDL formed on the portions PP of the first to third reflective electrodes RE1 to RE3 can be determined experimentally.

[0146] For example, in CASE 1, the identification layer DDL formed on the portion PP of the first reflective electrode RE1 may be 0 Å thick, the identification layer DDL formed on the portion PP of the second reflective electrode RE2 may be 200 Å thick, and the identification layer DDL formed on the portion PP of the third reflective electrode RE3 may be 200 Å thick. For example, in CASE 2, the identification layer DDL formed on the portion PP of the first reflective electrode RE1 may be 200 Å thick, the identification layer DDL formed on the portion PP of the second reflective electrode RE2 may be 0 Å thick, and the identification layer DDL formed on the portion PP of the third reflective electrode RE3 may be 200 Å thick. For example, in CASE 3, the identification layer DDL formed on the portion PP of the first reflective electrode RE1 may be 200 Å thick, the identification layer DDL formed on the portion PP of the second reflective electrode RE2 may be 200 Å thick, and the identification layer DDL formed on the portion PP of the third reflective electrode RE3 may be 0 Å thick. For example, in CASE 4, the identification layer DDL formed on the portion PP of the first reflective electrode RE1 may be 0 Å thick, the identification layer DDL formed on the portion PP of the second reflective electrode RE2 may be 200 Å thick, and the identification layer DDL formed on the portion PP of the third reflective electrode RE3 may be 400 Å thick. For example, in CASE 5, the identification layer DDL formed on the portion PP of the first reflective electrode RE1 may be 200 Å thick, the identification layer DDL formed on the portion PP of the second reflective electrode RE2 may be 0 Å thick, and the identification layer DDL formed on the portion PP of the third reflective electrode RE3 may be 400 Å thick. For example, in CASE 6, the identification layer DDL formed on the portion PP of the first reflective electrode RE1 may be 400 Å thick, the identification layer DDL formed on the portion PP of the second reflective electrode RE2 may be 600 Å thick, and the identification layer DDL formed on the portion PP of the third reflective electrode RE3 may be 0 Å thick.

[0147] Here, when the discrimination layer DDL is not disposed, the thickness of the discrimination layer DDL is set to 0 Å.

[0148] In this embodiment, six cases are illustrated, but the present invention is not limited to these six cases.

[0149] In one embodiment, the identification layer DDL can include a first identification layer DDL1 and a second identification layer DDL2. The first identification layer DDL1 and the second identification layer DDL2 can be selectively disposed on the portion PP of each of the first to third reflective electrodes RE1 to RE3. For example, depending on the resonance distance, the first to third reflective electrodes RE1 to RE3 may have none of the first identification layer DDL1 and the second identification layer DDL2 disposed on the portion PP, only the first identification layer DDL1 disposed, only the second identification layer DDL2 disposed, or all of the first identification layer DDL1 and the second identification layer DDL2 disposed.

[0150] For example, as shown in Figure 8 (i.e., CASE 6), assume that the thickness of the first identification layer DDL1 is 200 Å and the thickness of the second identification layer DDL2 is 400 Å. In this case, the second identification layer DDL2 is disposed on the portion PP of the first reflective electrode RE1, the first identification layer DDL1 and the second identification layer DDL2 are disposed on the portion PP of the second reflective electrode RE2, and the first identification layer DDL1 and the second identification layer DDL2 are not disposed on the portion PP of the third reflective electrode RE3.

[0151] FIG. 9 is a cross-sectional view showing an embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG.

[0152] 9, the light emitting structure EMS may have a light emitting portion EU. The light emitting structure EMS may be configured substantially identically in each of the first to third light emitting elements LD1 to LD3 of FIG.

[0153] The light-emitting portion EU may include at least one light-emitting portion EU that generates light in response to an applied current. The light-emitting portion EU may include an emitting layer EML, an electron transporting portion ETU, and a hole transporting portion HTU. The emitting layer EML may be disposed between the electron transporting portion ETU and the hole transporting portion HTU.

[0154] Each of the hole transport units HTU can include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc., as necessary.

[0155] Each of the electron transport units ETU can include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, and the like, as necessary.

[0156] The emitting layer EML can generate white light. For example, the emitting layer EML can include a stacked structure of a first sub-emitting layer configured to generate light of a first color and a second sub-emitting layer configured to generate light of a second color. The first color light and the second color light can be mixed to generate white light or light of a color close to white light. In such a case, an intermediate layer configured to transport holes and / or block electron transport can be further disposed between the first and second sub-emitting layers. However, the present invention is not limited to the method by which the emitting layer EML generates white light, and is not limited to white light.

[0157] The light emitting structure EMS may be formed by a method such as vacuum deposition or inkjet printing, but the embodiment is not limited thereto.

[0158] FIG. 10 is a cross-sectional view showing another embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG.

[0159] 10, the light emitting structure EMS′ may have a tandem structure in which first and second light emitting units EU1 and EU2 are stacked. The light emitting structure EMS′ may be substantially identical to each of the first to third light emitting devices LD1 to LD3 of FIG.

[0160] Each of the first and second light-emitting units EU1 and EU2 may include at least one light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0161] Each of the first and second hole transport units HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first and second hole transport units HTU1 and HTU2 may have the same structure or different structures.

[0162] Each of the first and second electron transport units ETU1 and ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first and second electron transport units ETU1 and ETU2 may have the same configuration as each other or different configurations.

[0163] A connection layer, which may be provided in the form of a charge generation layer CGL, may be disposed between the first light-emitting portion EU1 and the second light-emitting portion EU1 and connect them to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, embodiments are not limited thereto.

[0164] In an embodiment, the first and second light-emitting layers EML1 and EML2 can generate light of different colors. The light emitted from the first and second light-emitting layers EML1 and EML2 can be mixed and viewed as white light. For example, the first light-emitting layer EML1 can generate blue light, and the second light-emitting layer EML2 can generate yellow light. In an embodiment, the second light-emitting layer EML2 can include a stacked structure in which a first sub-light-emitting layer configured to generate red light and a second sub-light-emitting layer configured to generate green light are stacked. The red and green lights can be mixed to provide yellow light. In such a case, an intermediate layer configured to transport holes and / or block electron transport can be further disposed between the first and second sub-light-emitting layers.

[0165] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 may generate light of the same color.

[0166] FIG. 11 is a cross-sectional view showing still another embodiment of a light emitting structure included in any one of the first to third light emitting devices of FIG.

[0167] Referring to FIG. 11, the light emitting structure EMS'' may have a tandem structure in which the first to third light emitting units EU1' to EU3' are stacked. The light emitting structure EMS'' may be configured to be substantially the same for each of the first to third light emitting elements LD1 to LD3 of FIG. 6.

[0168] Each of the first to third light-emitting units EU1' to EU3' may include a light-emitting layer that generates light in response to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be disposed between the third electron-transporting unit ETU3' and the third hole-transporting unit HTU3'.

[0169] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc. The first to third hole transport units HTU1' to HTU3' may have the same structure or different structures.

[0170] Each of the first to third electron transport units ETU1' to ETU3' can include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first to third electron transport units ETU1' to ETU3' can have the same structure or different structures.

[0171] The first charge generation layer CGL1' is disposed between the first light emitting unit EU1' and the second light emitting unit EU2'. The second charge generation layer CGL2' is disposed between the second light emitting unit EU2' and the third light emitting unit EU3'.

[0172] In this embodiment, the first to third light emitting layers EML1' to EML3' may generate light of different colors. The light emitted from the first to third light emitting layers EML1' to EML3' may be mixed and perceived as white light. For example, the first light emitting layer EML1' may generate blue light, the second light emitting layer EML2' may generate green light, and the third light emitting layer EML3' may generate red light.

[0173] In other embodiments, two or more of the first to third light emitting layers EML1' to EML3' may generate light of the same color.

[0174] In one embodiment, unlike those shown in FIGS. 9 to 11, the light emitting structure EMS of FIG. 6 may include one light emitting portion in each of the first to third light emitting elements LD1 to LD3, and the light emitting portions included in the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the light emitting portion of the first light emitting element LD1 may emit red light, the light emitting portion of the second light emitting element LD2 may emit green light, and the light emitting portion of the third light emitting element LD3 may emit blue light. In this case, unlike that shown in FIG. 6, the light emitting portions of the first to third sub-pixels SP1 to SP3 may be separated from each other, and each may be disposed within the second opening OP2 of the pixel defining layer PDL. In this case, at least some of the color filters CF1 to CF3 may be omitted.

[0175] FIG. 12 is a plan view showing another embodiment of any one of the pixels of FIG.

[0176] Referring to FIG. 12, the first pixel PXL1' may include first to third sub-pixels SP1' to SP3'.

[0177] The first sub-pixel SP1' may include a first light-emitting region EMA1' and a non-light-emitting region NEA' surrounding the first light-emitting region EMA1'. The second sub-pixel SP2' may include a second light-emitting region EMA2' and a non-light-emitting region NEA' surrounding the second light-emitting region EMA2'. The third sub-pixel SP3' may include a third light-emitting region EMA3' and a non-light-emitting region NEA' surrounding the third light-emitting region EMA3'.

[0178] The first sub-pixel SP1' and the second sub-pixel SP2' may be arranged in the second direction DR2. The third sub-pixel SP3' may be arranged in the first direction DR1 relative to the first and second sub-pixels SP1' and SP2'.

[0179] The second sub-pixel SP2' may have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' may have a larger area than the second sub-pixel SP2'. Thus, the second light-emitting region EMA2' may have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' may have a larger area than the second light-emitting region EMA2'. However, embodiments are not limited thereto. For example, the first and second sub-pixels SP1', SP2' may have substantially the same area, and the third sub-pixel SP3' may have a larger area than the first and second sub-pixels SP1', SP2'. As such, the areas of the first to third sub-pixels SP1', SP3' may be variously modified depending on embodiments.

[0180] FIG. 13 is a plan view showing yet another embodiment of any one of the pixels of FIG.

[0181] Referring to FIG. 13, the first subpixel SP1″ may include a first light-emitting region EMA1″ and a non-light-emitting region NEA″ around the first light-emitting region EMA1″. The second subpixel SP2″ may include a second light-emitting region EMA2″ and a non-light-emitting region NEA″ around the second light-emitting region EMA2″. The third subpixel SP3″ may include a third light-emitting region EMA3″ and a non-light-emitting region NEA″ around the third light-emitting region EMA3″.

[0182] The first to third sub-pixels SP1" to SP3" may have a polygonal shape when viewed in the third direction DR3. For example, the first to third sub-pixels SP1" to SP3" may have a hexagonal shape as shown in FIG.

[0183] The first to third light-emitting regions EMA1'' to EMA3'' may have a circular shape when viewed from the third direction DR3. However, the embodiment is not limited thereto. For example, each of the first to third light-emitting regions EMA1'' to EMA3'' may have a polygonal shape.

[0184] The first and third sub-pixels SP1″ and SP3″ may be arranged in a first direction DR1. The second sub-pixel SP2″ may be arranged in a direction inclined at an acute angle (or diagonal direction) with respect to the first sub-pixel SP1″ based on the second direction DR2.

[0185] The sub-pixel arrangements shown in Figures 5, 12, and 13 are exemplary and not limiting examples. Each pixel includes two or more sub-pixels, and the sub-pixels can be arranged in various ways, each of the sub-pixels can have various shapes, and each of its light-emitting areas can also have various shapes.

[0186] 14 to 16 are cross-sectional views showing examples of the shape of the first lens of FIG.

[0187] For convenience of explanation, FIGS. 14 to 16 show only the first lens LS1, and the second and third lenses LS2 and LS3 (see FIG. 6) can also have substantially the same shape as the first lens LS1.

[0188] 14 to 16 show the cross-sectional shape of the first lens LS1 cut in the third direction DR3 (see FIG. 6). The shape of the first lens LS1 seen from the third direction DR3 (see FIG. 6) may be substantially the same as the light-emitting regions EMA1, EMA1', EMA1'', EMA2, EMA2', EMA2'', EMA3, EMA3', and EMA3'' described with reference to FIGS. 5, 12, and 13.

[0189] 14, the first lens LS1 may have a trapezoidal shape. For example, the width of the first lens LS1 may become narrower in the third direction DR3.

[0190] 15, the first lens LS1' may have a semicircular shape, for example, the first lens LS1' may have a shape of a lens convex in the third direction DR3.

[0191] 16, the first lens LS1″ may have a trapezoidal shape with the corners rounded off. For example, the corners of the first lens LS1″ may be rounded off from the trapezoidal shape so that the width of the first lens LS1″ becomes narrower in the third direction DR3.

[0192] FIG. 17 is a cross-sectional view showing a part of the first to third sub-pixels of the display device according to the embodiment of the present invention.

[0193] For ease of explanation, Figure 17 omits components other than the via layer VIAL, the first to third reflective electrodes RE1 to RE3, the discrimination layer DDL, the pixel definition film PDL, the first to third anode electrodes AE1 to AE3, the sacrificial layer VL, the light-emitting structure EMS, and the cathode electrode CE.

[0194] The display device according to this embodiment has substantially the same configuration as the display device of FIG. 6, except for the sacrificial layer VL, so the same reference numbers and symbols are used for the same or similar components, and duplicate explanations will be omitted.

[0195] 17, the display device may further include a sacrificial layer VL disposed between the first to third anode electrodes AE1 to AE3 and the pixel definition film PDL. The sacrificial layer VL is disposed on the first to third anode electrodes AE1 to AE3 and can protect the first to third anode electrodes AE1 to AE3. For example, without the sacrificial layer VL, the first to third anode electrodes AE1 to AE3 may be unintentionally etched during etching of the pixel definition film PDL. However, by disposing the sacrificial layer VL, even if the pixel definition film PDL is unintentionally over-etched during etching, the sacrificial layer VL may be etched instead of the first to third anode electrodes AE1 to AE3.

[0196] The sacrificial layer VL may include at least one of conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and aluminum (Al). For example, the thickness of the sacrificial layer VL may be 150 to 400 Å. However, the material of the sacrificial layer VL is not limited thereto.

[0197] In one embodiment, the sacrificial layer VL may have an undercut structure between the first to third anode electrodes AE1 to AE3 and the pixel definition film PDL. For example, the sacrificial layer VL may have an undercut structure recessed in the first direction DR1 or in the direction opposite to the first direction DR1 between the first to third anode electrodes AE1 to AE3 and the pixel definition film PDL.

[0198] FIG. 18 is a flowchart showing a method for manufacturing a display device according to an embodiment of the present invention.

[0199] Referring to FIG. 18, a method for manufacturing a display device may include providing a substrate (S100), forming a via layer on the substrate (S200), forming a reflective electrode on the via layer (S300), forming an identification layer (S400) so that the identification layer covers the via layer and the reflective electrode along the curvature of the via layer and the reflective electrode, etching the identification layer DDL to expose at least a portion of the reflective electrode (S500), and forming an anode electrode on the identification layer (S600).

[0200] 19 is a diagram showing the step S200 in FIG. 18, FIG. 20 is a diagram showing the step S300 in FIG. 18, FIG. 21 is a diagram showing the step S400 in FIG. 18, FIG. 22 is a diagram showing the step S500 in FIG. 18, and FIG. 23 is a diagram showing the step S600 in FIG. 18.

[0201] For convenience of explanation, FIGS. 19 to 23 show only the first subpixel SP1, and the second and third subpixels SP2 and SP3 (see FIG. 6) can also be manufactured in substantially the same manner as the first subpixel SP1.

[0202] 19, the method for manufacturing a display device can form a via layer VIAL on a substrate. The via layer VIAL can be formed on a pixel circuit layer PCL (see FIG. 6). The via layer VIAL has been described in detail above, so a duplicated description will be omitted.

[0203] 20, the method for manufacturing a display device may form a first reflective electrode RE1 on the via layer VIAL. The specific description of the reflective electrode including the first reflective electrode RE1 has been given above, so a duplicated description will be omitted.

[0204] 21, the method for manufacturing a display device may form the discrimination layer DDL along the bends of the via layer VIAL and the first reflective electrode RE1 so that the discrimination layer DDL covers the via layer VIAL and the first reflective electrode RE1. That is, the discrimination layer DDL may be formed along the bends without a separate planarization process.

[0205] 22, the method for manufacturing a display device may include etching the identification layer DDL to expose at least a portion of the first reflective electrode RE1. That is, the identification layer DDL may include a first opening OP1 that exposes at least a portion of the first reflective electrode RE1.

[0206] 23, the first anode electrode AE1 may be formed on the identification layer DDL. Specifically, the first anode electrode AE1 may be formed on at least a portion of the region of the identification layer DDL that overlaps with the first reflective electrode RE1 and on the first opening OP1. This allows the first anode electrode AE1 to be in direct contact with the first reflective electrode RE1.

[0207] 24 to 28 are diagrams showing a process of forming a first identification layer and a second identification layer according to a manufacturing method of a display device according to an embodiment of the present invention.

[0208] For convenience of explanation, FIGS. 24 to 28 show the process of forming the first identification layer DDL1 and the second identification layer DDL2 according to CASE 6 in FIG.

[0209] Referring to Figures 24 to 28, the thickness of the discrimination layer (i.e., the sum of the thicknesses of the first and second discrimination layers DDL1, DDL2) formed on a portion PP of the reflective electrode (i.e., the first to third reflective electrodes RE1 to RE3) may be different from each other in at least two of the first to third sub-pixels SP1 to SP3.

[0210] 24 and 25, the first discrimination layer DDL1 may be formed on the first to third reflective electrodes RE1 to RE3. The first discrimination layer DDL1 on the first reflective electrode RE1 and the third reflective electrode RE3 may be etched to expose a portion PP of each of the first reflective electrode RE1 and the third reflective electrode RE3.

[0211] 26, the second identification layer DDL2 may be formed on a portion PP of each of the first reflective electrode RE1 and the third reflective electrode RE3. The second identification layer DDL2 may be formed on the first identification layer DDL1 formed on the second reflective electrode RE2.

[0212] 27, the second identification layer DDL2 may be etched to expose a portion PP of the third reflective electrode RE3, so that the identification layer formed on the portion PP of the first reflective electrode RE1 may have a thickness of 400 Å, the identification layer formed on the portion PP of the second reflective electrode RE2 may have a thickness of 600 Å, and the identification layer formed on the portion PP of the third reflective electrode RE3 may have a thickness of 0 Å.

[0213] 28, the second identification layer DDL2 of the first subpixel SP1 may be etched to form a first opening OP1 that exposes at least a portion of the first reflective electrode RE1. The first identification layer DDL1 and the second identification layer DDL2 of the second subpixel SP2 may be etched to form a first opening OP1 that exposes at least a portion of the second reflective electrode RE2. The second identification layer DDL2 of the third subpixel SP3 may be etched to form a first opening OP1 that exposes at least a portion of the third reflective electrode RE3.

[0214] 29 to 31 are diagrams illustrating a process of forming a sacrificial layer according to a method of manufacturing a display device according to an embodiment of the present invention.

[0215] The display device according to this embodiment is substantially identical in configuration to the manufacturing method of the display device in Figure 18, except for the sacrificial layer VL, so the same reference numbers and symbols are used for the same or similar components, and duplicate explanations are omitted.

[0216] For convenience of explanation, FIGS. 29 to 31 show only the first subpixel SP1, and the second and third subpixels SP2 and SP3 (see FIG. 6) can also be manufactured in substantially the same manner as the first subpixel SP1.

[0217] 29, a sacrificial layer VL may be formed on the first anode electrode AE1. The sacrificial layer VL has been described in detail above, and therefore, a duplicated description will be omitted.

[0218] 30, a pixel definition film PDL including a second opening OP2 exposing at least a portion of the sacrificial layer VL may be formed on the sacrificial layer VL. The specific description of the pixel definition film PDL has been given above, so a duplicated description will be omitted.

[0219] 31, the sacrificial layer VL may be etched to expose at least a portion of the first anode electrode AE1. For example, the sacrificial layer VL may be wet-etched. This may cause the sacrificial layer VL to have an undercut structure between the first anode electrode AE1 and the pixel defining layer PDL.

[0220] FIG. 32 is a block diagram illustrating an embodiment of a display system.

[0221] Referring to FIG. 32, a display system 1000 may include a processor 1100 and one or more display devices 1210, 1220.

[0222] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 can include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be coupled to and control other components of the display system 1000 via a bus system.

[0223] 32, the display system 1000 is shown as including first and second display devices 1210, 1220. The processor 1100 may be coupled to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0224] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be configured similarly to the display device 100 described with reference to FIG. 1. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0225] Through the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be configured similarly to the display device 100 described with reference to FIG. 1. In such a case, the second image data IMG2 and the second control signal CTRL2 can be provided as the input image data IMG and the control signal CTRL, respectively, of FIG. 1.

[0226] The display system 1000 may include a computing system that provides a video display function, such as a portable computer, a mobile phone, a smartphone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system 1000 may also include at least one of a head mounted display device (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0227] FIG. 33 is a perspective view showing an application example of the display system of FIG.

[0228] 33, the display system 1000 of FIG. 32 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0229] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device housing case 2200. The head-mounted band 2100 may be connected to the display device housing case 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band may be configured to surround the sides of the user's head, and the vertical band may be configured to surround the top of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band 2100 may be realized in the form of a glasses frame, a helmet, or the like.

[0230] The display device housing case 2200 can house the first and second display devices 1210 and 1220 of Fig. 32. The display device housing case 2200 can further house the processor 1100 of Fig. 32.

[0231] FIG. 34 shows the head-mounted display device worn by the user of FIG.

[0232] 34, a first display panel DP1 of the first display device 1210 and a second display panel DP2 of the second display device 1220 are arranged in a head-mounted display device 2000. The head-mounted display device 2000 may further include one or more lenses LLNS, RLNS.

[0233] Within the display device housing 2200, the right eye lens RLNS can be disposed between the first display panel DP1 and the user's right eye, and the left eye lens LLNS can be disposed between the second display panel DP2 and the user's left eye.

[0234] The image output from the first display panel DP1 can be viewed by the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 to direct it toward the user's right eye. The right eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0235] The image output from the second display panel DP2 can be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 to direct it toward the user's left eye. The left eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0236] In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS may include an optical lens having a pancake-shaped cross section. In an embodiment, each of the right eye lens RLNS and the left eye lens LLNS may include a multi-channel lens including sub-regions having different optical properties. In this case, each display panel outputs images corresponding to the sub-regions of the multi-channel lens, and the output images pass through the corresponding sub-regions to be viewed by a user.

[0237] Although specific embodiments and application examples have been described herein, these are merely provided to facilitate a more comprehensive understanding of the present invention, and the present invention is not limited to the above-described embodiments. Those skilled in the art will appreciate that various modifications and variations can be made from these descriptions.

[0238] Therefore, the concept of the present invention should not be limited to the described embodiments, and not only the scope of the claims below, but also all modifications that are equivalent or equivalent to the scope of the claims can be said to fall within the scope of the concept of the present invention. [Industrial Applicability]

[0239] The present invention can be applied to display devices and electronic devices including the same, such as digital TVs, 3D TVs, mobile phones, smartphones, tablet computers, VR devices, PCs, home electronic devices, laptops, PDAs, PMPs, digital cameras, music players, portable game consoles, and navigation systems.

[0240] Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention as defined in the following claims.

[0241] According to a preferred specific embodiment, it is as follows:

[0242] The background to this case is as follows (i) to (iv).

[0243] (i) Organic light-emitting display panels with an array of organic light-emitting diodes (OLEDs) are widely used in mobile devices such as smartphones, tablet PCs, and smartwatches. In particular, they are being considered for use in next-generation displays that require high resolution, such as eyeglass displays.

[0244] (ii) The realization of Virtual Reality (VR) or Augmented Reality (AR) using eyeglass-type displays or head-mounted displays is being considered. The display panel used for this is required to have a diagonal dimension of about 1 inch (for example, 2 to 3 cm or 1.5 to 4 cm) and a resolution of about 3000 dpi or more (for example, 2500 to 4000 dpi).

[0245] (iii) When manufacturing such high-resolution organic light-emitting display panels, it is difficult to paint each colored light-emitting layer using a fine mask. Therefore, it is considered to make all sub-pixel organic light-emitting elements (OLEDs) emit white light (White OLED) and to place a color filter of a specific color on each sub-pixel. In particular, to support high resolution, it is considered to use an organic light-emitting display device using a substrate such as a silicon wafer (OLEDoS; OLED on Silicon).

[0246] (iv) For such high-resolution silicon-based organic light-emitting displays (OLEDoS), it is necessary to improve light utilization efficiency, manufacturing efficiency, etc., as well as product reliability.

[0247] Therefore, according to a particularly preferred embodiment, any combination of A1 to A6 or A1 to A11 below is used.

[0248] For each A1 sub-pixel, first to third reflective electrodes (RE1 to RE3) are arranged as full mirrors that direct light toward the light exit surface. As a specific example, the first to third reflective electrodes (RE1 to RE3) are three-layer films of titanium nitride (TiN) / aluminum (Al) / titanium (Ti), which have high reflectivity and durability.

[0249] A2 First to third anode electrodes (AE1 to AE3) made of a transparent conductive material (ITO, IZO, IGZO, ITZO or titanium nitride) are superimposed on the first to third reflective electrodes (RE1 to RE3).

[0250] A3 The upper surfaces of the first to third anode electrodes (AE1 to AE3) are covered with a light-emitting structure (EMS) including a light-emitting layer, etc., and a common electrode (cathode electrode CE) is disposed on the upper surface of the light-emitting structure, extending over the entire display surface or over a large number of pixels. The common electrode (cathode electrode CE) extends flatly without any irregularities or height differences.

[0251] A4 The distances from the first to third reflective electrodes (RE1 to RE3) to the common electrode (cathode electrode CE) are set so that optical resonance occurs and the light is amplified.

[0252] A5 When the pixel electrode for each subpixel is formed from a reflective electrode (RE1 to RE3) and a transparent anode electrode (AE1 to AE3) above it, an insulating spacer layer (identification layer DDL) is sandwiched between them. This spacer insulating layer (identification layer DDL) can be formed from silicon oxide (SiOx), silicon nitride (SiNx), silicon carbon nitride (SiCN), etc.

[0253] This insulating layer for the spacer (identification layer DDL) is sandwiched between the reflective electrodes (RE1 to RE3) and the anode electrodes (AE1 to AE3) except for the openings (OP1 to OP3) that connect the reflective electrodes (RE1 to RE3) and the anode electrodes (AE1 to AE3), and covers the areas surrounding the reflective electrodes (RE1 to RE3). As a result, the upper surfaces of the anode electrodes AE1 to AE3 are relatively flat, and it is not necessary to dispose a separate flattening film or perform a flattening process for the insulating film in the light emitting structure EMS.

[0254] A6 A pixel defining layer (PDL) and its opening are arranged on the bottom surface of the light emitting structure (EMS) so as to expose the region (PP) where the reflective electrodes (RE1 to RE3) and the anode electrodes (AE1 to AE3) are superimposed with an insulating layer (identification layer DDL) for spacers sandwiched therebetween.

[0255] A7: The thickness of the spacer insulating layer (identification layer DDL) can be made different between subpixels of different colors. To achieve this, multiple patterns of spacer insulating layers (identification layers DDL1, DDL2) can be appropriately overlapped (see Figure 8 of the present application).

[0256] A8 When etching the pixel defining layer (PDL) to form predetermined openings, a sacrificial layer (VL) can be disposed to cover the anode electrodes (AE1 to AE3) at the opening formation locations to prevent the anode electrodes (AE1 to AE3) from being etched (Fig. 17 of the present application).

[0257] A9 In the lower part of the light-emitting structure (EMS), including the light-emitting layer, a separator (SPR) is arranged to surround or appropriately divide the area of ​​each sub-pixel in order to prevent lateral leakage current between the sub-pixels. The separator (SPR) can be formed by voids (VD1, VD2) formed by trenches (TRCH1, TRCH2), or the like.

[0258] A10 A flat common electrode (cathode electrode CE) is covered with a sealing layer (TFE) made of an organic-inorganic laminated film, and on top of this sealing layer (TFE) an optical function layer (OFL) made of a microlens (lens array LA) for each subpixel and a color filter layer (CFL) is arranged, sandwiching an adhesive layer (APL).

[0259] A11: A pixel circuit layer having a CMOS (complementary metal-oxide semiconductor) structure or the like is provided in the display area on a substrate (SUB) made of a silicon wafer. [Explanation of symbols]

[0260] 100, 1210, 1220 display device 110 Display panel 120 Gate Drivers 130 Data Driver 140 Voltage Generator 150 Controller 160 Temperature Sensor 1000 Display System 1100 processor 2000 Head-mounted display device 2100 Headband 2200 Display device storage case

Claims

1. A substrate; a first insulating layer disposed on the substrate; a first electrode disposed on the first insulating layer; a second insulating layer formed on the first insulating layer and the first electrode along the bends of the first insulating layer and the first electrode; a second electrode formed on the second insulating layer; a light emitting structure disposed on the second electrode; a third electrode disposed on the light emitting structure.

2. the second insulating layer includes a first opening that exposes at least a portion of the first electrode; The display device of claim 1 , wherein the second electrode is in direct contact with the first electrode.

3. a third insulating layer including a second opening exposing at least a portion of the second electrode; The display device according to claim 2 , wherein the third insulating layer is disposed on a region of the second electrode that is in direct contact with the first electrode.

4. the substrate includes a display region in which first to third sub-pixels are arranged; The display device of claim 1 , wherein the thickness of the second insulating layer formed on the portion of the first electrode is different from each other in at least two of the first to third sub-pixels.

5. the second insulating layer includes a 2-1 insulating layer and a 2-2 insulating layer; 5. The display device according to claim 4, wherein the second-first insulating layer and the second-second insulating layer are selectively disposed on the portion of the first electrode.

6. a third insulating layer including a second opening exposing at least a portion of the second electrode; The display device of claim 1 , further comprising a sacrificial layer disposed between the second electrode and the third insulating layer.

7. The display device according to claim 6, wherein the sacrificial layer includes a conductive material.

8. 7. The display device according to claim 6, wherein the sacrificial layer has an under-cut structure between the second electrode and the third insulating layer.

9. The display device of claim 1 , wherein the light emitting structure outputs white light.

10. A substrate; a first insulating layer disposed on the substrate; a first electrode disposed on the first insulating layer; a second insulating layer formed on the first insulating layer and the first electrode and in direct contact with the first electrode; a second electrode formed on the second insulating layer; a light emitting structure disposed on the second electrode; a third electrode disposed on the light emitting structure.

11. a third insulating layer including a second opening exposing at least a portion of the second electrode; The display device according to claim 10, wherein the third insulating layer is disposed on a region of the second electrode that is in direct contact with the first electrode.

12. the substrate includes a display region in which first to third sub-pixels are arranged; 11. The display device of claim 10, wherein the thickness of the second insulating layer formed on the portion of the first electrode is different from each other in at least two of the first to third sub-pixels.

13. the second insulating layer includes a 2-1 insulating layer and a 2-2 insulating layer; 13. The display device according to claim 12, wherein the second-first insulating layer and the second-second insulating layer are selectively disposed on the portion of the first electrode.

14. a third insulating layer including a second opening exposing at least a portion of the second electrode; The display device of claim 10, further comprising: a sacrificial layer disposed between the second electrode and the third insulating layer.

15. The display device of claim 14, wherein the sacrificial layer includes a conductive material.

16. 15. The display device according to claim 14, wherein the sacrificial layer has an under-cut structure between the second electrode and the third insulating layer.

17. The display device of claim 10, wherein the light emitting structure outputs white light.

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