High-frequency semiconductor switch circuit

Abstract

To provide a high-frequency semiconductor switch circuit capable of reducing a pass loss without deteriorating a high isolation characteristic and a withstand voltage characteristic.SOLUTION: The high-frequency semiconductor switch circuit is provided with: a first switch device 100 in which high-frequency path switches 11 and 14 using FETs are connected in series is provided between a high-frequency input / output common terminal 3 and a high-frequency input / output individual terminal 1; and a first switch device 200 in which high-frequency path switches 21 and 24 using the FETs are connected in series is provided between the high-frequency input / output common terminal 3 and the high-frequency input / output individual terminal 2. In the high-frequency semiconductor switch circuit, a pass loss can be reduced without deteriorating a high isolation characteristic and a withstand voltage characteristic by using the FETs having a smaller performance index than other high-frequency path switches, with a RonCoff product, which is a product of an ON resistance Ron of the high-frequency path switches 14 and 24 connected to the high-frequency input / output individual terminals 1 and 2 and an OFF capacitance Coff of the switch, as a performance index.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a high frequency semiconductor switch circuit for switching high frequency signals, and more particularly to a circuit that reduces insertion loss without deteriorating isolation characteristics and withstand voltage characteristics. [Background technology]

[0002] As this type of high frequency semiconductor switch circuit, for example, one having a configuration as shown in FIG. 9 is known (see, for example, Patent Document 1). Such a conventional circuit will be described below with reference to FIG. This conventional circuit has one high frequency input / output common terminal 3X and two high frequency input / output individual terminals 1X and 2X, and is configured such that a first switch device 100X is provided between the high frequency input / output common terminal 3X and one of the high frequency input / output individual terminals 1X, and a second switch device 200X is provided between the high frequency input / output common terminal 3X and the other high frequency input / output individual terminal 2X.

[0003] The first and second switch devices 100X, 200X basically have the same configuration, and the first switch device 100X is configured with high-frequency path switches 11X, 12X connected in series and a high-frequency shunt switch 13X as its main components. The second switch device 200X is configured with high-frequency path switches 21X and 22X connected in series and a high-frequency shunt switch 23X as its main components. In this conventional example, field effect transistors (hereinafter referred to as "FETs" for convenience of explanation) are used for the high frequency path switches 11X, 12X, 21X, and 22X and the high frequency shunt switches 13X and 23X.

[0004] As will be described below, this conventional circuit is configured such that, depending on the control signals input to the two control signal input terminals 4X and 5X, one of the two high-frequency input / output individual terminals 1X and 2X is connected to the high-frequency input / output common terminal 3X via the first or second switch device 100X or 200X, thereby allowing the passage of high-frequency signals. Next, the operation of this conventional circuit will be described. Here, as an example, an operation will be described in which a high frequency signal input to the high frequency input / output individual terminal 1X is output to the high frequency input / output common terminal 3X.

[0005] First, a required control signal is input to one control signal input terminal 4X so as to bring the two high-frequency path switches 11X and 12X and the high-frequency shunt switch 23X into a conductive state. Furthermore, a required control signal is input to the other control signal input terminal 5X so as to bring the high-frequency shunt switch 13X and the two high-frequency path switches 21X and 22X into a cut-off state.

[0006] Here, a high-frequency switch in the on state (conducting state) generally generates losses and can be interpreted as a resistive element having an on-resistance Ron, and a high-frequency switch in the off state (cutoff state) generates leakage of high-frequency signals and can be interpreted as a capacitive element having an off-capacitance Coff. Therefore, the circuit shown in FIG. 9 in the above-mentioned operating state can be represented by the equivalent circuit shown in FIG. 10.

[0007] In FIG. 10, R11X represents the on-resistance of the high-frequency path switch 11X in the on-state, R12X represents the on-resistance of the high-frequency path switch 12X in the on-state, and R23X represents the on-resistance of the high-frequency shunt switch 23X in the on-state. In FIG. 10, C21X represents the off capacitance of the high-frequency path switch 21X in the off state, C22X represents the off capacitance of the high-frequency path switch 22X in the off state, and C13X represents the off capacitance of the high-frequency shunt switch 13X in the off state.

[0008] Thus, the high frequency signal input to the high frequency input / output individual terminal 1X is transmitted to the high frequency input / output common terminal 3X via the resistors R11X and R12X. The high-frequency signal that reaches the high-frequency input / output common terminal 3X attempts to leak to the high-frequency input / output individual terminal 2X via capacitor C21X. However, because the junction between capacitors C21X and C22X is held at ground potential by resistor R23X, most of the high-frequency signal attempting to leak is reflected back to the high-frequency input / output common terminal 3X, and only a small portion of the high-frequency signal reaches the high-frequency input / output individual terminal 2X via capacitor C22X.

[0009] In this way, when a high-frequency signal input to the high-frequency input / output individual terminal 1X is output from the high-frequency input / output common terminal 3X, a high level of isolation is ensured between one high-frequency input / output individual terminal 1X and the other high-frequency input / output individual terminal 2X by the resistor R23X provided by the high-frequency shunt switch 23X and the capacitor C22X provided by the high-frequency pass switch 22X.

[0010] Next, the operation when the voltage amplitude VRF of the input high frequency signal is large will be described below. In this case, a high frequency signal with a voltage amplitude VRF is applied between the terminals of the capacitor C13X and the capacitor C21X. Here, the capacitor C13X is an equivalent replacement for the high-frequency shunt switch 13X in the off state, so if the above-mentioned voltage amplitude VRF is equal to or less than the breakdown voltage Vbk of the switch FET, the high-frequency shunt switch 13X can maintain operation in the off state.

[0011] In the conventional circuit shown in FIG. 9, the high-frequency shunt switch 13X uses one FET, but in general, m (m is an integer equal to or greater than 1) FETs are connected in series and the voltage amplitude VRF of the high-frequency signal is divided among the m FETs. Therefore, in general, the high-frequency shunt switch 13X can operate up to a voltage amplitude that satisfies the following formula A:

[0012] VRF≦Vbk×m...Formula A

[0013] Furthermore, since the capacitor C21X is an equivalent replacement for the high-frequency path switch 21X in the off state, if the above-mentioned voltage amplitude VRF is equal to or less than the breakdown voltage Vbk of the switch FET, the high-frequency path switch 21X can maintain operation in the off state. In the conventional circuit shown in FIG. 9, the high-frequency path switch 21X uses one FET, but like the above-described high-frequency shunt switch 13X, it is generally configured to connect k FETs (k is an integer of 1 or more) in series and divide the voltage amplitude VRF of the high-frequency signal among the k FETs, and therefore can generally operate up to a voltage amplitude that satisfies the following formula B.

[0014] VRF≦Vbk×k...Formula B

[0015] Therefore, the smaller the voltage amplitude VRF defined by equation A or equation B, the greater the maximum voltage amplitude (withstand voltage) of the high-frequency signal that can be handled by the entire circuit. In this way, the high frequency path switch 12X and the high frequency path switch 22X do not affect the above-mentioned withstand voltage. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] Patent No. 344126 [Non-patent literature]

[0017] [Non-Patent Document 1] F. Gianesellon, A. Fleury et al., "Advanced 200-mm RF SOI Technology exhibiting 79 fs RON×COFF and 3.7V breakdown voltage targeting sub 6 GHz 5G FEM", 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2022. [Non-patent document 2] Paul Hurwitz, Amol Kalburge et al., "Innovation in Specialty Silicon Techoligy for 5G Front-End Modules", [online], Microwave journal, March 12, 2020, [Retrieved January 30, 2020] <URL:https: / / www.microwavejournal.com / articles / 33614-innovation-in-specialty-silicon-technology-for-5g-front-end-modules> Summary of the Invention [Problem to be solved by the invention]

[0018] However, in the conventional circuit shown in FIG. 9, for example, when the high-frequency input / output common terminal 3X and the high-frequency input / output individual terminal 1X are brought into a conductive state, a pass loss occurs due to the on-resistance of the two switch elements, the high-frequency path switch 11X and the high-frequency path switch 12X, resulting in a problem of increased pass loss for the entire circuit. One possible solution to this problem is to increase the gate width of the FET to reduce the on-resistance, but increasing the gate width increases the off-capacitance, which creates a new problem of degraded isolation.

[0019] In general, there is a trade-off between the on-resistance Ron and the off-capacitance Coff of a high-frequency switch, and it is well known that the product of Ron and Coff, which focuses on this trade-off between the on-resistance Ron and the off-capacitance Coff, is used as the figure of merit (FoM) of the device. From this point of view, one possible solution to the above problem is to use a device with a small RonCoff product. However, as shown in Non-Patent Documents 1 and 2, there is a trade-off between the RonCoff product and the breakdown voltage. Therefore, using a device with a small RonCoff product leads to the problem of a decrease in the withstand voltage of high-frequency signals, as shown in the above-described Equations A and B. Therefore, it may be possible to improve the RonCoff product while maintaining the breakdown voltage by adopting a more advanced technology node process or improving characteristics using low-k materials, but this would result in a new trade-off with process costs and development time, and the current situation is such that a final solution to the problem has not yet been provided.

[0020] The present invention has been made in view of the above circumstances, and provides a high-frequency semiconductor switch circuit that enables reduction of insertion loss without deteriorating high isolation characteristics and withstand voltage characteristics. [Means for solving the problem]

[0021] In order to achieve the above object of the present invention, a high-frequency semiconductor switch circuit according to the present invention comprises: a high frequency input / output common terminal and one or more high frequency input / output individual terminals, the high frequency input / output common terminal and the high frequency input / output individual terminals being connected to each other via high frequency switch devices; at least one of the high frequency switch devices includes first and second high frequency path switch groups connected in series between the high frequency input / output common terminal and the high frequency input / output individual terminal, and a high frequency shunt switch group connected between a connection point between the first and second high frequency path switch groups and a ground node, the first high frequency path switch group is configured by m (m is an integer of 1 or more) switch devices connected in series, the second high frequency path switch group is configured by a series connection of n switch devices (n is an integer of 1 or more), The high-frequency shunt switch group is configured by k (k is an integer equal to or greater than 1) switch devices connected in series, In a high frequency semiconductor switch circuit configured such that the first high frequency path switch group is connected to the high frequency input / output common terminal, The switch devices constituting the second high frequency path switch group have characteristics different from the switch devices constituting the first high frequency path switch group and the high frequency shunt switch group, and when RonCoff, which is the product of the on resistance Ron of the switch device and the off capacitance Coff of the switch, is taken as a figure of merit, the switch devices constituting the second high frequency path switch group are set to have a smaller figure of merit than the respective switch devices constituting the first high frequency path switch group and the high frequency shunt switch group. [Effects of the Invention]

[0022] According to the present invention, by differentiating the characteristics of a specific switch device that constitutes a high-frequency semiconductor switch circuit from the characteristics of the other switch devices, it is possible to reduce insertion loss while maintaining the same isolation characteristics and withstand voltage characteristics as conventionally, and to provide a high-frequency semiconductor switch circuit with better characteristics than conventionally available ones. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a circuit diagram showing a first example of a circuit configuration of a high-frequency semiconductor switch circuit according to an embodiment of the present invention. [Figure 2] 2 is an equivalent circuit diagram of the high-frequency semiconductor switch circuit shown in FIG. 1 when the high-frequency input / output common terminal and one of the high-frequency input / output individual terminals are in a conductive state. FIG. [Figure 3]2 is a characteristic diagram showing the change characteristics of insertion loss with respect to input frequency in the first circuit configuration example shown in FIG. 1. FIG. [Figure 4] FIG. 4 is a characteristic diagram showing the change in isolation versus input frequency in the first circuit configuration example. [Figure 5] FIG. 4 is a circuit diagram showing a second example of a circuit configuration of the high-frequency semiconductor switch circuit in the embodiment of the present invention. [Figure 6] 6 is an equivalent circuit diagram when the high frequency input / output common terminal and one of the high frequency input / output individual terminals are in a conductive state in the high frequency semiconductor switch circuit shown in FIG. 5. FIG. [Figure 7] FIG. 10 is a schematic diagram illustrating the influence of a body leakage current of an off switch in the second circuit configuration example. [Figure 8] FIG. 10 is a correlation diagram showing the correlation between body leakage current and a figure of merit. [Figure 9] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a conventional high-frequency semiconductor switch circuit. [Figure 10] 10 is an equivalent circuit diagram when the high frequency input / output common terminal and one of the high frequency input / output individual terminals in the conventional circuit shown in FIG. 9 are in a conductive state. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The components, arrangements, etc. described below do not limit the present invention, and various modifications can be made within the scope of the present invention. First, a first circuit configuration example of a high-frequency semiconductor switch circuit according to an embodiment of the present invention will be described with reference to FIG. The high frequency semiconductor switch circuit in the embodiment of the present invention has one high frequency input / output common terminal 3 and two high frequency input / output individual terminals 1 and 2, and is configured such that a first switch device 100 is provided between the high frequency input / output common terminal 3 and one of the high frequency input / output individual terminals 1, and a second switch device 200 is provided between the high frequency input / output common terminal 3 and the other high frequency input / output individual terminal 2.

[0025] As will be described in detail later, in this high-frequency semiconductor switch circuit, one of two high-frequency input / output individual terminals 1, 2 is connected to a high-frequency input / output common terminal 3 via a first or second switch device 100, 200 in response to a control signal input from the outside, thereby allowing a high-frequency signal to pass through.

[0026] The first and second switch devices 100, 200 in the embodiment of the present invention basically have the same configuration. For example, in FIG. 1, if an imaginary axis is imagined to pass through the high frequency input / output common terminal 3 in the vertical direction of the paper, the first and second switch devices 100, 200 have circuit configurations that are linearly symmetrical with respect to this imaginary axis. In the following description of the circuit configuration, the configuration of the first switch device 100 will be described, and this description will serve as a substitute for the description of the configuration of the second switch device 200. In the following description, the reference numerals of the components of the first switch device 100 will be followed by the reference numerals of the corresponding components of the second switch device 200, or the component name and reference numeral.

[0027] First, the first switch device 100 (200) is configured with first and second high-frequency path switches 11, 14 (21, 24) connected in series and a high-frequency shunt switch 13 (23) as main components. In the embodiment of the present invention, the first and second high-frequency path switches 11, 14 (21, 24) and the high-frequency shunt switch 13 (23) all use FETs as specific switch devices.

[0028] In the first switch device 100 (200), the source (or drain) of the first high-frequency path switch 11 (21) and the drain (or source) of the second high-frequency path switch 14 (24) are connected to each other, while the drain (or source) of the first high-frequency path switch 11 (21) is connected to the high-frequency input / output common terminal 3, and the source (or drain) of the second high-frequency path switch 14 (24) is connected to the high-frequency input / output individual terminal 1 (2). In addition, a first drain-source resistor 51 (61) is connected between the drain and source of the first high-frequency path switch 11 (21), and a second drain-source resistor 52 (62) is connected between the drain and source of the second high-frequency path switch 14 (24). Furthermore, the gate of the first high-frequency path switch 11 (21) is connected to the first control signal input terminal 4 (second control signal input terminal 5) via a first gate resistor 54 (64), and the gate of the second high-frequency path switch 14 (24) is connected to the first control signal input terminal 4 (second control signal input terminal 5) via a second gate resistor 55 (65).

[0029] On the other hand, the drain (or source) of the high-frequency shunt switch 13 (23) is connected to the above-mentioned mutual connection point of the high-frequency path switches 11, 14 (21, 24), while the source (or drain) is connected to a node (ground node) set to ground potential and is maintained at ground potential. A shunt drain-source resistor 53 (63) is connected between the drain and source of the high-frequency shunt switch 13 (23), while the gate is connected to the second control signal input terminal 5 (first control signal input terminal 4) via a shunt gate resistor 56 (66).

[0030] Here, the second high-frequency path switch 14 in the first switch device 100 has a lower withstand voltage and a smaller figure of merit than the first high-frequency path switch 11 and the high-frequency shunt switch 13, that is, an FET having a small RonCoff product, which is the product of the on-resistance Ron and the off-capacitance Coff, is used. Furthermore, the second high-frequency path switch 24 in the second switch device 200 has a lower breakdown voltage and a smaller figure of merit than the first high-frequency path switch 21 and the high-frequency shunt switch 23, that is, an FET having a small RonCoff product, which is the product of the on-resistance Ron and the off-capacitance Coff.

[0031] To configure the second high-frequency path switches 14, 24 with FETs that satisfy the above-mentioned conditions, for example, it is advisable to set the gate lengths of the second high-frequency path switches 14, 24 to be shorter than those of the first high-frequency path switches 11, 21 and the high-frequency shunt switches 13, 23. Another suitable method for reducing the RonCoff product of the second high frequency path switches 14 and 24 is to reduce the thickness of each gate oxide film. Furthermore, as another method for reducing the RonCoff product of the second high frequency path switches 14 and 24, it is also preferable to adjust the impurity concentration so as to obtain a desired RonCoff product.

[0032] Next, the circuit operation in the above configuration will be described. As an example of circuit operation, a case where a high frequency signal input to the high frequency input / output individual terminal 1 is output from the high frequency input / output common terminal 3 will be described. First, a required control signal is applied to the first control signal input terminal 4 to bring the first and second high-frequency path switches 11 and 14 and the high-frequency shunt switch 23 into a conductive state. On the other hand, a required control signal is applied to the second control signal input terminal 5 so as to put the high-frequency shunt switch 13 and the first and second high-frequency path switches 21 and 24 into a cut-off state.

[0033] Thus, the first and second high-frequency path switches 11 and 14 in the ON state can be replaced with resistors R11 and R14, respectively, and the high-frequency shunt switch 23 in the ON state can be replaced with resistor R23. On the other hand, the first and second high-frequency path switches 21 and 24 in the OFF state can be replaced with the capacitors C21 and C24, respectively, and the high-frequency shunt switch 13 in the OFF state can be replaced with the capacitor C13. As a result, the circuit shown in Figure 1 can be expressed as the equivalent circuit shown in Figure 2. In Figure 2, the notation "Low Ron" near resistor R14 means that the resistance value of resistor R14, which is the on-resistance as mentioned above, is lower than that of the FET in the conventional circuit. Thus, the high frequency signal input to the high frequency input / output individual terminal 1 reaches the high frequency input / output common terminal 3 via the resistors R14 and R11.

[0034] The high-frequency signal that reaches the high-frequency input / output common terminal 3 then attempts to leak via capacitor C21 to the high-frequency input / output individual terminal 2. However, because the connection point between capacitors C21 and C24 is maintained at ground potential via resistor R23, most of the high-frequency signal transmitted via capacitor C21 is reflected back to the high-frequency input / output common terminal 3, and only a small portion of the high-frequency signal leaks to the high-frequency input / output individual terminal 2 via capacitor C24.

[0035] 10, there is no change in the magnitude of the high-frequency signal that can leak to the high-frequency input / output individual terminal 2. Therefore, the isolation between the high-frequency input / output common terminal 3 and the high-frequency input / output individual terminal 2 is ensured to be as high as that of the conventional circuit. On the other hand, the second high frequency path switch 14 has a smaller RonCoff product, which is a figure of merit, than the high frequency path switch 12X in the conventional circuit that corresponds to this second high frequency path switch 14, so if Coff is the same as in the conventional circuit, the on resistance Ron will naturally be smaller than in the conventional circuit. Therefore, the total resistance value in the path through which the input high frequency signal passes becomes smaller, and the pass loss is improved.

[0036] Furthermore, if the voltage amplitude of the high frequency signal is VRF, a voltage with amplitude VRF is applied between the terminals of the capacitor C13 and the capacitor C21 (see FIG. 2). Here, the capacitor C13 is an equivalent replacement for the high-frequency shunt switch 13 in the off state, so if the above-mentioned voltage amplitude VRF is equal to or less than the breakdown voltage Vbk of the switch FET, the high-frequency shunt switch 13 can maintain operation in the off state. As explained in the conventional circuit (see FIG. 9), taking into consideration that a configuration in which m shunt switches are connected in series or a configuration in which k pass switches are connected in series is generally adopted, the relationship between the operating limit voltage of the FET for the amplitude VRF of the high-frequency signal and the breakdown voltage Vbk of the switch FET is expressed by Equation A and Equation B explained in the conventional circuit, but below they will be written again as Equation 1A and Equation 2A, respectively.

[0037] VRF≦Vbk×m...Formula 1A

[0038] VRF≦Vbk×k...Formula 2A

[0039] Therefore, the smaller the voltage amplitude VRF defined by Equation 1A or Equation 2A, the greater the maximum voltage amplitude (withstand voltage) of the high-frequency signal that can be handled by the entire circuit, and the operating limit voltage for the FET with amplitude VRF will be the same as that of the conventional circuit. FIG. 3 shows a characteristic diagram illustrating an example of the change in insertion loss versus input frequency in the first circuit configuration example described above, and FIG. 4 shows a characteristic diagram illustrating an example of the change in isolation versus input frequency in the first circuit configuration example, which will be described below.

[0040] First, in FIG. 3, the horizontal axis represents the frequency of the input high frequency signal, and the vertical axis represents the insertion loss. In FIG. 3, the solid characteristic line indicates the change characteristic of the insertion loss with respect to the frequency in the first circuit configuration example, and the dotted characteristic line indicates the same change characteristic in the conventional circuit (see FIG. 9). According to FIG. 3, it can be confirmed that the insertion loss in the first circuit configuration example is improved by approximately 0.02 dB compared to the conventional circuit.

[0041] Next, in FIG. 4, the horizontal axis represents the frequency of the input high frequency signal, and the vertical axis represents the isolation. In addition, in Figure 4, the solid characteristic line shows the change in isolation versus frequency in the first circuit configuration example, and the dotted characteristic line shows the same change in frequency in the conventional circuit (see Figure 9). The two characteristic lines show nearly identical characteristics, so they are almost overlapping in the figure. As described above, according to FIGS. 3 and 4, it can be seen that the high-frequency semiconductor switch circuit in the first circuit configuration example has improved insertion loss compared to the conventional circuit while maintaining the same isolation as the conventional circuit.

[0042] Thus, the high-frequency semiconductor switch circuit according to the embodiment of the present invention has smaller transmission loss than conventional circuits for high-frequency signals passing through the high-frequency input / output common terminal 3 and the high-frequency input / output individual terminals 1 and 2, while maintaining isolation characteristics and power resistance characteristics equivalent to those of conventional circuits. In the above-described configuration example, the first and second switch devices 100, 200 are controlled simultaneously by two control signals applied to the first and second control signal input terminals 4, 5, but they may also be controlled individually by providing a decoder circuit.

[0043] Next, a second circuit configuration example will be described with reference to FIG. The same components as those in the first circuit configuration example shown in FIG. 1 are given the same reference numerals, and detailed description thereof will be omitted. The following description will focus on the differences. In this second circuit configuration example, a first switch device 300 is provided between the high frequency input / output common terminal 3 and the high frequency input / output individual terminal 1, and a second switch device 400 is provided between the high frequency input / output common terminal 3 and the high frequency input / output individual terminal 2, and in response to a control signal applied from the outside, either one of the two high frequency input / output individual terminals 1, 2 is connected to the high frequency input / output common terminal 3 via the first or second switch device 300, 400, allowing high frequency signals to pass through. The basic configuration is the same as that of the first circuit configuration example described above.

[0044] The first and second switch devices 300, 400 differ from the first and second switch devices 100, 200 in the first circuit configuration example in that they are configured using a plurality of high-frequency path switches and a plurality of high-frequency shunt switches. The circuit configurations of the first and second switch devices 300, 400 will be specifically described below. First, the first and second switch devices 300, 400 in this second circuit configuration example have basically the same configuration, and like the first and second switch devices 100, 200 in the previous first circuit configuration example, have a circuit configuration that is linearly symmetrical with respect to a virtual axis passing through the high-frequency input / output common terminal 3.

[0045] That is, in FIG. 5, imagine an imaginary line connecting the high frequency input / output common terminal 3 and the high frequency input / output individual terminal 1, and move the second switch device 400 so that the high frequency input / output individual terminal 2 is positioned on a line that is imaginarily extended from the high frequency input / output common terminal 3 in the opposite direction to the high frequency input / output individual terminal 1, resulting in an arrangement as shown in FIG. Therefore, the first and second switch devices 300, 400 have circuit configurations that are symmetrical with respect to the imaginary line passing through the high frequency input / output common terminal 3 in the vertical direction of the paper in FIG.

[0046] In the following description of the circuit configuration, the configuration of the first switch device 300 will be described, and this description will serve as a substitute for the description of the configuration of the second switch device 400. In the following description, the reference numerals of the components of the first switch device 300 will be followed by the reference numerals of the corresponding components of the second switch device 400, or the component name and reference numeral, in parentheses.

[0047] First, the first switch device 300 (400) is configured with, as its main components, first and second high-frequency path switch groups 310, 320 (410, 420) connected in series between the high-frequency input / output common terminal 3 and the high-frequency input / output individual terminal 1 (2), and a high-frequency shunt switch group 330 (430) provided between the mutual connection point of these first and second high-frequency path switch groups 310, 320 (410, 420) and ground potential.

[0048] The first high-frequency path switch group 310 (410) is mainly composed of four series-connected high-frequency path switches 31a to 31d (41a to 41d) using FETs. The second high-frequency path switch group 320 (420) is mainly composed of two series-connected high-frequency path switches 31e and 31f (41e and 41f) using FETs.

[0049] In the first high frequency path switch group 310 (410), the source (or drain) of the high frequency path switch 31a (41a) is connected to the high frequency input / output common terminal 3, and the drain (or source) of the high frequency path switch 31d (41d) is connected to the connection point between the second high frequency path switch group 320 (420) and the high frequency shunt switch group 330 (430), which will be described later. The high frequency path switch 31b (41b) and the high frequency path switch 31c (41c) are connected in series between the drain (or source) of the high frequency path switch 31a (41a) and the source (or drain) of the high frequency path switch 31d (41d).

[0050] On the other hand, in the second high frequency path switch group 320 (420), the drain (or source) of the high frequency path switch 31e (41e) and the source (or drain) of the high frequency path switch 31f (41f) are connected to each other. The source (or drain) of the high frequency path switch 31e (41e) is connected to the connection point between the first high frequency path switch group 310 (410) and the high frequency shunt switch group 330 (430), and the drain (or source) of the high frequency path switch 31f (41f) is connected to the high frequency input / output individual terminal 1 (high frequency input / output individual terminal 2).

[0051] In addition, in the first high-frequency path switch group 310 (410), first to fourth drain-source resistors 71a to 71d (81a to 81d) for the switch group are connected between the drain and source of each of the high-frequency path switches 31a to 31d (41a to 41d), respectively. In the second high-frequency path switch group 320 (420), a fifth drain-source resistor 71e (81e) for the switch group and a sixth drain-source resistor 71f (81f) for the switch group are connected between the drain and source of each of the high-frequency path switches 31e, 31f (41e, 41f), respectively.

[0052] Furthermore, in the first high-frequency path switch group 310 (410), the bodies (back gates) of the high-frequency path switches 31a to 31d (41a to 41d) are connected to one terminal of a third control terminal first adjusting resistor 74a (fourth control terminal first adjusting resistor 84a) via first to fourth body resistors 73a to 73d (83a to 83d), respectively. The other end of this third control terminal first adjusting resistor 74a (fourth control terminal first adjusting resistor 84a) is connected to the third control signal input terminal 6 (fourth control signal input terminal 7).

[0053] Furthermore, in the second high-frequency path switch group 320 (420), the bodies (back gates) of the high-frequency path switches 31e, 31f (41e, 41f) are connected to one terminal of a third control terminal second adjustment resistor 74c (fourth control terminal second adjustment resistor 84c) via a fifth body resistor 73e (83e) and a sixth body resistor 73f (83f), respectively. The other end of this third control terminal second adjustment resistor 74c (fourth control terminal second adjustment resistor 84c) is connected to the third control signal input terminal 6 (fourth control signal input terminal 7).

[0054] Furthermore, in the first high-frequency path switch group 310 (410), the gates of the high-frequency path switches 31a to 31d (41a to 41d) are connected to one terminal of a first control terminal first adjusting resistor 74b (second control terminal first adjusting resistor 84b) via first to fourth switch group gate resistors 72a to 72d (82a to 82d), respectively. The other terminal of this first control terminal first adjusting resistor 74b (second control terminal first adjusting resistor 84b) is connected to the first control signal input terminal 4 (second control signal input terminal 5).

[0055] In the second high-frequency path switch group 320 (420), the gates of the high-frequency path switches 31e, 31f (41e, 41f) are connected to one terminal of a first control terminal second adjustment resistor 74d (second control terminal second adjustment resistor 84d) via a switch group fifth gate resistor 72e and a switch group sixth gate resistor 72f, respectively. The other terminal of this first control terminal second adjustment resistor 74d (second control terminal second adjustment resistor 84d) is connected to the first control signal input terminal 4 (second control signal input terminal 5).

[0056] On the other hand, the high-frequency shunt switch group 330 (430) is configured with four series-connected high-frequency shunt switches 32a to 32d (42a to 42d) using FETs as its main components. The high-frequency shunt switch group 330 (430) is provided so that the entire group is connected in series between the connection point of the first high-frequency path switch group 310 (410) and the second high-frequency path switch group 320 (420) and the ground potential. More specifically, first, the drain (or source) of the high-frequency shunt switch 32a (42a) is connected to the connection point between the drain (or source) of the high-frequency path switch 31d (41d) and the source (or drain) of the high-frequency path switch 31e (41e).

[0057] The source (or drain) of the high-frequency shunt switch 32d (42d) is maintained at the ground potential. The high-frequency shunt switch 32b (42b) and the high-frequency shunt switch 32c (42c) are connected in series between the source (or drain) of the high-frequency shunt switch 32a (42a) and the drain (or source) of the high-frequency shunt switch 32d (42d).

[0058] In addition, in the high-frequency shunt switch group 330 (430), first to fourth drain-source resistors 75a to 75d (85a to 85d) for the shunt group are connected between the drain and source of each of the high-frequency shunt switches 32a to 32d (42a to 42d), respectively. Furthermore, in the high-frequency shunt switch group 330 (430), the bodies (back gates) of the high-frequency shunt switches 32a to 32d (42a to 42d) are connected to one terminal of a third adjustment resistor 78a for the fourth control terminal (third adjustment resistor 88a for the third control terminal) via first to fourth body resistors 77a to 77d (87a to 87d) for the shunt group, respectively. The other terminal of the third adjustment resistor 78a for the fourth control terminal (third adjustment resistor 88a for the third control terminal) is connected to the fourth control signal input terminal 7 (third control signal input terminal 6).

[0059] Furthermore, in the high-frequency shunt switch group 330 (430), the gates of the high-frequency shunt switches 32a-32d (42a-42d) are connected to one terminal of a second control end third adjusting resistor 78b (first control terminal third adjusting resistor 88b) via first to fourth shunt group gate resistors 76a-76d (86a-86d), respectively. The other terminal of this second control end third adjusting resistor 78b (first control terminal third adjusting resistor 88b) is connected to the second control signal input terminal 5 (first control signal input terminal 4).

[0060] In this configuration, the operations of the first and second high-frequency path switch groups 310, 320 and the high-frequency shunt switch group 430 are controlled in response to control signals applied to the first control signal input terminal 4 and the third control signal input terminal 6, as will be described later. Furthermore, the operations of the first and second high-frequency path switch groups 410, 420 and the high-frequency shunt switch group 330 are controlled in response to control signals applied to the second control signal input terminal 5 and the fourth control signal input terminal 7, as will be described later.

[0061] The control signals applied to the first and third control signal input terminals 4, 6 and the control signals applied to the second and fourth control signal input terminals 5, 7 are set so that the operations of the first and second high-frequency path switch groups 310, 320 and the high-frequency shunt switch group 430 are opposite to the operations of the first and second high-frequency path switch groups 410, 420 and the high-frequency shunt switch group 330.

[0062] In the first switch device 300, the FETs used in the second high frequency path switch group 320 have a larger drain leakage current and a smaller figure of merit, i.e., RonCoff product, compared to the FETs used in the first high frequency path switch group 310 and the high frequency shunt switch group 330. Furthermore, in the second switch device 400, the FETs used in the second high frequency path switch group 420 have a larger drain leakage current and a smaller figure of merit, i.e., RonCoff product, than the FETs used in the first high frequency path switch group 410 and the high frequency shunt switch group 430.

[0063] Next, the circuit operation in the above configuration will be described. As an example of circuit operation, a case where a high frequency signal input to the high frequency input / output individual terminal 1 is output from the high frequency input / output common terminal 3 will be described. First, required control signals are applied to the first and third control signal input terminals 4 and 6 to bring the first and second high frequency path switch groups 310 and 320 and the high frequency shunt switch group 430 into a conductive state. On the other hand, required control signals are applied to the second and fourth control signal input terminals 5 and 7 to set the first and second high frequency path switch groups 410 and 420 and the high frequency shunt switch group 330 in the cutoff state.

[0064] Thus, the first and second high frequency path switch groups 310 and 320 in the ON state can be replaced with resistors R310 and R320, respectively, and the high frequency shunt switch group 430 in the ON state can be replaced with resistor R430. On the other hand, the first and second high frequency path switch groups 410, 420 in the OFF state can be replaced with capacitors C410 and C420, respectively, and the high frequency shunt switch group 330 in the OFF state can be replaced with capacitor C330. As a result, the circuit shown in FIG. 5 can be represented by the equivalent circuit shown in FIG.

[0065] Thus, the high frequency signal input to the high frequency input / output individual terminal 1 reaches the high frequency input / output common terminal 3 via the resistors R320 and R310 in the first and second high frequency path switch groups 320 and 310. Then, the high frequency signal that has reached the common high frequency input / output terminal 3 attempts to leak to the individual high frequency input / output terminal 2 via the off capacitance C410 of the high frequency path switch group 410.

[0066] However, since the connection point between the high frequency path switch group 410 and the high frequency path switch group 420 is at ground potential due to the on resistance R430 of the high frequency shunt switch group 430, most of the high frequency signals are reflected to the high frequency input / output common terminal 3, and only a small portion of the high frequency signals leak to the high frequency input / output individual terminal 2 via the off capacitance C420 of the high frequency path switch group 420. Here, for example, if the high frequency path switch group 420 is designed so that the off capacitance when configured using the same number of FETs as the FETs forming the high frequency path switch group 410 is the same as the above-mentioned off capacitance C420, there is no change in the magnitude of the high frequency signal that can leak to the high frequency input / output individual terminal 2. Therefore, even when the high frequency path switch group 420 is configured using two FETs as shown in Fig. 5, the isolation between the high frequency input / output common terminal 3 and the high frequency input / output individual terminal 2 is ensured to be as high as when the high frequency path switch group 420 is configured using the same number of FETs as the high frequency path switch group 410.

[0067] However, as described above, the FETs that make up the high frequency path switch group 420 have a smaller RonCoff product, which is a figure of merit, compared to the FETs that make up the high frequency path switch group 410, and therefore the on-resistance (equivalent to the on-resistance R430 described above, for example) is smaller, and the pass loss is improved. Furthermore, if the voltage amplitude of the high frequency signal is VRF, a voltage with amplitude VRF is applied between the terminals of the capacitor C330 and the capacitor C410 (see FIG. 6). In this case, the relationship between the voltage amplitude VRF and the withstand voltage of the FET can be expressed by Equation 1A and Equation 2A, as explained previously in the first circuit configuration example, and the operating limit voltage of the amplitude VRF for the FET is the same as in the conventional circuit.

[0068] On the other hand, when a switch is configured using a MOS FET or the like using SOI (Silicon On Insulator), the breakdown voltage is determined by factors other than Equations 1A and 2A, so the breakdown voltage in this case will be explained below. First, when a high-power radio-frequency signal VRF is input, a voltage corresponding to the radio-frequency signal is applied between the terminals of the radio-frequency shunt switch groups 330 and 430, respectively.

[0069] FIG. 7 is a schematic diagram illustrating the state of voltage application in the high-frequency shunt switch group 330. Hereinafter, the state of voltage application of high-frequency signals to shunt switches in the OFF state will be described with reference to this figure. First, for example, if the switch device is an N-type MOSFET on SOI, when the high-power high-frequency signal VRF described above is input, this signal is divided by the body-drain capacitance and body-source capacitance of each FET as shown in Figure 7. Here, if the switch group is configured by connecting k FETs of the same size in series (k=4 in this example), the voltage of the high frequency signal VRF is divided equally into 1 / 2k.

[0070] It is generally known that the drain-body-source structure of an N-type MOSFET is an NPN-type bipolar transistor structure, and therefore, even when a high-frequency signal voltage is applied, a body control voltage VBOFF (e.g., −2.5 V) is applied to prevent the above-mentioned bipolar transistor from turning on. However, when a high-frequency voltage is applied between the body and drain, a body leakage current (denoted as "ibleak" in Figure 7) occurs. This body leakage current flows through the body resistance RB, causing a voltage rise of ibleak×RB.

[0071] Here, if the resistor connected to the body terminal of each FET is RB2, and the resistor between this resistor RB2 and the fourth control signal input terminal 7 to which the body control voltage is applied is RB1 (see Figure 7), the body-source potential VBS can be expressed as in Equation 1 below.

[0072]

number

[0073] Here, if the threshold voltage of the parasitic bipolar transistor is VBS_ON, when the sum of the body-source potential VBS expressed in Equation 1 and the divided high-frequency signal voltage VRF / 2k exceeds VBS_ON, the parasitic bipolar transistor will turn on and the shunt switch will no longer be able to maintain its off state. Therefore, the maximum voltage amplitude (withstand voltage) of the high frequency signal that allows the switch circuit to operate can be expressed by the following equation 2.

[0074]

number

[0075] As a result, the smaller of the withstand voltage of the high-frequency signal calculated by the above-mentioned Equation 1A and Equation 2A and the withstand voltage of the high-frequency signal calculated by the above-mentioned Equation 2 becomes the withstand voltage (maximum voltage amplitude) that determines the withstand voltage characteristics of the switch circuit.

[0076] Incidentally, the relationship between the RonCoff product, which is a figure of merit for high-frequency switching FETs, and the body leakage current generally has a trade-off relationship, similar to the breakdown voltage, as shown in Figure 8. Therefore, configuring a circuit using only devices with a small RonCoff product will result in an increase in body leakage current, causing a problem of a decrease in breakdown voltage, as shown in Equation 2. In FIG. 8, the horizontal axis indicates the normalized RonCoff product, the vertical axis indicates the normalized body leakage current, and five examples of the body leakage current with respect to the RonCoff product are indicated by triangles.

[0077] In contrast to this, in the present invention, as explained above, FETs with a small figure of merit (RonCoff product) are used for the FETs that make up the high frequency path switch groups 320, 420, but the power handling capability is determined by the high frequency path switch groups 310, 410 and the high frequency shunt switch groups 330, 430. Therefore, even if FETs with large body leakage currents are used in some parts, the circuit as a whole maintains high voltage handling characteristics equivalent to those of conventional circuits, and moreover, achieves an improvement in passing loss compared to conventional circuits. [Industrial Applicability]

[0078] The present invention can be applied to high frequency semiconductor switch circuits where reduction of insertion loss is desired without deteriorating high isolation characteristics and withstand voltage characteristics. [Explanation of symbols]

[0079] 1...High frequency input / output individual terminals 2...High frequency input / output individual terminals 3...High frequency input / output common terminal 4...First control signal input terminal 5...Second control signal input terminal 6...Third control signal input terminal 7...Fourth control signal input terminal 11, 21...First high frequency pass switch 14, 24...Second high frequency pass switch 100, 300...First switch device 200, 400...Second switch device 310, 410...First high frequency path switch group 320, 420...Second high frequency path switch group 330, 430...High frequency shunt switches

Claims

1. a high frequency input / output common terminal and one or more high frequency input / output individual terminals, the high frequency input / output common terminal and the high frequency input / output individual terminals being connected to each other via high frequency switch devices; at least one of the high frequency switch devices includes first and second high frequency path switch groups connected in series between the high frequency input / output common terminal and the high frequency input / output individual terminal, and a high frequency shunt switch group connected between a connection point between the first and second high frequency path switch groups and a ground node, the first high frequency path switch group is configured by m (m is an integer of 1 or more) switch devices connected in series, the second high frequency path switch group is configured by a series connection of n switch devices (n is an integer of 1 or more), the high-frequency shunt switch group is configured by k (k is an integer of 1 or more) switch devices connected in series, In a high frequency semiconductor switch circuit configured such that the first group of high frequency path switches are connected to the high frequency input / output common terminal, a high-frequency semiconductor switch circuit characterized in that the switch devices constituting the second high-frequency path switch group have characteristics different from those of the switch devices constituting the first high-frequency path switch group and the high-frequency shunt switch group, and when RonCoff, which is the product of the on-resistance Ron and the off-capacitance Coff of the switch device, is used as a figure of merit, the switch devices constituting the second high-frequency path switch group have a smaller figure of merit than the respective switch devices constituting the first high-frequency path switch group and the high-frequency shunt switch group.

2. 2. The high-frequency semiconductor switch circuit according to claim 1, wherein the switch devices constituting the second high-frequency path switch group have a lower withstand voltage than the respective switch devices constituting the first high-frequency path switch group and the high-frequency shunt switch group.

3. 3. The high frequency semiconductor switch circuit according to claim 2, wherein each of the switch devices constituting the first and second high frequency path switch groups and the high frequency shunt switch group is a field effect transistor.

4. 4. The high-frequency semiconductor switch circuit according to claim 3, wherein the field-effect transistors constituting the second high-frequency path switch group have a gate length shorter than those of the field-effect transistors constituting the first high-frequency path switch group and the high-frequency shunt switch group.

5. 4. The high-frequency semiconductor switch circuit according to claim 3, wherein the field-effect transistors constituting the second high-frequency path switch group have thinner gate oxide film thicknesses than the field-effect transistors constituting the first high-frequency path switch group and the high-frequency shunt switch group.

6. 4. The high-frequency semiconductor switch circuit according to claim 3, wherein the field-effect transistors constituting the second high-frequency path switch group have impurity concentrations different from those of the field-effect transistors constituting the first high-frequency path switch group and the high-frequency shunt switch group.

7. 2. The high-frequency semiconductor switch circuit according to claim 1, wherein each switch device constituting the first and second high-frequency path switch groups and the high-frequency shunt switch group is formed using a field-effect transistor, and the field-effect transistor constituting the second high-frequency path switch group has a larger body leakage current than each field-effect transistor constituting the first high-frequency path switch group and the high-frequency shunt switch group.

8. 8. The high-frequency semiconductor switch circuit according to claim 7, wherein the field-effect transistors constituting the second high-frequency path switch group have thinner gate oxide film thicknesses than the field-effect transistors constituting the first high-frequency path switch group and the high-frequency shunt switch group.

9. 8. The high-frequency semiconductor switch circuit according to claim 7, wherein the field-effect transistors constituting the second high-frequency path switch group have impurity concentrations different from those of the field-effect transistors constituting the first high-frequency path switch group and the high-frequency shunt switch group.

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