Drive circuit for semiconductor device and power conversion device

Abstract

To improve a breakdown tolerance without increasing a switching loss of a semiconductor switching element, and achieve both a low loss performance Eoff and a high breakdown tolerance performance RBSOA.SOLUTION: A driving circuit 100 of a semiconductor device increases and holds a voltage of a gate driving device 120 to an intermediate voltage (Vint_com) higher than an off voltage for a second period (Tint) after a first period (Tdraw) in which a command logic part 110 issues a command of the off voltage lower than a driving voltage during turn-off, temporarily raises and holds a gate voltage (Vg) of an element at a voltage (Vint) higher than the off voltage and lower than a threshold voltage (Vth), in which a timing of an end of the first period (Tdraw) is later than a start of a mirror period and earlier than an end of the mirror period, and a timing of the end of a second period (Tint) is later than a timing at which the element reaches a surge voltage (Vsurge).SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a drive circuit for a semiconductor device and a power conversion device. [Background technology]

[0002] The global trend toward realizing a decarbonized society is driving steady market growth in electric vehicles (EVs), power grids, and railways. These applications use power conversion devices that output AC current based on DC power supplied from a DC power source to drive electric motors. Key components of power conversion devices include semiconductor switching elements and the gate drive circuits that drive them. IGBTs (Insulated Gate Bipolar Transistors), a type of semiconductor switching element, are required to have a high withstand voltage that allows them to block large currents flowing through them without breaking down, along with the increase in current density.As the current density of IGBTs increases, the withstand voltage decreases when the IGBT is turned off, which is a problem.

[0003] To address this issue, there are methods to increase the breakdown resistance of the IGBT itself, as well as methods to increase the breakdown resistance of the gate drive system or gate circuit that drives the IGBT. For example, there are methods that perform soft shutdown by controlling the gate voltage and current at turn-off, as shown in Patent Documents 1, 2, and 3.

[0004] Patent Document 1 describes a method for preventing oscillation of a semiconductor device by raising the gate voltage above the threshold voltage again when the device is turned off.

[0005] Patent Document 2 describes a method for suppressing surge voltage by appropriately controlling the gate current when a semiconductor element is turned off.

[0006] Patent Document 3 describes a method for suppressing surge voltage by appropriately controlling the gate current when a semiconductor element is turned off.

[0007] This section explains how to improve the interruption capability and reduce losses in IGBTs. FIG. 13 is a cross-sectional view of a side gate type IGBT. The side-gate IGBT 10 includes a collector electrode 11, a p-type collector layer 12, an n- drift layer 13, a p-base layer 14, an n+ emitter layer 15, a gate electrode 16, a gate oxide film (interlayer insulating film) 17, an emitter electrode 18, and a gate electrode terminal 19. The side-gate IGBT 10 has a structure in which the gate electrodes 16 are provided on both sides of the emitter electrode 18 .

[0008] FIG. 14 is a diagram showing the effect of turning off the side gate type IGBT 10 (hereinafter referred to as IGBT 10) shown in FIG. 13 when the gate is negative. In FIG. 14, when IGBT 10 is on, a gate voltage (Vg) equal to or greater than the threshold voltage (Vth) is applied to gate electrode 16, and when turning off, IGBT 10 is turned off by reducing the gate voltage (Vg) to a value equal to or less than the threshold voltage (Vth). At this time, negatively biasing Vg improves the speed at which carriers are extracted, not only reducing the turn-off loss (Eoff) but also ensuring redundancy against the IGBT turning back on due to noise, etc.

[0009] However, if the gate resistance (Rg) is reduced to speed up turn-off and the speed at which Vg is negatively biased is increased, Vg will be negatively biased faster than the holes (accumulated holes 20) accumulated inside the device can be discharged. When the gate is negatively biased, a hole accumulation layer 21 (see hatching in FIG. 14) is formed under the gate electrode 16, as shown in FIG. 14. When holes are discharged in this state, the current flowing through the IGBT 10 is concentrated in the region where the hole accumulation layer 21 is formed, increasing the electric field strength and current density in that region and inducing a dynamic avalanche (see symbol a in FIG. 14). When a dynamic avalanche is induced, the generated avalanche current increases the current flowing through the p base layer 14 under the n+ emitter layer 15 (see arrow b in FIG. 14), activating the parasitic npn transistor 22 (see dashed-line box in FIG. 14). This causes latch-up breakdown of the IGBT 10. In other words, the IGBT breakdown tolerance is reduced. To summarize, the following occurs:

[0010] When the potential at point A determined by the voltage drop when the avalanche current flows through p base layer 14 below n+ emitter layer 15)>(built-in potential of the pn junction consisting of p base-n+ emitter), parasitic npn transistor 22 turns on.

[0011] The above problem is not limited to the side-gate IGBT 10, but is similar to that of IGBTs with other structures, such as trench-gate IGBTs. However, in the case of the side-gate IGBT 10, it is difficult to deepen the trench to reduce the step, so the depth of the p-base layer 14 is inevitably shallow. As a result, the potential at point A in FIG. 14, which is determined by the potential drop caused by the avalanche current (see symbol b in FIG. 14) generated by the dynamic avalanche (see symbol a in FIG. 14) flowing through the p-base layer 14, is higher when the trench is shallow compared to when the trench is deep. Therefore, there is a concern that the parasitic npn transistor 22 is more likely to operate in the side-gate IGBT 10 than in a deep trench-gate IGBT. For this reason, the side-gate IGBT 10 has been used as an example for explanation. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-70164 [Patent Document 2] Japanese Patent Publication No. 2023-013594 [Patent Document 3] Japanese Patent Publication No. 2021-141662 Summary of the Invention [Problem to be solved by the invention]

[0013] Patent Document 1 describes a technology for reducing vibration by raising the gate voltage above the threshold voltage again after the surge voltage peak (Vds peak) when the semiconductor switching element is turned off. However, with the method described in Patent Document 1, the gate voltage rises above the threshold voltage again after turn-off, causing the semiconductor switching element to turn on again and increasing loss.

[0014] Patent Document 2 describes a method for softening the turn-off of a semiconductor switching element by controlling the gate current to adjust the switching speed. However, the method described in Patent Document 2 increases turn-off loss by slowing down the switching speed.

[0015] Patent Document 3 describes an example of active gate drive using current control by switching gate resistance. However, the method described in Patent Document 3 involves control by switching gate resistance, and although it is possible to change the gate drive speed during switching, it is difficult to control (or design) the gate voltage to a desired level so as to prevent inversion under the gate electrode 16 (see FIG. 14). Furthermore, because a change in gate resistance changes the turn-off loss, it is not possible to achieve both reduced loss and improved tolerance.

[0016] This section summarizes the challenges of improving the interruption capability and reducing losses in IGBTs. As shown in FIG. 14, it is important to prevent the formation of a hole accumulation layer 21 under the gate electrode 16 and suppress dynamic avalanche (see symbol a in FIG. 14) in order to improve the breakdown resistance of the IGBT itself.

[0017] FIG. 15 is a diagram illustrating the trade-off between the loss performance Eoff and the RBSOA (Reverse Bias Safe Operating Area) which indicates the breakdown resistance performance. The RBSOA is the range of current and voltage that the IGBT can use when it is turned off without degradation or destruction. As shown in Figure 15, increasing the gate resistance (Rg) to prevent breakdown slows down the speed at which the gate voltage (Vg) is negatively biased. This makes it difficult for a hole accumulation layer 21 (see Figure 14) to form under the gate electrode 16 when holes accumulated inside the device are discharged. This prevents strong inversion under the gate around the time when the product of the collector current Ic and the collector-emitter voltage Vce (= IGBT power consumption) reaches its maximum, thereby improving the IGBT's breakdown resistance. However, adjusting the gate resistance (Rg) has the problem of increasing the loss performance (Eoff) due to a decrease in switching speed. In other words, there is a trade-off between improving breakdown resistance performance (RBSOA) and reducing loss performance (Eoff), as shown in Figure 15, and achieving both is a challenge.

[0018] The present invention has been made in view of the above circumstances, and has as its object to provide a drive circuit for a semiconductor device and a power conversion device that improves breakdown resistance without increasing the switching loss of a semiconductor switching element, thereby achieving both low loss performance Eoff and high breakdown resistance performance RBSOA. [Means for solving the problem]

[0019] In order to solve the above problem, a drive circuit for a semiconductor device of the present invention is a drive circuit for a semiconductor device comprising: a command logic unit that issues a drive command signal for a semiconductor switching element; and a gate drive device that drives the gate of the semiconductor switching element based on the drive command signal from the command logic unit, wherein, when the semiconductor switching element is turned off, after a first period (Tdraw) in which the command logic unit issues a command for an off voltage lower than the drive voltage, the gate drive device raises and holds the voltage of the gate drive device to an intermediate voltage (Vint_com) that is higher than the off voltage for a second period (Tint), and temporarily raises and holds the gate voltage (Vg) of the semiconductor switching element to a voltage (Vint) that is higher than the off voltage and lower than a threshold voltage (Vth), and wherein the end timing of the first period (Tdraw) is later than the start timing of a mirror period and earlier than the end timing of the mirror period, and the end timing of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge). [Effects of the Invention]

[0020] According to the present invention, it is possible to provide a semiconductor device driver circuit and a power conversion device that improve the breakdown voltage without increasing the switching loss of the semiconductor switching element, thereby achieving both low loss performance (Eoff) and high breakdown voltage performance (RBSOA). [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a diagram illustrating the overall configuration of a power conversion device including a drive circuit for a semiconductor device according to a first embodiment of the present invention. [Figure 2] 1 is a circuit diagram of a gate driver of a semiconductor device driver circuit according to a first embodiment of the present invention. [Figure 3] 1 is a circuit diagram of a power supply for a gate driver of a driver circuit for a semiconductor device according to a first embodiment of the present invention. [Figure 4] 3A and 3B are diagrams illustrating an example of switching waveforms of a gate driver of a drive circuit of a semiconductor device according to the first embodiment of the present invention. [Figure 5] 5A to 5C are diagrams illustrating the effects of the drive circuit of the semiconductor device according to the first embodiment of the present invention. [Figure 6] 1 is a circuit diagram of a gate driver of a semiconductor device driver circuit according to a first embodiment of the present invention. [Figure 7] 1 is a diagram showing a schematic configuration of a semiconductor switching element according to a first embodiment of the present invention; [Figure 8] FIG. 1 is a diagram showing the operating waveforms of a typical dual gate drive; [Figure 9] FIG. 10 is a diagram showing switching waveforms during operation of the gate drive device of the drive circuit of the semiconductor device according to the second embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing switching waveforms during operation of the gate driving device according to the first modified example of the second embodiment of the present invention. [Figure 11] FIG. 10 is a diagram showing a schematic configuration of a semiconductor switching element according to a second modification of the second embodiment of the present invention. [Figure 12] FIG. 10 is a diagram showing a schematic configuration of a semiconductor switching element according to a third modified example of the second embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view of a side-gate IGBT. [Figure 14] FIG. 14 is a diagram showing the effect of turning off the side-gate IGBT shown in FIG. 13 when the gate is negative. [Figure 15] FIG. 1 is a diagram illustrating the trade-off between loss performance Eoff and RBSOA, which indicates breakdown resistance performance. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (First embodiment) A semiconductor device drive circuit according to a first embodiment of the present invention will be described. This embodiment is an example in which the semiconductor device drive circuit is applied to a control system for an inductive load using a three-phase inverter as a power conversion device. The semiconductor device is suitably applied to not only trench-gate IGBTs but also side-gate IGBTs, which are difficult to suppress the occurrence of dynamic avalanches.

[0023] [Overall configuration] FIG. 1 is a diagram showing the overall configuration of a power conversion device including a drive circuit for a semiconductor device according to a first embodiment. The power conversion device 200 shown in FIG. 1 outputs an AC current based on DC power supplied from a DC power supply 30 to drive an electric motor 50. The drive circuit 100 for the semiconductor device includes a command logic unit 110 and a gate drive device 120, and drives a semiconductor switching element 140 (semiconductor device; semiconductor element; element). The gate drive device 120 and the semiconductor switching element 140 constitute an inverter circuit 160. The power conversion device 200 includes an inverter circuit 160 and a command logic unit 110. A smoothing capacitor 40 is provided between the DC power supply 30 (power supply voltage=Vcc) and the positive electrode connecting line 160a and the negative electrode connecting line 160b of the inverter circuit 160.

[0024] The inverter circuit 160 includes series circuits of semiconductor switching elements 140 consisting of upper and lower arms for three phases, UVW phases. In FIG. 1, each of the semiconductor switching elements 140 of the upper and lower arms is configured with an IGBT. A high-potential side terminal of the IGBT of the upper arm of each phase is connected to a first end (positive electrode connection wire 160a) of the smoothing capacitor 40. A low-potential side terminal of the IGBT of the upper arm of each phase is connected to a high-potential side terminal of the IGBT of the lower arm of each phase. A low-voltage terminal of the IGBT of the lower arm of each phase is connected to a second end (negative electrode connection wire 160b) of the smoothing capacitor 40.

[0025] In each phase, the connection point between the low potential side terminal of the IGBT in the upper arm and the high potential side terminal of the IGBT in the lower arm is connected to one end of a winding of the motor 50. The other end of the winding of each phase is connected to a neutral point. The motor 50 is, for example, an induction motor.

[0026] Each IGBT is connected in anti-parallel to a freewheeling diode 150. Various types of diodes can be used as the freewheeling diode 150, such as a pn junction diode, a Schottky barrier diode, or a diode that uses both a pn junction and a Schottky junction.

[0027] The command logic unit 110 outputs an ON command instructing an ON state or an OFF command instructing an OFF state to the gate driver 120 as an ON / OFF drive command signal P for the semiconductor switching element 140. In response to this, the command logic unit 110 alternately turns ON the semiconductor switching element 140 of the upper arm and the semiconductor switching element 140 of the lower arm in each phase in order to control the control variable of the electric motor 50 to the command value. The control variable is, for example, the torque of the electric motor 50.

[0028] The gate driving device 120 is provided corresponding to each semiconductor switching element 140, acquires an on / off drive command signal P from the command logic unit 110, and turns the semiconductor switching element 140 on or off based on the acquired on / off drive command signal P.

[0029] Each semiconductor switching element 140 controls the power and torque supplied to the connected electric motor 50 by repeatedly turning on and off at high speed.

[0030] In this embodiment, the command logic unit 110 is provided outside the inverter circuit 160, but the command logic unit 110 may be incorporated into the inverter circuit 160. In this case, the semiconductor device driver circuit 100 is also incorporated into the inverter circuit 160.

[0031] [Gate drive unit] Fig. 2 is a circuit diagram of the gate driver 120 of the semiconductor device driver circuit 100 of Fig. 1. Fig. 3 is a circuit diagram of the power supply of the gate driver 120 of Fig. 2. FIG. 2 shows the semiconductor switching element 140 and its gate driver 120 associated with the lower arm of the U phase in the inverter circuit 160 of FIG. In FIG. 2, the semiconductor switching elements 140 in the upper arm of the U phase and the upper and lower arms of the V and W phases and their gate drivers 120 also have the same configuration as in FIG. In Figure 2, the configuration and operation of the semiconductor switching element 140 of the lower arm of the U phase and its gate drive device 120 are described, but the semiconductor switching elements 140 of the upper and lower arms of the V phase and W phase and their gate drive devices 120 also have the same configuration as in Figure 2.

[0032] As shown in FIG. 2, the gate driver 120 includes an intermediate voltage control unit (gate voltage control unit) 121, an ON / OFF control unit 122, a positive power supply (power supply voltage=Vp) 123, and a first PMOSFET (PMOSFET <1> )124(PMOSFET <1> ), second PMOSFET (PMOSFET <2> ) 125, an on-side gate resistor (Rgon) 126, a negative-side power supply (power supply voltage=Vm) 127, an off-side gate resistor (Rgoff) 128, an NMOSFET 129, an auxiliary power supply (power supply voltage=Vaux) 130, and an auxiliary gate resistor (Rgaux) 131.

[0033] The output section of the gate driver 120 is connected to the gate electrode G of the semiconductor switching element 140 via terminal G. The reference potential 132 of the gate driver 120 is connected to the emitter terminal E of the semiconductor switching element 140. Furthermore, the input section of the gate driver 120 is connected to the P output and Q output of the command logic unit 110 via input terminals P and Q.

[0034] The positive power supply 123 is a PMOSFET <1> The source of 124 is connected to the auxiliary power supply 130. <2> 125 sources are connected. PMOSFET <1> The drain of 124 is connected to one end of the on-side gate resistor (Rgon) 126, and <2> The drain of 125 is connected to one end of an auxiliary gate resistor (Rgaux) 131 . The drain of the NMOSFET 129 is connected to one end of the off-side gate resistor (Rgoff) 128 , and the source of the NMOSFET 129 is connected to the negative-side power supply 127 . The other end of the ON-side gate resistor (Rgon) 126 , the other end of the auxiliary gate resistor (Rgaux) 131 , and the other end of the OFF-side gate resistor (Rgoff) 128 are all connected to an output terminal G of the output section of the gate driver 120 . PMOSFET <1> The gates of the NMOSFET 124 and the NMOSFET 129 are both connected to the output of the on / off control unit 122. <2> The gate of 125 is connected to the output of the intermediate voltage control section 121 .

[0035] FIG. 3 is a power supply circuit diagram of the gate driver 120. The gate driver 120 is supplied with a positive power supply 123 (power supply voltage=Vp), a negative power supply 127 (power supply voltage=Vm), and an auxiliary power supply 130 (power supply voltage=Vaux).

[0036] As described above, the gate driver 120 includes an ON / OFF control unit 122, a positive power supply (power supply voltage=Vp) 123, a first PMOSFET (PMOSFET <1> )124(PMOSFET <1> ), an ON-side gate resistor (Rgon) 126, a negative-side power supply (power supply voltage = Vm) 127, an NMOSFET 129, and an OFF-side gate resistor (Rgoff) 128 are newly added to the configuration of the ON / OFF control unit 122 that operates in response to an intermediate voltage drive command signal Q from the command logic unit 110, an auxiliary power supply (power supply voltage = Vaux) 130, a second PMOSFET (PMOSFET <2> ) 125, and auxiliary gate resistor (Rgaux) 131 have been added. As a result, in addition to the conventional positive power supply (power supply voltage = Vp) 123 and negative power supply (power supply voltage = Vm) 127, a new power supply, auxiliary power supply (power supply voltage = Vaux) 130, has been added.

[0037] [Operation description] The operation of the gate driver 120 of this embodiment will be described below. <Operation by input of ON / OFF drive command signal P> An on / off drive command signal P is input from the command logic unit 110 to the on / off control unit 122 of the gate driver 120 . The on / off control unit 122 of the gate driver 120 controls the PMOSFET while the on / off drive command signal P is being input from the command logic unit 110. <1> This causes a current (gate current) to flow from the positive-side power supply 123 to the gate of the semiconductor switching element 140 via the on-side gate resistor (Rgon) 126.

[0038] At this time, the capacitance between the gate and emitter of the semiconductor switching element 140 is charged and a voltage (for example, +15 V) exceeding the threshold voltage of the semiconductor switching element 140 is applied, turning on the semiconductor switching element 140 and causing a current to flow (turn on) through the semiconductor switching element 140. The turn-on switching speed is controlled by adjusting the resistance value (Rgon) of the on-side gate resistor (Rgon) 126.

[0039] Further, while the on / off control unit 122 of the gate driver 120 is not receiving the on / off drive command signal P from the command logic unit 110, the on / off control unit 122 controls the PMOSFET <1> This operates to turn off NMOSFET 124 and turn on NMOSFET 129. As a result, a gate current flows from the gate of semiconductor switching element 140 through OFF-side gate resistor (Rgoff) 128 toward the negative side power supply.

[0040] At this time, the capacitance between the gate and emitter terminals of the semiconductor switching element 140 is discharged and a voltage (for example, −15 V) lower than the threshold voltage of the semiconductor switching element 140 is applied, turning off the semiconductor switching element 140 and cutting off (turning off) the current of the semiconductor switching element 140. The switching speed of the turn-off is controlled by adjusting the resistance value (Rgoff) of the off-side gate resistor (Rgoff) 128.

[0041] <dV / dt during switching transition> The semiconductor switching element 140 is turned on / off by charging and discharging the gate capacitance. At this time, the gate-collector capacitance Cgc changes due to fluctuations dV / dt in the collector-emitter voltage Vce, and a Miller period occurs in which the gate-emitter voltage Vge becomes flat in order to charge and discharge Cgc.

[0042] However, the mirror period defined in this embodiment does not refer to the mirror period in the narrow sense in which the gate-emitter voltage Vge becomes flat, but refers to the period that begins when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes greater than the on-voltage (Vce(sat)) and ends when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes the same as the power supply voltage Vcc of the element (Vce=Vcc).

[0043] <Medium voltage drive operation by medium voltage drive command signal Q input> Basic Concept In this embodiment, during the mirror period, an intermediate voltage drive command signal Q is input to drive the second PMOSFET (PMOSFET <2> ) 125 is turned on to connect the auxiliary power supply (power supply voltage=Vaux) 130 and connect the auxiliary gate resistor (Rgaux) 131 to the gate of the semiconductor switching element 140, thereby changing the gate voltage (Vg) to an intermediate voltage Vint shown in (Equation 1) described later, and further maintaining this intermediate voltage Vint for the Tint period.

[0044] Fig. 4 is a diagram showing an example of the switching waveform of the gate driver 120. The upper part of Fig. 4 shows a gate drive command (= the output waveform of the drive circuit of the semiconductor device), the middle part of Fig. 4 shows the gate-emitter voltage waveform of the IGBT, and the lower part of Fig. 4 shows the collector-emitter voltage and current waveform of the IGBT.

[0045] Tdraw is the time (first period) during which the gate drive command shown in the upper part of FIG. 4 first issues a command for a voltage (off voltage) lower than the drive voltage. Tint is the time during which the gate drive command shown in the upper part of FIG. 4 issues a voltage command for the intermediate voltage Vint_com, which is higher than the off voltage. Vint is the gate voltage (Vg) applied to the gate of the semiconductor switching element 140 (hereinafter referred to as the element as appropriate) in the gate-emitter voltage waveform of the IGBT shown in the middle of Fig. 4. Vint temporarily raises and maintains the gate voltage (Vg) of the element to a voltage (Vint) that is greater than the off-voltage and less than the threshold voltage (Vth) (second period). Vsuege is the surge voltage that occurs in the voltage and current waveform between the collector and emitter of the IGBT shown in the lower part of Figure 4. The reasons for the restrictions on the values ​​of Tdraw, Tint, and Vint are as follows:

[0046] <tdraw> If the Vint_com command is issued earlier than Vce>Vce(sat), the gate voltage rises before the carriers have been sufficiently discharged, slowing down the switching of the element and increasing Eoff. When a Vint_com command is issued after Vce=Vcc, the gate begins to rise when the collector current Ic begins to decrease. IGBTs break down when dI / dt occurs due to current concentration caused by carrier discharge, so the effect of improving the withstand voltage cannot be obtained.

[0047] <tint> By issuing a Vint_com command (continuing to issue a Vint_com command) until the surge voltage Vsuege has passed, it is possible to prevent strong inversion under the gate when strong power is applied to the device. This suppresses dynamic avalanche near the gate, which can cause latch-up, improving the withstand voltage. Ideally, it is preferable to maintain the gate voltage (Vg) at Vint until the IGBT current becomes zero, as this prevents strong inversion throughout the entire carrier discharge period and improves the withstand voltage.

[0048] <vint> When Vint > Vth, the IGBT turns on again and the collector current Ic increases. As a result, not only does Eoff increase, but an excessive current also flows when a voltage higher than the on-voltage (Vce(sat)) is applied to the device, leading to a risk of destruction due to the heat generated thereby. Therefore, Vint < Vth is necessary. Consequently, Vint_com < Vth is necessary. Note that if the condition Vint < Vth is satisfied by adjusting the length of Tint, Vint_com < Vth is not necessarily required.

[0049] <Features of this embodiment> · The end of Tdraw (reference c in FIG. 4) is later than the timing when Vce > Vce(sat) (start of the Miller period) (reference d in FIG. 4) and earlier than the time when Vce of the device becomes Vcc (end of the Miller period) (reference e in FIG. 4). Therefore, Tdraw is a constant period indicated by arrow f in FIG. 4.

[0050] · The timing at the end of Tint (reference g in FIG. 4) is later than the timing when the device encounters the surge voltage (Vsurge) (reference h in FIG. 4) (period of arrow i in FIG. 4).

[0051] <Operation description> When the IGBT is turned off, an intermediate voltage drive command signal Q is input from the command logic unit 110 to the intermediate voltage control unit 121 (FIG. 2) of the gate drive device 120 between the timing when the collector-emitter voltage Vce of the device becomes greater than the on-voltage (Vce(sat)) (start of the Miller period) and the time when the collector-emitter voltage Vce of the device becomes the same as the power supply voltage Vcc of the device (Vce = Vcc) (end of the Miller period). The Miller period is the period from when the collector-emitter voltage Vce > Vce(sat) until the timing when Vce = Vcc (reference e in FIG. 4) and the collector current Ic starts to decrease.

[0052] The on-voltage (Vce(sat)) is a common name and is more accurately called the collector-emitter saturation voltage, which is the voltage value between the collector and emitter when a specified voltage is applied between the gate and emitter and a specified current flows through the collector. The collector-emitter voltage Vce is sometimes simply called the collector voltage Vce.

[0053] As shown in the upper part of Figure 4, during turn-off, the gate voltage (Vg) is first biased to an off-voltage lower than the drive voltage, and then biased again to a positive voltage below the threshold voltage for a certain period (Tdraw) (first period). The timing for starting the positive bias occurs during the period when the collector-emitter voltage Vce fluctuates dV / dt (i.e., the Miller period), and the timing for returning to the off-voltage occurs after the collector-emitter voltage Vce reaches a surge voltage (Vsuege). This prevents strong inversion under the gate around the time when the product of the collector current Ic and the collector-emitter voltage Vce (= IGBT power consumption) reaches its maximum, thereby improving RBSOA.

[0054] At the time of the above-mentioned turn-off, the command logic unit 110 inputs an intermediate voltage drive command signal Q to the intermediate voltage control unit 121 (FIG. 2) of the gate driver 120 between the timing when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes greater than the on-voltage (Vce(sat)) (start of the mirror period) and the time when the collector-emitter voltage Vce of the semiconductor switching element 140 becomes the same as the power supply voltage Vcc of the element (Vce=Vcc) (end of the mirror period).

[0055] The intermediate voltage control unit 121 generates an intermediate voltage control signal based on the intermediate voltage drive command signal Q, and controls the PMOSFET <2> Apply 125 to the gate of the PMOSFET <2> Turn on 125. PMOSFET <2> When 125 is turned on, an auxiliary power supply (power supply voltage=Vaux) 130 is connected to one end of an ON-side gate resistor (Rgon) 126 and one end of an OFF-side gate resistor (Rgoff) 128 through an auxiliary gate resistor (Rgaux) 131 .

[0056] The gate voltage (Vg) of the element is maintained at a voltage (Equation 1) determined by the auxiliary power supply (power supply voltage = Vaux) 130, the negative power supply (power supply voltage = Vm) 127, the off-side gate resistance (Rgoff) 128, and the auxiliary gate resistance (Rgaux) 131.

[0057]

number

[0058] Vint_com: Gate driver design voltage Vaux: Auxiliary power supply voltage Vm: Negative power supply voltage Rgoff: Gate resistance between the negative power supply and the semiconductor switching element Rgaux: Gate resistance between the auxiliary power supply and the semiconductor switching element

[0059] As shown in the middle of Figure 4, when the intermediate voltage drive command signal Q is input, the gate voltage (Vg) of the element changes from negative (symbol j in Figure 4) to voltage Vint_com (Equation 1) determined by the auxiliary power supply (power supply voltage = Vaux) 130, negative side power supply (power supply voltage = Vm) 127, off-side gate resistance (Rgoff) 128, and auxiliary gate resistance (Rgaux) 131, and rises sharply (symbol k in Figure 4), and is maintained at the intermediate voltage Vint.

[0060] The timing relationship between the period when the gate voltage (Vg) changes from negative to positive and transitions to the intermediate voltage Vint, which is lower than the threshold voltage Vth (symbol j→k in Figure 4), and the end of the mirror period, Vce = Vcc (symbol e in Figure 4), is an important timing specification. In other words, one of the timing conditions is that the timing when the gate voltage (Vg) starts to rise to the intermediate voltage Vint (symbol j→k in Figure 4) is earlier than the timing when the collector current Ic starts to fall (when Vce = Vcc) (symbol e in Figure 4).

[0061] In other words, the intermediate voltage drive command signal Q is input before the collector current Ic starts to drop and at a timing that anticipates that the gate voltage (Vg) will be maintained at the intermediate voltage Vint and completed. As can be seen from (Equation 1), the slope of the voltage rise as the gate voltage (Vg) transitions to the intermediate voltage Vint is set by the auxiliary power supply voltage Vaux, the negative power supply voltage Vm, the gate resistance Rgoff between the negative power supply and the element, and the gate resistance Rgaux between the auxiliary power supply and the element. If the auxiliary power supply voltage Vaux, the negative power supply voltage Vm, and the gate resistance Rgoff are assumed to be constants (constant values), the slope of the voltage rise of the gate voltage (Vg) is determined by the value of the gate resistance Rgaux. The end of Tdraw is not controlled by the on-off drive command signal P, which continues to issue an off command after issuing an off command. The period from when the on-off drive command signal P becomes an off command until the intermediate voltage drive command signal Q issues a Vint_com command is Tdraw, and the period from when the intermediate voltage drive command signal Q issues an off command is Tint.

[0062] The above describes the timing of the start of the intermediate voltage drive command signal Q. The intermediate voltage drive command signal Q changes the gate voltage (Vg) to the intermediate voltage Vint shown in (Equation 1) during the mirror period, and then maintains this intermediate voltage Vint for the Tint period. The end of the Tint period is determined by the intermediate voltage drive command signal Q issuing an OFF command.

[0063] As shown in the voltage and current waveforms between the collector and emitter of the IGBT in the bottom half of Figure 4, it is known from experience that dynamic avalanche occurs in the element when the collector current Ic is on a slope (symbol l in Figure 4). For this reason, when this collector current Ic is on a slope (when dI / dt is applied), the intermediate voltage Vint is maintained for the Tint period. Furthermore, the Vint_com command continues to be issued until the surge voltage Vsuege (symbol h in Figure 4) is passed. Therefore, the end of Tint (symbol g in Figure 4) is later (period indicated by arrow i in Figure 4) than the moment when the element experiences the surge voltage (Vsurge) (symbol h in Figure 4). The timing at which the element experiences the surge voltage (Vsurge) is the point at which the risk of destruction is highest, and by making the timing at which Tint ends (symbol g in Figure 4) later (later) than the timing at which the surge voltage (Vsurge) occurs (symbol h in Figure 4), the element is protected from destruction by the surge voltage.

[0064] After the semiconductor switching element 140 (hereinafter referred to as the semiconductor element or element as appropriate) experiences a surge voltage (Vsurge), the command logic unit 110 inputs an OFF drive command signal P to the gate driver 120, thereby turning off the PMOSFET. <2> 125 is turned off, and the gate voltage Vg is controlled to the negative power supply (power supply voltage=Vm) 127.

[0065] <Modification> In the circuit diagram of the gate driver 120 in FIG. 2, the auxiliary power supply 130 (power supply voltage = Vaux) and the positive-side power supply 123 (power supply voltage = Vp) may be common (Vp = Vaux). By commonizing the power supply voltage Vaux and the positive-side power supply voltage Vp, the auxiliary power supply 130 (power supply voltage = Vaux) can be omitted (reducing the size of the power supply circuit in FIG. 3). When the power supply voltage Vaux and the positive-side power supply voltage Vp are common, the gate voltage (Vg) only needs to satisfy (Equation 1). However, when the power supply voltage Vaux and the positive-side power supply voltage Vp are common, increasing the power supply voltage Vaux to the positive-side power supply voltage Vp increases the threshold voltage Vth. To avoid this, the value of Rgaux must be increased. This slows down the speed at which the gate voltage (Vg) is increased (from j to k in FIG. 4), thereby increasing the turn-off loss. For this reason, from the viewpoint of reducing loss, it is preferable to provide an auxiliary power supply 130 (power supply voltage=Vaux) and reduce the value of Rgaux to quickly raise the gate voltage (Vg).

[0066] Incidentally, as shown in the voltage and current waveforms between the collector and emitter of the IGBT in the lower part of Figure 4, as Vg increases, the carrier discharge speed slows down, and the slope of Vce becomes somewhat gentler at the timing of symbol c in Figure 4.

[0067] For the above reasons, the "auxiliary power supply" in claim 1 also includes the "positive power supply voltage" in the case of the above common use.

[0068] [Effects of the first embodiment] As described above, the drive circuit 100 (FIG. 2) for a semiconductor device according to the first embodiment includes a command logic unit 110 that issues a drive command signal for the semiconductor switching element 140, and a gate drive device 120 that drives the gate of the semiconductor switching element 140 based on the drive command signal (ON / OFF drive command signal P) from the command logic unit 110. When the semiconductor switching element 140 is turned off, the gate drive device 120 changes the voltage of the gate drive device 120 to an intermediate voltage (Vint in FIG. 4) that is higher than the OFF voltage after a first period (Tdraw in FIG. 4) during which the command logic unit 110 issues a command for an OFF voltage that is lower than the drive voltage. The voltage is raised and maintained for the second period (Tint in FIG. 4), and the gate voltage (Vg) of the semiconductor switching element 140 is temporarily raised and maintained at a voltage (Vint in FIG. 4) that is greater than the off-voltage and less than the threshold voltage (Vth) (symbol k in FIG. 4). The timing at which the first period (Tdraw in FIG. 4) ends (symbol g in FIG. 4) is later than the start (symbol d in FIG. 4) of the mirror period (arrow f in FIG. 4) and earlier than the end (symbol e in FIG. 4) of the mirror period, and the timing at which the second period (Tint in FIG. 4) ends (symbol g in FIG. 4) is later than the timing (symbol h in FIG. 4) at which the semiconductor switching element 140 experiences a surge voltage (Vsurge in FIG. 4).

[0069] With this configuration, the semiconductor device driver circuit 100 (FIG. 2) quickly biases the gate voltage (Vg) negative (symbol j in FIG. 4) during the first half of the dV / dt period when the loss performance Eoff occurs, improving switching speed and preventing an increase in the loss performance Eoff. At the same time, the gate voltage (Vg) is raised to a positive intermediate voltage Vint (symbol j→k in FIG. 4) only during the dI / dt period when the risk of device breakdown is high, preventing the accumulation of positive charge (hole accumulation layer) and thus preventing strong inversion. Furthermore, by positioning the end of the intermediate voltage Vint (symbol g in FIG. 4) at Tint after the timing of the surge voltage (Vsurge) (symbol h in FIG. 4), the device can be protected from damage by the surge voltage.

[0070] Therefore, it is possible to realize a waveform in which the gate voltage is maintained positive at the timing when a high Ic×Vce product (conduction loss) occurs without compromising the switching speed (dV / dt).As a result, it is possible to realize an internal state of the device in which dynamic avalanche (symbol a in FIG. 14) under the gate electrode 16 (FIG. 14) is suppressed by the drive circuit 100 of this semiconductor device, without increasing the gate resistance (Rg) for preventing breakdown.

[0071] FIG. 5 is a diagram illustrating the effect of this embodiment from the perspective of the trade-off between loss performance Eoff and RBSOA, which indicates breakdown resistance performance. As described above, the driving circuit 100 of this semiconductor device can realize an internal state of the device in which dynamic avalanche (symbol a in Figure 14) under the gate electrode 16 (Figure 14) is suppressed without increasing the gate resistance (Rg). As indicated by the white arrow m in Fig. 5, this embodiment can achieve a favorable result by moving away from the Eoff-RBSOA tradeoff while maintaining the tradeoff relationship between Eoff and RBSOA (see the solid line in Fig. 5) by adjusting Rg. For example, when the turn-off loss is 100%, the maximum breaking current can be increased by 50% or more without increasing Rg, thereby improving breakdown resistance. Therefore, it is possible to improve the breakdown resistance without increasing the switching loss of the IGBT, and to achieve both low loss performance Eoff and high breakdown resistance performance RBSOA.

[0072] Furthermore, in the driving circuit 100 (FIG. 2) of the semiconductor device, the gate driving device 120 controls the gate voltage (Vg) to the intermediate voltage (Vint_com) shown in (Equation 1) during the turn-off operation of the semiconductor switching element 140.

[0073] In this way, the design voltage (Vint_com) of the gate driver 120 when the intermediate voltage Vint is introduced can be designed based on the auxiliary power supply voltage Vaux, the negative power supply voltage Vm, the gate resistance Rgoff, and the gate resistance Rgaux. In particular, optimal values ​​for the gate resistance Rgaux and the auxiliary power supply voltage Vaux can be designed.

[0074] In addition, in the drive circuit 100 (FIG. 2) of the semiconductor device, the semiconductor switching element 140 includes an IGBT, and the length of the second period (Tint) is variable depending on the breakdown voltage and cutoff current (Ic) of the IGBT (the current when the collector current Ic is viewed from the cutoff characteristics).

[0075] By doing this, the higher the breakdown voltage (i.e., the thicker the chip) or the larger the cutoff current (Ic) of the semiconductor device drive circuit 100, the more carriers are stored inside the chip at turn-off, so by extending the gate lift time, it is possible to expect a reliable improvement in the breakdown voltage.

[0076] In addition, in the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧twice the rated current), after a first period (Tdraw in FIG. 4) in which the command logic unit 110 issues a command for an off voltage lower than the drive voltage, when the semiconductor switching element 140 is turned off, the gate drive device 120 raises and holds the voltage of the gate drive device 120 to an intermediate voltage (Vint_com in FIG. 4) higher than the off voltage for a second period (Tint in FIG. 4), and also raises the gate voltage (Vg) of the semiconductor switching element 140 to a value higher than the off voltage. The voltage is temporarily raised and maintained at a voltage (Vint in FIG. 4) that is lower than the threshold voltage (Vth) that the semiconductor switching element 140 can tolerate (symbol k in FIG. 4), and gate drive control is performed such that the end timing (symbol g in FIG. 4) of the first period (Tdraw in FIG. 4) is later than the start (symbol d in FIG. 4) of the mirror period (arrow f in FIG. 4) and earlier than the end timing (symbol e in FIG. 4) of the mirror period, and the end timing (symbol g in FIG. 4) of the second period (Tint in FIG. 4) is later than the timing (symbol h in FIG. 4) at which the semiconductor switching element 140 experiences a surge voltage (Vsurge in FIG. 4).

[0077] By doing so, the driving circuit 100 of the semiconductor device can be driven at a higher speed by simplifying the driving under conditions other than overcurrent, where the risk of breakdown is low.

[0078] Furthermore, in the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧twice the rated current), it increases the resistance value (Rgoff) of the OFF-side gate resistor.

[0079] In this way, the semiconductor device driver circuit 100 can reliably cut off the power supply so that the system does not break down when an overcurrent occurs by increasing the gate resistance while ignoring the increase in loss.

[0080] Furthermore, in the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧twice the rated current), it switches off the gate voltage in multiple stages.

[0081] In this way, the semiconductor device driver circuit 100 can reliably cut off the power so that the system does not break down when an overcurrent occurs by driving the gate while ignoring the increase in loss.

[0082] Furthermore, in the drive circuit 100 (FIG. 2) of the semiconductor device, when the gate drive device 120 detects an overcurrent (for example, Ic≧2 times the rated current), it detects the inflection point of the collector-emitter voltage Vce (dynamic avalanche due to the overcurrent) when dV / dt falls below a predetermined value.

[0083] When an overcurrent occurs, a dynamic avalanche occurs, causing a phenomenon in which dV / dt becomes smaller during turn-off. The semiconductor device driver circuit 100 can detect the current and transition to an operation to protect the system.

[0084] (Second embodiment) A drive circuit for a semiconductor device according to a second embodiment of the present invention will be described below. This embodiment is an example in which the present invention is applied to a drive circuit for a semiconductor device of a dual-gate IGBT having two independently controllable gates. 6 is a circuit diagram of a gate driver 120A of a semiconductor device driver circuit 100A according to the second embodiment, in which the same components as those in FIG. Fig. 6 shows a semiconductor switching element 140 and its gate driver 120A associated with the lower arm of the U phase in the inverter circuit 160 of Fig. 1. While Fig. 6 describes the configuration and operation of the semiconductor switching element 140 and its gate driver 120A associated with the lower arm of the U phase, the semiconductor switching elements 140 and their gate drivers 120A associated with the upper and lower arms of the V phase and W phase have similar configurations.

[0085] Compared to the semiconductor device drive circuit 100 shown in FIG. 2, the semiconductor device drive circuit 100A shown in FIG. 6 has two gate terminals of the semiconductor switching element 140A, a control gate Gc and a switching gate Gs, and accordingly, the on / off control unit 122 shown in FIG. 2 has been changed to a delay control unit 122A in FIG. 6. Gate resistance on the Gc side (Rgcon, Rgcoff), NMOSFET <2> , PMOSFET <3> Therefore, the gate resistances Rgon and Rgoff in the first embodiment are now Rgson and Rgsoff, respectively. Also, the auxiliary power supply is connected to the Gc side. The detailed configuration is as follows: The symbol Gc is used to denote a control gate Gc, a second gate electrode Gc, or a terminal Gc. Similarly, the symbol Gs is used to denote a switching gate, a first gate electrode, or a terminal.

[0086] As shown in FIG. 6, the gate driver 120A includes an intermediate voltage control unit 121, a delay control unit 122A, a positive power supply (power supply voltage=Vp) 123, a PMOSFET <1> 124A, 3rd PMOSFET (PMOSFET <3> )124B, PMOSFET <2> 125, on-side gate resistor (Rgcon) 126A, on-side gate resistor (Rgson) 126B, negative power supply (power supply voltage = Vm) 127, off-side gate resistor (Rgcoff) 128A, off-side gate resistor (Rgsoff) 128B, first NMOSFET (NMOSFET <1> ) 129A, second NMOSFET (NMOSFET <2> ) 129B, an auxiliary power supply (power supply voltage=Vaux) 130, and an auxiliary gate resistor (Rgaux) 131.

[0087] The output section of the gate driver 120A is connected to the first gate electrode Gs and the second gate electrode Gc of the semiconductor switching element 140A via terminals Gs and Gc. The reference potential of the gate driver 120A is connected to the emitter terminal E of the semiconductor switching element 140A. The input section of the gate driver 120A is connected to the Pd output and the Q output of the command logic unit 110 via input terminals Pd and Q.

[0088] The positive power supply 123 is a PMOSFET <1> 124A, and PMOSFET <3> The source of 124B is connected to the auxiliary power supply 130 via a PMOSFET. <2> 125 sources are connected to each other. PMOSFET <1> 124A and PMOSFET <3> The drain of 124B is connected to one end of the on-side gate resistors (Rgcon) 126A and (Rgson) 126B. <2> The drain of 125 is connected to one end of the auxiliary gate resistor (Rgaux) 131, and the NMOSFET <1> 129A and NMOSFET <2> The drains of the gate resistors 129B are connected to one end of the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B, respectively.

[0089] The other ends of the on-side gate resistors (Rgcon) 126A and (Rgson) 126B, the other end of the auxiliary gate resistor (Rgaux) 131, and the other ends of the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B are all connected to the output of the gate driver 120A. <1> 129A and NMOSFET <2> The source of 129B is connected to the negative power supply 127. <1> 124A and PMOSFET <3> 124B gate and NMOSFET <1> 129A and NMOSFET <2> The gates of 129B and 129C are both connected to the output of the delay control section 122A. <2> The gate of 125 is connected to the output of the intermediate voltage control section (gate voltage control section) 121 .

[0090] FIG. 7 is a diagram showing a schematic configuration of the semiconductor switching element 140A. The semiconductor cell 240 of the semiconductor switching element 140A has an outer periphery region cell 240a, a central region cell 240b, a gate (Gc) electrode pad 241, and a gate (Gs) electrode pad 242.

[0091] The semiconductor switching element 140A drives and controls the central region cell 240b with different gate electrodes (Gc) and (Gs). Here, the control gate electrode (Gc) is turned off first before turning off (FIG. 8). By turning off the control gate electrode (Gc) before the switching gate electrode (Gs), some of the carriers accumulated in the central region cell 240b are discharged, preventing current concentration in the peripheral part of the active region during turn-off, thereby improving the turn-off interruption capability.

[0092] [Operation description] The operation of the gate driver 120A of this embodiment will be described below. 6, a drive command signal Pd is input from the command logic unit 110 to a delay control unit 122A of a gate driver 120A. While the drive command signal Pd is being input, the gate driver 120A controls the PMOSFET <1> 124A and PMOSFET <3> Turn on 124B, NMOSFET <1> 129A and NMOSFET <2> The delay control unit 122A is operated to turn off the on-side gate resistors (Rgcon) 126A and (Rgson) 126B, thereby causing a gate current to flow from the positive-side power supply 123 to the control gate (Gc) (first gate) and switching gate (Gs) (second gate) of the semiconductor switching element 140A via the on-side gate resistors (Rgcon) 126A and (Rgson) 126B.

[0093] At this time, the capacitance between the gate and emitter of the semiconductor switching element 140A is charged, and a voltage (for example, +15 V) exceeding the threshold voltage of the semiconductor switching element 140A is applied, turning on the semiconductor switching element 140A and causing a current to flow through the semiconductor switching element 140A (turning it on). The turn-on switching speed is controlled by adjusting the resistance values ​​(Rgcon, Rgson) of the on-side gate resistors (Rgcon) 126A and (Rgson) 126B.

[0094] Normally, when turned on, the first and second gate electrodes are turned on simultaneously. That is, when turned on, the time difference set by delay control section 122A is set to zero, but a delay may be provided.

[0095] Furthermore, while the drive command signal Pd is not input from the command logic unit 110, the gate driver 120A controls the PMOSFET <1> 124A and PMOSFET <3> Turn off 124B, NMOSFET <1> 129A and NMOSFET <2> The intermediate voltage control unit 121 is operated to turn on the gates (Gc and Gs) of the semiconductor switching element 140A, and the gate resistors (Rgcoff) 128A and (Rgsoff) 128B are turned on. This causes a gate current to flow from the gates (Gc and Gs) of the semiconductor switching element 140A to the negative power supply 127 via the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B.

[0096] At this time, the capacitance between the gate and emitter terminals of the semiconductor switching element is discharged and a voltage (for example, −15 V) lower than the threshold voltage of the semiconductor switching element 140A is applied, turning off the semiconductor switching element 140A and cutting off the current through the semiconductor switching element 140A (turning it off). The switching speed of the turn-off is controlled by adjusting the resistance values ​​(Rgcoff, Rgsoff) of the off-side gate resistors (Rgcoff) 128A and (Rgsoff) 128B.

[0097] FIG. 8 is a diagram showing the operating waveforms of a general dual gate drive. Normally, at the time of turn-off, the first gate electrode (Gc) is turned off before the second gate electrode (Gs). That is, at the time of turn-off, the time difference (Tpre_off) set by the delay control unit 122A is set to Tpre_off (≧0). In a situation where all gates are urgently shut off due to a system abnormality, the delay may be set to zero (Tpre_off ≒ 0).

[0098] Returning to FIG. 6, by increasing the number of gate terminals of the semiconductor switching element 140A to two and setting the time difference (Tpre_off) set by the delay control unit 122A to Tpre_off (≧0), the carriers accumulated inside the semiconductor when the element is turned off are reduced compared to the semiconductor switching element 140 of the first embodiment, resulting in an improved turn-off speed (=reduced Eoff). The important point to note about this configuration is that, in principle, the first gate electrode (Gc) becomes negatively biased at turn-off, which causes strong inversion under the first gate electrode. Below, we will explain why the configuration of the second embodiment can improve the problem of strong inversion under the first gate electrode.

[0099] In the second embodiment, at the time of turn-off, an additional voltage is applied to the Gc side in addition to the normal turn-off of the general dual gate drive of Fig. 8. Specifically, after the lapse of Tdraw from Gc off, the command logic unit 110 inputs an on / off drive command signal P to the gate driver 120A, and the PMOSFET <2> 125 is turned on, and the gate voltage Vg of the semiconductor switching element 140A (semiconductor element) is maintained at a voltage (Equation 2) determined by the auxiliary power supply (power supply voltage = Vaux) 130, the negative power supply (power supply voltage = Vm) 127, the off-side gate resistance (Rgoff) 128, and the auxiliary gate resistance (Rgaux) 131.

[0100]

number

[0101] Vint_com: Gate driver design voltage Vaux: Auxiliary power supply voltage Vm: Negative power supply voltage Rgcoff: Gate resistance between the negative power supply and the semiconductor switching element Rgaux: Gate resistance between the auxiliary power supply and the semiconductor switching element

[0102] At this time, Tdraw must be a positive value and shorter than Tpre_off (Tdraw <Tpre_off)。 After the semiconductor switching element 140A (semiconductor element) experiences a surge voltage (Vsurge), the command logic unit 110 inputs an on / off drive command signal P to the gate driver 120A, thereby turning on and off the PMOSFET. <2> 125 is turned off, and the gate voltage (Vg) of the semiconductor switching element 140A (semiconductor element) is controlled to the negative power supply voltage. An example of a waveform when the above operation is performed is shown in FIG.

[0103] FIG. 9 is a diagram showing the switching waveforms during the operation of the gate driving device 120A of the second embodiment. The upper diagram in FIG. 9 shows the first gate (Gc) command and the second gate (Gs) command, the middle diagram in FIG. 9 shows the first gate voltage (Vgc) and the second gate voltage (Vgs), and the lower diagram in FIG. 9 shows the collector current Ic and Vce.

[0104] The drive circuit 100A of the semiconductor device of this embodiment is an IGBT in which the semiconductor switching element 140A is driven and controlled by two gates, and has a preparation period (= reduction time of accumulated charge: Tpre_off) for turning off the first gate (Gc) prior to turning off the second gate (Gs). After a certain period (Tdraw) when the first gate turns off first, the gate drive device 120A is provided that raises and holds the voltage of the gate drive circuit of the first gate to an intermediate voltage (Vint_com) greater than the off voltage for a certain period (Tint). The gate drive device 120A temporarily raises and holds the first gate voltage (Vgc) of the semiconductor switching element 140A to a voltage (Vint) greater than the off voltage and less than the threshold voltage (Vth) (reference numeral n in FIG. 9), and is characterized in that the length of Tdraw at this time is shorter than Tpre_off (reference numeral o in FIG. 9).

[0105] The reason for making Tdraw shorter than Tpre_off (reference numeral o in FIG. 9) and making Vgc < Vth (reference numeral n in FIG. 9) is as follows. The semiconductor switching element 140A continues to conduct only with the second gate Gs even after the first gate Gc turns off, and turns off when Gs turns off. Therefore, dV / dt and dI / dt occur, and the risk of breakdown occurs after the off command is input to Gs. Therefore, by raising the Gc gate earlier (Tdraw < Tpre_off) than the off command is input to Gs, it is possible to eliminate the strong inversion layer of holes generated under the Gc gate at the time of turn-off. Also, by making the voltage (Vgc) of the Gc gate equal to or lower than Vth, re-turn-on of the device does not occur, and an increase in Eoff is prevented.

[0106] [Effects of the Second Embodiment] The drive circuit 100A (FIG. 6) of the semiconductor device according to the second embodiment is a drive circuit 100A of a semiconductor device including a gate drive device 120A that drives and controls a dual-gate IGBT having two gates. The gate drive device 120 has a preparation period (= reduction time of accumulated charge: Tpre_off) for turning off the first gate (Gc) prior to turning off the second gate (Gs), and after a certain period (Tdraw) when the first gate has turned off first, the gate voltage of the first gate (Gc) is increased and held at an intermediate voltage (Vint) greater than the off voltage for a certain period (Tint), and the first gate voltage (Vgc) of the IGBT is temporarily increased and held at a voltage (Vint) greater than the off voltage and less than the threshold voltage (Vth). At this time, the length of the certain period (Tdraw) is shorter than the preparation period (Tpre_off).

[0107] With this configuration, in the drive circuit 100A (FIG. 6) of the semiconductor device, in view of the fact that the risk of breakdown occurs in the semiconductor switching element 140A after an off command is input to the second gate (Gs), by lifting the Gc gate earlier (Tdraw < Tpre_off) than an off command is input to the second gate (Gs), the strong inversion layer of holes generated under the first gate (Gc) can be eliminated at the time of turn-off. Also, by setting the voltage (Vgc) of the first gate (Gc) to be less than or equal to Vth, re-turn-on of the device does not occur, and an increase in the loss performance Eoff can be prevented. As a result, similar to the first embodiment, the breakdown tolerance can be improved without increasing the switching loss of the IGBT, and both low loss performance Eoff and high breakdown tolerance performance RBSOA can be achieved.

[0108] [Modification Example 1 of the Second Embodiment] FIG. 10 is a diagram showing the switching waveform during the operation of the gate drive device of Modification Example 1 of the second embodiment. The same reference numerals are given to the same timings as in FIG. 9. Modification Example 1 of the second embodiment is that the gate drive device 120 (FIG. 4) of the first embodiment is added to the second gate (Gs) side. For example, by introducing a circuit connected to the auxiliary power supply 130 between the gate resistors Rgsoff and Rgson on the Gs side in FIG. 6, in the same way as on the first gate (Gc) side, the drive shown in FIG. 10 can be realized. The operation is the same as in the second embodiment up to the point where an OFF command is input to the second gate (Gs), and after the OFF command is input to the second gate (Gs), the drive of the first embodiment is added to the second gate (Gs) side. This also eliminates the strong hole inversion layer on the second gate (Gs) side, further improving the reliability of the entire device.

[0109] [Modification 2 of the Second Embodiment] 11 is a diagram showing a schematic configuration of a semiconductor switching element according to Modification 2 of Embodiment 2. Components that are the same as those in FIG. 7 are given the same reference numerals, and explanations of overlapping parts will be omitted. The semiconductor switching element of variant 2 includes a semiconductor cell 240 and a semiconductor cell 250, and the semiconductor cell 250 has an outer periphery region cell 250a, a central region cell 250b, and two first gate (Gc) electrode pads 251 connected to the outer periphery region cell 250a.

[0110] The semiconductor switching element of variant 2 is configured by connecting the collector electrodes of a chip Hc with a high efficiency of hole injection from the collector side (low on-voltage) and the emitter electrodes of a chip Hs with a low efficiency of hole injection from the collector side (high on-voltage) in parallel. Gate electrodes Gc and Gs connected to the gates of Hc and Hs are connected to terminals Gc and Gs of the output part of the gate driver 120A of FIG. 6, respectively. The Hs chip, which has high conductivity and low conduction loss, and the Hs chip, which has high speed and low switching loss, are spatially separated. This configuration, when combined with driving by the gate driver 120A of the second embodiment, which provides a delay (Tpre_off) between Gc off and Gs off, has the advantage of further reducing the loss generated in the semiconductor switching element 140A.

[0111] [Modification 3 of the Second Embodiment] 12 is a diagram showing a schematic configuration of a semiconductor switching element according to Modification 3 of Embodiment 2. The same components as those in FIG. 7 are given the same reference numerals, and explanations of overlapping parts will be omitted. The semiconductor switching element of Modification 3 includes a semiconductor cell 260 and a semiconductor cell 270. The semiconductor cell 260 includes an outer periphery region cell 260a, a central region cell 260b, and a gate (Gs) electrode pad 262 connected to the central region cell 260b. The semiconductor cell 270 includes an outer periphery region cell 270a, a central region cell 277b, and a gate (Gc) electrode pad 271 connected to the outer periphery region cell 260a.

[0112] The semiconductor switching element of variant 3 is configured by connecting the collector electrodes of a chip Hc with a high efficiency of hole injection from the collector side (low on-voltage) and the emitter electrodes of a chip Hs with a low efficiency of hole injection from the collector side (high on-voltage) in parallel. Gate electrodes Gc and Gs connected to the gates of Hc and Hs are connected to terminals Gc and Gs of the output part of the gate driver 120A of FIG. 6, respectively. By configuring the Hs chip with high conductivity and low conduction loss and the Hs chip with high speed and low switching loss on separate chips, the configuration is more spatially separated than the configuration in Fig. 11. This configuration has the advantage that, when combined with driving by the gate driver 120A of the second embodiment in which a delay (Tpre_off) is provided between Gc off and Gs off, the effect of reducing losses generated in the semiconductor switching element 140A is further enhanced.

[0113] [Modification 4 of the Second Embodiment] Furthermore, in a drive circuit 100A (FIG. 6) for a semiconductor device, two or more semiconductor switching elements each having different on-voltages and capable of being driven and controlled by two or more gates are mounted on the same substrate with their collector electrodes and emitter electrodes connected in parallel, and the drive circuit 100A includes a gate drive device that drives each gate with a time difference (Tpre_off) between their operations, wherein the gate drive device 120A raises and holds the gate voltage of a preceding gate that turns off prior to a switching gate that is to be turned off last to an intermediate voltage (Vint_com) that is greater than the off-voltage for a certain period (Tdraw) after the preceding gate is turned off, and temporarily raises and holds the gate voltage of the preceding gate of the semiconductor switching element to a voltage (Vint) that is greater than the off-voltage and less than a threshold voltage (Vth), and the length of the certain period (Tdraw) during the temporary raising and holding is shorter than the time difference (Tpre_off).

[0114] [Fifth Modification of the Second Embodiment] In the drive circuit 100A of the semiconductor device (FIG. 6), the gate drive device 120A may have a configuration similar to that of the gate drive device 120 of FIG. 2, that is, when the semiconductor switching element 140A is turned off, after a first period (Tdraw) in which the command logic unit 110 (FIG. 6) issues a command for an off voltage lower than the drive voltage, the voltage of the gate drive device is raised and maintained at an intermediate voltage (Vint_com) higher than the off voltage for a second period (Tint), and the gate voltage (Vg) of the semiconductor switching element 140A is temporarily raised and maintained at a voltage (Vint) higher than the off voltage and lower than a threshold voltage (Vth), so that the end timing of the first period (Tdraw) is later than the start timing of the mirror period and earlier than the end timing of the mirror period, and the end timing of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

[0115] [Modification 6 of the Second Embodiment] The semiconductor device driver circuit 100A (FIG. 6) monitors the collector-emitter voltage (Vce), which is the element voltage of the semiconductor switching element 140A during the time difference (Tpre_off), and if the value exceeds the threshold value (Vce_th) (Vce>Vce_th), the gate driver 120A changes the voltage of the gate driver 120A to an intermediate voltage (Vint_c) greater than the off voltage after a first period (Tdraw) during which the command logic unit 110 (FIG. 6) issues a command for an off voltage lower than the drive voltage when the semiconductor switching element is turned off. The semiconductor switching element 140A may be configured to temporarily raise and hold the first gate voltage (Vgs) of the semiconductor switching element at a voltage (Vint) that is greater than the off-voltage and less than the threshold voltage (Vth) for only the second period (Tint), and to operate gate driving such that the timing of the end of the first period (Tdraw) is later than the start of the mirror period and earlier than the end of the mirror period, and the timing of the end of the second period (Tint) is later than the timing at which the semiconductor switching element 140A experiences the surge voltage (Vsurge).

[0116] The present invention is not limited to the above-described embodiments and modifications, and includes other modifications and applications as long as they do not deviate from the gist of the present invention as set forth in the claims. For example, the above-described embodiments have been described in detail to facilitate understanding of the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0117] The semiconductor devices (semiconductor switching elements) of the semiconductor device drive circuits 100 and 100A may be MOSFETs, unipolar devices such as JFETs (Junction Field Effect Transistors), or bipolar devices such as IGBTs. Depending on the device, the main terminals and sense terminals may be called "collector" and "emitter" instead of the above-mentioned "drain" and "source."

[0118] Furthermore, the power conversion device 200 to which the drive circuits 100, 100A of this semiconductor device are applied can be applied to motor drive systems for various types of moving objects, including railway cars and electric vehicles, as well as industrial systems, PCS (Power Conditioning Systems) in solar power generation devices and wind power generation devices, smart grids (power distribution systems), etc. [Explanation of symbols]

[0119] 100,100A semiconductor device driver circuit 110 Command Logic Unit 120,120A gate driver 140, 140A semiconductor switching element (semiconductor device; semiconductor element; element) 160 Inverter circuit 160a Inverter circuit positive connection wire 160b Negative connection wire of inverter circuit 121 Intermediate voltage control section (gate voltage control section) 122 On / Off control section 122A Delay control section 123 Positive power supply (power supply voltage = Vp) 124 PMOSFET <1> 125 PMOSFET <2> 126 On-side gate resistance (Rgon) 127 Negative power supply (power supply voltage = Vm) 128 OFF side gate resistance (Rgoff) 129 NMOSFET 130 Auxiliary power supply (power supply voltage = Vaux) 131 Auxiliary gate resistor (Rgaux) 200 Power conversion device 240,250 are semiconductor cells 250a Periphery area cell 250b central region cell 251 First gate (Gc) electrode pad Tdraw 1st period Tint 2nd period< / vint> < / tint> < / tdraw>

Claims

1. A drive circuit for a semiconductor device, comprising: a command logic unit that issues a drive command signal for a semiconductor switching element; and a gate drive device that drives a gate of the semiconductor switching element based on the drive command signal from the command logic unit, The gate driver When the semiconductor switching device is turned off, after a first period (Tdraw) during which the command logic unit issues a command for an off voltage lower than the driving voltage, the voltage of the gate driver is increased to an intermediate voltage (Vint_com) higher than the off voltage for a second period (Tint), and maintained at this voltage; The gate voltage (Vg) of the semiconductor switching element is temporarily increased to and maintained at a voltage (Vint) that is greater than the off-voltage and smaller than a threshold voltage (Vth), The timing of the end of the first period (Tdraw) is later than the start of the mirror period and earlier than the end of the mirror period; The timing of the end of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

1. A driving circuit for a semiconductor device comprising:

2. The gate driver controls the gate voltage (Vg) to an intermediate voltage (Vint_com) expressed by the following formula during the turn-off operation of the semiconductor switching element: [Equation 1] Vint_com: Gate driver design voltage Vaux: Auxiliary power supply voltage Vm: Negative power supply voltage Rgoff: Gate resistance between the negative power supply and the semiconductor switching element Rgaux: Gate resistance between the auxiliary power supply and the semiconductor switching element 2. The semiconductor device driver circuit according to claim 1.

3. The semiconductor switching element includes an IGBT, and the length of the second period (Tint) is variable depending on the breakdown voltage and the interruption current (Ic) of the IGBT.

2. The semiconductor device driver circuit according to claim 1.

4. The gate driver When an overcurrent is detected, after a first period (Tdraw) during which the command logic unit issues a command for an off voltage lower than the drive voltage when the semiconductor switching element is turned off, the voltage of the gate driver is increased to an intermediate voltage (Vint_com) higher than the off voltage and maintained for a second period (Tint); The gate voltage (Vg) of the semiconductor switching element is temporarily increased to and maintained at a voltage (Vint) that is greater than the off-voltage and smaller than a threshold voltage (Vth), The timing of the end of the first period (Tdraw) is later than the start of the mirror period and earlier than the end of the mirror period; The timing of the end of the second period (Tint) is later than the timing at which the semiconductor switching element experiences a surge voltage (Vsurge).

2. The semiconductor device driver circuit according to claim 1.

5. The gate driver When an overcurrent is detected, the resistance value (Rgoff) of the off-side gate resistor is increased.

3. The semiconductor device driver circuit according to claim 2.

6. The gate driver When an overcurrent is detected, the gate voltage is switched in multiple stages to turn off the device.

2. The semiconductor device driver circuit according to claim 1.

7. The gate driver When an overcurrent is detected, the inflection point of the collector-emitter voltage Vce is detected when dV / dt falls below a predetermined value.

2. The semiconductor device driver circuit according to claim 1.

8. A drive circuit for a semiconductor device including a gate drive device that drives and controls a dual-gate IGBT having two gates, The gate driver A preparatory period (Tpre_off) is provided in which the first gate (Gc) is turned off prior to the second gate (Gs) being turned off, and a certain period (Tdraw) after the first gate is turned off in advance, the gate voltage of the first gate is raised to an intermediate voltage (Vint_com) higher than the off voltage and maintained for a certain period (Tint); The first gate voltage (Vgc) of the IGBT is temporarily raised and held at a voltage (Vint) that is greater than the off-voltage and less than the threshold voltage (Vth), and the length of the certain period (Tdraw) during which the voltage is temporarily raised and held is shorter than the preparation period (Tpre_off).

1. A driving circuit for a semiconductor device comprising:

9. a command logic unit that commands a drive command signal for the semiconductor switching element; The gate driver When the semiconductor switching device is turned off, after a first period (Tdraw) during which the command logic unit issues a command for an off voltage lower than the driving voltage, the voltage of the gate driver is increased to an intermediate voltage (Vint_com) higher than the off voltage for a second period (Tint), and maintained at this voltage; The second gate voltage (Vgs) of the semiconductor switching element is temporarily raised and maintained at a voltage (Vint) that is greater than the off-voltage and less than the threshold voltage (Vth), the timing of the end of the first period (Tdraw) is later than the start of a mirror period and earlier than the end of the mirror period, and the timing of the end of the second period (Tint) is later than the timing of the semiconductor switching element experiencing a surge voltage (Vsurge). Activating the gate drive 9. The semiconductor device driver circuit according to claim 8.

10. A power conversion device comprising a drive circuit for a semiconductor device according to any one of claims 1 to 9.

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