Multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component capable of prevent an occurrence of cracks in a multilayer body.SOLUTION: A multilayer ceramic capacitor includes a multilayer body 10 and a pair of external electrodes 40 disposed at both end portions of the multilayer body 10. One of the external electrodes 40 includes a main surface-side external electrode 411A. The main surface-side external electrode 411A includes a main surface-side base electrode layer 511A, a main surface-side conductive resin layer 611A disposed above the main surface-side base electrode layer 511A, and a main surface-side plated layer 711A disposed above the main surface-side conductive resin layer 611A. In a cross-sectional view along a lamination direction T and a length direction L, the main surface-side conductive resin layer 611A includes a conductive resin layer recess 611c recessed towards a side of the multilayer body 10 at a boundary surface 611k with the main surface-side plated layer 711A.SELECTED DRAWING: Figure 5B

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. In recent years, multilayer ceramic capacitors have been required to be durable in harsh environments, such as those subject to bending stress caused by thermal expansion. To address this demand, a technique using a thermosetting conductive resin paste for the external electrodes of a multilayer ceramic capacitor has been known. Patent Document 1 illustrates this type of technique. Patent Document 1 describes a multilayer ceramic capacitor having external electrodes with a layered structure in which an electrode layer formed by applying a conductive paste by dipping and baking the paste, a conductive epoxy-based thermosetting resin layer, a nickel-plated layer, and a tin-based layer are sequentially stacked. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-162771 Summary of the Invention [Problem to be solved by the invention]

[0004] The multilayer ceramic capacitor of Patent Document 1 can prevent cracks from occurring in the laminate by stress relaxation caused by sacrificial fracture and deformation of the resin layer. However, in recent years, durability in even harsher environments has been required, and in such environments, the stress relaxation effect may not function as well, potentially causing cracks in the laminate.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate. [Means for solving the problem]

[0006] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of ceramic layers and a plurality of internal conductor layers alternately stacked in a height direction, and including a first main surface and a second main surface opposing each other in the height direction, a first end face and a second end face opposing each other in a length direction perpendicular to the height direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the height direction and the length direction; and a pair of external electrodes disposed spaced apart from each other at both ends in the length direction of the laminate, wherein the internal conductor layers are connected to a first internal conductor extending to the first end face. and a second internal conductor layer extending to the second end face, the external electrode including a main surface side external electrode arranged on at least one of the first main surface and the second main surface, the main surface side external electrode having a main surface side base electrode layer, a main surface side conductive resin layer arranged in a layer above the main surface side base electrode layer, and a main surface side plating layer arranged in a layer above the main surface side conductive resin layer, and in a cross-sectional view along the height direction and the length direction, the main surface side conductive resin layer has a conductive resin layer recess that is recessed toward the laminate at the boundary surface with the main surface side plating layer. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5A] 3 is an enlarged view of a portion indicated by V in FIG. 2, showing a cross section of a first main surface side external electrode. FIG. [Figure 5B]3 is an enlarged view of a portion indicated by V in FIG. 2, showing a cross section of a first main surface side external electrode. FIG. [Figure 6A] FIG. 2 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment, showing a first step of forming external electrodes on a laminate. [Figure 6B] 4A and 4B are diagrams illustrating a method for manufacturing the multilayer ceramic capacitor according to the embodiment, showing a second step of forming external electrodes on the laminate. [Figure 6C] 4A and 4B are diagrams illustrating a method for manufacturing the multilayer ceramic capacitor according to the embodiment, showing a third step of forming external electrodes on the laminate. [Figure 7A] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a double structure. [Figure 7B] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a triple structure. [Figure 7C] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a four-element structure. DETAILED DESCRIPTION OF THE INVENTION

[0009] A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment will be described below with reference to FIGS. 1 to 4. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 of the embodiment. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 of FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 of FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor 1 of FIG. 2.

[0010] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40.

[0011] 1 to 4 show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T as the height direction of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as the WT cross section. The cross section shown in FIG. 4 is also referred to as the LW cross section.

[0012] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W.

[0013] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, some or all of the surfaces constituting the laminate 10 may be formed with irregularities.

[0014] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12A and a second main surface side outer layer portion 12B arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0016] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes the internal electrode layer 30 located closest to the first principal surface TS1 in the stacking direction T to the internal electrode layer 30 located closest to the second principal surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0017] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The dielectric material may also be one in which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to the above main components.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 30 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 1500 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0019] The multiple internal electrode layers 30 include first internal electrode layers 31 as multiple first internal conductor layers and second internal electrode layers 32 as multiple second internal conductor layers. The multiple first internal electrode layers 31 are arranged on the multiple dielectric layers 20. The multiple second internal electrode layers 32 are arranged on the multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20. In the following, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as internal electrode layers 30.

[0020] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32, and a first lead portion 31B led from the first opposing portion 31A to the first end face LS1. The first lead portion 31B is exposed at the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31, and a second lead portion 32B led from the second opposing portion 32A to the second end face LS2. The second lead portion 32B is exposed at the second end face LS2.

[0022] In the embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming a capacitance and exhibiting the characteristics of a capacitor.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0024] The dimension in the width direction W of the first facing portion 31A and the dimension in the width direction W of the first lead portion 31B may be the same dimension, or one of the dimensions may be smaller. The dimension in the width direction W of the second facing portion 32A and the dimension in the width direction W of the second lead portion 32B may be the same dimension, or one of the dimensions may be smaller.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 1500 or less.

[0027] The first main surface side outer layer portion 12A is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12A is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface side outer layer portion 12A may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0028] The second main surface side outer layer portion 12B is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 12B is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface side outer layer portion 12B may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. FIG. 4 shows the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0030] The laminate 10 has a side surface outer layer portion WG. The side surface outer layer portion WG has a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second side surface WS2. Figures 3 and 4 show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portions are also called W gaps or side gaps.

[0031] The laminate 10 has an end surface side outer layer portion LG. The end surface side outer layer portion LG has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second end surface LS2. Figures 2 and 4 show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portions are also called L gaps or end gaps.

[0032] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0033] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A is disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0034] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B is disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2. In the embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20, thereby forming a capacitance. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0036] The first external electrode 40A has a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A has a first Ni plating layer 71A as a lower plating layer and a first Sn plating layer 72A as an upper plating layer.

[0037] The second external electrode 40B has a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B has a second Ni plating layer 71B as a lower plating layer and a second Sn plating layer 72B as an upper plating layer.

[0038] Here, the layers constituting the first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the LW cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to particularly distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40. When there is no need to particularly distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the base electrode layer 50. Furthermore, when it is not necessary to distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, the first conductive resin layer 60A and the second conductive resin layer 60B may be collectively referred to as the conductive resin layer 60. When it is not necessary to distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B may be collectively referred to as the plating layer 70. When it is not necessary to distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as the Ni plating layer 71. When it is not necessary to distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72.

[0039] The base electrode layer 50 includes a first base electrode layer 50A and a second base electrode layer 50B.

[0040] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0041] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In the embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0042] The first base electrode layer 50A and the second base electrode layer 50B of the embodiment are firing layers. The firing layer preferably contains a metal component and either a glass component or a ceramic component, or both. This improves adhesion between the laminate 10 and the base electrode layer. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, and Li. The presence of a glass component can help sinter the metal component in the base electrode layer and promote sintering. The ceramic component may be the same ceramic material as that of the dielectric layer 20, or a different ceramic material. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, and CaZrO3.

[0043] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate and then applying a conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, it is preferable to form the baked layer by adding a ceramic material instead of a glass component and baking it. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be formed in multiple layers.

[0044] The thickness in the length direction L of the first base electrode layer 50A located on the first end surface LS1 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center in the stacking direction T and width direction W of the first base electrode layer 50A.

[0045] The thickness in the length direction L of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center in the stacking direction T and width direction W of the second base electrode layer 50B.

[0046] When the first base electrode layer 50A is provided on at least a portion of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction T of the first base electrode layer 50A provided on this portion is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and width direction W.

[0047] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the widthwise thickness of the first base electrode layer 50A provided on this portion is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and stacking direction T.

[0048] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction T of the second base electrode layer 50B provided on this portion is preferably, for example, approximately 3 μm or more and 40 μm or less at the center in the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0049] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the widthwise thickness of the second base electrode layer 50B provided on this portion is preferably, for example, approximately 3 μm or more and 40 μm or less at the center in the length direction L and stacking direction T of the second base electrode layer 50B provided on this portion.

[0050] The external electrode 40 has a conductive resin layer 60 that is disposed on the base electrode layer 50 and contains a resin component and a metal component.

[0051] The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0052] The first conductive resin layer 60A is disposed so as to cover the first base electrode layer 50A. In the embodiment, the first conductive resin layer 60A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. The second conductive resin layer 60B is disposed so as to cover the second base electrode layer 50B. In the embodiment, the second conductive resin layer 60B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. Here, the dimension of the first conductive resin layer 60A in the length direction L on the first main surface TS1 and the second main surface TS2 is longer than the dimension of the first base electrode layer 50A in the length direction L on the first main surface TS1 and the second main surface TS2. Furthermore, the dimension in the length direction L on the first principal surface TS1 and the second principal surface TS2 of the second conductive resin layer 60B is longer than the dimension in the length direction L on the first principal surface TS1 and the second principal surface TS2 of the second base electrode layer 50B.

[0053] The thickness in the longitudinal direction L of the first conductive resin layer 60A located on the first end face LS1 side is preferably, for example, approximately 5 μm or more and 200 μm or less at the center of the first conductive resin layer 60A in the stacking direction T and width direction W.

[0054] The thickness in the longitudinal direction L of the second conductive resin layer 60B located on the second end face LS2 side is preferably, for example, approximately 5 μm or more and 200 μm or less at the center of the second conductive resin layer 60B in the stacking direction T and width direction W.

[0055] When the first conductive resin layer 60A is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and width direction W of the first conductive resin layer 60A provided on this portion.

[0056] When the first conductive resin layer 60A is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the widthwise thickness of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the first conductive resin layer 60A provided on this portion.

[0057] When the second conductive resin layer 60B is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and width direction W of the second conductive resin layer 60B provided on this portion.

[0058] When the second conductive resin layer 60B is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the widthwise thickness of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 5 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the second conductive resin layer 60B provided on this portion.

[0059] The conductive resin layer 60 is disposed on the base electrode layer 50. Then, the plating layer 70 is disposed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0060] The conductive resin layer 60 has a resin portion as a resin component and a conductive filler as filler powder dispersed in the resin portion.

[0061] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin portion of the conductive resin layer 60 preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0062] Because the conductive resin layer 60 contains such a resin portion, it is more flexible than the base electrode layer 50, which is made of, for example, a plating film or a fired product of a metal component and a glass component. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer 60 functions as a buffer layer. Therefore, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0063] The conductive fillers are dispersed in a substantially uniform distribution within the resin portion. The conductive fillers are primarily responsible for the electrical conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, an electrical path is formed within the conductive resin layer 60, providing electrical continuity between the base electrode layer 50 and the plating layer 70.

[0064] The metal constituting the conductive filler may be Ag alone, an alloy containing Ag, or a metal powder with Ag coated on its surface. Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and highly weather-resistant. Therefore, Ag metal powder is suitable as a conductive filler. Furthermore, when using a metal powder with Ag coated on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder containing any of these metals as the metal powder.

[0065] Furthermore, the conductive filler may be Cu or Ni that has been subjected to an oxidation prevention treatment. The conductive filler may also be a metal powder in which the surface of the metal powder is coated with Sn, Ni, or Cu. When using a metal powder in which the surface of the metal powder is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof. It is more preferable that the conductive filler has a core of Cu particles. It is also more preferable that at least a portion of the surface of the Cu particles is coated with a Cu-Ag alloy of Cu and Ag. At least a portion of the surface of the Cu particles may be coated with Ag. This improves affinity with Ni plating and improves electrical properties.

[0066] The shape of the conductive filler is not particularly limited. The conductive filler may be spherical, flat, or the like. It is preferable to use a mixture of spherical metal powder and flat metal powder. In other words, the conductive filler as the filler powder includes flat powder or spherical powder.

[0067] The conductive filler may have an average particle size of, for example, 0.3 μm or more and 10 μm or less.

[0068] The average particle size of the conductive filler contained in the conductive resin layer 60 is calculated by using a laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0069] The plating layer 70 includes a first plating layer 70A and a second plating layer 70B.

[0070] The first plating layer 70A is disposed so as to cover the first conductive resin layer 60A. In the embodiment, the first plating layer 70A is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0071] The second plating layer 70B is disposed so as to cover the second conductive resin layer 60B. In the embodiment, the second plating layer 70B is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0072] The plating layer 70 preferably has a two-layer structure of a Ni plating layer 71 and a Sn plating layer 72. A first Sn plating layer 72A is preferably disposed on the first Ni plating layer 71A, and a second Sn plating layer 72B is preferably disposed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the base electrode layer 50 and the conductive resin layer 60 from being eroded by solder when the multilayer ceramic capacitor 1 is mounted. The Sn plating layer 72 improves the wettability of the solder when the multilayer ceramic capacitor 1 is mounted. This makes it easier to mount the multilayer ceramic capacitor 1.

[0073] The thickness of each of the first Ni plated layer 71A and the first Sn plated layer 72A is preferably 1 μm or more and 15 μm or less.

[0074] The thickness of each of the second Ni plated layer 71B and the second Sn plated layer 72B is preferably 1 μm or more and 15 μm or less.

[0075] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the dimension in the length direction L of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension in the stacking direction T of the multilayer ceramic capacitor 1 is defined as the T dimension, then the T dimension is preferably 0.05 mm or more and 10 mm or less. If the dimension in the width direction W of the multilayer ceramic capacitor 1 is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0076] The multilayer ceramic capacitor 1 of this embodiment having the above basic configuration has the following features in the external electrodes 40, that is, the first external electrode 40A and the second external electrode 40B.

[0077] The external electrode 40 of the embodiment includes a main surface-side external electrode arranged on at least one of the first main surface TS1 and the second main surface TS2. In detail, as described above, the first external electrode 40A of the embodiment is arranged on the first end face LS1 and extends from the first end face LS1 to part of the first main surface TS1 and part of the second main surface TS2, as well as part of the first side surface WS1 and part of the second side surface WS2. That is, as shown in Figures 2 and 4, the first external electrode 40A of the embodiment includes a first end face side external electrode 400A as an end face side external electrode arranged on the first end face LS1, a first main face side external electrode 411A as a main face side external electrode arranged on the first main face TS1, and a second main face side external electrode 412A as a main face side external electrode arranged on the second main face TS2, and as shown in Figure 4, a first side face side external electrode 421A arranged on the first side face WS1 and a second side face side external electrode 422A arranged on the second side face WS2.

[0078] As described above, the first external electrode 40A includes a first base electrode layer 50A, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. In the embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. The first conductive resin layer 60A is disposed so as to cover the first base electrode layer 50A, and the first plating layer 70A is disposed so as to cover the first conductive resin layer 60A.

[0079] 2 and 4, the first end face side external electrode 400A of the embodiment includes a first end face side base electrode layer 500A disposed on the first end face LS1, a first end face side conductive resin layer 600A formed above the first end face side base electrode layer 500A, and a first end face side plating layer 700A formed above the first end face side conductive resin layer 600A. The first end face side base electrode layer 500A is part of the first base electrode layer 50A. The first end face side conductive resin layer 600A is part of the first conductive resin layer 60A. The first end face side plating layer 700A is part of the first plating layer 70A and includes a first Ni plating layer 71A and a first Sn plating layer 72A on the first Ni plating layer 71A.

[0080] 2, the first main surface side external electrode 411A of the embodiment includes a first main surface side base electrode layer 511A as a main surface side base electrode layer arranged on the first main surface TS1, a first main surface side conductive resin layer 611A as a main surface side conductive resin layer formed above the first main surface side base electrode layer 511A, and a first main surface side plating layer 711A as a main surface side plating layer formed above the first main surface side conductive resin layer 611A. The first main surface side base electrode layer 511A is part of the first base electrode layer 50A. The first main surface side conductive resin layer 611A is part of the first conductive resin layer 60A. The first main surface side plating layer 711A is part of the first plating layer 70A, and has a first Ni plating layer 71A and a first Sn plating layer 72A on the first Ni plating layer 71A.

[0081] 2, the second main surface side external electrode 412A of the embodiment includes a second main surface side base electrode layer 512A as a main surface side base electrode layer arranged on the second main surface TS2, a second main surface side conductive resin layer 612A as a main surface side conductive resin layer formed above the second main surface side base electrode layer 512A, and a second main surface side plating layer 712A as a main surface side plating layer formed above the second main surface side conductive resin layer 612A. The second main surface side base electrode layer 512A is part of the first base electrode layer 50A. The second main surface side conductive resin layer 612A is part of the first conductive resin layer 60A. The second main surface side plating layer 712A is part of the first plating layer 70A, and has a first Ni plating layer 71A and a first Sn plating layer 72A on the first Ni plating layer 71A.

[0082] 4, the first side surface side external electrode 421A of the embodiment includes a first side surface side base electrode layer 521A disposed on the first side surface WS1, a first side surface side conductive resin layer 621A formed above the first side surface side base electrode layer 521A, and a first side surface side plating layer 721A formed above the first side surface side conductive resin layer 621A. The first side surface side base electrode layer 521A is part of the first base electrode layer 50A. The first side surface side conductive resin layer 621A is part of the first conductive resin layer 60A. The first side surface side plating layer 721A is part of the first plating layer 70A and includes a first Ni plating layer 71A and a first Sn plating layer 72A on the first Ni plating layer 71A.

[0083] 4, the second side surface side external electrode 422A of the embodiment includes a second side surface side base electrode layer 522A disposed on the second side surface WS2, a second side surface side conductive resin layer 622A formed above the second side surface side base electrode layer 522A, and a second side surface side plating layer 722A formed above the second side surface side conductive resin layer 622A. The second side surface side base electrode layer 522A is part of the first base electrode layer 50A. The second side surface side conductive resin layer 622A is part of the first conductive resin layer 60A. The second side surface side plating layer 722A is part of the first plating layer 70A and includes a first Ni plating layer 71A and a first Sn plating layer 72A on the first Ni plating layer 71A.

[0084] The thickness of each of the first Ni plating layer 71A and the first Sn plating layer 72A of the above-mentioned first main surface side base electrode layer 511A, second main surface side base electrode layer 512A, first side surface side base electrode layer 521A and second side surface side base electrode layer 522A is preferably, for example, 5 μm or more and 10 μm or less.

[0085] The thickness of each of the first Ni plating layer 71A and the first Sn plating layer 72A of the above-mentioned first main surface side plating layer 711A, second main surface side plating layer 712A, first side surface side plating layer 721A and second side surface side plating layer 722A is preferably, for example, 1 μm or more and 4 μm or less.

[0086] As described above, the second external electrode 40B of the embodiment is disposed on the second end face LS2 and is formed to extend from the second end face LS2 to part of the first main face TS1 and part of the second main face TS2, and part of the first side face WS1 and part of the second side face WS2. That is, the second external electrode 40B of the embodiment includes a second end face-side external electrode 400B as an end face-side external electrode disposed on the first end face LS1, a first main face-side external electrode 411B as a main face-side external electrode disposed on the first main face TS1, and a second main face-side external electrode 412B as a main face-side external electrode disposed on the second main face TS2, as shown in Fig. 2, and a first side face-side external electrode 421B arranged on the first side face WS1 and a second side face-side external electrode 422B arranged on the second side face WS2, as shown in Fig. 4.

[0087] As described above, the second external electrode 40B includes a second base electrode layer 50B, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. In the embodiment, the second base electrode layer 50B extends from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2. The second conductive resin layer 60B is disposed so as to cover the second base electrode layer 50B, and the second plating layer 70B is disposed so as to cover the second conductive resin layer 60B.

[0088] 2 and 4, the second end face side external electrode 400B of the embodiment includes a second end face side base electrode layer 500B disposed on the second end face LS2, a second end face side conductive resin layer 600B formed above the second end face side base electrode layer 500B, and a second end face side plating layer 700B formed above the second end face side conductive resin layer 600B. The second end face side base electrode layer 500B is part of the second base electrode layer 50B. The second end face side conductive resin layer 600B is part of the second conductive resin layer 60B. The second end face side plating layer 700B is part of the second plating layer 70B and includes a second Ni plating layer 71B and a second Sn plating layer 72B on the second Ni plating layer 71B.

[0089] 2, the first main surface side external electrode 411B of the embodiment includes a first main surface side base electrode layer 511B as a main surface side base electrode layer arranged on the first main surface TS1, a first main surface side conductive resin layer 611B as a main surface side conductive resin layer formed above the first main surface side base electrode layer 511B, and a first main surface side plating layer 711B as a main surface side plating layer formed above the first main surface side conductive resin layer 611B. The first main surface side base electrode layer 511B is part of the second base electrode layer 50B. The first main surface side conductive resin layer 611B is part of the second conductive resin layer 60B. The first main surface side plating layer 711B is part of the second plating layer 70B, and has a second Ni plating layer 71B and a second Sn plating layer 72B on the second Ni plating layer 71B.

[0090] 2, the second main surface side external electrode 412B of the embodiment includes a second main surface side base electrode layer 512B as a main surface side base electrode layer arranged on the second main surface TS2, a second main surface side conductive resin layer 612B as a main surface side conductive resin layer formed above the second main surface side base electrode layer 512B, and a second main surface side plating layer 712B as a main surface side plating layer formed above the second main surface side conductive resin layer 612B. The second main surface side base electrode layer 512B is part of the second base electrode layer 50B. The second main surface side conductive resin layer 612B is part of the second conductive resin layer 60B. The second main surface side plating layer 712B is part of the second plating layer 70B, and includes a second Ni plating layer 71B and a second Sn plating layer 72B on the second Ni plating layer 71B.

[0091] 4, the first side surface side external electrode 421B of the embodiment includes a first side surface side base electrode layer 521B disposed on the first side surface WS1, a first side surface side conductive resin layer 621B formed above the first side surface side base electrode layer 521B, and a first side surface side plating layer 721B formed above the first side surface side conductive resin layer 621B. The first side surface side base electrode layer 521B is part of the second base electrode layer 50B. The first side surface side conductive resin layer 621B is part of the second conductive resin layer 60B. The first side surface side plating layer 721B is part of the second plating layer 70B and includes a second Ni plating layer 71B and a second Sn plating layer 72B on the second Ni plating layer 71B.

[0092] 4, the second side surface side external electrode 422B of the embodiment includes a second side surface side base electrode layer 522B disposed on the second side surface WS2, a second side surface side conductive resin layer 622B formed above the second side surface side base electrode layer 522B, and a second side surface side plating layer 722B formed above the second side surface side conductive resin layer 622B. The second side surface side base electrode layer 522B is part of the second base electrode layer 50B. The second side surface side conductive resin layer 622B is part of the second conductive resin layer 60B. The second side surface side plating layer 722B is part of the second plating layer 70B and includes a second Ni plating layer 71B and a second Sn plating layer 72B on the second Ni plating layer 71B.

[0093] The thickness of each of the second Ni plating layer 71B and the first Sn plating layer 72B of the above-mentioned first main surface side base electrode layer 511B, second main surface side base electrode layer 512B, first side surface side base electrode layer 521B and second side surface side base electrode layer 522B is preferably, for example, 5 μm or more and 10 μm or less.

[0094] The thickness of the second Ni plating layer 71B and the thickness of the second Sn plating layer 72B of the above-mentioned first main surface side plating layer 711B, second main surface side plating layer 712B, first side surface side plating layer 721B and second side surface side plating layer 722B are preferably, for example, 1 μm or more and 4 μm or less.

[0095] FIG. 2 shows an LT cross section of the multilayer ceramic capacitor 1 and the laminate 10 taken along the lamination direction T and the longitudinal direction L. In this LT cross section, the first main surface side external electrode 411A of the first external electrode 40A has a first main surface side recess 510A recessed toward the laminate 10. The first main surface side recess 510A is formed on the surface of the first main surface side external electrode 411A. The first main surface side recess 510A has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., in the direction perpendicular to the paper surface of FIG. 2. The first main surface side recess 510A may be formed over the entire length of the first main surface side external electrode 411A along the width direction W. The first main surface side recess 510A is located approximately in the center of the first main surface side external electrode 411A in the longitudinal direction L.

[0096] 2, the second main surface side external electrode 412A of the first external electrode 40A has a second main surface side recess 520A recessed toward the laminate 10 in the LT cross section. The second main surface side recess 520A is formed on the surface of the second main surface side external electrode 412A. The second main surface side recess 520A has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., the front-to-back direction of the paper surface of FIG. 2. The second main surface side recess 520A may be formed over the entire length of the second main surface side external electrode 412A along the width direction W. The second main surface side recess 520A is located approximately in the vicinity of the center of the second main surface side external electrode 412A in the length direction L.

[0097] 2, the first main surface side external electrode 411B of the second external electrode 40B has a first main surface side recess 510B recessed toward the laminate 10 in the LT cross section. The first main surface side recess 510B is formed on the surface of the first main surface side external electrode 411B. The first main surface side recess 510B has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., the front-to-back direction of the paper surface of FIG. 2. The first main surface side recess 510B may be formed over the entire length of the first main surface side external electrode 411B along the width direction W. The first main surface side recess 510B is located approximately in the vicinity of the center of the first main surface side external electrode 411B in the length direction L.

[0098] 2, the second main surface side external electrode 412B of the second external electrode 40B has a second main surface side recess 520B recessed toward the laminate 10 in the LT cross section. The second main surface side recess 520B is formed on the surface of the second main surface side external electrode 412B. The second main surface side recess 520B has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., the front-to-back direction of the paper surface of FIG. 2. The second main surface side recess 520B may be formed over the entire length of the second main surface side external electrode 412B along the width direction W. The second main surface side recess 520B is located approximately in the vicinity of the center of the second main surface side external electrode 412B in the length direction L.

[0099] FIG. 4 shows an LW cross section of the multilayer ceramic capacitor 1 and the laminate 10 taken along the length direction L and width direction W. In this LW cross section, the first side surface side external electrode 421A of the first external electrode 40A has a first side surface side recess 530A recessed toward the laminate 10. The first side surface side recess 530A is formed on the surface of the first side surface side external electrode 421A. The first side surface side recess 530A has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., in the direction from the front to the back of the paper surface of FIG. 4. The first side surface side recess 530A may be formed over the entire length of the first side surface side external electrode 421A along the stacking direction T. The first side surface side recess 530A is located approximately in the vicinity of the center of the first side surface side external electrode 421A in the length direction L. The first side surface recess 530A may communicate with either or both of the above-mentioned first main surface recess 510A and second main surface recess 520A, or may not communicate with both.

[0100] As shown in FIG. 4, the second side surface side external electrode 422A of the first external electrode 40A has a second side surface side recess 540A recessed toward the laminate 10 in an LW cross section. The second side surface side recess 540A is formed on the surface of the second side surface side external electrode 422A. The second side surface side recess 540A has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., the front-to-back direction of the paper surface of FIG. 4. The second side surface side recess 540A may be formed over the entire length of the second side surface side external electrode 422A along the stacking direction T. The second side surface side recess 540A is disposed approximately near the center of the second side surface side external electrode 422A in the length direction L. The second side surface side recess 540A may communicate with either or both of the first main surface side recess 510A and the second main surface side recess 520A, or it may not communicate with both.

[0101] As shown in FIG. 4, the first side surface side external electrode 421B of the second external electrode 40B has a first side surface side recess 530B recessed toward the laminate 10 in an LW cross section. The first side surface side recess 530B is formed on the surface of the first side surface side external electrode 421B. The first side surface side recess 530B has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., in the direction from the front to the back of the paper surface of FIG. 4. The first side surface side recess 530B may be formed over the entire length of the first side surface side external electrode 421B along the stacking direction T. The first side surface side recess 530B is disposed approximately near the center of the first side surface side external electrode 421B in the length direction L. The first side surface side recess 530B may communicate with either or both of the first main surface side recess 510B and the second main surface side recess 520B.

[0102] As shown in FIG. 4, the second side surface side external electrode 422B of the second external electrode 40B has a second side surface side recess 540B recessed toward the laminate 10 in an LW cross section. The second side surface side recess 540B is formed on the surface of the second side surface side external electrode 422B. The second side surface side recess 540B has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., the front-to-back direction of the paper surface of FIG. 4. The second side surface side recess 540B may be formed over the entire length of the second side surface side external electrode 422B along the stacking direction T. The second side surface side recess 540B is disposed approximately near the center of the second side surface side external electrode 422B in the length direction L. The second side surface side recess 540B may communicate with either or both of the first main surface side recess 510B and the second main surface side recess 520B.

[0103] The first main surface side external electrode 411A and the second main surface side external electrode 412A of the first external electrode 40A and the first main surface side external electrode 411B and the second main surface side external electrode 412B of the second external electrode 40B have the same configuration. Furthermore, the first side surface side external electrode 421A and the second side surface side external electrode 422A of the first external electrode 40A and the first side surface side external electrode 421B and the second side surface side external electrode 422B of the second external electrode 40B also have the same configuration as the four main surface side external electrodes 411A, 412A, 411B, 412B.

[0104] The first and second main surface recesses 510A, 520A of the first external electrode 40A and the first and second main surface recesses 510B, 520B of the second external electrode 40B have the same configuration. Furthermore, the first and second side surface recesses 530A, 540A of the first external electrode 40A and the first and second side surface recesses 530B, 540B of the second external electrode 40B also have the same configuration as the four main surface recesses 510A, 520A, 510B, 520B.

[0105] Therefore, the first main surface side external electrode 411A and the first main surface side recess 510A of the first external electrode 40A will be described below as representative of these four main surface side external electrodes and main surface side recesses, and these four side surface side external electrodes and side surface side recesses, thereby explaining the four main surface side external electrodes and main surface side recesses, and the four side surface side external electrodes and side surface side recesses.

[0106] The first main surface side external electrode 411A of the first external electrode 40A corresponds to the second main surface side external electrode 412A, the first side surface side external electrode 421A, and the second side surface side external electrode 422A of the first external electrode 40A, and the first main surface side external electrode 411B, the second main surface side external electrode 412B, the first side surface side external electrode 421B, and the second side surface side external electrode 422B of the second external electrode 40B. The first main surface side recess 510A of the first external electrode 40A corresponds to the second main surface side recess 520A, the first side surface side recess 530A, and the second side surface side recess 540A of the first external electrode 40A, and the first main surface side recess 510B, the second main surface side recess 520B, the first side surface side recess 530B, and the second side surface side recess 540B of the second external electrode 40B.

[0107] The first base electrode layer 50A, the first conductive resin layer 60A, and the first plating layer 70A of the first external electrode 40A correspond to the second base electrode layer 50B, the second conductive resin layer 60B, and the second plating layer 70B of the second external electrode 40B. The first Ni plating layer 71A and the first Sn plating layer 72A of the first plating layer 70A of the first external electrode 40A correspond to the second Ni plating layer 71B and the second Sn plating layer 72B of the second plating layer 70B of the second external electrode 40B.

[0108] 5A and 5B are enlarged views of the portion indicated by V in FIG. 2, and are LT cross-sectional views showing the first main surface side external electrode 411A of the first external electrode 40A. Note that FIGS. 5A and 5B show an XYZ Cartesian coordinate system similar to that shown in FIGS. 1 to 4. Note that hatching is omitted in FIGS. 5A and 5B to clearly show the symbols, symbol leads, and dimension lines.

[0109] 5A and 5B, the first main surface side external electrode 411A of the first external electrode 40A has a first main surface side base electrode layer 511A and a first main surface side conductive resin layer 611A arranged on the first main surface TS1, and a first main surface side plating layer 711A including a first Ni plating layer 71A and a first Sn plating layer 72A. The first main surface side recess 510A is formed by recessing three layers, namely, the outermost first Sn plating layer 72A, the first Ni plating layer 71A below the first Sn plating layer 72A, and the first main surface side conductive resin layer 611A below the first Ni plating layer 71A, toward the laminate 10 in the stacking direction T (corresponding to the Z direction in FIGS. 5A and 5B).

[0110] 5A and 5B, the surface of the first main surface side external electrode 411A has the above-mentioned first main surface side recess 510A, as well as a first raised portion 710 and a second raised portion 720. The first raised portion 710 is formed inside the first main surface side recess 510A in the length direction L, i.e., on the center side of the length direction L of the laminate 10 (the side away from the first end face LS1 in the length direction L). The second raised portion 720 is formed outside the first main surface side recess 510A in the length direction L, i.e., on the outside side of the length direction L of the laminate 10 (the side closer to the first end face LS1 in the length direction L). In other words, the first main surface side external electrode 411A has a first main surface side recess 510A, and, sandwiched between the first main surface side recess 510A, a first raised portion 710 arranged at the center in the longitudinal direction L of the laminate 10 and a second raised portion 720 arranged at the end side in the longitudinal direction L of the laminate 10.

[0111] 5A indicates a region in the length direction L of the first main surface side recess 510A in this embodiment. The region 700 in the length direction L of the first main surface side recess 510A is based on the distance in the length direction L between a first midpoint 510m1 of a line connecting the deepest portion 510d of the first main surface side recess 510A to the apex 710p of the first raised portion 710, and a second midpoint 510m2 of a line connecting the deepest portion 510d of the first main surface side recess 510A to the apex 720p of the second raised portion 720. The deepest portion 510d of the first main surface side recess 510A refers to a portion of the first main surface side recess 510A that is closest to the first main surface TS1 of the laminate 10 in the stacking direction T. The apex 710p of the first raised portion 710 is the point on the surface of the first raised portion 710 that is farthest from the first main surface TS1 of the laminate 10 in the stacking direction T. The apex 720p of the second raised portion 720 is the point on the surface of the second raised portion 720 that is farthest from the first main surface TS1 of the laminate 10 in the stacking direction T.

[0112] The distance in the stacking direction T between the apex 710p of the first raised portion 710 and the first main surface TS1 of the laminate 10 is the height 710H of the first raised portion 710. The distance in the stacking direction T between the apex 720p of the second raised portion 720 and the first main surface TS1 of the laminate 10 is the height 720H ​​of the second raised portion 720.

[0113] In the embodiment, the height 710H of the first raised portion 710 is preferably greater than the height 720H ​​of the second raised portion 720. The height 710H of the first raised portion 710 and the height 720H ​​of the second raised portion 720 may be the same as or different from each other. If they are different, as described above, the height 710H of the first raised portion 710 may be greater than the height 720H ​​of the second raised portion 720, or conversely, the height 710H of the first raised portion 710 may be less than the height 720H ​​of the second raised portion 720.

[0114] In this embodiment, the depth D of the first main surface recess 510A refers to the shortest distance between the deepest part 510d and a line connecting the apex 710p of the first raised part 710 and the apex 720p of the second raised part 720.

[0115] In this embodiment, the depth D of the first main surface recess 510A is preferably 3 μm or more and 10 μm or less.

[0116] In this embodiment, the depth D of the first main surface recess 510A is preferably greater than the thickness of the Ni plating layer 71A in the stacking direction T of the first main surface external electrode 411A.

[0117] As shown in FIG. 5A, in this embodiment, the distance L1 in the length direction L between the apex 710p of the first raised portion 710 and the apex 720p of the second raised portion 720 is preferably 100 μm or more and 160 μm or less.

[0118] As shown in FIG. 5A, the distance L1 is preferably longer than the distance L2 in the length direction L between the inner end 411e of the first main surface side external electrode 411A in the length direction L and the apex 710p of the first raised portion 710.

[0119] 2, L4 denotes the distance in the length direction L of the end face side outer layer portions LG (first end face side outer layer portion LG1, second end face side outer layer portion LG2) of the laminate 10. In FIG. 5A, L4 denotes the distance in the length direction L of the first end face side outer layer portion LG1. In the embodiment, it is preferable that the distance L1 in the length direction L between the apex 710p of the first raised portion 710 and the apex 720p of the second raised portion 720 is longer than the distance L4 in the length direction L of the first end face side outer layer portion LG1 of the laminate 10.

[0120] The distance L1 is preferably greater than the maximum thickness of the first principal surface side external electrode 411A in the stacking direction T. The distance L1 is also preferably greater than the maximum thickness of the first principal surface side conductive resin layer 611A in the stacking direction T. The distance L1 is also preferably greater than the maximum thickness of the first principal surface side base electrode layer 511A in the stacking direction T.

[0121] 5A, a distance L3 in the length direction L between the inner end 411e of the first main surface side external electrode 411A and the deepest part 510d of the first main surface side recess 510A is preferably longer than a distance L4 in the length direction L of the end face side outer layer portion LG of the laminate 10. The distance L3 is preferably, for example, 300 μm or more.

[0122] In this embodiment, the depth D of the first principal surface recess 510A is preferably 5% to 15% of the maximum thickness of the first principal surface external electrode 411A in the stacking direction T.

[0123] As shown in FIG. 5A, in the embodiment, the distance L5 in the longitudinal direction L between the inner end 560a of the first principal surface side base electrode layer 511A and the deepest part 510d of the first principal surface side recess 510A is preferably 15 μm or more and 25 μm or less.

[0124] As shown in FIG. 5A, in the embodiment, the distance L6 in the length direction L between the inner end 560a of the first principal surface side base electrode layer 511A and the apex 710p of the first raised portion 710 is preferably 40 μm or more and 80 μm or less.

[0125] As described above, the first main surface side recess 510A is formed by three layers: the outermost first Sn plating layer 72A, the first Ni plating layer 71A below the first Sn plating layer 72A, and the first main surface side conductive resin layer 611A below the first Ni plating layer 71A, being recessed toward the laminate 10 in the stacking direction T. In other words, the first main surface side base electrode layer 511A does not have a recess recessed toward the laminate 10 in the stacking direction T.

[0126] 5B, in a cross-sectional view taken along the stacking direction T and the longitudinal direction L, the first main surface side conductive resin layer 611A has a conductive resin layer recess 611c recessed toward the laminate 10 at an interface 611k with the first Ni plating layer 71A of the first main surface side plating layer 711A. The conductive resin layer recess 611c corresponds to the first main surface side recess 510A in the longitudinal direction L and is formed at approximately the same position as the first main surface side recess 510A in the longitudinal direction L. The region of the conductive resin layer recess 611c in the longitudinal direction L corresponds to the region of the first main surface side recess 510A in the longitudinal direction L (denoted by reference numeral 700 in FIG. 5A).

[0127] 5B , in the LT cross-sectional view, the deepest part 611d of the conductive resin layer recess 611c is located inside the inner end part 560a of the first principal surface side base electrode layer 511A, that is, toward the center in the longitudinal direction L of the laminate 10. The deepest part 611d of the conductive resin layer recess 611c refers to the part of the conductive resin layer recess 611c that is closest to the first principal surface TS1 of the laminate 10 in the stacking direction T.

[0128] The thickness 611t of the conductive resin layer 611A at the deepest part 611d of the conductive resin layer recess 611c is preferably 5 μm or more and 20 μm or less, and the thickness 611t is the distance between the deepest part 611d and the first main surface TS1 in the stacking direction T.

[0129] 5B , in an LT cross-sectional view, the first principal surface side conductive resin layer 611A has the above-mentioned conductive resin layer recess 611c, as well as a first conductive resin layer bulge 810 and a second conductive resin layer bulge 820. The first conductive resin layer bulge 810 is formed inside the conductive resin layer recess 611c in the length direction L. The second conductive resin layer bulge 820 is formed outside the conductive resin layer recess 611c in the length direction L. In other words, the first principal surface side conductive resin layer 611A has the conductive resin layer recess 611c, and the first conductive resin layer bulge 810 and the second conductive resin layer bulge 820, which are located at the center of the laminate 10 in the length direction L and on either side of the conductive resin layer recess 611c, respectively.

[0130] The first main surface TS1 is the surface of the laminate 10 that is closest, i.e., that is closest to, the vertex 810p of the first conductive resin layer bulge 810 and the vertex 820p of the second conductive resin layer bulge 820. The distance in the stacking direction T between the vertex 810p of the first conductive resin layer bulge 810 and the first main surface TS1 of the laminate 10 is the height 810H of the first conductive resin layer bulge 810. Furthermore, the distance in the stacking direction T between the vertex 820p of the second conductive resin layer bulge 820 and the first main surface TS1 of the laminate 10 is the height 820H of the second conductive resin layer bulge 820.

[0131] In the embodiment, the height 810H of the first conductive resin layer swell 810 is preferably higher than the height 820H of the second conductive resin layer swell 820. The height 810H of the first conductive resin layer swell 810 and the height 820H of the second conductive resin layer swell 820 may be the same or different. When they are different, as described above, the height 810H of the first conductive resin layer swell 810 may be higher than the height 820H of the second conductive resin layer swell 820, or conversely, the height 810H of the first conductive resin layer swell 810 may be lower than the height 820H of the second conductive resin layer swell 820.

[0132] In this embodiment, the height 810H of the first conductive resin layer protrusion 810 is preferably 15 μm or more and 30 μm or less, while the height 820H of the second conductive resin layer protrusion 820 is preferably 5 μm or more and 20 μm or less.

[0133] The multilayer ceramic capacitor 1 of the embodiment is mounted on a substrate. Mounting on the substrate may involve joining the external electrodes 40 to terminals of the substrate by soldering. When the first main surface side external electrode 411A is joined to the substrate by soldering, flexural stress generated in the first main surface side external electrode 411A is concentrated particularly at the inner end 411e of the first main surface side external electrode 411A or the inner end 611e of the first main surface side conductive resin layer 611A shown in FIG. 5B and is transmitted to the laminate 10 as tensile stress, which may cause cracks or the like in the laminate 10. In the multilayer ceramic capacitor 1 of the embodiment, the first main surface side external electrode 411A has the first main surface side recess 510A, and the first main surface side conductive resin layer 611A has the conductive resin layer recess 611c. This distributes the above-mentioned flexural stress to the first main surface side recess 510A and the conductive resin layer recess 611c, or to the periphery of these recesses. This reduces the flexural stress, preventing cracks from occurring in the laminate 10. As a result, durability in harsh environments is improved.

[0134] The dimensions of the thickness of each layer constituting the first principal surface side external electrode 411A, the depth of the first principal surface side recess 510A, and the height of each raised portion are measured, for example, by the following method. That is, the multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to a position approximately half the dimension in the width direction W. This exposes the LT cross section at the center position in the width direction W of the multilayer ceramic capacitor 1. Next, using a digital microscope, the dimensions of the LT cross section exposed by polishing are measured.

[0135] Next, a method for manufacturing the multilayer ceramic capacitor 1 of the embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of the embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0136] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0137] On the dielectric sheets, a conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0138] A predetermined number of dielectric sheets without a printed internal electrode layer pattern are stacked to form a portion that will become the first main surface-side outer layer portion 12A on the first main surface TS1 side. A dielectric sheet with a printed first internal electrode layer pattern and a dielectric sheet with a printed second internal electrode layer pattern are stacked in this order on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets without a printed internal electrode layer pattern are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface-side outer layer portion 12B on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0139] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0140] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0141] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0142] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0143] In this embodiment, dipping is performed so that the first base electrode layer 50A extends from the first end face LS1 to parts of the first main surface TS1 and the second main surface TS2. Also, dipping is performed so that the second base electrode layer 50B extends from the second end face LS2 to parts of the first main surface TS1 and the second main surface TS2. At the same time, dipping is preferably performed so that the first base electrode layer 50A extends to parts of the first side surface WS1 and the second side surface WS2. Also, dipping is preferably performed so that the second base electrode layer 50B extends to parts of the first side surface WS1 and the second side surface WS2.

[0144] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the ceramic material added. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 10 with the fired layer formed.

[0145] Next, the conductive resin layer 60 is formed. The conductive resin layer 60 of the embodiment is formed on the surface of the base electrode layer 50 and on part of the surface of the laminate 10.

[0146] First, a conductive resin paste is prepared by dispersing conductive fillers in a thermosetting resin as a base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and conductive fillers. Therefore, the conductive fillers are uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0147] Thereafter, a conductive resin paste is applied onto the base electrode layer 50 using a dipping method, and a heat treatment is performed at a temperature of 200°C to 550°C. This causes the resin portion to thermally harden, forming the conductive resin layer 60. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable that the oxygen concentration be kept below 100 ppm.

[0148] In this embodiment, dipping is performed so that the first conductive resin layer 60A extends from the first end face LS1 to parts of the first main surface TS1 and the second main surface TS2. Also, dipping is performed so that the second conductive resin layer 60B extends from the second end face LS2 to parts of the first main surface TS1 and the second main surface TS2. At the same time, dipping is preferably performed so that the first conductive resin layer 60A extends to parts of the first side face WS1 and the second side face WS2. Also, dipping is preferably performed so that the second conductive resin layer 60B extends to parts of the first side face WS1 and the second side face WS2.

[0149] Thereafter, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed in this order using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0150] Here, in order to obtain the groove-shaped recesses described above in each of the main surface side external electrodes and each of the side surface side external electrodes of the external electrode 40 as in the embodiment, for example, the following method can be mentioned.

[0151] 6A to 6C are schematic diagrams illustrating steps for forming a base electrode layer 50 and a conductive resin layer 60 in this method. As shown in FIG. 6A, a base electrode paste 50P that will become the base electrode layer 50 is applied by dipping to an end portion of the laminate 10 in the longitudinal direction L, and then a conductive resin paste 60P that will become the conductive resin layer 60 is applied by dipping. Next, as shown in FIG. 6B, the laminate 10 is passed relatively between a pair of rod-shaped jigs 90 arranged facing each other. The passing direction here is the front-to-back direction of the paper in FIG. 6B. As a result, groove-shaped recesses G are formed by the tips of the pair of rod-shaped jigs 90 on both sides of the conductive resin paste 60P, i.e., the conductive resin layer 60, as shown in FIG. 6C. The recesses G become the above-mentioned first main surface recess 510A, second main surface recess 520A, first side surface recess 530A, second side surface recess 540A, first main surface recess 510B, second main surface recess 520B, first side surface recess 530B, and second side surface recess 540B. Thereafter, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60.

[0152] Note that recesses can also be formed by appropriately adjusting the viscosity of base electrode paste 50P and conductive resin paste 60P or by devising a dipping method.

[0153] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0154] The configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 4. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 7A, 7B, and 7C.

[0155] The multilayer ceramic capacitor 1 shown in FIG. 7A is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that serves as a floating internal conductor layer that is not drawn out to either the first end face LS1 or the second end face LS2.

[0156] The multilayer ceramic capacitor 1 shown in FIG. 7B is a triple-structure multilayer ceramic capacitor 1 including a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35.

[0157] The multilayer ceramic capacitor 1 shown in FIG. 7C is a four-layer structure multilayer ceramic capacitor 1 having, as the floating internal electrode layers 35, a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C.

[0158] In this way, by providing the floating internal electrode layers 35 as the internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, and the multilayer ceramic capacitor 1 can have a high withstand voltage. It goes without saying that the multilayer ceramic capacitor 1 of the embodiment may have a multi-connection structure of four or more.

[0159] 7A, 7B, and 7C, the first external electrode 40A and the second external electrode 40B each have a main surface side external electrode, and each of these main surface side external electrodes has a main surface side recess. Although not shown, the conductive resin layer constituting each main surface side external electrode has a conductive resin layer recess that is recessed toward the laminate at the boundary with the main surface side plating layer.

[0160] 7A, 7B, and 7C, the first external electrode 40A and the second external electrode 40B each have a side surface external electrode, and these side surface external electrodes have a side surface recess. Although not shown, the conductive resin layer constituting each side surface external electrode has a conductive resin layer recess that is recessed toward the laminate at the boundary with the side surface plating layer.

[0161] In particular, multilayer ceramic capacitors 1 having a two-, three-, or four-layer structure including floating internal electrode layers 35 as shown in FIGS. 7A to 7C are effective for use under high voltages. However, under high voltages, it is preferable to apply a shrinkage stress to the laminate 10 as a countermeasure against electrostriction. To achieve this, the plating thickness of the external electrodes on the main surfaces and side surfaces of the laminate 10 is increased. However, in this case, the tensile stress applied to the inner end 411e of the external electrode 40 and the inner end 611e of the conductive resin layer 60A shown in FIG. 5B increases, resulting in a problem of reduced resistance to flexure. However, by providing recesses (first main surface recesses, second main surface recesses) in the main surface-side external electrodes and recesses in the conductive resin layer as in the embodiment, for example, it is possible to improve resistance to flexure as described above and suppress the occurrence of cracks and the like in the laminate 10.

[0162] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following advantages.

[0163] (1) The multilayer ceramic capacitor 1 according to the embodiment includes a laminate 10 including dielectric layers 20 as a plurality of ceramic layers and internal electrode layers 30 as a plurality of internal conductor layers alternately stacked in a stacking direction T as a height direction, and including a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first end face LS1 and a second end face LS2 facing a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing a width direction W perpendicular to the stacking direction T and the length direction L; and The external electrode 40 includes a pair of external electrodes 40 spaced apart from each other, and the internal electrode layer 30 includes a first internal electrode layer 31 as a first internal conductor layer drawn to the first end face LS1 and a second internal electrode layer 32 as a second internal conductor layer drawn to the second end face LS2. The external electrodes 40 include a first main surface side external electrode 411A and a second main surface side external electrode 412A as main surface side external electrodes, and a first main surface side external electrode 411B and a second main surface side external electrode 412C as main surface side external electrodes, which are arranged on the first main surface TS1 and the second main surface TS2, respectively. The first and second main surface side external electrodes 411A and 412A, and the first and second main surface side external electrodes 411B and 412B, respectively, include a first and second main surface side base electrode layer 511A and 512A, and a first and second main surface side base electrode layer 511B and 512B, as main surface side base electrode layers, and a first and second main surface side conductive resin layer 611A and 612A, as main surface side conductive resin layers formed above these main surface side base electrode layers; and a first main surface side conductive resin layer 611B and a second main surface side conductive resin layer 612B, and a first main surface side plating layer (main surface side plating layer) 711A and the first main surface side plating layer 711B, and a second main surface side plating layer 712A and the second main surface side plating layer 712B, which are arranged above these main surface side conductive resin layers, and when viewed in a cross section along the stacking direction T and the length direction L, each main surface side conductive resin layer has a conductive resin layer recess 611c that is recessed toward the laminate 10 at the boundary surface 611k with the main surface side plating layer.

[0164] When the multilayer ceramic capacitor 1 of the embodiment is mounted on a substrate by soldering, the flexural stress generated in the first principal surface side external electrode 411A is not concentrated at the inner end 611e of the first principal surface side conductive resin layer 611A, but is dispersed to the conductive resin layer recess 611 or the periphery of the conductive resin layer recess 611. This provides a flexural stress relaxation effect, making it possible to prevent cracks from occurring in the laminate 10.

[0165] (2) In the multilayer ceramic capacitor 1 according to the embodiment, when viewed in cross section along the stacking direction T and the longitudinal direction L, it is preferable that the deepest portion 611d of the conductive resin layer recess 611c is located closer to the center of the laminate 10 in the longitudinal direction L than the inner end portion 560a of the first main surface side base electrode layer 511A in the longitudinal direction L.

[0166] This provides a flexural stress relaxation effect, making it possible to prevent cracks from occurring in the laminate 10.

[0167] (3) In the multilayer ceramic capacitor 1 according to the embodiment, in a cross-sectional view along the stacking direction T and the length direction L, the first main surface side conductive resin layer 611A has a first conductive resin layer bulge 810 arranged toward the center in the length direction L of the laminate 10 and a second conductive resin layer bulge 820 arranged toward the end in the length direction L of the laminate 10, with the conductive resin layer recess 611c sandwiched between them, and it is preferable that a height 810H of the first conductive resin layer bulge 810, which is the shortest distance from the surface of the laminate 10 to an apex 810p of the first conductive resin layer bulge 810, is higher than a height 820H of the second conductive resin layer bulge 820, which is the shortest distance from the surface of the laminate 10 to an apex 820p of the second conductive resin layer bulge 820.

[0168] This provides a flexural stress relaxation effect, making it possible to prevent cracks from occurring in the laminate 10.

[0169] In the multilayer ceramic capacitor 1 of the embodiment, each of the first external electrode 40A and the second external electrode 40B includes a side surface side external electrode, and this side surface side external electrode may also include a conductive resin layer having a conductive resin layer recess, similar to the main surface side external electrode.

[0170] That is, the multilayer ceramic capacitor 1 of the embodiment includes a laminate 10 including dielectric layers 20 as a plurality of ceramic layers and internal electrode layers 30 as a plurality of internal conductor layers alternately stacked in a stacking direction T as a height direction, and including a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first end face LS1 and a second end face LS2 facing a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing a width direction W perpendicular to the stacking direction T and the length direction L; a pair of external electrodes 40 arranged at a distance from each other at both ends of the laminate 10 in the longitudinal direction L, The internal electrode layer 30 is a first internal electrode layer 31 as a first internal conductor layer drawn to the first end face LS1; a second internal electrode layer 32 as a second internal conductor layer drawn to the second end face LS2, The external electrode 40 is a side-side external electrode disposed on at least one of the first side surface WS1 and the second side surface WS2; The side surface side external electrode is a side surface base electrode layer; a side surface-side conductive resin layer disposed above the side surface-side base electrode layer; a side surface-side plating layer disposed above the side surface-side conductive resin layer, In a cross-sectional view along the stacking direction T and the length direction L, the side surface side conductive resin layer has a conductive resin layer recess that is recessed toward the stack body at the boundary surface with the side surface side plating layer.

[0171] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0172] For example, the multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having many external electrodes.

[0173] In the above-described embodiment, a multilayer ceramic capacitor using a dielectric ceramic is exemplified as a multilayer ceramic electronic component, but the multilayer ceramic electronic component of the present disclosure is not limited to this and can be applied to various other multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic, thermistors using semiconductor ceramic, inductors using magnetic ceramic, etc. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ferrite. [Explanation of symbols]

[0174] 1. Multilayer ceramic capacitors (multilayer ceramic electronic components) 10 Laminate 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 31 First internal electrode layer (first internal conductor layer) 32 Second internal electrode layer (second internal conductor layer) 40 External electrode 411A First main surface side external electrode (main surface side external electrode) 411B First main surface side external electrode (main surface side external electrode) 412A Second main surface side external electrode (main surface side external electrode) 412B Second main surface side external electrode (main surface side external electrode) 511A First main surface side base electrode layer (main surface side base electrode layer) 511B First main surface side base electrode layer (main surface side base electrode layer) 512A Second main surface side base electrode layer (main surface side base electrode layer) 512B Second principal surface side base electrode layer (principal surface side base electrode layer) 560a Inner end 611A First main surface side conductive resin layer (main surface side conductive resin layer) 611B First main surface side conductive resin layer (main surface side conductive resin layer) 611c Conductive resin layer recess 611d Deepest part of the recess in the conductive resin layer 611k Boundary surface 612A Second main surface side conductive resin layer (main surface side conductive resin layer) 612B Second main surface side conductive resin layer (main surface side conductive resin layer) 711A First main surface side plating layer (main surface side plating layer) 711B First main surface side plating layer (main surface side plating layer) 712A Second main surface plating layer (main surface plating layer) 712B Second main surface side plating layer (main surface side plating layer) 810 First conductive resin layer protrusion 810H Height of the protruding part of the first conductive resin layer 810p Top of the protruding part of the first conductive resin layer 820 Protruding portion of second conductive resin layer 820H Height of the raised part of the second conductive resin layer 820p Top of the raised part of the second conductive resin layer L lengthwise T Stacking direction (height direction) W width direction LS1 First end face LS2 Second end face TS1 First principal surface TS2 Second principal surface WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including a plurality of ceramic layers and a plurality of internal conductor layers alternately stacked in a height direction, and including a first main surface and a second main surface opposing each other in the height direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction and the length direction; a pair of external electrodes disposed at opposite ends of the laminate in the longitudinal direction and spaced apart from each other; The internal conductor layer is a first internal conductor layer extending to the first end face; a second internal conductor layer extending to the second end surface, The external electrode is a main surface side external electrode disposed on at least one of the first main surface and the second main surface, The main surface side external electrode is a main surface-side base electrode layer; a main surface-side conductive resin layer disposed above the main surface-side base electrode layer; a main surface-side plating layer disposed above the main surface-side conductive resin layer, the main surface-side conductive resin layer has a conductive resin layer recess that is recessed toward the laminate at the boundary with the main surface-side plating layer, in a cross-sectional view along the height direction and the length direction.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein, in a cross-sectional view taken along the height direction and the length direction, a deepest portion of the recess of the conductive resin layer is located closer to the center of the laminate in the length direction than an inner end portion of the main surface side base electrode layer in the length direction.

3. In a cross-sectional view along the height direction and the length direction, The main surface side conductive resin layer is a first conductive resin layer protrusion disposed on a central side in the length direction of the laminate and a second conductive resin layer protrusion disposed on an end side in the length direction of the laminate, with the conductive resin layer recess sandwiched therebetween; 3. The multilayer ceramic electronic component according to claim 1, wherein a height of the protruding portion of the first conductive resin layer, which is the shortest distance from the surface of the laminate to the apex of the protruding portion of the first conductive resin layer, is higher than a height of the protruding portion of the second conductive resin layer, which is the shortest distance from the surface of the laminate to the apex of the protruding portion of the second conductive resin layer.

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