On-chip heater temperature calibration

Abstract

SOLUTION: There are provided a system, a method, and a circuit element for calibrating a heater (225) used to heat an adjustable resistive network (224) during a trimming procedure, and a circuit that includes an adjustable resistive network including a first resistive segment (R8-R17), a heater element (225) thermally coupled to the adjustable resistive network (224), a calibration resistor (R13) including a second resistive segment thermally coupled to the first resistive segment (R8-R17), and interface circuitry (275, 276) coupled to the calibration resistor.SELECTED DRAWING: Figure 2

Description

[Background technology]

[0001] Integrated circuits (ICs), particularly analog integrated circuits, rely on precise, temperature-stable voltage and / or current sources. Conventionally, extremely precise voltage sources can be fabricated, for example, by using bandgap or buried Zener circuit elements. It is desirable to create current sources that exhibit both process and temperature stability. Summary of the Invention

[0002] In one example, a circuit is provided that includes an adjustable resistive network including a first resistive segment, a heater element thermally coupled to the adjustable resistive network, a calibration resistor including a second resistive segment thermally coupled to the first resistive segment, and an interface circuit element coupled to the calibration resistor.

[0003] In one example, a system is provided that includes an adjustable resistance network, a calibration resistor thermally coupled to the adjustable resistance network, interface circuitry coupled to the calibration resistor, and a heater thermally coupled to the adjustable resistance network, the system including a processor coupled to the heater and the interface circuitry, the processor configured to retrieve a calibration value from a non-volatile memory, generate a power control signal to apply a power pulse to the heater, measure a resistance value of the calibration resistor using the interface circuitry, and adjust the power control signal to vary a voltage level or duration of the power pulse based on a comparison of the calibration value to a value based on the measured resistance value.

[0004] In one example, a method is provided that includes using a processor to command a power supply to provide a power pulse to a heater, measuring a resistance value of a calibration resistor thermally coupled to an adjustable resistance network, reading a calibration value for the calibration resistor, and adjusting the power pulse based on a comparison of the calibration value to a value based on the measured resistance value. [Brief explanation of the drawings]

[0005] Some examples of circuits, devices and / or methods are described below, by way of example only, and in this context, reference is made to the accompanying figures.

[0006] [Figure 1] FIG. 2 is a block diagram of an example current source according to one aspect of the present description.

[0007] [Figure 2] 2 is a block diagram of an example trimming system for the current source of FIG. 1 according to one aspect of the present description.

[0008] [Figure 3] 1 illustrates an example physical layout of an adjustable resistance network with a calibration resistor, according to one aspect of the present description.

[0009] [Figure 4] FIG. 4 is a cross-sectional view of the adjustable resistance network of FIG. 3, according to one embodiment of the present description.

[0010] [Figure 5] 1 is a graph of resistance versus temperature for an exemplary silicided polysilicon resistor.

[0011] [Figure 6] 1 is a graph of resistance versus temperature for an example silicided polysilicon resistor, illustrating the parabolic or quadratic relationship between resistance and temperature centered within the operating range of an IC.

[0012] [Figure 7] 1 is a graph of resistance versus temperature for an example silicided polysilicon resistor, illustrating how the quadratic relationship between resistance and temperature can affect resistance calculations.

[0013] [Figure 8]1 is a graph of resistance versus temperature for an example silicided polysilicon resistor, illustrating how the temperature coefficient of resistance can be calculated during a trim procedure for an adjustable resistor network, in accordance with one aspect of the present description.

[0014] [Figure 9] 1 is a graph of resistance versus temperature for an example silicided polysilicon resistor, illustrating how the temperature coefficient of resistance can be calculated during a trim procedure for an adjustable resistor network, in accordance with one aspect of the present description.

[0015] [Figure 10] 1 is a flowchart outlining an exemplary method for trimming an adjustable resistor network, according to one aspect of the present description.

[0016] [Figure 11] 1 is a flowchart outlining an exemplary method for verifying that a desired heating level is achieved during trimming, according to one aspect of the present description.

[0017] [Figure 12] 1 is a flowchart outlining an exemplary method for calibrating a power pulse applied to a heater, according to one aspect of the present description.

[0018] [Figure 13] 1 is a flowchart outlining an exemplary method for calibrating a power pulse applied to a heater, according to one aspect of the present description. DETAILED DESCRIPTION OF THE INVENTION

[0019] The drawings may not be drawn to scale.

[0020] Resistive components used in integrated circuit (IC) processing often have extremely large temperature coefficients of resistance (TCR) (e.g., measured on the order of 1000 ppm / °C) and large process tolerances (e.g., ±30%). To compensate for such variations, IC devices that are required to generate precisely controlled currents may include adjustable resistor networks that can be adjusted on an IC-by-IC basis to provide zero or near-zero temperature coefficients over an operating temperature range. An adjustable resistor network includes one or more resistors having a positive temperature coefficient (hereinafter referred to as R) connected to one or more resistors having a negative temperature coefficient (hereinafter referred to as R). As described in more detail below, an adjustable resistor network is adjusted or trimmed by selectively shorting, opening, or otherwise isolating one or more of these resistors, resulting in an adjustable resistor network that not only provides a desired resistance at one particular temperature, but also reduces the variation of this resistance over an operating temperature range.

[0021] FIG. 1 illustrates a block diagram of an exemplary current source circuit element 100 that provides a highly accurate on-chip bias current IBIAS. Current source circuit element 100 includes a differential amplifier 118, a transistor 119, an adjustable resistor network 124, a heating element 125, an adjustable voltage source 114, and a bonding pad 108. In operation, adjustable voltage source 114 provides a voltage having a temperature coefficient lower than that of adjustable resistor network 124 after a trimming operation. The voltage output by adjustable voltage source 114 is input to differential amplifier 118, which adjusts the gate voltage of transistor 119 so that the voltage across adjustable resistor network 124 approaches the voltage generated by adjustable voltage source 114. In this manner, the voltage generated by adjustable voltage source 114 does not significantly affect the output current of the current source circuit element. Furthermore, the current flowing through adjustable resistor network 124 flows from the drain of transistor 119 to the source of transistor 119. The current flowing into the drain of transistor 119 becomes the current IBIAS generated by current source circuitry 100. Heater element 125 receives the voltage applied to bond pad 108 of the integrated circuit. Applying a voltage to bond pad 108 causes heater element 125 to heat adjustable resistor network 124. As explained below, this heating technique allows for the measurement of temperature coefficients, and based on this information, adjustable resistor network 124 can be appropriately adjusted.

[0022] FIG. 2 shows an example current source 200 in more detail, including an adjustable resistor network 224. Current source 200 also includes an adjustable voltage source 214 (shown in more detail), an amplifier 202, an NMOS transistor 203, and a heater element 225. Adjustable voltage source 214 operates to provide a voltage shown at node 201 to amplifier 202. Making the voltage at node 201 adjustable, rather than fixed, provides a means to compensate for process variations in the resistance of the adjustable resistor network used to generate the bias current. Adjustment of adjustable voltage source 214 occurs independently of a trim process that adjusts the temperature coefficient of the bias current. The voltage at node 201 is typically set after the temperature coefficient has been adjusted. Adjustable voltage source 214 includes reference resistors R1 through R7 coupled in series between a fixed, temperature-invariant reference voltage (shown as V1) and ground. NMOS transistors Q4 through Q7 are coupled across resistors R3 through R6, respectively. Also coupled to the gate of transistor Q4 is an inverter 215.

[0023] The voltage at node 201 is changed or adjusted based on the state of digital control signals IREF0-IREF3. These control signals are generated by digital nonvolatile memory (NVM) 262. The values ​​programmed into NVM 262 determine which of resistors R3-R6 are shorted and which are not. The resistance values ​​of R3-R6 are binary-weighted, with R3 being the largest. Thus, IREF3 is the most significant bit of digital control word IREF0-IREF3. In other examples, the relative resistance values ​​of R3-R6 may have different weightings. Inverter 215 is used so that the voltage at node 201 generated when NVM 262 is not yet programmed (IREF0-IREF3 are all low) is approximately in the middle of the range of voltages that can be generated by adjustable voltage source 214. This simplifies lab testing of current source 200. Capacitor 213 is connected to the output of adjustable voltage source 214 to provide noise filtering.

[0024] Adjustable resistor network 224 provides the resistance required to convert the voltage generated by adjustable voltage source 214 to a current. Amplifier 202 regulates the voltage across adjustable resistor network 224 to within a predetermined equivalent range (based on the tolerance of amplifier 202) of the voltage at node 201. Adjustable resistor network 224 includes resistors R8-R17 and is thermally coupled to heater element 225 and optional Faraday shield 212 (which may be grounded). While resistors R8-R17 are described as being connected in series, in other examples, these resistors are arranged in parallel or in a series-parallel configuration. The adjustable resistor network is arranged in several trim sets coupled in series with each other. Each trim set includes pairs of trim resistors R9-R10, R11-R12, R13-R14, and R15-R16 coupled in series with each other. A pair of NMOS trim transistors Q8-Q9, Q10-Q11, Q12-Q13, and Q14-Q15 is associated with each pair of trim resistors, so that one NMOS transistor is coupled across one of resistors R9-R16. Inverters 204, 208, 210, and 212 each invert one of the TC0-3 inputs. The gate of transistor Q9 and inverter 204 are also coupled to inverter 206.

[0025] In operation, trim signals TC0-TC3 are provided by NVM 261 to NMOS transistors Q8-Q15 to control the temperature coefficients of adjustable resistor network 224. Resistors R9, R11, R13, and R15 are fabricated from a first material (e.g., a material with a positive temperature coefficient R), and resistors R10, R12, R14, and R16 are fabricated from a second material (e.g., a material with a negative temperature coefficient R). Resistors in a given pair (R9-R10, R11-R12, R13-R14, or R15-R16) are selected to have the same nominal resistance at a test temperature (e.g., 25°C). Therefore, regardless of the values ​​of TC0-TC3, the total resistance of the series of resistors R8-R17 remains approximately the same. Process variations will cause differences between these resistors, but the presence of adjustable voltage source 214 provides a means to trim out this error after the temperature coefficients have been set by programming NVM 261 which controls TC0-3.

[0026] The resistors controlled by TC0-TC3 are binary-weighted, with resistors R9 and R10 being the largest. Thus, the resistance of resistor R9 is equal to twice the resistance of resistor R11, which is equal to four times the resistance of resistor R13, which is equal to eight times the resistance of resistor R15. The resistance of resistor R10 is equal to twice the resistance of resistor R12, which is equal to four times the resistance of resistor R14, which is equal to eight times the resistance of resistor R16. The resistance of resistor R9 is approximately equal to the resistance of resistor R10, the resistance of resistor R11 is approximately equal to the resistance of resistor R12, the resistance of resistor R13 is approximately equal to the resistance of resistor R14, and the resistance of resistor R15 is approximately equal to the resistance of resistor R16.

[0027] An example of how one of the control signals, TC0, functions is as follows: When the TC0 signal is low, resistor R16 is not shorted by Q15, and resistor R16 adds a temperature coefficient term of a first polarity to adjustable resistor network 224. When the TC0 signal is high, resistor R15 is not shorted by Q14, and resistor R15 adds a temperature coefficient term of a second polarity to adjustable resistor network 224. TC1 and TC2 behave similarly to TC0. When TC3 is low, resistor R9 adds a temperature coefficient term of a second polarity, and when TC3 is high, resistor R10 adds a temperature coefficient term of a first polarity. The reversal of polarity of TC3 relative to inputs TC0-2, resulting from the insertion of inverter 206, ensures that when NVM 261 is not programmed and TC0-TC3 are all low, the temperature coefficients of the series-connected resistors R8-R17 are approximately in the middle of their range of possible values. This simplifies lab testing. Resistors R8 and R17 may be made from either a first material type (e.g., a material having a positive temperature coefficient Rp) or a second material type (e.g., a material having a negative temperature coefficient Rn). The material type and sizing of resistors R8 and R17 relative to resistors R9-R16 are selected so that the total series resistance of the series of resistors R8-R17 exhibits a zero temperature coefficient for nominal values ​​of resistance and temperature coefficient.

[0028] In addition to the particular resistive material and nominal resistance value of the adjustable resistive network, the physical layout of the resistors of the adjustable resistive network on the integrated circuit is appropriate for achieving a zero or low temperature coefficient without introducing undesirable thermal sensitivity. FIG. 3 illustrates a top view of an example layout of an adjustable resistive network 324, and FIG. 4 illustrates a cross-section of the integrated circuit along section line AA in FIG. 3. Looking at the cross-section of FIG. 4, the resistor resides on a semiconductor wafer 406. An insulating layer 405 of deposited or grown insulating material, such as silicon dioxide, is formed on top of the semiconductor wafer 406 during fabrication. A layer of resistive thin-film material 424, such as doped polysilicon, is deposited and patterned on top of the insulating layer 405 to create an array of physical resistive segments made of resistive material of approximately constant thickness. Members of the array of physical resistive segments formed by the resistive thin-film material function as the calibration resistive segments 311 and the adjustable resistive network 324.

[0029] There are several approaches to forming an array of physical resistive segments. In one example, a resistive thin film material is deposited, photoresist is spin-on, openings are patterned in the photoresist, the material in the openings is etched away, and then the photoresist is removed. In another example, a molecular or ion beam is scanned to selectively deposit the resistive material (if slowly). In another example, the resistive material is selectively deposited through a shadow mask. In yet another example, photoresist is spin-on, holes are drilled in the photoresist where the resistive material is desired, the resistive material is deposited over the entire area, and a process to lift-off the photoresist removes the resistive material that did not fall into the holes in the patterned array.

[0030] Although the calibration resistor segment 311 is illustrated in FIGS. 3 and 4 as being on the same layer as the other segments of the adjustable resistor network, other arrangements are possible. For example, the calibration resistor segment and the adjustable resistor network segment may be located among three adjacent or nearby layers of an IC. Adjacent or nearby layers mean layers that exhibit similar average temperatures during the trim process. The calibration resistor segment may be located on the first and third layers, and the adjustable resistor network segment may be located on the second layer. As long as the average temperatures of the first and third layers are similar to the temperature of the second layer, the calibration resistor provides a good proxy for the temperature of the adjustable resistor network.

[0031] A second layer of insulating material 407 (such as silicon dioxide) is deposited on top of the resistive thin film material 424 and planarized. Openings are then etched through the second layer of insulating material 407 to form contacts 413 to the resistive thin film material. These contacts 413 can be deposited along with the first metallization layer 412, or in a second step, deposited on the surface of the second layer of insulating material 407 and polished to the surface, in which case the contacts 413 can be made from a different conductive material (such as tungsten).

[0032] A first metallization layer 412, such as aluminum or an aluminum alloy, is then formed by evaporation or sputtering, followed by patterning and etching. A third insulating layer 408 (such as silicon dioxide) is deposited on top of the first metallization layer 412 and then planarized. Although not shown in FIG. 4 , vias may be formed through the third insulating layer. Next, a second metallization layer 425, such as aluminum or an aluminum alloy, is deposited and patterned. A fourth insulating layer 409 (such as silicon dioxide) is deposited on top of the second metallization layer and then planarized. Vias 417 are patterned and etched through the fourth insulating layer 409. The conductive material filling these vias may be the third metal 416 or another conductive material (such as tungsten) that is deposited on the surface of the fourth insulating layer 409 and polished.

[0033] Next, a third metallization layer 416, e.g., aluminum or an aluminum alloy, is deposited and patterned. Finally, a fifth insulating layer 411 is deposited over the third metallization layer 416. This step completes the fabrication of the semiconductor wafer 406. While the above description assumes an aluminum or aluminum alloy metallization, fabrication techniques based on single or double damascene processes may be used to fabricate a copper or copper alloy metallization without substantially altering the final cross-section depicted in FIG. 4.

[0034] FIG. 3 shows a top view of an example tunable resistive network 324 and the layout of an example serpentine metal line 325 that forms the resistive element of the heater. The tunable resistive network 324 includes multiple resistive segments (hereinafter "segments") 302, 304. Segment 302 is made of a first resistive material, and segment 304 is made of a second resistive material. In an actual implementation of the resistive network, there may be more segments of each type than shown in this simplified illustration. In this example, the first resistive material has a small negative temperature coefficient and the second resistive material has a larger positive temperature coefficient. However, in other examples, the first resistive material has a large negative temperature coefficient and the second resistive material has a smaller positive temperature coefficient. For any given process, the relative magnitudes of the two temperature coefficients depend on the composition of the two resistive materials. In other words, the positive temperature coefficient material may have a temperature coefficient that is smaller, equal to, or larger than the absolute value of the temperature coefficient of the negative temperature coefficient material. The relative number of segments 302, 304 is selected to achieve an overall zero or near-zero temperature coefficient after trimming.

[0035] In the cross section of Figure 4, a serpentine metal resistor used as a heater is constructed on the second metallization layer 426. A metal plate (shown in Figure 4 but not in Figure 3) on the third metallization layer 416 helps improve lateral thermal conductivity and therefore functions as a heat spreader. Because metal has a much higher thermal conductivity than most insulating materials used in integrated circuits, such as silicon dioxide, the heat spreader improves lateral thermal conductivity throughout the array of resistor segments. The heat spreader is important because the vertical dimensions of the array of resistor segments are much smaller than the horizontal dimensions, so a large vertical heat flow to the substrate still occurs despite the insulating material being a poor thermal conductor. One or more of the heat spreaders may also be connected to ground or another low-impedance circuit node to reduce capacitive coupling between the resistor and other circuit components, such as the heater. Such a capacitive shielding structure is sometimes called a Faraday shield. The Faraday shield constructed on the first metallization layer 412 also serves as a heat spreader itself. In a process with only one metallization layer, the Faraday shield and heat spreader may be omitted and the heater may be constructed on the first and only metallization layer. A process with multiple metallization layers allows for the selection of the metal layer on which the heater is constructed and may include a Faraday shield and one or more heat spreader layers to reduce noise coupling between the segments and the heater.

[0036] While the examples of Figures 3 and 4 assume that both resistive materials are doped polysilicon, alternatively, one or both of the resistive materials may comprise alternative thin-film materials deposited under the first metallization layer, between metallization layers, or on top of the top metallization layer. While polysilicon resistors may have poor TCR and narrow absolute thickness tolerances, the doping levels of polysilicon resistors can be constructed and arranged to produce materials with either a negative or positive temperature coefficient. In an additional example, polysilicon is selectively silicided to reduce MOS gate resistance and improve contact resistance because silicided polysilicon exhibits a large positive temperature coefficient. Polysilicon resistors scale approximately linearly with temperature, while silicides scale approximately linearly with temperature.

[0037] As an example, one of the resistive materials in the adjustable resistive network 324 (e.g., the first resistive material of segment 302) is a high sheet resistance (HSR) polysilicon resistor, and the other resistive material in the adjustable resistive network 324 (e.g., the second resistive material of segment 304) is a low sheet resistance (LSR) polysilicon resistor. The LSR polysilicon resistive segment 304 and the HSR polysilicon resistive segment 302 have identical or substantially identical thermal properties, such as thickness, density, specific heat, and thermal conductivity, but have positive and negative TCRs, respectively. For example, when the illustrated LSR polysilicon resistive segment 304 is heated, its resistance increases uniformly or linearly at approximately +800 ppm / °C. In contrast, when the HSR polysilicon resistive segment 302 is heated, its resistance decreases uniformly or linearly at approximately -400 ppm / °C. In the trimming process, the combination of the positive TCR, LSR polysilicon resistor segments 304 and the negative TCR, HSR polysilicon resistor segments 302 in the adjustable resistor network 324 is adjusted to provide an overall network temperature coefficient of resistance of zero or near zero. Additionally, the resistor segments 302 and 304 may be advantageously constructed and arranged to reduce the impact of external thermal gradient effects, for example, by using a common centroid layout.

[0038] The trimming process begins by measuring the combined resistance of the resistor network at the temperature of the test facility, referred to below as "room temperature." This temperature may be measured by equipment external to the integrated circuit or may rely on air conditioning to maintain a nominal temperature of, for example, 25°C. Next, the power supply is controlled to provide a predetermined power pulse of a predetermined voltage level for a predetermined duration applied to the heater, with the voltage and time selected to raise the temperature of the resistor network to the desired value. A second measurement of the resistance is then taken. The appropriate time and temperature can be determined by laboratory measurements of a sample device in a suitable heating chamber or system. Subsequently, by comparing the resistance values ​​of the same sample at temperature after activating the heater at various voltages and durations, a heater voltage and duration that will achieve the desired temperature is selected. However, the performance of the sample used for characterization may not exactly match that of an actual generating unit, a factor that is addressed by the circuit elements, systems, and methods described herein.

[0039] Locating the resistive heater element in the second metallization layer 425 directly above (or directly below) the layer of resistive thin-film material 424 that forms the tunable resistor network promotes better thermal coupling and confines the heating element to a small portion of the overall circuit area, thereby heating only the tunable resistor network. The extremely tight thermal coupling reduces thermal gradients across both the negative TCR portion (including segment 302) and the positive TCR portion (including segment 304) of the tunable resistor network. The thermal coupling also provides a fast first-order thermal response time constant in the range of about 20 to about 50 microseconds (μs). This results in a settling time of less than about 100 μs, which does not significantly impact test and trimming times. In one example, when the resistive heater element in the second metallization layer 425 is energized, the local temperature of the tunable resistor network in the layer of resistive thin-film material 424 is about 30 to 60°C higher than the average temperature of the bulk silicon substrate or die. While the adjustable resistive network 120 is heating, the average temperature of the bulk silicon substrate or die remains relatively unchanged throughout the power-on phase.

[0040] Alternatively, the resistive heater element can be rapidly energized using a voltage jump, for example, from 0 V to a second voltage, approximately 48 V in one example, thereby generating a heat pulse. Energizing the resistive heater element rapidly changes the temperature (ΔT) of the resistive segments 302 and 304 of the adjustable resistor network 324, for example, by approximately 40° C. This temperature can be set by the pulse voltage level. In this manner, ΔT can affect the trimming process more than absolute temperature because it can provide a repeatable temperature look-ahead signal, allowing the combination of the first resistive segment 302 and the second resistive segment 304 to be adjusted to achieve a zero or near-zero TCR.

[0041] Returning to FIG. 2 , trim controller 260 (e.g., a 4-bit controller such as a processor, current splitter, or current miner) interfaces with adjustable resistor network 224 on lines TC0-3 and adjustable voltage source 214 on lines IREF0-3. While four lines TC0-3 and four lines IREF0-3 are illustrated, the number of lines for the TC and IREF control signals may vary, and numbers other than four may be selected depending on the desired trim resolution. On each of lines IREF0-3 and TC0-3, trim controller 260 places a constant voltage representing either a logic high or one, or a logic low or zero. In this manner, values ​​IREF0-3 may be represented as one digital word, and values ​​TC0-3 may be represented as a second digital word. Trim controller 260 may be entirely integrated on an IC, or only a portion of the controller may be integrated, with the remainder implemented in external test hardware. In either case, the trim controller calculates values ​​to place in TC0-3 to provide the lowest possible TCR and stores these calculations in nonvolatile memory (NVM) 261, which is part of trim controller 260 located on the integrated circuit. Trim controller 260 also calculates values ​​to place in IREF0-3 to set the total resistance as close as possible to the desired value and stores these calculations in NVM 262, which is part of trim controller 260 located on the integrated circuit. Then, when power is applied, the integrated portion of the trim controller can retrieve these values ​​from NVM 261 and NVM 262 and apply these values ​​to IREF0-3 and TC0-3, thereby trimming the adjustable resistor network to the proper value and minimum temperature coefficient. In other examples, the values ​​for IREF0-3 and TC0-3 can be stored in the same NVM. In other examples, NVM 261 and / or NVM 262 may not be part of trim controller 260 but may reside elsewhere on the integrated circuit.

[0042] In a simple trim algorithm, the trim controller 260 applies default values ​​for TC0-3, which can reduce temperature fluctuations when both the resistivity and temperature coefficients of the two resistive materials are equal to predetermined nominal values. The trim controller then measures the resistance of the adjustable resistive network 224 before and after the heater element 225 is energized. Using these data and the process minimum values ​​of resistivity and temperature coefficient, the trim controller can change the overall TCR of the adjustable resistive network 224 by changing the value of the digital word represented by TC0-3, thereby varying the number of first resistive material segments 302 and the number of second resistive material segments 304 in the adjustable resistive network 224.

[0043] The voltage level and duration of a given power pulse applied to heater element 225 are two factors that control the amount of heating that occurs in adjustable resistor network 224 during the trimming process. The voltage level and duration of the power pulse are determined during the initial characterization of the IC device, as described above. However, the packaging of the IC can also affect the amount of heating in the adjustable resistor network. For example, different packages contain background substrates of different thicknesses, which alter the thermal capacity of the substrate. In another example, the mold compound used to encapsulate a plastic-packaged integrated circuit may be changed. In a third example, the device may be placed in a different type of package, such as a hermetically sealed metal can or a chip-scale package with only a minimal thickness of insulating film applied to the surface of the integrated circuit. Thus, if the IC is placed in a different packaging configuration than that used for initial testing, or if some other test parameter changes, simply applying the same voltage pulse may not result in the same change in the temperature of the adjustable resistor network.

[0044] In particular, consider the case where the temperature-sensitive component is a polysilicon (poly) resistor. Because polysilicon varies only approximately linearly with temperature, a more accurate model of its behavior includes both a linear temperature coefficient and a quadratic temperature coefficient calculated by quadratic least-squares regression from measured data, rather than a single (linear) temperature coefficient calculated by linear least-squares regression. The following applies when a poly resistor is characterized by both linear and quadratic temperature coefficients. Assume a process that can fabricate poly resistors with positive and negative linear temperature coefficients (RP and RN, respectively). By properly selecting the values ​​of RP and RN and connecting them in series, parallel, or series-parallel, the linear temperature coefficient of the entire tunable resistor network is approximately zero. Because the values ​​and temperature coefficients of RP and RN both exhibit process variation, the temperature coefficient of the resistor network will vary with process. Also, the quadratic temperature coefficients of RP and RN will almost certainly not cancel each other out.

[0045] An on-chip heater can be used to measure the residual temperature coefficients and adjust the values ​​of R and R in the adjustable resistor network, thereby reducing the overall variation caused by the residual linear and quadratic coefficients of the combined adjustable resistor network. This represents a significant improvement over the simplest possible trim algorithm, which assumes process nominal values ​​for sheet resistance and temperature coefficient to extrapolate a trim code based on measurements at room and high temperatures. To obtain information that reduces the residual quadratic component of the temperature coefficient of the adjustable resistor network, it is desirable to generate a known and repeatable temperature rise when the heater is activated, regardless of the nature of the IC's packaging. This can be achieved, at least approximately, by using selected resistor segments having only positive or negative temperature coefficients as temperature-variable calibration resistors. In one example, the calibration resistor is electrically coupled to the adjustable resistor network. In another example, the calibration resistor is not electrically coupled to the adjustable resistor network, but is thermally coupled to the adjustable resistor network. It is advantageous to select resistor segments for the calibration resistors that are made of a material with a larger temperature coefficient and a smaller process variation in the temperature coefficient. By measuring the resistance of the calibration resistor both at room temperature and at the elevated temperature resulting from the heater being activated, an estimate of the elevated temperature can be obtained.

[0046] Figure 5 illustrates the resistance of a silicided poly resistor as a function of temperature. Silicides are stoichiometric compounds of silicon and certain other elements, such as titanium, cobalt, and nickel. Because silicides are deterministic compounds, they have relatively stable material properties. Also, because silicides are metallic in nature, they have a relatively large positive linear temperature coefficient (TCL) (e.g., 2000-4000 ppm / °C). Poly resistors can also have a very small quadratic temperature coefficient (TCQ) (e.g., less than 1 ppm / °C). These properties make silicides ideal for building integrated calibration resistors that can be integrated into poly resistor arrays (e.g., tunable resistance networks). These same calibration resistors can serve as the positive (or negative) segments of the tunable resistance network.

[0047] Line 505 in Figure 5 shows the nominal behavior of a particular silicided polysilicon, expressed as a normalized value R / R0. Here, R is the resistance at a given temperature, and R0 is the resistance at room temperature, assumed to be 25°C. Due to the material having a quadratic temperature coefficient of less than 1 ppm / °C, the relationship between resistance and temperature is nearly linear. The gray triangle 510 formed by the dashed line represents the limits of process variation. The small size of triangle 510 illustrates that this resistor can be used as a fairly accurate temperature sensor even without knowing its exact temperature coefficient. The relatively small process variation in the nominal resistance and the nearly perfect linearity of the calibration resistor allow for temperature extrapolation. Therefore, measuring the resistance at two temperatures (e.g., 25°C and 85°C) is sufficient to characterize the resistance of the calibration resistor over its operating temperature range (e.g., -40°C to 150°C).

[0048] However, because doped polysilicon exhibits somewhat greater nonlinearity than silicided poly, and the linear temperature coefficient (TCR) is largely offset by trimming, the quadratic temperature coefficient (TCQ) (also called the parabolic or quadratic temperature coefficient) forms an important component of the final trimmed resistance value of the resistor device, as illustrated by line 605 in FIG. 6. Due to the parabolic nature of the TCR of the adjustable resistor network, the trimming process should be performed at a precise temperature. FIG. 7 illustrates the case where the adjustable resistor network is trimmed at an actual temperature of 100°C (as indicated by line 705) rather than the intended temperature of 85°C. The extrapolation of the normalized resistance value based on these two cases is clearly different, as suggested by the dotted and dashed lines. This inaccurate temperature may be the result of voltage pulses supplied to the on-chip resistive heater that are calibrated based on different packaging arrangements of the same IC.

[0049] One approach to calculating the temperature coefficient of a tunable resistor network relies on observations regarding the nature of nonlinear temperature variations. Now, with reference to FIG. 8, mid But, T mid =(T min +T max ) / 2, where T min and T max are the minimum and maximum operating temperatures, respectively. The function of resistance with respect to temperature is T mid It can be observed that in most cases the cubic and all higher order terms affect the resistance to a much lesser extent than the quadratic terms. If the linear terms are cancelled out, leaving only the constant and quadratic terms as significant contributors to the resistance, then the resistance versus temperature function (shown by line 805) becomes T mid This shift in the resistance versus temperature function is illustrated by line 905 in Figure 9, where nom And, T mid T nom As high as the temperature T heated When measuring the resistance at (in the form of a formula, T heated =2 Tmid -T nom ), if the linear components are properly cancelled, T heated The resistance value at T nom It should be equal to the resistance at T heated The resistance value at T nom If the resistance is greater than the value at T, the positive linear temperature coefficient remains. heated The resistance value at T nom If the resistance is less than the resistance at , a negative linear temperature coefficient remains. In either case, this linear temperature coefficient TCL is equal to: TIFF2025134993000002.tif651

[0050] If temperature is measured in degrees Celsius, TCL has units of ppm / °C. The temperature coefficient trim can be set based on knowledge of the weight of each bit and the value of the linear temperature coefficient calculated as described above. As an example of this procedure, T min = -40°C, and T max = 125℃. Then, T mid = 42.5℃. nom = 25℃, T heated = 60°C. If the linear temperature coefficient is properly cancelled, R(25°C) should equal R(60°C). Measure the actual resistance at these two temperatures and assume R(25°C) = 101.6 kΩ and R(60°C) = 102.2 kΩ. The linear temperature coefficient then equals TCL = 169 ppm / °C.

[0051] Referring again to FIG. 3 , to address this potential variation in the thermal response of the adjustable resistor network and the resulting suboptimal trimming process, the highly temperature-sensitive calibration resistor segment 311 is placed in close proximity to the adjustable resistor network 324 so that it is thermally coupled to the adjustable resistor network. As used herein, “thermally coupled” means that the calibration resistor segment 311 is in close thermal contact with the adjustable resistor network or is close enough to exhibit a very similar thermal or temperature response compared to the adjustable resistor network. The calibration resistor segments may be distributed as evenly as possible across the adjustable resistor network. The calibration resistor and the adjustable resistor network are not used simultaneously, so one or more segments of the adjustable resistor network may be connected to selectively act as the calibration resistor.

[0052] For example, the resistive segments 311 of the calibration resistor may be interdigitated with the remaining segments of the adjustable resistive network, meaning that the segments of the calibration resistor are on the same integrated circuit layer as the segments of the adjustable resistive network and are interspersed among the segments of the adjustable resistive network.

[0053] Interdigitation is a type of common centroid layout. The centroid of a two-dimensional shape (e.g., an integrated device) is equal to the geometric mean of the locations of all points within that shape. A simple method for finding the centroid is to apply the principle of centroid symmetry, which states that the centroid of a shape lies on any axis of symmetry that passes through it. A rectangle is bisected by vertical and horizontal axes of symmetry, and the centroid is at their intersection. The idea behind common centroid layout is that the effect of a static spatial temperature gradient on two matching devices is proportional to the separation between their centroids. Therefore, reducing the centroid separation between devices to zero cancels the effect of a (linear) temperature gradient on matching. For example, in a tunable resistor array, each device may contain two separate rectangular regions (e.g., resistor segments): two of the rectangular regions belong to resistor A and two of the rectangular regions belong to resistor B. If these segments are arranged in an ABBA order, the centroids of the two A segments are midway between them (another application of the centroid symmetry principle). Similarly, the centroids of the two B segments are midway between them. Therefore, these two centroids align and the device is placed in a common centroid array. This type of common centroid array is called interdigitated because the segments slide between each other like two interdigitated fingers of a hand.

[0054] In this example, the calibration resistor segment 311 includes four RP segments 304 of the adjustable resistor network 324. In other examples, the calibration resistor may be electrically isolated from the adjustable resistor network 324 but may have segments interdigitated with the adjustable resistor network 324. The calibration resistor may be a selected plurality of RN segments or a selected plurality of RP segments, with either type (RN or RP) having a relatively large linear temperature coefficient. The relative variation in temperature coefficient of the selected segments over process is much smaller than the relative variation of the combined adjustable resistor network. This is because the combined resistor network incorporates both RP and RN segments in an effort to lower the overall temperature coefficient of the adjustable resistor network. The RP and RN segments are typically interdigitated for matching purposes, providing close thermal contact and reducing the effects of lateral thermal gradients generated by other components on the integrated circuit during normal operation.

[0055] Returning to FIG. 2 , interface circuitry provides one or more electrical connections that allow the resistance of the calibration resistor to be measured. In the illustrated example, the interface circuitry includes bond pad 275 and NMOS transistors 276, 277 so that the resistance of the calibration resistor can be measured directly with an external ohmmeter or other resistance-measuring device. Conductive pad or bond pad 275 allows connection by wire bond (or probe needle, if testing is performed at a probe) to the top of resistor R13 (which is the calibration resistor that includes segment 311 in FIG. 3 ). When activated, NMOS transistors 276, 277 electrically isolate the calibration resistor from the adjustable resistance network, allowing the resistance of the calibration resistor to be measured.

[0056] NMOS transistor 276, also referred to as the calibration switch, connects the low side of resistor R13 to ground when a calibration measurement is performed. The calibration measurement process is triggered by applying a calibration signal comprising a constant voltage representing a logic high or one to calibration trigger input C at the gate of NMOS transistor 276. In an alternative example, a logic low or zero may be used to measure the calibration resistor using a different type of switch. In response to a quiesce signal (which in the example of FIG. 2 is also calibration signal C), NMOS transistor 277, also referred to as the current source quiesce switch, causes amplifier 202 to disable NMOS transistor 203, thereby preventing current from flowing from IBIAS to bonding pad 275 during calibration. In this way, the only current flowing from IBIAS to bonding pad 275 during calibration is the current flowing from bonding pad 275 to ground (through calibration resistor R13).

[0057] The calibration resistance value of the calibration resistor measured using the interface circuitry serves as a proxy for the temperature of the calibration resistor and, due to their thermal proximity, the temperature of the adjustable resistor network. Thus, by measuring the calibration resistance value, one can confirm that the adjustable resistor network is heated to the desired temperature during trimming.

[0058] An exemplary heater calibration system 270 includes a processor 272 and an ohmmeter 271 (or other circuitry for measuring resistance) connectable to a bonding pad 275. In one example, the heater calibration system 270 is implemented in circuitry external to the IC. In another example, the heater calibration system 270 is implemented in circuitry located within the IC. During the calibration process, the processor 272 generates a power supply (PS) control signal that controls an external power supply to provide a predetermined power pulse (PP) to the input V3 for the heater during trimming of the adjustable resistor network 224. The processor 272 also generates a logic high or 1 value for the calibration trigger C. The ohmmeter 271 measures the calibration resistance of the calibration resistor R13 via the bonding pad 275. Processor 272 compares the calibration values ​​stored in NVM 287 (e.g., the calibrated resistance values ​​or the "expected" / calibrated temperature rise) to values ​​that processor 272 derives from the measured calibrated resistance values. Although NVM 287 is shown included in trim controller 260, NVM 287 may be located elsewhere on the IC. The calibration values ​​may be stored in an NVM that stores other values, such as NVM 261 or NVM 262.

[0059] Ohmmeter 271 may or may not be external to the IC, while other components, such as NVM 287, are included in the IC. In another example, rather than an external ohmmeter, an analog-to-digital converter (ADC) on the IC may be used to measure the calibration resistor value by converting the voltage measured across the calibration resistor when a given current is injected into the calibration resistor and delivering the digital result. In effect, the ADC and current source function as an on-chip ohmmeter. In this example, the interface circuitry may not include NMOS transistors 276, 277 or bond pad 275, but instead may include appropriate connection features for connecting the calibration resistor to the ADC and current source.

[0060] The heater calibration system 270 generates a temperature result that may indicate an estimated heating amount of the adjustable resistor network based on the measured calibration resistance value. The result may be a yes / no indication of whether the adjustable resistor network has heated to within a desired temperature tolerance (i.e., the measured resistance value matches the calibration resistance value). The result may be used to trigger a recalibration of the power pulses PP provided to the heater elements 225.

[0061] FIG. 10 is a flowchart outlining an example method 1000 for calibrating the temperature coefficient of a tunable resistor network in an integrated circuit (IC) installed in a packaging arrangement. Method 1000 may be implemented, for example, by trim controller 260 of FIG. 2. The method includes, at 1010, measuring a first resistance value of the tunable resistor network at a first temperature. The first temperature is often room temperature or approximately 25° C., but may also be another temperature imposed on the chip by a temperature forcing system. Note that this resistance measurement is of the entire tunable resistor network as described above for the trimming process, and not of the calibration resistor. The resistance value may be measured by applying predetermined values ​​to TC0-3 and IREF0-3 of FIG. 2 and measuring the bias current IBIAS, or by any other technique capable of measuring the total resistance value of tunable resistor network 224.

[0062] At 1020, a predetermined power pulse is selected based on the packaging configuration. The predetermined power pulse has a predetermined magnitude of power for a predetermined time. The appropriate power and duration of the power pulse can be estimated by characterizing the integrated circuits constructed in a particular packaging configuration. First, these devices are placed in an oven or thermal forcing system, and a calibration resistor is measured at various known temperatures. The devices are then brought to the first temperature referenced in step 1010, a power pulse is applied, and the calibration resistance value is measured immediately thereafter (e.g., within a few microseconds). By comparing this resistance value with previously measured resistance values ​​of the calibration resistor at various temperatures, the temperature can be estimated. This process is repeated with different power pulses to determine the amount of power and power application time used as the predetermined power pulse to achieve a desired second temperature, e.g., 85°C. In this manner, the predetermined power pulse is selected to produce a calibrated temperature rise (e.g., 60°C) in the device under test.

[0063] At 1030, a predetermined power pulse is applied to a heater element within the IC to heat the adjustable resistor network to a second temperature. At 1040, the resistance of the resistor network is measured (again) using the same predetermined values ​​of TC0-3 and IREF0-3 applied at 1010. At 1050, the linear two-point temperature coefficient of the adjustable resistor network is calculated. In one example, the linear two-point temperature coefficient is calculated by taking the difference between the second resistance value and the first resistance value, dividing by the first resistance to normalize the result, dividing by one million to convert the result to parts per million (ppm), and dividing by the "expected" / calibrated temperature rise calculated at 1020. At 1060, the appropriate trim is selected to reduce the temperature coefficient of the adjustable resistor network. This may be accomplished by selecting appropriate values ​​for TC0-3 based on the temperature coefficient calculated in 1050 and knowledge of the effect of each trim bit TC0-3 on the temperature coefficient of the adjustable resistor network, as derived from simulation or characterization. The effects of both linear and quadratic components of the temperature coefficient of the adjustable resistor network may be considered, and a trim configuration may be selected that reduces resistance value deviation over the entire temperature range. In 1070, the NVM is programmed (e.g., selected values ​​of TC0-3 are programmed into NVM 261 (see FIG. 2)) with the appropriate trim to reduce the temperature coefficient of the adjustable resistor network.

[0064] One advantage of an integrated calibration resistor is that it can be used to verify that the packaging configuration of the integrated circuit under test corresponds to the packaging configuration initially used during the determination of the predetermined power pulse for the heater. FIG. 11 is a flowchart outlining an example method 1100 for setting the temperature coefficient of a tunable resistor network, including this packaging verification. Method 1100 may be implemented, for example, by processor 272 of heater calibration system 270 of FIG. 2. At 1110, a first resistance value of the tunable resistor network is measured at a first temperature (e.g., room temperature). At 1120, a first resistance value of the calibration resistor is measured at the first temperature. At 1130, a predetermined power pulse is selected (e.g., based on the packaging configuration used during initial characterization). At 1140, the power pulse is applied to the heater. At 1150, a second resistance value of the tunable resistor network at a second (elevated) temperature is measured. A second resistance value of the calibration resistor is measured at a (same) second temperature at 1160. At 1170, the temperature coefficient of the resistance value of the adjustable resistor network is calculated.

[0065] At 1175, a calculated (elevated) temperature of the adjustable resistor network is calculated based on the first and second measured resistance values ​​of the calibration resistor. In one example, the “estimated” calculated temperature is calculated by dividing the second measured resistance value of the calibration resistor by the first measured resistance value to determine a value of R / R0, and indexing this value against line 505 of FIG. 5 , which represents the nominal behavior of the calibration resistor, to determine the second temperature. For example, if line 505 represents the calibration resistor used and the second measured calibration resistance value is 1.2 times the first measured calibration resistance value, the second temperature would be 100°C, and the “estimated” calculated temperature rise resulting from operating the heater with a given power pulse would be 75°C. At 1180, a determination is made as to whether the “estimated” calculated temperature rise is comparable (e.g., within tolerance) to the “expected” / calibrated temperature rise (e.g., 60°C determined during characterization at 1020 of method 1000). Because room temperature can fluctuate slightly, an "estimated" calculated temperature rise is used rather than an absolute calculated temperature to mitigate the effects of fluctuations in the first temperature. If the "estimated" calculated temperature rise matches the "expected" / calibrated temperature rise within a reasonable error margin (e.g., ±20%), the method proceeds to 1185, where the adjustable resistor network is adjusted to reduce its temperature coefficient. If the "estimated" / calculated temperature rise is not within the expected range, then at 1196, the unit is discarded as bad and testing of that unit is terminated. If a large number of units are discarded in this manner, the test engineer may decide to determine a new amount of power and / or time to apply that power as a new power pulse to be used in testing the units.

[0066] FIG. 12 is a flowchart outlining an example method 1200 for automatically adjusting the power pulse applied to a heater element during a trimming process. Method 1200 may be implemented, for example, by processor 272 of heater calibration system 270 of FIG. 2. Method 1200 may not involve operator intervention or test program rewriting to adjust the power pulse. This is because the same test method can be used for all packaging configurations of ICs that include an adjustable resistor network. Also, because method 1200 automatically compensates for variations in heater metallization resistance, using method 1200 means that a constant power may not be applied to the heater, only a constant voltage.

[0067] At 1210, a first resistance value of the adjustable resistor network is measured at a first temperature (e.g., room temperature). At 1220, a first resistance value of the calibration resistor is measured at the first temperature. At 1230, a predetermined power pulse is selected (e.g., based on the packaging configuration used during initial characterization). At 1240, the power pulse is applied to the heater. At 1250, a second resistance value of the adjustable resistor network is measured at a second (elevated) temperature. At 1260, a second resistance value of the calibration resistor is measured at the (same) second temperature. At 1270, the temperature coefficient of the resistance value of the adjustable resistor network is calculated.

[0068] At 1275, a calculated (elevated) temperature of the adjustable resistance network is calculated based on the first and second measured resistance values ​​of the calibration resistor. In one example, the "estimated" / calculated temperature is calculated by dividing the second measured resistance value of the calibration resistor by the first measured resistance value to determine a value of R / R0, and indexing this value against line 505 of FIG. 5, which represents the nominal behavior of the calibration resistor, to determine the second temperature. For example, if line 505 represents the calibration resistor used and the second measured calibration resistance value is 1.2 times the first measured calibration resistance value, the "estimated" / calculated temperature would be 100°C, and the "estimated" / calculated temperature rise resulting from operating the heater with a given power pulse would be 75°C. At 1280, a determination is made as to whether the "estimated" / calculated temperature rise is comparable to (e.g., within tolerance of) the "expected" / calibrated temperature rise value (e.g., 60° C. determined during characterization at 1020 of method 1000). Because room temperature can fluctuate slightly, the "estimated" / calculated temperature rise is used rather than the absolute calculated temperature to mitigate the effects of fluctuations in the first temperature. If the "estimated" / calculated temperature rise matches the "expected" / calibrated temperature rise within a reasonable margin of error (e.g., ±10%), the method proceeds to 1285, where the tunable resistor network is adjusted to reduce its temperature coefficient.

[0069] If the "estimated" / calculated temperature rise does not fall within the expected range, then at 1290 it is determined whether the "estimated" / calculated temperature rise is within some extended range of the "expected" / calibrated temperature rise. If so, then at 1297 a modified power pulse is determined for use in subsequent unit testing. The current power pulse may be modified based on the "estimated" / calculated temperature rise, and parameters describing the modified pulse are saved for further unit testing. At 1298, after cooling, the modified pulse is applied to the unit to complete the trim operation. If at 1280 the "estimated" / calculated temperature rise is not within the expected range and is outside the extended range of the "expected" / calibrated temperature rise, then at 1299 the unit is deemed bad and discarded.

[0070] There are several ways to modify a given power pulse based on an "estimated" / calculated temperature rise (e.g., in 1297). In one example, a modified value of the applied voltage (while holding the application time constant) is calculated by multiplying the voltage of the given power pulse by the "estimated" / calibrated temperature rise and dividing by the "estimated" / calculated temperature rise. In another example, the modified value V of the voltage of the given pulse is calculated by multiplying the voltage of the given power pulse by the "estimated" / calibrated temperature rise and dividing by the "estimated" / calculated temperature rise. mod The modified value of V is used to replace the previously used voltage V old , "expected" / calibrated temperature rise ΔT exp , and the "estimated" / calculated temperature rise ΔT est It is calculated using the following formula: TIFF2025134993000003.tif449 where the attenuation constant k is a constant greater than zero and less than one (e.g., 0.1). The constant k provides attenuation such that if a single measurement deviates significantly from the desired value due to imperfections in the device under test, it does not unduly affect the measurements of subsequent units.

[0071] In another example, a new time period for which an existing voltage is applied is calculated to determine a modified power pulse. This approach allows a constant voltage source to be used to drive the heater, which can be advantageous, for example, when testing multiple units in parallel.

[0072] 13 is a flowchart outlining an example method 1300 for calibrating a heater that heats an adjustable resistive network during a trimming procedure in response to a power pulse having a predetermined voltage level and duration. Method 1300 may be implemented by processor 272 of FIG. 2. The method includes, at 1310, commanding a power supply to provide a power pulse to the heater. The method includes, at 1320, measuring a resistance value of a calibration resistor thermally coupled to the adjustable resistive network. The method includes, at 1330, reading a calibration value for the calibration resistor. The method includes, at 1340, adjusting the predetermined voltage level or duration of the power pulse based on a comparison of the calibration value to a value based on the measured resistance value.

[0073] As mentioned above, the quality of the trimming results can be improved by providing a calibration resistor to more directly determine the temperature of the adjustable resistor network during trimming.

[0074] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. Thus, if device A generates a signal to control device B to perform an action, (a) in a first example, device A is directly coupled to device B, or (b) in a second example, device A is coupled to device B through an intervening component C, where intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A through the control signal generated by device A.

[0075] Although these methods are illustrated and described above as a series of acts or events, the illustrated order of such acts or events is not limiting. For example, some acts or events may occur in a different order and / or concurrently with other acts or events apart from those illustrated and / or described herein. Also, some illustrated acts or events are optional for implementing one or more aspects or embodiments of the present description. Also, one or more acts or events depicted herein may be performed in one or more separate acts and / or phases. In some embodiments, the methods described above may be implemented in a computer-readable medium using instructions stored in a memory.

[0076] Modifications in the described examples are possible and other implementations are possible within the scope of the claims.

Claims

1. A circuit comprising: an adjustable resistive network including a first resistive segment; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including a second resistive segment thermally coupled to the first resistive segment; an interface circuit element coupled to the calibration resistor; The circuit includes:

2. 2. The circuit of claim 1, The circuit, wherein the first resistive segment is disposed on a layer of an integrated circuit and the second resistive segment is also disposed on the layer.

3. 2. The circuit of claim 1, A circuit, wherein the first resistive segment is disposed on a first layer of an integrated circuit, and the second resistive segment is disposed on a second layer of the integrated circuit, the first layer being adjacent or proximate to the second layer.

4. 2. The circuit of claim 1, A circuit wherein the first resistive segment is a member of an array of physical resistive segments fabricated from a resistive material, and the second resistive segment is a member of the array of the physical resistive segments.

5. 2. The circuit of claim 1, The second resistive segment is interdigitated with the first resistive segment.

6. 2. The circuit of claim 1, The second resistive segment belongs to the first resistive segment.

7. 2. The circuit of claim 1, The second resistive segment does not belong to the first resistive segment.

8. 2. The circuit of claim 1, The circuit, wherein the interface circuit element includes a conductive pad coupled to the calibration resistor.

9. 2. The circuit of claim 1, The circuit, wherein the interface circuit element includes one or more switches that, when activated, electrically isolate the calibration resistor from the adjustable resistance network.

10. 1. A system comprising: an adjustable resistor network; a calibration resistor thermally coupled to the adjustable resistance network; an interface circuit element coupled to the calibration resistor; a heater thermally coupled to the adjustable resistance network; a processor coupled to the heater and the interface circuitry; wherein the processor: Retrieve the calibration values ​​from non-volatile memory, generating a power control signal to apply a power pulse to the heater; measuring the resistance of the calibration resistor with the interface circuitry; adjusting the power supply control signal to vary the voltage level or duration of the power pulse based on a comparison of the calibration value with a value based on the measured resistance value; The system is configured as follows:

11. 11. The system of claim 10, the processor: calculating a temperature of the adjustable resistor network based on the measured resistance; determining a calculated temperature rise based on the calculated temperature; comparing the calculated temperature rise to a calibrated temperature rise indicated by the calibration value stored in the non-volatile memory; adjusting the power pulses based on the comparison. The system is configured as follows:

12. 11. The system of claim 10, the interface circuitry includes a plurality of switches configured, when actuated, to electrically isolate the calibration resistor from the adjustable resistance network; The system, wherein the processor is configured to generate a calibration signal that actuates the plurality of switches.

13. 1. A method comprising: Using a processor, commanding a power supply to provide a power pulse to the heater; measuring the resistance of a calibration resistor thermally coupled to the adjustable resistance network; reading a calibration value for the calibration resistor; adjusting the power pulses based on a comparison of the calibration value to a value based on the measured resistance; A method comprising:

14. 14. The method of claim 13, Using the processor, determining a calculated temperature rise of the adjustable resistor network in response to heat from the heater based on the measured resistance value; comparing the calculated temperature rise to the calibration value, the calibration value indicating a calibrated temperature rise; selectively modifying the power pulse based on a comparison of the calculated temperature rise and the calibrated temperature rise; A method comprising:

15. 15. The method of claim 14, and, with the processor, selectively modifying a voltage level of the power pulse based on a product of the voltage level and the calibrated temperature rise divided by the calculated temperature rise.

16. 15. The method of claim 14, The processor is used to determine a first voltage level (V ｏｌｄ ) and the calibrated temperature rise (ΔT ｅｘｐ ) and the calculated temperature rise (ΔT ｅｓｔ ) and a decay constant k having a value between 0 and 1, ｍｏｄ ), wherein the relationship is V ｍｏｄ =V ｏｌｄ (1 + k (ΔT ｅｘｐ / ΔT ｅｓｔ -1)).

17. 15. The method of claim 14, and selectively modifying, with the processor, a duration of the power pulse based on a comparison of the calculated temperature rise to the calibrated temperature rise.

18. 14. The method of claim 13, Using the processor, measuring a first resistance value of the calibration resistor at a first temperature; raising the adjustable resistive network to a second temperature; measuring a second resistance value of the calibration resistor at the second temperature; determining the calibration value by storing a value derived from the second resistance value as the calibration value; A method comprising:

19. 20. The method of claim 18, Using the processor, determining a calibrated temperature rise of the adjustable resistor network in response to heat generated by the heater based on the measured resistance value; storing the calibrated temperature rise as the calibrated value; A method comprising:

20. 14. The method of claim 13, generating, with the processor, calibration signals that actuate a plurality of switches to electrically isolate the calibration resistor from the adjustable resistance network before measuring the resistance value.

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