Protection element and I / O circuit including the same

Abstract

To solve such a problem that there is room for further consideration for suppressing an increase in circuit area on an ESD protection function.SOLUTION: A protection element (X) includes a drain region (3) electrically connected to an external terminal (T1), a gate region (4) formed as a gate, a source region (2) formed as a source, and a back gate region (5) formed as a back gate. The source region (2) includes: a low resistance region (2b) electrically connected to the gate region (4) directly or through a resistive element (10); and a high resistance region (2a) having a resistance value higher than that of the low resistance region (2b). The low resistance region (2b) is electrically connected to the back gate region (5) through the high resistance region (2a).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a protection element and an I / O (Input / Output) circuit including the same. [Background technology]

[0002] Conventionally, an I / O circuit including a protection element is used as an ESD (Electro Static Discharge) protection function for the internal circuit of a semiconductor device.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-258200

[0005] [overview] The ESD protection function disclosed in Patent Document 1 leaves room for further consideration in order to prevent an increase in circuit area.

[0006] The protection element disclosed in this specification includes a drain region, a gate region, a source region, and a back gate region. The drain region is electrically connected to an external terminal. The gate region is formed as a gate. The source region is formed as a source. The back gate region is formed as a back gate. The source region includes a low resistance region electrically connected to the gate region directly or via a resistance element, and a high resistance region having a resistance value higher than that of the low resistance region. The low resistance region is electrically connected to the back gate region via the high resistance region.

[0007] The I / O circuit disclosed in this specification includes a protection element having the above configuration and a resistance element connected between the gate region and the source region.

[0008] The I / O circuit disclosed in this specification includes a plurality of protection elements having the above-described configuration, and the back gate region of each protection element is common. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the internal configuration of a semiconductor device 1 of the comparative example. [Figure 2] FIG. 2 is an enlarged layout diagram showing a part of the internal configuration of the I / O circuit 100Y. [Figure 3] FIG. 3 is a diagram showing the semiconductor device 1 of the present disclosure. [Figure 4] FIG. 4 is an enlarged layout diagram showing a part of the internal configuration of the I / O circuit 100X. [Figure 5] FIG. 5 is a cross-sectional perspective view showing a part of the internal structure of the protection element X. As shown in FIG. [Figure 6] FIG. 6 is a graph showing the relationship between the trigger voltage V1 and the breakdown voltage V2 of the protection element X. [Figure 7] FIG. 7 is a diagram showing the configuration of a modified example of the protection element X of the present disclosure. [Figure 8] FIG. 8 shows the trigger voltage V1′ and breakdown voltage V2′ of the protective element according to the modified example. [Figure 9] FIG. 9 is a diagram showing the configuration of a further modified example of the protection element X. In FIG. [Figure 10] FIG. 10 is a perspective cross-sectional view showing a part of another modified example of the protection element X. In FIG. [Figure 11] FIG. 11 is a diagram showing the configuration of a further modified example of the I / O circuit 100X.

[0010] [Detailed explanation] <Regarding the I / O circuit 100Y of the comparative example> First, the I / O circuit 100Y will be described as a comparative example to the protection element X and I / O circuit 100X of the present disclosure. Next, problems with the comparative example will be described, followed by a description of the protection element X and I / O circuit 100X of the present disclosure. The I / O circuits 100Y and 100X can be mounted on a semiconductor device 1. The semiconductor device 1 is an LSI (Large Scale Integration) that combines digital and analog circuits.

[0011] 1 is a diagram showing the internal configuration of a semiconductor device 1 of a comparative example. As shown in FIG.

[0012] The I / O circuit 100Y is responsible for ESD protection and signal input / output functions for the internal circuit 50. The internal circuit 50 is a digital / analog circuit having a predetermined function formed inside the I / O circuit 100Y.

[0013] The I / O circuit 100Y includes an external terminal T1, a protection element Y, and a resistance element 10. The external terminal T1 is used as a signal input / output terminal, a power supply terminal, or a ground terminal for communication with the outside of the semiconductor device 1. The protection element Y is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0014] The drain terminal of the protection element Y is connected to the external terminal T1. The gate terminal of the protection element Y is connected to a first terminal of the resistor element 10. The source terminal of the protection element Y, together with the back gate of the protection element Y and the second terminal of the resistor element 10, is connected to the ground terminal GND. The first terminal of the internal circuit 50, together with the drain terminal of the protection element Y, is connected to the external terminal T1. The second terminal of the internal circuit 50, together with the source terminal of the protection element Y, is connected to the ground terminal GND.

[0015] The protection element Y may be a P-channel MOSFET. In this case, the source terminal of the protection element Y is connected to the external terminal T1. In this case, the drain terminal of the protection element Y, together with the back gate of the protection element Y and the second terminal of the resistor element 10, is connected to the ground terminal GND.

[0016] 2 is an enlarged layout diagram showing a portion of the internal configuration of the I / O circuit 100Y. As shown in FIG. 2, the I / O circuit 100Y is provided with a plurality of protection elements Y. The protection elements Y are arranged in a first direction (the up-down direction in this figure).

[0017] The protection element Y includes a source region 2, a drain region 3, a gate region 4, and a back gate region 5.

[0018] The source regions 2 and the drain regions 3 are arranged alternately in a first direction. The source regions 2 and the drain regions 3 are formed on a P-type well region (not shown). The source regions 2 and the drain regions 3 are formed of an N-type semiconductor.

[0019] The source region 2 is a region formed as the source of the protection element Y. The source region 2 is entirely silicided.

[0020] The drain region 3 is a region formed as the drain of the protection element Y. The entire drain region 3 is silicided. A non-silicide region 6 is formed around the drain region 3. Details of the non-silicide region 6 are as follows.

[0021] The non-silicide region 6 is formed in a ring shape so as to surround the entire drain region 3. The non-silicide region 6 has a lower impurity concentration and a higher electrical resistance value than the silicided regions (here, the source region 2 and the drain region 3).

[0022] The non-silicide region 6 is formed through the following first to fourth processes. In the first process, a silicide blocking layer (for example, a layer of oxide film) is overlaid on a target region (the region where the non-silicide region 6 is to be formed) on the silicon wafer. In the second process, a metal film (specifically, a cobalt film, a nickel film, a titanium film, etc.) is formed on the surface of the silicon wafer by sputtering. At this time, the formation of the metal film is inhibited by the silicide blocking layer in the portion where the silicide blocking layer on the silicon wafer overlaps. In the third process, the silicon wafer is heated. At this time, the portion where the metal film is formed is silicided. In other words, the portion where the formation of the metal film is inhibited (the portion where the silicide blocking layer is overlaid) is not silicided. In the fourth process, the metal film and the silicide blocking layer are removed. Through these first to fourth processes, the region that is not silicided becomes the non-silicide region 6.

[0023] The gate region 4 is located between the source region 2 and the drain region 3 with respect to the first direction. The gate region 4 is a region formed as the gate of the protection element Y. As described above, the gate region 4 is electrically connected to the source region 2 through a resistance element 10 disposed outside the protection element Y (see FIG. 1).

[0024] The back gate region 5 is formed as a common back gate for each protection element Y. The back gate region 5 is formed of a P-type semiconductor. The back gate region 5 is formed in an annular shape so as to surround the drain region 3 and the source region 2 of each protection element Y. The back gate region 5 is electrically connected and conductive to the source region 2 of each protection element Y.

[0025] <Regarding the ESD protection function> As described above, the I / O circuit 100Y has an ESD protection function for protecting the internal circuit 50 from surges. This ESD protection function is established by the resistance element 10 lowering the trigger voltage of the protection element Y to a voltage value lower than the breakdown voltage V2. Specifically, it is as follows.

[0026] In the protection element Y, a parasitic bipolar transistor (not shown) is formed by the drain region 3, the P-type well region (not shown), and the source region 2. The trigger voltage described above is a voltage at which the parasitic bipolar transistor of the protection element Y becomes conductive (ON). When the parasitic bipolar transistor becomes conductive, a current flows from the external terminal T1 through the parasitic bipolar transistor to the ground terminal GND.

[0027] As described above, the I / O circuit 100Y is set so that the trigger voltage is lowered below the breakdown voltage V2 by using the resistive element 10. The breakdown voltage V2 is the voltage at which the internal circuit 50 is broken down.

[0028] Suppose an overvoltage occurs at the external terminal T1 due to ESD or the like. Then, when the voltage at the external terminal T1 reaches the trigger voltage, the parasitic bipolar transistor of the protection element Y becomes conductive. As a result, the current caused by the overvoltage does not flow into the internal circuit 50 but flows into the ground terminal GND. In this way, the I / O circuit 100Y performs the ESD protection function for the internal circuit 50.

[0029] <Considerations regarding circuit area> However, the number of components in the I / O circuit 100Y increases due to the placement of the resistive element 10. Furthermore, the placement of the resistive element 10 increases the circuit area of ​​the I / O circuit 100Y.

[0030] To address this problem, the protection element X and I / O circuit 100X of the present disclosure are capable of lowering the trigger voltage while suppressing increases in circuit area and the number of components. The protection element X and I / O circuit 100X according to each embodiment of the present disclosure will be described in detail below. The protection element X and I / O circuit 100X according to each embodiment of the present disclosure include components common to the protection element Y and I / O circuit 100Y described above. Therefore, the common components are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0031] <Regarding the Protection Element X and the I / O Circuit 100X of the First Embodiment of the Present Disclosure> Fig. 3 is a diagram illustrating a semiconductor device 1 according to the present disclosure. As illustrated in Fig. 3, an I / O circuit 100X according to the present disclosure can be mounted on the semiconductor device 1, similar to the I / O circuit 100Y. The I / O circuit 100X includes an external terminal T1 and a protection element X. The protection element X is an N-channel MOSFET.

[0032] The drain terminal of the protection element X is connected to the external terminal T1. The gate terminal of the protection element X, together with the source terminal of the protection element X, is connected to the ground terminal GND. The source terminal of the protection element X is electrically connected to the back gate via a high-resistance region 2a inside the protection element X. The first terminal of the internal circuit 50, together with the drain terminal of the protection element X, is connected to the external terminal T1. The second terminal of the internal circuit 50, together with the source terminal of the protection element X, is connected to the ground terminal GND.

[0033] 4 is a layout diagram showing an enlarged view of a portion of the internal configuration of the I / O circuit 100X. As shown in Fig. 4, the I / O circuit 100X is provided with a plurality of protection elements X. The protection elements X are arranged in a first direction (the up-down direction in this figure).

[0034] 5 is a cross-sectional perspective view partially illustrating the internal configuration of the protection element X. As shown in FIGS. 4 and 5, the protection element X includes a source region 2x, a drain region 3, a gate region 4, and a back gate region 5.

[0035] The source regions 2x and the drain regions 3 are arranged alternately in the first direction. The source regions 2x and the drain regions 3 are formed on a P-type well region 8. The source regions 2x are formed of an N-type semiconductor.

[0036] The source region 2x is a region formed as the source of the protection element X. The source region 2x includes a high-resistance region 2a and a low-resistance region 2b. The high-resistance region 2a has a higher electrical resistance value than the low-resistance region 2b. The high-resistance region 2a is a region that is not silicided. The low-resistance region 2b is a region that is silicided. The high-resistance region 2a is formed in the same manner as the non-silicide region 6. The high-resistance region 2a has a lower impurity concentration than the low-resistance region 2b.

[0037] The source region 2x is electrically connected to the back gate region 5 via the high resistance region 2a. More specifically, a pair of low resistance regions 2b are arranged with the high resistance region 2a sandwiched between them in a second direction (the left-right direction in FIG. 4) perpendicular to the first direction. Of the pair of low resistance regions 2b, the one farther from the connection node n between the source region 2x and the back gate region 5 is directly electrically connected to the gate region 4 (not shown). Of the pair of low resistance regions 2b, the one closer to the connection node n between the source region 2x and the back gate region 5 is directly electrically connected to the back gate region 5. In this way, the high resistance region 2a is arranged between the pair of low resistance regions 2b and electrically connected to each other, so that the low resistance region 2b, which is the majority of the source region 2x, is electrically connected to the back gate region 5 via the high resistance region 2a and becomes conductive.

[0038] The low resistance regions 2b of each protection element X are positioned to overlap with each other in the second direction. In other words, the low resistance regions 2b are aligned in a straight line along the first direction.

[0039] The gate region 4 is disposed in the first direction between the source region 2x and the drain region 3. As described above, the gate region 4 is electrically connected to the source region 2x.

[0040] The back gate region 5 is formed as a common back gate for each protection element X. The back gate region 5 is formed of a P-type semiconductor. The back gate region 5 is formed on the P-type well region 8. The back gate region 5 is formed in an annular shape so as to surround the drain region 3 and the source region 2x of each protection element X. As described above, the back gate region 5 is electrically connected to and conducts with the source region 2x of each protection element X.

[0041] An NPN-type parasitic bipolar transistor 9 is formed by the drain region 3, the P-type well region 8, and the source region 2x (the dashed part shown in FIG. 5). The emitter of the parasitic bipolar transistor 9 is connected to the source region 2, the collector is connected to the drain region 3, and the base is connected to the back gate region 5.

[0042] <Regarding the ESD protection function> Similar to the previous protection element Y, the protection element X functions as an ESD protection for the internal circuit 50. Specifically, it is as follows.

[0043] FIG. 6 is a graph showing the relationship between the trigger voltage V1 and the breakdown voltage V2 of the protection element X. Assume that an overvoltage occurs at the external terminal T1 due to ESD or the like. Then, as shown in FIG. 6, when the drain region 3 (the collector of the parasitic bipolar transistor 9) reaches the trigger voltage V1, the parasitic bipolar transistor 9 conducts and enters the snap-back region i. As a result, a surge current flows from the external terminal T1 through the parasitic bipolar transistor 9 to the ground terminal GND. More specifically, it is as follows.

[0044] Let's say that a surge such as ESD causes the voltage at external terminal T1 (i.e., the voltage applied to the collector of parasitic bipolar transistor 9) to reach trigger voltage V1. Then, part of the surge current flows from the collector to the base via the base to the ground terminal GND. At this time, the combined resistance of resistance component 11 in the P-type well region and high-resistance region 2a increases the base voltage of parasitic bipolar transistor 9. As a result, part of the surge current begins to flow from the base to the emitter of parasitic bipolar transistor 9. Then, parasitic bipolar transistor 9 turns on (conducts).

[0045] As described above, the combined resistance of the current path from the collector to the base to the ground terminal GND includes the resistance of the high-resistance region 2a. Therefore, compared to the aforementioned protection element Y, which does not have the high-resistance region 2a, the base voltage of the parasitic bipolar transistor 9 increases significantly when a current flows from the collector to the base to the ground terminal GND. In other words, the voltage at which the parasitic bipolar transistor 9 turns on, and thus the trigger voltage, is lowered. Therefore, the high-resistance region 2a reduces the trigger voltage V1 to a voltage value lower than the breakdown voltage V2, enabling the ESD protection function of the protection element X to operate before the external terminal T1 reaches the breakdown voltage V2.

[0046] As described above, the high-resistance region 2a is formed in a portion of the source region 2. Therefore, the trigger voltage V1 can be reduced to a voltage value lower than the breakdown voltage V2 without adding an external resistive element 10 as in the previously described protective element Y. Therefore, it is possible to provide a protective element X that has an ESD protection function while suppressing an increase in the circuit area and the number of components.

[0047] As described above, the low-resistance regions 2b of each protection element X are aligned in a straight line along the first direction. This makes it easier to form a silicide blocking layer that blocks silicidation of the high-resistance regions 2a. This also makes it easier to layout the arrangement of each element in the I / O circuit 100X at the design stage. This helps prevent cost increases.

[0048] <Modification> The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the present invention. For example, as shown in FIG. 7, an I / O circuit 100X may be configured to include a resistive element 10. One end of the resistive element 10 is connected to the gate terminal of a protective element X. The other end of the resistive element 10 is connected to the source terminal of the protective element X.

[0049] With this configuration, the trigger voltage of the protection element X can be further reduced according to the resistance value of the resistance element 10. Even if the voltage value of the breakdown voltage V2' of the internal circuit 50 is lower than the voltage value of the trigger voltage V1 mentioned above, as shown in the graph of FIG. 8, the trigger voltage V1 can be reduced to a voltage value (trigger voltage V1' shown in FIG. 8) lower than the breakdown voltage V2'. Therefore, even if the breakdown voltage V2' of the internal circuit 50 is relatively low, the trigger voltage V1' can be reduced to a voltage value lower than the breakdown voltage V2', thereby protecting the internal circuit 50 from overvoltage such as ESD.

[0050] Although the protection element X in the above embodiment is an N-channel MOSFET, a P-channel MOSFET may also be used. In this case, the connection relationship between the protection element X and other elements is as follows:

[0051] 9 is a diagram showing a modified example of the I / O circuit 100X of the present disclosure. As shown in FIG. 9, the gate terminal of the protection element X is connected to the external terminal T1, together with the source terminal of the protection element X and a first terminal of the internal circuit 50. The source terminal of the protection element X is electrically connected to the back gate via a high-resistance region 2a inside the protection element X. The drain terminal of the protection element X is connected to the ground terminal GND, together with a second terminal of the internal circuit 50.

[0052] In this case, as shown in FIG. 10, the parasitic bipolar transistor 9 becomes a PNP-type parasitic bipolar transistor.

[0053] In this case, similarly to the above-described modification (see FIG. 7), the I / O circuit 100X can be configured to include a resistive element 12. As shown in FIG. 11, a first terminal of the resistive element 12 is connected to a gate terminal of the protective element X, and a second terminal of the resistive element 12 is connected to a source terminal of the protective element X.

[0054] <Additional Notes> The protection element (X) described in the specification comprises a drain region (3) electrically connected to an external terminal (T1), a gate region (4) formed as a gate, a source region (2) formed as a source, and a back gate region (5) formed as a back gate, and the source region (2) includes a low resistance region (2b) electrically connected to the gate region (4) directly or via a resistance element (10), and a high resistance region (2a) having a higher resistance value than the low resistance region (2b), and the low resistance region (2b) is configured to be electrically connected to the back gate region (5) via the high resistance region (2a) (first configuration).

[0055] In the protection element (X) according to the first configuration, the high resistance region (2a) may be configured to have a lower impurity concentration than the low resistance region (2b) (second configuration).

[0056] The I / O circuit (100X) disclosed in the specification may be configured to include a protection element (X) according to the first or second configuration and a resistive element (10) connected between the gate region (4) and the source region (2) (third configuration).

[0057] The I / O circuit (100X) disclosed in the specification may include a plurality of protection elements (X) according to the first or second configuration, and the back gate regions (5) of the protection elements (X) may be configured to be common (fourth configuration).

[0058] In the I / O circuit (100X) of the fourth configuration, the source regions (2) and drain regions (3) of each protection element (X) are arranged alternately along a first direction, and each high resistance region (2a) is arranged along the first direction so as to overlap with each other in a second direction perpendicular to the first direction (fifth configuration). [Explanation of symbols]

[0059] 1. Semiconductor device 2 Source Area 2a High resistance area 2b Low resistance region 2x source region 3. Drain region 4 Gate Region 5 Back gate region 6 Non-silicide region 8 P-type well region 9 Parasitic Bipolar Transistor 10 Resistive element 11 Resistance component 50 Internal circuit 100X I / O circuit 100Y I / O circuit GND grounding end T1 external terminal V1, V1´ trigger voltage V2, V2´ breakdown voltage X protection element Y protection element i Snapback area

Claims

1. a drain region that is electrically connected to an external terminal; a gate region formed as a gate; a source region formed as a source; a back gate region formed as a back gate; Equipped with The source region is a low resistance region electrically connected to the gate region directly or via a resistance element; a high resistance region having a resistance value higher than that of the low resistance region; wherein the low resistance region is electrically connected to the back gate region via the high resistance region.

2. 2. The protection element according to claim 1, wherein the high resistance region has a lower impurity concentration than the low resistance region.

3. The protection element according to claim 1 or 2; the resistive element connected between the gate region and the source region; An I / O circuit comprising:

4. A plurality of protection elements according to claim 1 or 2 are included, The I / O circuit has a common back gate region for each of the protection elements.

5. the source region and the drain region of each of the protection elements are alternately arranged along a first direction, 5. The I / O circuit according to claim 4, wherein the high resistance regions are arranged along the first direction so as to overlap each other in a second direction perpendicular to the first direction.

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