Semiconductor device

Abstract

To provide a semiconductor device capable of reducing fluctuations in threshold voltage.SOLUTION: A semiconductor device includes: a semiconductor substrate having a first main surface; a gate insulating film provided on the first main surface; a gate electrode provided on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode provided on the interlayer insulating film; a passivation film covering the first electrode and including an opening formed therein; and a plating film provided on the first electrode in the opening. The first main surface is provided with a gate trench. The semiconductor device has a first region at least covering an edge of the opening, in plan view perpendicular to the first main surface, and the first main surface in the first region is not provided with the gate trench.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A semiconductor device is disclosed in which a plating film is formed on a metal layer containing aluminum. The plating film contacts the metal layer within an opening formed in a protective film. The plating film is formed by immersing the metal layer in a plating solution. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-201160 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor devices, when forming a plating film, plating solution may accumulate near the inner wall of the opening, corroding the metal layer or plating film and creating a corroded area. The corroded area contains metal ions, such as sodium ions, in the plating solution. The metal ions may diffuse into the gate insulating film during operation of the semiconductor device, causing a change in the threshold voltage.

[0005] An object of the present disclosure is to provide a semiconductor device that can reduce fluctuations in threshold voltage. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure comprises a semiconductor substrate having a first main surface, a gate insulating film provided on the first main surface, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode, a first electrode provided on the interlayer insulating film, a passivation film covering the first electrode and having an opening formed therein, and a plating film provided on the first electrode within the opening, wherein a gate trench is provided in the first main surface, and the semiconductor device has a first region covering at least the edge of the opening in a plan view perpendicular to the first main surface, and the first main surface within the first region is free of the gate trench. [Effects of the Invention]

[0007] According to the present disclosure, the fluctuation in threshold voltage can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram showing an opening in a passivation film in a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an interlayer insulating film and a first main surface of the semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) showing the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) showing the semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) showing the semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) showing the semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a fifth cross-sectional view showing the semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 10]FIG. 10 is a cross-sectional view (part 3) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a semiconductor device according to a first modification of the embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to a second modification of the embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a semiconductor device according to a third modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be given the same reference numerals, and the same description will not be repeated. In the following description, an XYZ Cartesian coordinate system will be used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the semiconductor device. The XY plane view will be referred to as a planar view, and the +Z direction from an arbitrary point will sometimes be referred to as upward, upper side, or top, and the -Z direction will sometimes be referred to as downward, lower side, or bottom.

[0011] [1] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate having a first main surface, a gate insulating film provided on the first main surface, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode, a first electrode provided on the interlayer insulating film, a passivation film covering the first electrode and having an opening formed therein, and a plating film provided on the first electrode within the opening, wherein a gate trench is provided in the first main surface, and the first main surface has a first region covering at least an edge of the opening in a plan view perpendicular to the first main surface, and the first main surface within the first region is free of the gate trench.

[0012] In this case, in a plan view perpendicular to the first principal surface, the gate electrode is not present under the corroded portion, and the electric field applied to the mobile ions present in the corroded portion can be reduced. This reduces the diffusion of mobile ions from the first electrode into the gate insulating film, thereby reducing the fluctuation of the threshold voltage.

[0013] [2] In [1], the interlayer insulating film may include a first insulating film and a second insulating film provided on the first insulating film, the first insulating film being a non-doped silicate glass film, and the second insulating film being a film having a smaller diffusion coefficient of mobile ions than the first insulating film. In this case, mobile ions diffusing through the first electrode in the first region toward the gate electrode are captured by the second insulating film. This reduces the diffusion of mobile ions from the first electrode into the gate insulating film. This reduces the fluctuation in threshold voltage.

[0014] [3] In [2], the second insulating film may contain at least one of phosphosilicate glass, boron phosphosilicate glass, and silicon nitride. Phosphosilicate glass, boron phosphosilicate glass, and silicon nitride have high performance in capturing mobile ions. Therefore, it is easy to reduce the diffusion of mobile ions into the gate insulating film.

[0015] [4] In any of [1] to [3], the gate electrode may be absent in the first region, thereby reducing the capacitance between the gate and the source.

[0016] [5] In any one of [1] to [4], the semiconductor substrate may have a source region of a first conductivity type including the first main surface and a contact region of a second conductivity type including the first main surface, and the semiconductor substrate may have the contact region but not the source region in the first region. In this case, the capacitance between the drain and source can be reduced.

[0017] [6] In any of [1] to [5], the plating film may have a corroded portion along the edge of the opening, and the first region may cover at least the entire corroded portion in a plan view perpendicular to the first main surface. In this case, it is easy to reduce the diffusion of mobile ions into the gate insulating film.

[0018] [7] In [6], the edge of the opening may extend along a first axis parallel to the first major surface, and the relationship W2 + T1 × 2 ≦ W1 ≦ W2 + T1 × 10 may be satisfied, where W1 is the width of the first region along a second axis parallel to the first major surface and perpendicular to the first axis, W2 is the width of the corroded portion along the second axis parallel to the first major surface, and T1 is the thickness of the first electrode. Mobile ions contained in the corroded portion diffuse along the second axis over a length at least equal to the thickness of the first electrode. When W2 + T1 × 2 ≦ W1, mobile ions diffusing along the second axis can also be captured by the second insulating film, making it easier to reduce diffusion of mobile ions into the gate insulating film. When W1 ≦ W2 + T1 × 10, on-resistance is less likely to increase.

[0019] [8] In [7], a width along the second axis from the edge of the opening to an end of the first region within the opening may be 100 μm or less, in which case the on-resistance is less likely to increase.

[0020] [9] In any of [1] to [8], the semiconductor substrate may be a silicon carbide substrate, which makes it easier to obtain an excellent breakdown voltage.

[0021] [Details of the embodiments of the present disclosure] [Configuration of Semiconductor Device] An embodiment of the present disclosure relates to a so-called vertical MOS (Metal Oxide Semiconductor) field effect transistor (FET) using silicon carbide. FIG. 1 is a schematic diagram showing an opening in a passivation film in a semiconductor device according to an embodiment. FIG. 2 is a diagram showing an interlayer insulating film and a first main surface in a semiconductor device according to an embodiment. FIGS. 3 to 7 are cross-sectional views showing a semiconductor device according to an embodiment. FIG. 2 corresponds to region II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 corresponds to a cross-sectional view taken along line VV in FIG. 1. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG. 1.

[0022] As shown in FIGS. 1 to 7, the semiconductor device 100 according to the embodiment includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

[0023] The silicon carbide substrate 10 is an example of a semiconductor substrate. When the silicon carbide substrate 10 is used, an excellent breakdown voltage can be easily obtained. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction as viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 includes the first main surface 1, and the silicon carbide single crystal substrate 50 includes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 include, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0024] The silicon carbide epitaxial layer 40 includes a drift region 11, a body region 12, a source region 13, and a contact region 18.

[0025] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. An electric field relaxation region may be provided in drift region 11. The electric field relaxation region has p-type conductivity (second conductivity type).

[0026] Body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. Body region 12 is provided on drift region 11. The lower end surface of body region 12 and the upper end surface of drift region 11 are in contact with each other.

[0027] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 includes the first main surface 1.

[0028] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first main surface 1. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are provided at regular intervals (first pitch P1) along the X axis. The Y axis is an example of the first axis, and the X axis is an example of the second axis. The side surfaces 3 penetrate the source region 13, the body region 12, and part of the drift region 11, and reach the drift region 11. The bottom surface 4 is continuous with the side surfaces 3. The bottom surface 4 is located in the drift region 11. For example, the bottom surface 4 is parallel to the first main surface 1 and the second main surface 2. The side surfaces 3 are inclined with respect to a plane including the bottom surface 4.

[0029] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and the body region 12 and is in contact with the drift region 11. The contact region 18 includes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between the gate trenches 5 adjacent along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent along the X-axis.

[0030] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.

[0031] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 includes, for example, silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0032] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is formed of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap multiple gate trenches 5.

[0033] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be flat. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0034] The interlayer insulating film 83 is, for example, a non-doped silicate glass (NSG) film.

[0035] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged such that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0036] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is provided in the contact hole 90. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is formed of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be formed of a material containing, for example, titanium (Ti), aluminum, and silicon. The contact electrode 61 is in ohmic contact with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the interlayer insulating film 83 and the contact electrode 61. The source wiring 62 is formed of a material containing, for example, aluminum.

[0037] The semiconductor device 100 has a gate runner 63. The gate runner 63 is formed simultaneously with the source electrode 60 and is made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82.

[0038] The semiconductor device 100 has a passivation film 87. The passivation film 87 covers the upper surface of the source electrode 60. An opening 121 is formed in the passivation film 87, exposing a portion of the source electrode 60. The opening 121 has a first edge 121A extending along the X-axis and a second edge 121B extending along the Y-axis. The opening 121 is formed between two gate runners 63 adjacent to each other along the Y-axis. A source plating film 86 is formed in the opening 121. An opening 122 is formed in the passivation film 87, exposing a portion of the gate pad 65 connected to the gate runner 63. A gate plating film is formed in the opening 122. An opening 123 may be formed in the passivation film 87, in addition to the openings 121 and 122.

[0039] Corrosion portions 89 may occur in the plating film 86 along the edges of the openings 121. The corrosion portions 89 occur, for example, inside the openings 121. The corrosion portions 89 contact the source electrode 60 and the plating film 86. The corrosion portions 89 occur when plating solution accumulates near the inner wall of the openings 121 during the formation of the plating film 86, corroding the source electrode 60 and the plating film 86. The corrosion portions 89 contain metal ions in the plating solution. The metal ions include, for example, sodium ions (Na + ), potassium ions (K + ), calcium ions (Ca + ), lithium ion (Li + ), chloride ions (Cl - ) is included.

[0040] 1, the semiconductor device 100 has a first region 101. In a plan view, the first region 101 covers a first edge 121A and a second edge 121B of the opening 121. The first region 101 may have an annular shape in a plan view. As shown in FIG. 4, in a cross-sectional view perpendicular to the Y axis, the first region 101 may include a position X1 directly below the second edge 121B of the opening 121.

[0041] 4 to 6 , there is no gate trench 5 in the first main surface 1 in the first region 101. There is no gate electrode 82 in the first region 101. There is no contact hole 90 in the interlayer insulating film 83 in the first region 101. The upper surface of the contact region 18 in the first region 101 is covered with the interlayer insulating film 83.

[0042] As shown in FIGS. 4 and 7 , a gate trench 5 is present on the first main surface 1 outside the first region 101. A gate electrode 82 is present outside the first region 101. A contact hole 90 is present outside the first region 101 between two gate trenches 5 adjacent to each other along the X-axis. The upper surfaces of the contact regions 18 outside the first region 101 are not covered with the interlayer insulating film 83. The upper surfaces of the contact regions 18 outside the first region 101 are in contact with the source electrode 60.

[0043] The first region 101 may cover at least the entire corroded portion 89 in a plan view. As shown in FIG. 4, in a cross-sectional view perpendicular to the Y axis, the width W1 of the first region 101 may be equal to or greater than the width W2 of the corroded portion 89. When the thickness of the source electrode 60 is T1, the relationship W2 + T1 × 2 ≦ W1 ≦ W2 + T1 × 10 may be satisfied. The thickness T1 of the source electrode 60 is the length along the Z axis from the top surface of the interlayer insulating film 83 to the top surface of the source electrode 60. The width W3 along the X axis from the second edge 121B of the opening 121 to the end of the first region 101 within the opening 121 may be 100 μm or less.

[0044] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is formed of a material containing nickel silicide, for example. The drain electrode 70 may be formed of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0045] [Method for manufacturing semiconductor device] Next, a description will be given of a method for manufacturing the semiconductor device 100. Figures 8 to 10 are cross-sectional views showing a method for manufacturing the semiconductor device 100 according to the embodiment.

[0046] First, as shown in Fig. 8, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0047] 9, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, and the contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11.

[0048] Next, as shown in FIG. 10, a plurality of gate trenches 5 are formed in the first main surface 1 outside the first region 101. No gate trenches 5 are formed in the first main surface 1 within the first region 101. Next, a gate insulating film 81 is formed. Next, a gate electrode 82 is formed outside the first region 101. No gate electrode 82 is formed within the first region 101. Next, an interlayer insulating film 83 is formed. Next, contact holes 90 are formed in the interlayer insulating film 83 and gate insulating film 81 outside the first region 101. No contact holes 90 are formed in the interlayer insulating film 83 and gate insulating film 81 within the first region 101.

[0049] Next, the source electrode 60, the gate pad 65, the drain electrode 70, the passivation film 87, and the plating film 86 are formed (see FIGS. 3 and 4).

[0050] In this manner, the semiconductor device 100 can be manufactured.

[0051] In the semiconductor device 100, as described above, the first main surface 1 in the first region 101 does not have a gate trench 5. In this case, in a plan view perpendicular to the first main surface 1, the gate electrode 82 does not exist under the corroded portion 89, and the electric field applied to the mobile ions present in the corroded portion 89 can be reduced. This reduces the diffusion of mobile ions from the source electrode 60 into the gate insulating film 81. This reduces the fluctuation in the threshold voltage.

[0052] There is no gate electrode 82 in the first region 101. In this case, the capacitance between the gate and the source can be reduced.

[0053] The first region 101 may cover at least the entire corroded portion 89 in plan view. In this case, the diffusion of mobile ions into the gate insulating film 81 is easily reduced.

[0054] If the width of the first region 101 along the X-axis is W1, the width of the corroded portion 89 along the X-axis is W2, and the thickness of the source electrode 60 is T1, the relationship W2 + T1 × 2 ≦ W1 ≦ W2 + T1 × 10 may be satisfied. Mobile ions contained in the corroded portion 89 diffuse along the X-axis over a length at least equal to the thickness T1 of the source electrode 60. If W2 + T1 × 2 ≦ W1, the mobile ions diffusing along the X-axis can also be captured by the second insulating film 85, making it easier to reduce the diffusion of mobile ions into the gate insulating film 81. If W1 ≦ W2 + T1 × 10, the on-resistance is less likely to increase.

[0055] A width W3 along the X axis from second edge 121B of opening 121 to the end of first region 101 within opening 121 may be 100 μm or less. In this case, the on-resistance is less likely to increase.

[0056] [First Modified Example] A first modification of the embodiment will be described. The first modification differs from the above-described embodiment in that a gate electrode is located in the first region and the interlayer insulating film includes a first insulating film and a second insulating film. Fig. 11 is a cross-sectional view showing a semiconductor device according to the first modification of the embodiment. Fig. 11 corresponds to a cross-sectional view taken along line IV-IV in Fig. 1.

[0057] As shown in FIG. 11 , the semiconductor device 200 according to the first modification has a gate electrode 82 in a first region 101. In the semiconductor device 200 according to the first modification, the interlayer insulating film 83 includes a first insulating film 84 and a second insulating film 85. The interlayer insulating film 83 has a stacked structure in which the second insulating film 85 is stacked on the first insulating film 84. The first insulating film 84 is, for example, a non-doped silicate glass film. The second insulating film 85 is a film in which the diffusion coefficient of mobile ions is smaller than that of the first insulating film 84. The mobile ions are, for example, metal ions. The metal ions may be cations such as sodium ions, potassium ions, calcium ions, or lithium ions. The metal ions may be anions such as chloride ions. The second insulating film 85 includes, for example, at least one of phosphosilicate glass, boron phosphosilicate glass, and silicon nitride.

[0058] Other than the above, the present embodiment is the same as the above-described embodiment.

[0059] The semiconductor device 200 can be manufactured by a method similar to that of the semiconductor device 100. However, in the first modification, when the gate electrode 82 is formed in the first region 101 and the interlayer insulating film 83 is also formed, the first insulating film 84 is formed, and then the second insulating film 85 is formed on the first insulating film 84.

[0060] The semiconductor device 200 according to the first modification also provides the same effects as those of the above-described embodiment.

[0061] In the semiconductor device 200, the interlayer insulating film 83 includes a first insulating film 84 and a second insulating film 85 provided on the first insulating film 84. The first insulating film 84 is a non-doped silicate glass film. The second insulating film 85 is a film having a smaller diffusion coefficient of mobile ions than the first insulating film 84. In this case, mobile ions are less likely to diffuse through the interlayer insulating film 83 than when the interlayer insulating film 83 has a single-layer structure of the first insulating film 84. Therefore, even when the gate electrode 82 is present in the first region 101, the diffusion of mobile ions into the gate insulating film 81 can be reduced.

[0062] The second insulating film 85 may contain at least one of phosphosilicate glass, boron phosphosilicate glass, and silicon nitride. Phosphosilicate glass, boron phosphosilicate glass, and silicon nitride have high performance in capturing mobile ions, and therefore, the diffusion of mobile ions into the gate insulating film 81 can be easily reduced.

[0063] [Second Modification] A second modification of the embodiment will be described. The second modification differs from the first modification in that there is no gate electrode in the first region. Fig. 12 is a cross-sectional view showing a semiconductor device according to the second modification of the embodiment. Fig. 12 corresponds to a cross-sectional view taken along line IV-IV in Fig. 1.

[0064] 12, the semiconductor device 300 according to the second modification does not have a gate electrode 82 inside the first region 101. Outside the first region 101, the gate electrode 82 is present.

[0065] Other than the above, the second modification is the same as the first modification.

[0066] The semiconductor device 300 can be manufactured by the same method as the method for manufacturing the semiconductor device 100. However, in the second modification, when forming the interlayer insulating film 83, after forming the first insulating film 84, the second insulating film 85 is formed on the first insulating film 84.

[0067] The semiconductor device 300 according to the second modification also provides the same effects as those of the first modification.

[0068] The semiconductor device 300 does not have a gate electrode 82 in the first region 101. In this case, the capacitance between the gate and the source can be reduced.

[0069] [Third Modification] A third modified example of the embodiment will be described. The third modified example differs from the second modified example in that silicon carbide substrate 10 in the first region does not have source region 13 but has contact region 18. Fig. 13 is a cross-sectional view showing a semiconductor device according to the third modified example of the embodiment. Fig. 13 corresponds to a cross-sectional view taken along line IV-IV in Fig. 1.

[0070] 13 , in a semiconductor device 400 according to the third modification, a silicon carbide substrate 10 in a first region 101 does not have a source region 13 but has a contact region 18. The contact region 18 may be provided throughout the entire first region 101. In a cross-sectional view perpendicular to the Y axis, a width W4 of the contact region 18 including a position X1 directly below the second edge 121B of the opening 121 may be equal to or greater than the width W1 of the first region 101.

[0071] Other than the above, the second modified example is the same as the second modified example.

[0072] The semiconductor device 400 can be manufactured by the same method as the semiconductor device 100. However, in the third modification, when ions are implanted into the silicon carbide epitaxial layer 40, the source region 13 is not formed in the first region 101, and only the contact region 18 is formed.

[0073] The semiconductor device 400 according to the third modification also provides the same effects as those of the second modification.

[0074] In semiconductor device 400, silicon carbide substrate 10 in first region 101 does not have source region 13, but has contact region 18. In this case, the capacitance between the drain and source can be reduced.

[0075] In the present disclosure, the width W1, the width W2, the width W3, the width W4 and the thickness T1 can be measured using, for example, a scanning electron microscope (SEM).

[0076] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0077] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Region 12 Body Region 13 Source Region 18 Contact Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate Runner 65 Gate Pad 70 drain electrode 81 Gate insulating film 82 gate electrode 83 Interlayer insulating film 84 First insulating film 85 Second insulating film 86 Plating film 87 Passivation Film 89 Corroded area 90 Contact Holes 100, 200, 300, 400 Semiconductor equipment 101 First area 121, 122, 123 Openings 121A First Edge 121B Second Edge F1 dashed arrow P1 First pitch W1, W2, W3, W4 width X1 position

Claims

1. a semiconductor substrate having a first main surface; a gate insulating film provided on the first main surface; a gate electrode provided on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode provided on the interlayer insulating film; a passivation film covering the first electrode and having an opening formed therein; a plating film provided on the first electrode within the opening; Equipped with a gate trench is provided in the first main surface; a first region covering at least an edge of the opening in a plan view perpendicular to the first main surface; the first main surface in the first region is free of the gate trench; Semiconductor device.

2. the interlayer insulating film includes a first insulating film and a second insulating film provided on the first insulating film, the first insulating film is a non-doped silicate glass film, the second insulating film has a smaller diffusion coefficient of mobile ions than the first insulating film; The semiconductor device according to claim 1 .

3. the second insulating film includes at least one of phosphosilicate glass, boron phosphosilicate glass, and silicon nitride; The semiconductor device according to claim 2 .

4. The gate electrode is not present in the first region. The semiconductor device according to claim 1 .

5. The semiconductor substrate is a source region including the first major surface and having a first conductivity type; a contact region including the first major surface and having a second conductivity type; and The semiconductor substrate in the first region does not have the source region but has the contact region. The semiconductor device according to claim 1 .

6. the plating film has a corroded portion along the edge of the opening, the first region covers at least the entire corroded portion in a plan view perpendicular to the first main surface; The semiconductor device according to claim 1 .

7. the edge of the opening extends along a first axis parallel to the first major surface; When the width of the first region along a second axis parallel to the first main surface and perpendicular to the first axis is defined as W1, the width of the corroded portion along the second axis parallel to the first main surface is defined as W2, and the thickness of the first electrode is defined as T1, W2+T1×2≦W1≦W2+T1×10 Satisfy the relationship of The semiconductor device according to claim 6.

8. a width along the second axis from the edge of the opening to an end of the first region within the opening is 100 μm or less; The semiconductor device according to claim 7 .

9. The semiconductor substrate is a silicon carbide substrate. The semiconductor device according to claim 1 .

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