Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device on which a wiring layer with suitable characteristics can be formed, and a method of manufacturing the same.SOLUTION: According to one embodiment, a semiconductor device comprises a first insulation film. The device further comprises a first wiring layer including a first layer provided within the first insulation film and including tungsten and nitrogen and a second layer provided within the first insulation film with the first layer interposed and including tungsten. The nitrogen concentration in the first layer is higher than that in the second layer. The ratio of the number of nitrogen atoms to the sum of the number of tungsten atoms in the first layer and the number of the nitrogen atoms is smaller than 40%.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a semiconductor device including a wiring layer such as an electrode layer, it is desirable to reduce the electrical resistance of the wiring layer and to suppress the diffusion of atoms from the wiring layer to other layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-26869 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-310842 [Patent Document 3] U.S. Patent No. 8,053,365 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of forming a wiring layer having suitable characteristics and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a first insulating film. The device further includes a first wiring layer including a first layer provided in the first insulating film and containing tungsten and nitrogen, and a second layer provided in the first insulating film with the first layer interposed therebetween and containing tungsten. The nitrogen concentration in the first layer is higher than the nitrogen concentration in the second layer. The ratio of the number of nitrogen atoms to the sum of the number of tungsten atoms and the number of nitrogen atoms in the first layer is less than 40%. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a perspective view showing a structure of a semiconductor device according to a first embodiment; [Figure 2] 4 is a cross-sectional view (1 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] 4 is a cross-sectional view (2 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view (3 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 4 is a cross-sectional view (4 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 4 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment. [Figure 7] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 8] 3A to 3C are cross-sectional views showing details of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 4 is a graph relating to characteristics of the semiconductor device of the first embodiment. [Figure 10] 6 is another graph relating to the characteristics of the semiconductor device according to the first embodiment. [Figure 11] FIG. 4 is a cross-sectional view showing the structure of a semiconductor device according to a modified example of the first embodiment. [Figure 12] 10A and 10B are cross-sectional views showing the structure of a semiconductor device according to a second embodiment and the structure of a semiconductor device according to a modified example of the second embodiment. [Figure 13] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing the structure of a columnar portion of a third embodiment. [Figure 16] 10 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 17] 10 is a cross-sectional view (2 / 2) illustrating a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 17, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) 1 is a perspective view showing the structure of a semiconductor device according to a first embodiment, which includes, for example, a three-dimensional semiconductor memory.

[0009] The semiconductor device of this embodiment includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a block insulating film 5, and an electrode layer 6. The block insulating film 5 includes an insulating film 5a and an insulating film 5b. The electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The electrode layer 6 is an example of a first wiring layer. The barrier metal layer 6a is an example of a first layer. The electrode material layer 6b is an example of a second and third layer, and also an example of a wiring material layer in the first wiring layer.

[0010] In FIG. 1, multiple electrode layers and multiple insulating films are alternately stacked on a substrate, and memory holes Ha are provided in these electrode layers and insulating films. FIG. 1 shows one of these electrode layers, electrode layer 6. These electrode layers function, for example, as word lines of a three-dimensional semiconductor memory. FIG. 1 also shows the X and Y directions, which are parallel to the surface of the substrate and perpendicular to each other, and the Z direction, which is perpendicular to the surface of the substrate. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity.

[0011] The core insulating film 1, the channel semiconductor layer 2, the tunnel insulating film 3, the charge storage layer 4, and the insulating film 5a are formed in the memory hole Ha and constitute a memory cell of the three-dimensional semiconductor memory. The insulating film 5a is formed on the side surfaces of the electrode layer and the insulating film in the memory hole Ha, and the charge storage layer 4 is formed on the side surface of the insulating film 5a. The charge storage layer 4 can store signal charges of the three-dimensional semiconductor memory. The tunnel insulating film 3 is formed on the side surface of the charge storage layer 4, and the channel semiconductor layer 2 is formed on the side surface of the tunnel insulating film 3. The channel semiconductor layer 2 functions as a channel of the three-dimensional semiconductor memory. The core insulating film 1 is formed on the side surface of the channel semiconductor layer 2. The insulating film 5a is an example of a third insulating film. The tunnel insulating film 3 is an example of a fourth insulating film.

[0012] The insulating film 5a is, for example, an SiO2 film (silicon oxide film). The charge storage layer 4 is, for example, an SiN film (silicon nitride film). The tunnel insulating film 3 is, for example, an SiO2 film. The channel semiconductor layer 2 is, for example, a polysilicon layer. The core insulating film 1 is, for example, an SiO2 film.

[0013] The insulating film 5b, the barrier metal layer 6a, and the electrode material layer 6b are formed between two of the insulating films, and are formed in this order on the lower surface of the upper insulating film, the upper surface of the lower insulating film, and the side surface of the insulating film 5a. The insulating films and the block insulating film 5 are examples of first insulating films. The insulating films are also examples of second insulating films.

[0014] The insulating film 5b is, for example, an Al2O3 film (aluminum oxide film). The barrier metal layer 6a is, for example, a W (tungsten) layer containing N (nitrogen) atoms as impurity atoms. The electrode material layer 6b is, for example, a W layer. Further details of the barrier metal layer 6a and the electrode material layer 6b will be described later.

[0015] 2 to 5 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0016] First, a substrate 11 is prepared, and a laminated film 12 including a plurality of sacrificial layers 13 and a plurality of insulating films 14 is formed on the substrate 11 (FIG. 2). The laminated film 12 is formed by alternately stacking a plurality of sacrificial layers 13 and a plurality of insulating films 14 on the substrate 11. The laminated film 12 may be formed directly on the substrate 11, or may be formed on the substrate 11 via another layer. The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The sacrificial layer 13 is, for example, a SiN film. The insulating film 14 is, for example, a SiO2 film. The sacrificial layer 13 is an example of a fourth layer. The insulating film 14 is an example of a first and second insulating film.

[0017] Next, a plurality of memory holes Ha are formed in the stacked film 12 by photolithography and RIE (Reactive Ion Etching) (FIG. 2). FIG. 2 shows one of these memory holes Ha. Each memory hole Ha in this embodiment has a circular shape in a plan view and penetrates the stacked film 12.

[0018] Next, an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 are formed in this order on the side surface of the stacked film 12 in each memory hole Ha (FIG. 3). The insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, and the channel semiconductor layer 2 are formed to have a tubular shape extending in the Z direction. The core insulating film 1 is formed to have a columnar shape extending in the Z direction.

[0019] Next, a plurality of slits (not shown) are formed in the laminated film 12, and the sacrificial layer 13 is removed through these slits with a chemical solution such as an aqueous solution of phosphoric acid. As a result, a plurality of recesses Hb are formed in the laminated film 12 (FIG. 4). The recesses Hb are an example of first recesses.

[0020] Next, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are formed in this order on the surfaces of the insulating films 5a and 14 in each recess Hb (FIG. 5). As a result, a block insulating film 5 including the insulating films 5a and 5b is formed. Furthermore, an electrode layer 6 including the barrier metal layer 6a and the electrode material layer 6b is formed in each recess Hb. Furthermore, a stacked film 12 including multiple electrode layers 6 and multiple insulating films 14 alternately is formed on the substrate 11. In this manner, a replacement step is performed in which the sacrificial layer 13 is replaced with the electrode layer 6. The insulating film 14 and the block insulating film 5 are examples of a first insulating film.

[0021] Each recess Hb is formed between two insulating films 14 adjacent to each other in the Z direction. In each recess Hb, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are formed, in that order, on the lower surface of the upper insulating film 14, the upper surface of the lower insulating film 14, and the side surface of the insulating film 5a. As a result, each electrode layer 6 is formed between the insulating films 14 with the insulating film 5b interposed therebetween. Meanwhile, in each memory hole Ha after the replacement step, a charge storage layer 4 is provided on the side surface of the plurality of electrode layers 6 with the insulating film 5a interposed therebetween, and a channel semiconductor layer 2 is provided on the side surface of the charge storage layer 4 with the tunnel insulating film 3 interposed therebetween.

[0022] In this way, the semiconductor device of this embodiment is manufactured (FIG. 5). FIG. 1 shows a part of the semiconductor device shown in FIG.

[0023] Next, the first embodiment and a comparative example will be compared with each other with reference to FIGS.

[0024] FIG. 6 is a cross-sectional view showing the structure of a semiconductor device as a comparative example of the first embodiment.

[0025] FIG. 6(a) shows the structure of the semiconductor device of this comparative example. Similar to FIG. 5, FIG. 6(a) shows the charge storage layer 4, the block insulating film 5, the electrode layer 6, the insulating film 14, and the like. However, the electrode layer 6 of this comparative example includes a barrier metal layer 6a' instead of the barrier metal layer 6a. FIG. 6(a) also shows a seam Ga formed in the electrode material layer 6b when the electrode material layer 6b is formed. This seam Ga is an air gap extending generally parallel to the XY plane. As shown in FIG. 6(a), the electrode material layer 6b of this comparative example includes metal layers 21 and 22 formed in this order on the side, top, and bottom surfaces of the barrier metal layer 6a'.

[0026] The barrier metal layer 6a' is, for example, a TiN film (titanium nitride film). Each of the metal layers 21 and 22 is, for example, a W layer. In this comparative example, the barrier metal layer 6a' and the metal layer 22 are polycrystalline layers, and the metal layer 21 is an amorphous layer. Therefore, the resistivity of the metal layer 22 is lower than that of the metal layer 21.

[0027] In this comparative example, metal layer 21 is formed using WF6 gas and B2H6 gas, and metal layer 22 is formed using WF6 gas and H2 gas (W represents tungsten, F represents fluorine, B represents boron, and H represents hydrogen). Therefore, metal layers 21 and 22 contain F atoms as impurity atoms.

[0028] FIG. 6(b) is a cross-sectional view illustrating the problem with the semiconductor device of this comparative example. In this comparative example, when the thickness of the electrode layer 6 is reduced to miniaturize the semiconductor device, it becomes difficult to embed the electrode material layer 6b in the recess Hb (see FIG. 5), and large seams Ga are likely to form in the electrode material layer 6b. Because the concentration of F atoms in the electrode layer 6 is high at the surface of the electrode layer 6, the F atoms in the electrode layer 6 are present in high concentration on the surface of the electrode layer 6 facing the seams Ga. As a result, the F atoms in the electrode layer 6 are likely to diffuse through the seams Ga, which may cause defects in the semiconductor device (e.g., insulation defects). Therefore, it is desirable to suppress the diffusion of F atoms by using a barrier metal layer 6a'. The arrows in FIG. 6(b) indicate the diffusion of F atoms from the electrode layer 6 to other layers.

[0029] FIG. 7 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0030] As shown in Fig. 7, the electrode layer 6 of this embodiment includes a barrier metal layer 6a. The electrode material layer 6b of this embodiment also includes metal layers 25 and 26 formed in this order on the side, upper, and lower surfaces of the barrier metal layer 6a. The barrier metal layer 6a is an example of the first layer. The metal layer 25 is an example of the third layer. The metal layer 26 is an example of the second layer.

[0031] The barrier metal layer 6a of this embodiment contains W atoms and N atoms. The barrier metal layer 6a is, for example, a W layer containing N atoms as impurity atoms, as described above. That is, the barrier metal layer 6a contains, for example, W as a main component. A W layer containing N atoms as impurity atoms is referred to as a W(N) layer. As will be described later, when the composition ratio of W atoms to N atoms in a WN film is 6:4, the ratio k of the number n2 of N atoms to the sum of the number n1 of W atoms and the number n2 of N atoms in the W(N) layer of this embodiment is smaller than 40% (i.e., k = n2 / (n1 + n2) < 0.40). Furthermore, the ratio of the number of W atoms to the total number of atoms in the barrier metal layer 6a of this embodiment is greater than 60%. In this embodiment, the barrier metal layer 6a is a crystalline layer, for example, a polycrystalline layer.

[0032] The metal layer 25 is, for example, a W layer. The metal layer 26 is, for example, a W layer. Each of the metal layers 25 and 26 may or may not contain N atoms as impurity atoms. However, the N concentration in the barrier metal layer 6a of this embodiment is higher than the N concentration in the metal layer 26 even when the metal layer 26 contains N atoms as impurity atoms. The N concentration in the metal layer 26 is, for example, 7.0×10 19 ~2.0×20 20 atoms / cm 3Similarly, the N concentration in the barrier metal layer 6a of this embodiment is higher than the N concentration in the metal layer 25, even when the metal layer 25 contains N atoms as impurity atoms. In this embodiment, the metal layer 26 is a polycrystalline layer, and the metal layer 25 is an amorphous layer. Therefore, the resistivity of the metal layer 26 is lower than the resistivity of the metal layer 25.

[0033] The barrier metal layer 6a is formed, for example, by forming a WN film by CVD and then annealing the WN film to a W(N) layer, as described below. In this embodiment, the WN film is annealed using a predetermined gas, such as H (hydrogen) gas (H annealing). The annealing is performed, for example, at a temperature higher than 400°C, preferably at a temperature higher than 500°C. In this embodiment, the amorphous WN film is crystallized by the annealing and transformed into a crystalline W(N) layer (barrier metal layer 6a). The annealing is performed, for example, at a temperature higher than 400°C and lower than 1050°C. The annealing duration is, for example, one hour, but may be any other duration. In this embodiment, a W(N) layer (barrier metal layer 6a) with a k fraction of less than 40% is formed from a WN film with a k fraction of 40%, and the N concentration in the W(N) layer is lower than the N concentration in the WN film. The WN film is an example of the first layer.

[0034] The WN film for forming the barrier metal layer 6a is formed using, for example, a source gas containing W and a reducing gas containing N. The source gas is, for example, WF6 gas. The reducing gas is, for example, NH3 (ammonia) gas. In this case, the WN film and the W(N) layer (barrier metal layer 6a) formed from the WN film may contain F atoms and H atoms as impurity atoms. The source gas may contain a halogen other than F, for example, Cl (chlorine). For example, when the WN film is formed using WOCl4 gas and NH3 gas, the WN film or W(N) layer may contain Cl atoms, O atoms, and H atoms as impurity atoms (O represents oxygen). The WN film for forming the barrier metal layer 6a may be formed by a method other than CVD.

[0035] The metal layer 25 is formed using, for example, a source gas containing W and F and a reducing gas containing B and H. The source gas is, for example, WF6 gas. The reducing gas is, for example, B2H6 gas. In this case, the metal layer 25 may contain F atoms, B atoms, and H atoms as impurity atoms. The source gas may contain a halogen other than F, for example, Cl. An example of such a source gas is WOCl4 gas. In this case, the metal layer 25 may contain Cl atoms and O atoms as impurity atoms. On the other hand, the reducing gas may contain Si instead of B. Examples of such a reducing gas are SiH4 gas and Si2H6 gas. In this case, the metal layer 25 may contain Si atoms and H atoms as impurity atoms.

[0036] The metal layer 26 is formed, for example, using a source gas containing W and F and a reducing gas containing H. The source gas is, for example, WF6 gas. The reducing gas is, for example, H2 gas. In this case, the metal layer 26 may contain F atoms and H atoms as impurity atoms. The source gas may contain a halogen other than F, for example, Cl. An example of such a source gas is WOCl4 gas. In this case, the metal layer 26 may contain Cl atoms and O atoms as impurity atoms.

[0037] According to this embodiment, by forming the electrode layer 6 using a W(N) layer (barrier metal layer 6a), it is possible to make the metal layer 25 thinner than when the barrier metal layer is a TiN film. As a result, by thinning the metal layer 25, which is a high-resistance layer, it is possible to reduce the electrical resistance of the electrode layer 6. In addition, the W(N) layer is more effective in suppressing the diffusion of F atoms than a WN film. Therefore, according to this embodiment, by forming the electrode layer 6 using a W(N) layer, it is possible to effectively suppress the diffusion of F atoms. This also applies to halogen atoms other than F atoms. Further details of this content will be described later.

[0038] 8A to 8C are cross-sectional views showing details of the method for manufacturing the semiconductor device of the first embodiment. More specifically, Fig. 8A to 8C show the process for forming the structure shown in Fig. 7.

[0039] When forming the electrode layer 6 in each recess Hb, first, a barrier metal layer 6c is formed on the surface of the insulating film 5b (FIG. 8(a)). The barrier metal layer 6c is, for example, a WN film. In this embodiment, the barrier metal layer 6c is formed by CVD using WF6 gas and NH3 gas, and the composition ratio of W atoms to N atoms in the barrier metal layer 6c is 6:4. Therefore, the ratio k of the number n2 of N atoms to the sum of the number n1 of W atoms and the number n2 of N atoms in the barrier metal layer 6c is 40% (i.e., k = n2 / (n1 + n2) = 0.40). The barrier metal layer 6c is an example of the first layer.

[0040] Next, the barrier metal layer 6c is annealed (FIG. 8(b)). The annealing is performed, for example, using a predetermined gas (e.g., H2 gas) at a temperature higher than 400°C. The annealing is performed, for example, at a temperature higher than 500°C and lower than 1050°C. As a result, the barrier metal layer 6c is transformed into a barrier metal layer 6a. The barrier metal layer 6a is, for example, a W(N) layer, i.e., a W layer containing N atoms as impurity atoms. In this embodiment, the WN film (barrier metal layer 6c), which is an amorphous layer, is crystallized by the annealing and transformed into a crystalline W(N) layer (barrier metal layer 6a). In this embodiment, the barrier metal layer 6c, whose proportion k is 40%, is transformed into a barrier metal layer 6a, whose proportion k is less than 40%, and the N concentration in the barrier metal layer 6a becomes lower than the N concentration in the barrier metal layer 6c.

[0041] Next, a metal layer 25 is formed on the surface of the barrier metal layer 6a (FIG. 8(c)). The metal layer 25 is, for example, a W layer containing W as a main component, and is formed using WF6 gas and B2H6 gas. The metal layer 25 of this embodiment is formed as an amorphous layer at, for example, 300°C or lower (preferably 200°C or lower). The metal layer 25 of this embodiment is formed as an initial film for the electrode material layer 6b. Furthermore, the N concentration in the barrier metal layer 6a of this embodiment is higher than the N concentration in the metal layer 25.

[0042] Next, a metal layer 26 is formed on the surface of the metal layer 25 (FIG. 8(c)). The metal layer 26 is, for example, a W layer containing W as a main component, and is formed using WF6 gas and H2 gas. The metal layer 26 of this embodiment is formed as a polycrystalline layer at, for example, 450°C. In this embodiment, the metal layer 26 is formed at a temperature higher than the temperature at which the metal layer 25 is formed. The metal layer 26 may be formed to include a seam of Ga. The metal layer 26 is, for example, an LFW (Low-Fluorine Tungsten) layer or a CVD-W (Chemical-Vapor-Deposition Tungsten) layer. The metal layer 26 of this embodiment forms the electrode material layer 6b together with the metal layer 25. Furthermore, the N concentration in the barrier metal layer 6a of this embodiment is higher than the N concentration in the metal layer 26. The metal layer 26 has an N concentration of, for example, 7.0×10 19 ~2.0×20 20 atoms / cm 3 The N concentration is a value measured by, for example, SIMS (Secondary Ion Mass Spectrometry) analysis.

[0043] In this embodiment, the metal layer 25 may also be changed from an amorphous layer to a polycrystalline layer during or after the formation of the metal layer 26. In this case, the metal layer 25 is crystallized by annealing at, for example, 600° C. or higher, preferably 750° C. or higher, and changes from an amorphous layer to a polycrystalline layer.

[0044] FIG. 9 is a graph relating to the characteristics of the semiconductor device of the first embodiment.

[0045] FIG. 9(a) shows the results of XPS (X-ray Photoelectron Spectroscopy) analysis of the barrier metal layer 6a. The horizontal axis represents the annealing temperature of the barrier metal layer 6a. The vertical axis represents the intensity of N atoms (N intensity) in the barrier metal layer 6a. As the N concentration in the barrier metal layer 6a decreases, the N intensity decreases. FIG. 9(a) shows the results of XPS analysis when annealing was performed using H gas or Ar (argon) gas (comparative example) as the predetermined gas.

[0046] 9(a) shows that annealing using H gas reduces the N concentration in the barrier metal layer 6a. Therefore, it is desirable to anneal the barrier metal layer 6c of this embodiment using H gas. Also, it is clear from FIG. 9(a) that the N intensity for H gas begins to decrease from 400°C, and the N intensity at 500°C is significantly lower than the N intensity at 400°C. Therefore, the barrier metal layer 6c of this embodiment is annealed at a temperature higher than 400°C, preferably at a temperature of 500°C or higher.

[0047] In FIG. 9(a), the N intensity of the barrier metal layer 6a annealed at 500°C or higher is higher than the N intensity of the LFW layer (metal layer 26). In this case, the N concentration in the barrier metal layer 6a is higher than the N concentration in the LFW layer. As described above, the ratio k of the barrier metal layer 6a in this embodiment is less than 40%, and preferably 10% or less. The ratio k of the barrier metal layer 6a in this embodiment is, for example, 5% or less. As shown in FIG. 9(a), annealing at 500°C or higher using H2 gas can significantly reduce the N concentration in the barrier metal layer 6a. Therefore, a barrier metal layer 6a with a ratio k of 10% or less or 5% or less can be achieved by annealing at 500°C or higher using H2 gas, for example.

[0048] FIG. 9(b) shows the results of X-ray scattering for the barrier metal layer 6a. The horizontal axis represents the scattering angle (2θ). The vertical axis represents the scattering intensity. FIG. 9(b) shows the results of X-ray scattering for the barrier metal layer 6c annealed using H2 gas at 300°C, 400°C, 500°C, 580°C, or 650°C. FIG. 9(b) also shows the results of X-ray scattering for the LFW layer (metal layer 26) as a comparative example.

[0049] 9(b) shows that an X-ray scattering peak is observed when the annealing temperature is 500°C or higher. This shows that the barrier metal layer 6a of this embodiment is a crystalline layer. Also, FIG. 9(b) shows that the LFW layer (metal layer 26) of this embodiment is also a crystalline layer.

[0050] FIG. 10 is another graph relating to the characteristics of the semiconductor device of the first embodiment.

[0051] FIG. 10 shows the results of XPS analysis of the barrier metal layer 6a. The horizontal axis represents the annealing temperature of the barrier metal layer 6c. The vertical axis represents the intensity (F intensity) of F atoms in the barrier metal layer 6a. The F intensity decreases as the F concentration in the barrier metal layer 6a decreases. FIG. 10 shows the results of XPS analysis when annealing is performed using H gas or Ar gas (comparative example) as the predetermined gas.

[0052] 10, when annealing is performed using H gas, the F concentration in the barrier metal layer 6a can be reduced to approximately the F concentration in the LFW layer (metal layer 26) by annealing at 500° C. Therefore, annealing at 500° C. or higher is effective not only for reducing the N concentration in the barrier metal layer 6a but also for reducing the F concentration in the barrier metal layer 6a.

[0053] FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the first embodiment.

[0054] The structure of the semiconductor device of this modification (FIG. 11) is similar to that of the semiconductor device of the first embodiment (FIG. 7). However, whereas the electrode material layer 6b of the first embodiment includes metal layers 25 and 26, the electrode material layer 6b of this modification includes only the metal layer 26. The semiconductor device of this modification can be manufactured, for example, by the method shown in FIGS. 9(a) to 9(c) by omitting the step of forming the metal layer 25.

[0055] As described above, each electrode layer 6 of this embodiment includes a barrier metal layer 6a that is a W(N) layer and an electrode material layer 6b (metal layers 25, 26) that is a W layer. Therefore, according to this embodiment, it is possible to form an electrode layer 6 having suitable properties. For example, it is possible to reduce the electrical resistance of the electrode layer 6 and to suppress the diffusion of F atoms from the electrode layer 6 to other layers.

[0056] (Second embodiment) FIG. 12 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment and the structure of a semiconductor device according to a modification of the second embodiment.

[0057] FIG. 12(a) shows a semiconductor device of the second embodiment. The semiconductor device of this embodiment includes an interlayer insulating film 31 formed on the substrate 11 described above, and a wiring layer 32 formed in the interlayer insulating film 31. The wiring layer 32 is, for example, one of multiple wiring layers forming the multilayer wiring structure of the semiconductor device of this embodiment, and includes one or more wirings. FIG. 12(a) shows one of these wirings. The wiring layer 32 may be a plug layer including one or more contact plugs or one or more via plugs. The interlayer insulating film 31 is an example of a first insulating film. The wiring layer 32 is an example of a first wiring layer.

[0058] The wiring layer 32 shown in FIG. 12(a) includes a barrier metal layer 32a and a wiring material layer 32b formed in this order in the interlayer insulating film 31. The barrier metal layer 32a is formed on the side and top surfaces of the interlayer insulating film 31. The wiring material layer 32b includes a metal layer 42 formed on the side and top surfaces of the barrier metal layer 32a. FIG. 12(a) also shows a seam Gb formed in the metal layer 42 when the metal layer 42 is formed. This seam Gb is an air gap extending generally parallel to the Z direction. The barrier metal layer 32a is an example of the first layer. The metal layer 42 is an example of the second layer.

[0059] The barrier metal layer 32a of this embodiment corresponds to the barrier metal layer 6a of the first embodiment and is formed by the same method as the barrier metal layer 6a of the first embodiment. Therefore, the barrier metal layer 32a is, for example, a W(N) layer and has the same N concentration as the barrier metal layer 6a.

[0060] Furthermore, the metal layer 42 of this embodiment corresponds to the metal layer 26 of the first embodiment and is formed by the same method as the metal layer 26 of the first embodiment. Therefore, the metal layer 42 is, for example, a W layer and has the same N concentration as the metal layer 26.

[0061] The wiring layer 32 of this embodiment does not include a metal layer corresponding to the metal layer 26 of the first embodiment. Therefore, the wiring layer 32 of this embodiment has a structure similar to that of the electrode layer 6 of the modified example of the first embodiment shown in FIG.

[0062] 12(b) shows a semiconductor device according to a modification of the second embodiment. The structure of the semiconductor device according to this modification is similar to that of the semiconductor device according to the second embodiment shown in FIG. 12(a). However, the wiring material layer 32b according to this modification includes a metal layer 41 between the barrier metal layer 32a and the metal layer 42. The metal layer 41 is an example of the third layer.

[0063] The metal layer 41 of this modification corresponds to the metal layer 25 of the first embodiment and is formed by the same method as the metal layer 25 of the first embodiment. Therefore, the metal layer 41 is, for example, a W layer and has the same N concentration as the metal layer 25.

[0064] 13A to 13C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the second embodiment.

[0065] First, an interlayer insulating film 31 is formed on the substrate 11, and then a wiring groove Hc is formed in the interlayer insulating film 31 by photolithography and RIE (FIG. 13(a)). The interlayer insulating film 31 may be formed directly on the substrate 11, or may be formed on the substrate 11 via another layer. The wiring groove Hc is an example of a first recess.

[0066] Next, a barrier metal layer 32c is formed on the side and upper surfaces of the interlayer insulating film 31 in the wiring trench Hc (FIG. 13(b)). The barrier metal layer 32c is, for example, a WN film. In this embodiment, the barrier metal layer 32c is formed by CVD using WF6 gas and NH3 gas, and the composition ratio of W atoms to N atoms in the barrier metal layer 32c is 6:4. Therefore, the ratio k of the number n2 of N atoms to the sum of the number n1 of W atoms and the number n2 of N atoms in the barrier metal layer 32c is 40% (i.e., k = n2 / (n1 + n2) = 0.40). The barrier metal layer 32c is an example of a first layer. Note that the barrier metal layer 32c formed outside the wiring trench Hc is not shown.

[0067] Next, the barrier metal layer 32c is annealed (FIG. 13(c)). The annealing is performed, for example, using a predetermined gas (e.g., H2 gas) at a temperature higher than 400°C. The annealing is performed, for example, at a temperature higher than 500°C and lower than 1050°C. As a result, the barrier metal layer 32c is transformed into the barrier metal layer 32a. The barrier metal layer 32a is, for example, a W(N) layer, i.e., a W layer containing N atoms as impurity atoms. In this embodiment, the amorphous WN film (barrier metal layer 32c) is crystallized by the annealing and transformed into a crystalline W(N) layer (barrier metal layer 32a). In this embodiment, the barrier metal layer 32c with a k ratio of 40% is transformed into the barrier metal layer 32a with a k ratio of less than 40%, and the N concentration in the barrier metal layer 32a becomes lower than the N concentration in the barrier metal layer 32c.

[0068] Next, a metal layer 42 (wiring material layer 32b) is formed on the side and upper surfaces of the barrier metal layer 32a in the wiring trench Hc (FIG. 13(c)). The metal layer 42 is, for example, a W layer containing W as a main component, and is formed using WF6 gas and H2 gas. The metal layer 42 of this embodiment is formed as a polycrystalline layer at, for example, 450°C. The metal layer 42 may be formed to include a seam Gb. The metal layer 42 is, for example, an LFW layer or a CVD-W layer. The N concentration in the barrier metal layer 32a of this embodiment is higher than the N concentration in the metal layer 42. The metal layer 42 has an N concentration of, for example, 7.0×10 19 ~2.0×20 20 atoms / cm 3 The metal layer 42 formed outside the wiring trench Hc is not shown.

[0069] Thereafter, the barrier metal layer 32a and the metal layer 42 formed outside the wiring trench Hc are removed by, for example, CMP (Chemical Mechanical Polishing), resulting in the wiring layer 32 including the barrier metal layer 32a and the metal layer 42 being formed in the wiring trench Hc.

[0070] In this manner, the semiconductor device of the second embodiment shown in Fig. 12(a) is manufactured. When manufacturing the semiconductor device of the modified example of the second embodiment shown in Fig. 12(b), the metal layer 41 is formed after the barrier metal layer 32a is formed and before the metal layer 42 is formed. The method for forming the metal layer 41 is the same as the method for forming the metal layer 25 in the step of Fig. 8(c).

[0071] As described above, the wiring layer 32 of this embodiment includes the barrier metal layer 32a, which is a W(N) layer, and the wiring material layer 32b, which is a W layer. Therefore, according to this embodiment, it is possible to form the wiring layer 32 having preferable characteristics. For example, like the electrode layer 6 of the first embodiment, it is possible to reduce the electrical resistance of the wiring layer 32 and suppress the diffusion of F atoms from the wiring layer 32 to other layers.

[0072] (Third embodiment) 14 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment. The semiconductor device according to this embodiment is, for example, a three-dimensional semiconductor memory, and is manufactured by bonding an array wafer including an array region 101 and a circuit wafer including a circuit region 102. The relationship between this embodiment and the first and second embodiments will be described later.

[0073] The array region 101 includes a memory cell array 111 including a plurality of memory cells, an insulating film 112 on the memory cell array 111, and an interlayer insulating film 113 below the memory cell array 111. The insulating film 112 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 113 is, for example, a silicon oxide film or a stacked film including a silicon oxide film and another insulating film.

[0074] The circuit region 102 is provided below the array region 101. Figure 14 shows the boundary surface (bonding surface) S between the array region 101 and the circuit region 102. The circuit region 102 includes an interlayer insulating film 114 below the interlayer insulating film 113, and a substrate 115 below the interlayer insulating film 114. The interlayer insulating film 114 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The substrate 115 is, for example, a semiconductor substrate such as a silicon substrate.

[0075] 14 shows the X and Y directions, which are parallel to and perpendicular to the surface of substrate 115, and the Z direction, which is perpendicular to the surface of substrate 115. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity.

[0076] The array region 101 includes a plurality of word lines WL and source lines SL as a plurality of electrode layers in a memory cell array 111. FIG. 14 shows a staircase structure 121 of the memory cell array 111. Each word line WL is electrically connected to a word wiring layer 123 via a contact plug 122. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug 124 and is also electrically connected to a source line SL. The source line SL includes a lower layer SL1 that is a semiconductor layer and an upper layer SL2 that is a metal layer.

[0077] The circuit region 102 includes a plurality of transistors 131. Each transistor 131 includes a gate electrode 132 provided on the substrate 115 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 115. The circuit region 102 further includes a plurality of contact plugs 133 provided on the gate electrodes 132, source diffusion layers, or drain diffusion layers of these transistors 131, and a wiring layer 134 provided on these contact plugs 133 and including a plurality of wirings.

[0078] The circuit region 102 also includes a wiring layer 135 provided on the wiring layer 134 and including a plurality of wirings, and a wiring layer 136 provided on the wiring layer 135 and including a plurality of wirings. The circuit region 102 further includes a plurality of via plugs 137 provided on the wiring layer 136 and a plurality of metal pads 138 provided on these via plugs 137. The metal pads 138 are, for example, metal layers including a Cu (copper) layer. The circuit region 102 functions as a control circuit (logic circuit) that controls the operation of the array region 101. This control circuit is composed of transistors 131 and the like, and is electrically connected to the metal pads 138.

[0079] The array region 101 includes a plurality of metal pads 141 provided on the metal pads 138, and a plurality of via plugs 142 provided on the metal pads 141. The metal pads 141 are, for example, a metal layer including a Cu layer. The array region 101 further includes a wiring layer 143 provided on the via plugs 142 and including a plurality of wirings, and a wiring layer 144 provided on the wiring layer 143 and including a plurality of wirings. The bit lines BL are included in the wiring layer 144. The control circuit is electrically connected to the memory cell array 111 via the metal pads 141, 138, etc., and controls the operation of the memory cell array 111 via the metal pads 141, 138, etc.

[0080] The array region 101 also includes a plurality of via plugs 145 provided on the wiring layer 144, metal pads 146 provided on the via plugs 145 and the insulating film 112, and a passivation insulating film 147 provided on the metal pads 146 and the insulating film 112. The metal pads 146 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device of this embodiment. The passivation insulating film 147 is, for example, a laminated film including a silicon oxide film and a silicon nitride film, and has an opening P that exposes the top surface of the metal pads 146. The metal pads 146 can be electrically connected to a mounting substrate or another device via a bonding wire, a solder ball, a metal bump, or the like through the opening P.

[0081] 15 is a cross-sectional view showing the structure of a columnar portion CL of the third embodiment, showing one of the plurality of columnar portions CL shown in FIG.

[0082] 15, the memory cell array 111 includes a plurality of word lines WL and a plurality of insulating films 151 alternately stacked on an interlayer insulating film 113 (see FIG. 14). The word lines WL are, for example, metal layers including a W layer. The insulating films 151 are, for example, silicon oxide films.

[0083] The columnar portion CL includes, in this order, a block insulating film 152, a charge storage layer 153, a tunnel insulating film 154, a channel semiconductor layer 155, and a core insulating film 156. The charge storage layer 153 is, for example, an insulating film such as a silicon nitride film, and is formed on the side surfaces of the word line WL and the insulating film 151 via the block insulating film 152. The channel semiconductor layer 155 is, for example, a polysilicon layer, and is formed on the side surfaces of the charge storage layer 153 via the tunnel insulating film 154. The block insulating film 152, the tunnel insulating film 154, and the core insulating film 156 are, for example, silicon oxide films.

[0084] 16 and 17 are cross-sectional views showing a method for manufacturing the semiconductor device of the third embodiment.

[0085] Fig. 16 shows an array wafer W1 and a circuit wafer W2. Specifically, Fig. 16 shows one of a plurality of array regions 101 included in the array wafer W1 and one of a plurality of circuit regions 102 included in the circuit wafer W2.

[0086] The orientation of the array wafer W1 in Fig. 16 is opposite to the orientation of the array region 101 in Fig. 14. In this embodiment, multiple semiconductor devices are manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Fig. 16 shows the array wafer W1 before its orientation is reversed for bonding, and Fig. 14 shows the array region 101 after its orientation is reversed for bonding, bonding, and dicing.

[0087] 16 further shows the top surface S1 of the array wafer W1 and the top surface S2 of the circuit wafer W2. The array wafer W1 includes a substrate 116 provided under an insulating film 112. The substrate 116 is, for example, a semiconductor substrate such as a silicon substrate.

[0088] In this embodiment, as shown in FIG. 16, first, a memory cell array 111, an insulating film 112, an interlayer insulating film 113, a staircase structure 121, a metal pad 141, etc. are formed on a substrate 116 of an array wafer W1, and an interlayer insulating film 114, a transistor 131, a metal pad 138, etc. are formed on a substrate 115 of a circuit wafer W2. For example, via plugs 145, a wiring layer 144, a wiring layer 143, a via plug 142, and a metal pad 141 are formed in this order on the substrate 116. Also, contact plugs 133, a wiring layer 134, a wiring layer 135, a wiring layer 136, a via plug 137, and a metal pad 138 are formed in this order on the substrate 115. Next, as shown in FIG. 17, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 113 and the interlayer insulating film 114. Next, the array wafer W1 and the circuit wafer W2 are annealed. As a result, the metal pad 141 and the metal pad 138 are bonded together.

[0089] Thereafter, the substrate 115 is thinned by CMP, the substrate 116 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device shown in Figure 14 is manufactured. Note that the metal pads 146 and the passivation insulating film 147 are formed on the insulating film 112, for example, after the substrate 115 is thinned and the substrate 116 is removed.

[0090] 14 shows the boundary surface between interlayer insulating film 113 and interlayer insulating film 114 and the boundary surface between metal pad 141 and metal pad 138, but these boundaries generally become invisible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of metal pad 141 or the side surface of metal pad 138, or the positional deviation between the side surface of metal pad 141 and the side surface of metal pad 138.

[0091] Next, the relationship between this embodiment and the first and second embodiments will be described.

[0092] Each word line WL of this embodiment may be formed by, for example, the same method as the electrode layer 6 of the first embodiment. This makes it possible to reduce the electrical resistance of the word line WL and to suppress the diffusion of F atoms from the word line WL to other layers. In this case, the substrate 116, insulating film 151, block insulating film 152, charge storage layer 153, tunnel insulating film 154, channel semiconductor layer 155, and core insulating film 156 of this embodiment correspond to the substrate 11, insulating film 14, block insulating film 5, charge storage layer 4, tunnel insulating film 3, channel semiconductor layer 2, and core insulating film 1 of the first embodiment, respectively. However, the substrate 116 of this embodiment is removed after bonding the array wafer W1 and the circuit wafer W2, and therefore does not remain in the manufactured semiconductor device.

[0093] Furthermore, at least one of the wiring layers 134, 135, 136, 143, and 144 of this embodiment may be formed by, for example, the same method as the wiring layer 32 of the second embodiment. This makes it possible to reduce the electrical resistance of the wiring layer and to suppress the diffusion of F atoms from the wiring layer to other layers. In this case, the substrate 116 or 115 of this embodiment corresponds to the substrate 11 of the second embodiment, and the interlayer insulating film 113 or 114 of this embodiment corresponds to the interlayer insulating film 31 of the second embodiment. However, the substrate 116 of this embodiment is removed after the array wafer W1 and the circuit wafer W2 are bonded together, and therefore does not remain in the manufactured semiconductor device.

[0094] As described above, according to this embodiment, like the first and second embodiments, it is possible to form a wiring layer having suitable characteristics.

[0095] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0096] 1: core insulating film, 2: channel semiconductor layer, 3: tunnel insulating film, 4: charge storage layer, 5: block insulating film, 5a: insulating film, 5b: insulating film, 6: electrode layer, 6a: barrier metal layer, 6a': barrier metal layer, 6b: electrode material layer, 6c: barrier metal layer, 11: substrate, 12: laminated film, 13: sacrificial layer, 14: insulating film, 21: metal layer, 22: metal layer, 23: metal layer, 24: metal layer, 25: metal layer, 26: metal layer, 31: Interlayer insulating film, 32: Wiring layer, 32a: Barrier metal layer, 32b: wiring material layer, 32c: barrier metal layer, 41: metal layer, 42: metal layer, 101: array area, 102: circuit area, 111: memory cell array, 112: insulating film, 113: interlayer insulating film, 114: interlayer insulating film, 115: substrate, 116: substrate, 121: staircase structure portion, 122: contact plug, 123: word wiring layer, 124: via plug, 131: transistor; 132: gate electrode; 133: contact plug; 134: wiring layer, 135: wiring layer, 136: wiring layer, 137: via plug, 138: metal pad, 141: metal pad, 142: via plug, 143: wiring layer, 144: wiring layer, 145: via plug, 146: metal pad, 147: passivation insulating film, 151: insulating film, 152: block insulating film, 153: charge storage layer, 154: tunnel insulating film, 155: channel semiconductor layer, 156: core insulating film

Claims

1. a first insulating film; a first wiring layer including: a first layer provided in the first insulating film and containing tungsten and nitrogen; and a second layer provided in the first insulating film via the first layer and containing tungsten; the nitrogen concentration in the first layer is higher than the nitrogen concentration in the second layer; the ratio of the number of nitrogen atoms to the sum of the number of tungsten atoms and the number of nitrogen atoms in the first layer is less than 40%; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein said first layer contains tungsten as a main component and nitrogen atoms as impurity atoms.

3. The semiconductor device according to claim 1 , wherein the first layer is a crystalline layer.

4. The nitrogen concentration in the second layer is 7.0×10 １９ ~2.0 x 20 ２０ atoms / cm ３ 2. The semiconductor device according to claim 1, wherein:

5. The semiconductor device according to claim 1 , wherein the second layer contains fluorine or chlorine.

6. 2. The semiconductor device according to claim 1, wherein said first layer is a barrier metal layer, and said second layer is a wiring material layer.

7. 2. The semiconductor device according to claim 1, wherein said first wiring layer further includes a third layer provided between said first layer and said second layer and containing tungsten.

8. The semiconductor device according to claim 7 , wherein the third layer contains boron or silicon.

9. further comprising a stacked film including a plurality of electrode layers and a plurality of second insulating films alternately; the first wiring layer is one of the plurality of electrode layers, the first insulating film includes two second insulating films among the plurality of second insulating films; The semiconductor device according to claim 1 .

10. a charge storage layer provided on a side surface of the plurality of electrode layers via a third insulating film; a semiconductor layer provided on a side surface of the charge storage layer via a fourth insulating film; The semiconductor device according to claim 9 , further comprising:

11. forming a first insulating film; forming a first layer containing tungsten and nitrogen on the first insulating film; annealing the first layer at a temperature greater than 400°C; forming a second layer containing tungsten on the first layer after the annealing; A method for manufacturing a semiconductor device, comprising:

12. The method for manufacturing a semiconductor device according to claim 11, wherein the annealing is performed at a temperature lower than 1050°C.

13. The annealing is performed using H ２ The method for manufacturing a semiconductor device according to claim 11, wherein the method is carried out using (hydrogen) gas.

14. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the first layer before the annealing is a WN film (tungsten nitride film).

15. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the first layer is formed by CVD (Chemical Vapor Deposition).

16. The method for manufacturing a semiconductor device according to claim 11 , wherein the first layer is crystallized by the annealing.

17. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the annealing is performed so that the nitrogen concentration in the first layer after the annealing is lower than the nitrogen concentration in the first layer before the annealing.

18. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the first layer and the second layer are formed so that a nitrogen concentration in the first layer after the annealing is higher than a nitrogen concentration in the second layer, and a ratio of the number of nitrogen atoms to a sum of the number of tungsten atoms and the number of nitrogen atoms in the first layer after the annealing is smaller than 40%.

19. forming a laminated film including a plurality of fourth layers and a plurality of second insulating films alternately; removing the fourth layers to form a plurality of first recesses in the film stack; forming a plurality of electrode layers in the plurality of first recesses; It further includes: The method for manufacturing a semiconductor device according to claim 11 , wherein the first layer and the second layer are included in one electrode layer of the plurality of electrode layers.

20. forming a charge storage layer on a side surface of the plurality of fourth layers via a third insulating film; forming a semiconductor layer on a side surface of the charge storage layer via a fourth insulating film; It further includes: The method for manufacturing a semiconductor device according to claim 19 , wherein the plurality of fourth layers are removed after the semiconductor layer is formed.

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