Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of improving electrical characteristics.SOLUTION: A semiconductor memory device according to one embodiment comprises a laminated body, a plurality of columnar bodies, a plurality of bit lines, and a plurality of separation parts. The plurality of separation parts are arranged apart from each other in a third direction. The plurality of separation parts include a first separation part and a second separation part adjacent to each other among the plurality of separation parts. The plurality of columnar bodies include three or more columnar bodies arranged in a first row extending in the third direction in a region between the first separation part and the second separation part, and two or more columnar bodies arranged in a second row extending in the third direction and adjacent to the first row in a second direction. The three or more columnar bodies and the two or more columnar bodies are alternately arranged with respect to the third direction. The three or more columnar bodies and the two or more columnar bodies are electrically connected to different bit lines among the plurality of bit lines.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-41054 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor memory device that can improve electrical characteristics. [Means for solving the problem]

[0005] In one embodiment, a semiconductor memory device includes a stack, a plurality of pillars, a plurality of bit lines, and a plurality of dividing portions. The stack includes a plurality of gate electrode layers and a plurality of insulating layers. The gate electrode layers and the insulating layers are alternately stacked layer by layer in a first direction. The pillars extend in the first direction within the stack. Transistors are formed at intersections between the pillars and the gate electrode layers. The bit lines are arranged on one side of the stack in the first direction. The bit lines are aligned in a second direction intersecting the first direction. The bit lines each extend in a third direction intersecting the first and second directions. The dividing portions are arranged separately in the third direction. Each of the dividing portions extends in the first direction within the stack. When the one side is defined as the bottom, the dividing portions divide one or more gate electrode layers, including a lowest layer, of the plurality of gate electrode layers in the third direction. The plurality of dividing portions include a first dividing portion and a second dividing portion that are adjacent to each other among the plurality of dividing portions. The plurality of pillars include, in a region between the first dividing portion and the second dividing portion, three or more pillars arranged in a first row extending in the third direction and two or more pillars arranged in a second row extending in the third direction and adjacent to the first row in the second direction. The three or more pillars and the two or more pillars are arranged alternately in the third direction. The three or more pillars and the two or more pillars are electrically connected to different bit lines among the plurality of bit lines. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a part of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing a part of a semiconductor memory device according to a first embodiment. [Figure 4] 4 is an enlarged cross-sectional view showing a region surrounded by line F4 of the semiconductor memory device shown in FIG. 3. [Figure 5]FIG. 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device shown in FIG. 4. [Figure 6] FIG. 4 is a cross-sectional view taken along line F6-F6 of the semiconductor memory device shown in FIG. 3. [Figure 7] 7 is an enlarged cross-sectional view showing a region surrounded by line F7 of the semiconductor memory device shown in FIG. 6; [Figure 8] FIG. 4 is a cross-sectional view taken along line F8-F8 of the semiconductor memory device shown in FIG. 3. [Figure 9] 9 is an enlarged cross-sectional view showing a region surrounded by line F9 of the semiconductor memory device shown in FIG. 8. [Figure 10] 9 is an enlarged cross-sectional view showing a region surrounded by line F10 of the semiconductor memory device shown in FIG. 8. [Figure 11] 4 is an enlarged cross-sectional view showing a region surrounded by line F11 of the semiconductor memory device shown in FIG. 3. [Figure 12] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 4A and 4B are cross-sectional views illustrating a manufacturing method around the bit line according to the first embodiment. [Figure 14] 4A and 4B are cross-sectional views illustrating a manufacturing method around the bit line according to the first embodiment. [Figure 15] 4A and 4B are cross-sectional views illustrating a manufacturing method around the bit line according to the first embodiment. [Figure 16] 4A to 4C are diagrams for explaining advantages of the semiconductor memory device of the first embodiment. [Figure 17] 4A to 4C are diagrams for explaining advantages of the semiconductor memory device of the first embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing a part of a semiconductor memory device according to a first modified example of the first embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing a part of a semiconductor memory device according to a second modification of the first embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a part of a semiconductor memory device according to a second embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing a part of a semiconductor memory device according to a second embodiment. [Figure 22] FIG. 10 is a diagram for explaining advantages of the semiconductor memory device according to the second embodiment. [Figure 23] FIG. 11 is a cross-sectional view showing a part of a semiconductor memory device according to a first modified example of the second embodiment. [Figure 24] FIG. 10 is a cross-sectional view showing a part of a semiconductor memory device according to a second modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a semiconductor memory device according to an embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions will be assigned the same reference numerals. Further, duplicate descriptions of those components may be omitted. In the following description, reference numerals with a distinguishing number or letter at the end may have the number or letter at the end omitted if they do not need to be distinguished from each other.

[0008] In this application, terms are defined as follows: "Parallel," "orthogonal," or "same" may include the cases of "substantially parallel," "substantially orthogonal," or "substantially the same," respectively. "Connection" is not limited to mechanical connection, but may also include electrical connection. That is, "connection" is not limited to the case where multiple elements are directly connected, but may include the case where multiple elements are connected via another element interposed therebetween. "Overlapping" is not limited to the case where multiple elements are in contact with each other, but may also include the case where multiple elements are separated (the case where the projected images of multiple elements overlap when viewed from a certain direction).

[0009] Define the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction as follows. The +X direction is the direction in which the word line WL, which will be described later, extends (see FIG. 3). The -X direction is the opposite direction of the +X direction. When the +X direction and the -X direction are not distinguished, they are simply referred to as the X direction. The +Y direction is a direction that intersects (for example, is orthogonal to) the X direction. The +Y direction is the direction in which the bit line BL extends (see FIG. 6). The -Y direction is the opposite direction of the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction that intersects (for example, is orthogonal to) the X direction and the Y direction. The +Z direction is the direction from the bit line BL, which will be described later, toward the laminate 40 (see FIG. 3). The -Z direction is the opposite direction of the +Z direction. When the +Z direction and the -Z direction are not distinguished, they are simply referred to as the Z direction.

[0010] In this application, the +Z direction side may be referred to as "up" and the -Z direction side may be referred to as "down". However, these expressions are for convenience of explanation and do not define the direction of gravity. The Z direction is an example of the "first direction". The X direction is an example of the "second direction". The Y direction is an example of the "third direction". Also, in the drawings described below, illustrations of configurations not related to the explanation may be omitted.

[0011] (First Embodiment) <A1. Configuration of the Semiconductor Memory Device> FIG. 1 is a block diagram showing a part of the semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device and is a NAND type flash memory. The semiconductor memory device 1 can be connected to an external host device and is used as a storage space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0012] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer of 1 or more). A block BLK is a set of memory cell transistors. A block BLK is used as an erasure unit of data. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0013] The command register 12 holds a command CMD received by the semiconductor memory device 1 from the host device. The address register 13 holds address information ADD received by the semiconductor memory device 1 from the host device. The address information ADD is used for selection of a block BLK, a word line, and a bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erasure operation, etc. based on the command CMD held in the command register 12.

[0014] The driver module 15 includes a voltage generation circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line in a write operation. The sense amplifier module 17 determines the data value stored in each memory cell transistor based on the voltage of each bit line in a read operation, and transfers the determination result to the host device as read data DAT.

[0015] <A2. Electrical Configuration of Memory Cell Array> FIG. 2 is a diagram showing a partial equivalent circuit of the memory cell array 11. FIG. 2 shows one block BLK included in the memory cell array 11. A block BLK includes a plurality of strings STR (for example, four strings STR0 to STR3).

[0016] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes, for example, a plurality of memory cell transistors MT0 to MTn (n is an integer equal to or greater than 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0017] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to one of word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage section in response to a voltage applied to the control gate via the word line WL, thereby retaining data in a non-volatile manner.

[0018] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor STD is connected to one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor STD is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. The drain-side select transistor STD connects the NAND string NS to the bit line BL when a predetermined voltage is applied to the corresponding drain-side select gate line SGD.

[0019] The drain of the source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of the source-side select transistor STS is connected to a source line SL. The control gate of the source-side select transistor STS is connected to a source-side select gate line SGS. The source-side select transistor STS connects the NAND string NS to the source line SL when a predetermined voltage is applied to the source-side select gate line SGS.

[0020] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the corresponding word lines WL0 to WLn, respectively. In the same string STR, the control gate of the drain side selection transistor STD is commonly connected to the corresponding drain side selection gate line SGD. The control gate of the source side selection transistor STS is commonly connected to the source side selection gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS to which the same column address is assigned in a plurality of strings STR.

[0021] In this embodiment, the block size of the semiconductor memory device 1 is, for example, 100 MB or more. The "block size" is the capacity of the block BLK. Also, the page length of the semiconductor memory device 1 is, for example, 16 kB or more. The "page length" is the capacity defined by the number of memory cell transistors MT corresponding to the same word line WL and the same drain side selection gate line SGD.

[0022] <A3. Physical Configuration of Semiconductor Memory Device> Next, the physical configuration of the semiconductor memory device 1 will be described. FIG. 3 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 includes, for example, a first chip 2 and a second chip 3.

[0023] <3.1 First Chip> The first chip 2 is a circuit chip including a peripheral circuit. The first chip 2 includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0024] The semiconductor substrate 21 is, for example, a substrate serving as the base of the first chip 2. At least a part of the semiconductor substrate 21 is plate-shaped along the X direction and the Y direction. The semiconductor substrate 21 is formed of a semiconductor material such as silicon, for example.

[0025] The peripheral circuit 22 is a circuit for operating the memory cell array 11 described above. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17 described above. The insulating portion 23 covers the peripheral circuit 22. The plurality of pads 24 are provided on the surface of the insulating portion 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0026] <3.2 Second Chip> The second chip 3 is an array chip including the memory cell array 11. The second chip 3 has, for example, a memory cell array 11, an insulating portion 31, and a plurality of pads 32. Here, the insulating portion 31 and the plurality of pads 32 will be described, and the memory cell array 11 will be described later.

[0027] The insulating portion 31 covers the memory cell array 11. The plurality of pads 32 are provided on the surface of the insulating portion 31. Each pad 32 is electrically connected to a wiring (for example, wiring 71 or wiring 72) included in the wiring portion 70 of the memory cell array 11 described later. In the present embodiment, the plurality of pads 24 of the first chip 2 and the plurality of pads 32 of the second chip 3 are faced and bonded to integrate the first chip 2 and the second chip 3.

[0028] <A4. Physical Configuration of Memory Cell Array> Next, the physical configuration of the memory cell array 11 will be described. As shown in FIG. 3, the memory cell array 11 has a laminate 40, a source line SL, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for the memory pillars, a plurality of contacts VY for the memory pillars, a contact CC for the conductive layer, a wiring portion 70, and a plurality of dividing portions DV (see FIG. 6).

[0029] <4.1 Laminate> First, the laminate 40 will be described. Fig. 4 is an enlarged cross-sectional view of the region surrounded by line F4 of the semiconductor memory device 1 shown in Fig. 3. The stacked body 40 includes a plurality of conductive layers 41 and a plurality of insulating layers 42. The plurality of conductive layers 41 and the plurality of insulating layers 42 are stacked alternately one layer at a time in the Z direction.

[0030] The conductive layers 41 extend in the X and Y directions. Each conductive layer 41 is made of a conductive material such as tungsten or molybdenum. The conductive layers 41 are an example of a "gate electrode layer."

[0031] Of the multiple conductive layers 41, one or more (for example, multiple) conductive layers 41 located at the bottom function as drain-side select gate lines SGD. The drain-side select gate lines SGD are provided in common to multiple memory pillars MH aligned in the X direction or Y direction. The intersections between the drain-side select gate lines SGD and channel layers 52 (described later) of each memory pillar MH function as the above-mentioned drain-side select transistors STD.

[0032] Of the multiple conductive layers 41, one or more (for example, multiple) conductive layers 41 located at the top function as a source-side select gate line SGS. The source-side select gate line SGS is provided in common to multiple memory pillars MH aligned in the X direction or Y direction. The intersection of the source-side select gate line SGS and the channel layer 52 of each memory pillar MH functions as the source-side select transistor STS described above.

[0033] Of the multiple conductive layers 41, at least some of the remaining conductive layers 41 provided between the conductive layers 41 functioning as the drain-side select gate lines SGD and the source-side select gate lines SGS function as word lines WL. The word lines WL are provided in common to the multiple memory pillars MH aligned in the X and Y directions. In this embodiment, the intersections of the word lines WL and the channel layers 52 of each memory pillar MH function as memory cell transistors MT. The memory cell transistors MT will be described in detail later.

[0034] The insulating layer 42 is an interlayer insulating film provided between two conductive layers 41 adjacent to each other in the Z direction, and insulates the two conductive layers 41. The insulating layer 42 extends in the X direction and the Y direction. The insulating layer 42 is formed of, for example, a film containing silicon and oxygen.

[0035] <4.2 Source line> The source line SL is disposed above the stacked body 40. The source line SL is a conductive layer extending in the X and Y directions. The source line SL is made of a conductive material such as polysilicon or tungsten.

[0036] <4.3 Memory pillar> The memory pillars MH are aligned in the X and Y directions (see FIG. 3). Each memory pillar MH extends in the Z direction within the stack 40 and penetrates the stack 40. The upper end of each memory pillar MH contacts a source line SL. Meanwhile, the lower end of each memory pillar MH contacts a contact CH, which will be described later. The memory pillar MH is an example of a "columnar body."

[0037] Fig. 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device 1 shown in Fig. 4. The memory pillar MH includes, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating core 53, and a cap portion 54 (see Fig. 4).

[0038] The memory film 51 is provided on the outer periphery of the channel layer 52. The memory film 51 is located between the plurality of conductive layers 41 and the channel layer 52. The memory film 51 includes, for example, a block insulating film 61, a charge trapping film 62, and a tunnel insulating film 63.

[0039] The block insulating film 61 is provided between the plurality of conductive layers 41 and the charge trap film 62. The block insulating film 61 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the charge trap film 62. The block insulating film 61 is formed in a ring shape and extends in the Z direction. For example, the block insulating film 61 extends over the entire length of the memory pillar MH in the Z direction. The block insulating film 61 is a laminated structure film in which a plurality of insulating films, such as a film containing silicon and oxygen or a film containing metal and oxygen, are stacked. An example of a film containing metal and oxygen is aluminum oxide. The block insulating film 61 may include a high-dielectric-constant material (high-k material) such as silicon nitride or hafnium oxide.

[0040] The charge trap film 62 is located between the block insulating film 61 and the tunnel insulating film 63. The charge trap film 62 is formed in a ring shape and extends in the Z direction. For example, the charge trap film 62 extends over the entire length of the memory pillar MH in the Z direction. The charge trap film 62 is a functional film that has a large number of crystal defects (trap levels) and can trap charges in the crystal defects. The charge trap film 62 is formed of, for example, a film containing silicon and nitrogen. The portions of the charge trap film 62 adjacent to each word line WL are an example of a "charge storage section" that can store information by accumulating charges.

[0041] The tunnel insulating film 63 is provided between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is, for example, annular along the outer peripheral surface of the channel layer 52 and extends in the Z direction along the channel layer 52. The tunnel insulating film 63 extends, for example, over the entire length of the memory pillar MH in the Z direction. The tunnel insulating film 63 is a potential barrier between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0042] The channel layer 52 is provided inside the memory film 51. The channel layer 52 is formed in a ring shape. The channel layer 52 extends in the Z direction. For example, the channel layer 52 covers the entire length of the memory pillar 50 in the Z direction. The channel layer 52 is formed of a semiconductor material such as polysilicon. The channel layer 52 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 52 forms a channel to electrically connect the bit line BL and the source line SL.

[0043] As a result, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed by the end of the word line WL adjacent to the memory pillar MH, the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52. Note that the memory film 51 may have a floating gate type charge storage portion (floating gate electrode) as the charge storage portion instead of the charge trap film 62. The floating gate electrode is formed of, for example, polysilicon containing impurities.

[0044] The insulating core 53 is provided inside the channel layer 52. The insulating core 53 fills at least a portion of the inside of the channel layer 52. The insulating core 53 is formed of a film containing silicon and oxygen. A portion of the insulating core 53 is formed in an annular shape along the inner circumferential surface of the channel layer 52 and may have a hollow portion (air gap) inside. The insulating core 53 extends in the Z direction. For example, the insulating core 53 spans most of the memory pillar MH in the Z direction except for the upper end portion of the memory pillar MH (see FIG. 4).

[0045] Returning to FIG. 4 , the cap portion 54 will now be described. The cap portion 54 is provided below the insulating core 53. The cap portion 54 is a semiconductor portion made of a semiconductor material such as amorphous silicon or polysilicon. The cap portion 54 may be doped with impurities. The cap portion 54 is disposed on the inner periphery of the lower end of the memory film 51 and is formed integrally with the channel layer 52. The cap portion 54, together with the lower end of the channel layer 52, forms the lower end of the memory pillar MH. The contact CH contacts the cap portion 54 from the -Z direction.

[0046] 4.4 Bit lines Next, returning to FIG. 3, the bit lines BL will be described. The bit line BL is a wiring for selecting one memory pillar MH from among the multiple memory pillars MH. The multiple bit lines BL are arranged below (on the -Z direction side of) the stack 40. The multiple bit lines BL are spaced apart in the X direction and lined up in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends so as to pass below the corresponding multiple memory pillars MH. The below side with respect to the stack 40 is an example of "one side in the first direction with respect to the stack."

[0047] When viewed from the Z direction, each bit line BL overlaps with multiple memory pillars MH (see FIG. 6). Each bit line BL is connected to the channel layer 52 of the memory pillar MH via a contact VY and a contact CH, which will be described later. This allows any memory cell transistor MT to be selected from multiple memory cell transistors MT arranged three-dimensionally by combining a word line WL and a bit line BL.

[0048] <4.5 Contact CH for memory pillar> The contacts CH are arranged between the memory pillars MH and the bit lines BL. Each contact CH is an electrical connection portion that electrically connects the contact VY and the memory pillar MH. The contact CH has, for example, a cylindrical or truncated cone shape. When viewed from the Z direction, the outer shape of the contact CH is, for example, the same as or slightly smaller than the outer shape of the memory pillar MH.

[0049] The contacts CH are disposed below the corresponding memory pillars MH and are in contact with the lower ends of the memory pillars MH. The contacts CH are in contact with, for example, the cap portions 54 of the memory pillars MH (see FIG. 4). The connection area between the contacts CH and the memory pillars MH (the overlapping area when viewed from the Z direction) is larger than the connection area between the contacts VY and the contacts CH, which will be described later. The contacts CH are formed of, for example, a metal material such as tungsten or molybdenum. Even if the materials of the contacts CH and the memory pillars MH are different, good electrical connectivity between the contacts CH and the memory pillars MH can be ensured by increasing the connection area between the contacts CH and the memory pillars MH to a certain extent.

[0050] <4.6 VY contact for memory pillar> The contacts VY are arranged between the contacts CH and the bit lines BL. Each contact VY is an electrical connection portion that electrically connects the bit line BL to the contact CH. The width of the contact VY in the X direction is smaller than the width of the contact CH in the X direction.

[0051] The contact VY is disposed above the corresponding bit line BL and is in contact with the lower end of the contact CH and the bit line BL. The contact VY is disposed at a position offset in the X direction from the center of the contact CH and the center of the memory pillar MH. The contact VY is formed of a metal material such as tungsten or molybdenum. The material forming the contact VY is, for example, the same as the material forming the contact CH. Even if the connection area between the contact VY and the contact CH is small, good electrical connectivity between the contact CH and the contact VY is ensured by using the same or similar material for the contact VY and the contact CH.

[0052] 4.7 Contacts for Conductive Layers in Staircase Regions 3, the contacts CC are electrical connection parts that electrically connect the conductive layer 41 and the wiring 72 (described later) included in the wiring section 70. The contacts CC are arranged, for example, in a staircase region in the laminate 40 where the ends of the conductive layers 41 are arranged in a staircase pattern. The contacts CC extend in the Z direction and, for example, have different lengths in the Z direction. The upper end of each contact CC is in contact with the corresponding conductive layer 41. The upper end of each contact CC is electrically connected to the corresponding conductive layer 41.

[0053] <4.8 Wiring section> Next, a description will be given of the wiring section 70. The wiring section 70 is disposed, for example, between the stacked body 40 and the semiconductor substrate 21. The wiring section 70 includes, for example, a plurality of wirings 71, a plurality of vias V1, and a plurality of wirings 72.

[0054] The wiring 71 is an electrical connection portion that electrically connects the bit line BL and the pad 32. The multiple wirings 71 are arranged, for example, below the multiple bit lines BL. Each wiring 71 extends, for example, in the X direction or the Y direction. A via V1 is provided between the wiring 71 and the bit line BL to electrically connect the wiring 71 and the bit line BL.

[0055] The wiring 72 is an electrical connection portion that electrically connects the contact CC for the conductive layer and the pad 32. The wiring 72 is electrically connected to the conductive layer 41 via the contact CC for the conductive layer. A voltage is applied to the wiring 72 to select the conductive layer 41 (word line WL, drain side select gate line SGD, or source side select gate line SGS).

[0056] <A5. Division part of the laminate> Next, the division part DV will be described. FIG. 6 is a cross-sectional view along the F6-F6 line of the semiconductor memory device 1 shown in FIG. 3. In the present embodiment, a plurality of division parts DV are provided in the laminate 40. The plurality of division parts DV are arranged separately in the Y direction. The plurality of division parts DV each extend in the Z direction within the laminate 40 and divide one or more conductive layers 41 including the lowermost layer among the plurality of conductive layers 41 in the Y direction. The plurality of division parts DV include, for example, a plurality of division parts ST and a plurality of division parts SHE.

[0057] <5.1 Division part ST> The division part ST is a wall part that divides the laminate 40 in the Y direction. The plurality of division parts ST are arranged separately in the Y direction. The division part ST extends in the Z direction, penetrates the laminate 40, and extends in the X direction. That is, the division part ST is a wall part along the Z direction and the X direction. The division part ST divides each of all the conductive layers 41 included in the laminate 40 in the Y direction. The division part ST includes, for example, an insulating part STa and a conductive part STb.

[0058] The insulating part STa extends in the Z direction and penetrates the laminate 40. The insulating part STa divides each of the plurality of conductive layers 41 included in the laminate 40 in the Y direction. The insulating part STa is formed, for example, of a film containing silicon and oxygen.

[0059] The conductive portion STb is provided inside the insulating portion STa. The conductive portion STb extends in the Z direction and penetrates the stack 40. The upper end of the conductive portion STb is in contact with the source line SL. The conductive portion STb is made of a conductive material such as tungsten or molybdenum. The conductive portion STb may function as, for example, an electrical connection portion that connects the source line SL and wiring in the memory cell array 11.

[0060] <5.2 Divided part SHE> The dividing portion SHE is a dividing portion that is shallower in the Z direction than the dividing portion ST, and is a wall portion that divides the lower end portion of the stack 40 in the Y direction. The dividing portions SHE are arranged separately in the Y direction. In this embodiment, a plurality of (for example, three) dividing portions SHE are present between two dividing portions ST adjacent to each other in the Y direction. The dividing portion SHE is provided at the lower end portion of the stack 40, and extends in the Z direction partway through the stack 40, and also extends in the X direction. In other words, the dividing portion SHE is a wall portion that extends along the Z direction and the X direction.

[0061] The dividing portion SHE penetrates some of the conductive layers 41, including the lowest layer, of the plurality of conductive layers 41, and divides the some of the conductive layers 41 in the Y direction. For example, the dividing portion SHE penetrates each of all of the conductive layers 41 that function as drain-side select gate lines SGD. On the other hand, the dividing portion SHE does not reach the conductive layers 41 that function as word lines WL. The dividing portion SHE divides only the conductive layers 41 that function as drain-side select gate lines SGD in the Y direction. The dividing portion SHE is formed, for example, from a film containing silicon and oxygen.

[0062] 7 is an enlarged cross-sectional view of the region surrounded by line F7 in the semiconductor memory device 1 shown in FIG. 6. In this embodiment, the dividing portion SHE is provided so as to bite into a portion of the lower end of the memory pillar MH. That is, when viewed from the Z direction, a portion of the dividing portion SHE and a portion of the memory pillar MH overlap. As a result, as will be described in detail later, when viewed from the Z direction, the multiple memory pillars MH are arranged at equal intervals regardless of the presence or absence of the dividing portion SHE.

[0063] FIG. 8 is a cross-sectional view taken along the F8-F8 line of the semiconductor memory device 1 shown in FIG. 3. In the present embodiment, the conductive layer 41 corresponding to the drain-side select gate line SGD is divided in the Y direction by the dividing portion ST and the dividing portion SHE. As a result, the drain-side select gate line SGD extending in the X direction is formed. The region R defined by the dividing portion ST or the dividing portion SHE corresponds to one string STR.

[0064] In other words, the laminate 40 has a plurality of regions R defined by a plurality of dividing portions ST and a plurality of dividing portions SHE. The plurality of regions R include, for example, a first region R1, a second region R2, a third region R3, and a fourth region R4. The first region R1, the second region R2, the third region R3, and the fourth region R4 exist between two adjacent dividing portions ST in the Y direction.

[0065] In the present embodiment, three dividing portions SHE (dividing portions SHE1, SHE2, SHE3) exist between two adjacent dividing portions ST (dividing portions ST1, ST2) in the Y direction. The dividing portion SHE1, the dividing portion SHE2, and the dividing portion SHE3 are arranged in this order from the dividing portion ST1 toward the dividing portion ST_{2}. As a result, the first region R1 is defined between the dividing portion ST1 and the dividing portion SHE1. The second region R2 is defined between the dividing portion SHE1 and the dividing portion SHE2. The third region R3 is defined between the dividing portion SHE2 and the dividing portion SHE3. The fourth region R4 is defined between the dividing portion SHE3 and the dividing portion ST2.

[0066] <A6. Connection Structure between Memory Pillar and Bit Line> Next, the connection structure between the memory pillar MH and the bit line BL will be described. FIG. 9 is an enlarged cross-sectional view showing the region surrounded by the F9 line of the semiconductor memory device 1 shown in FIG. 8. In FIG. 9, for convenience of explanation, the illustration of the contact CH is omitted. This is the same for some of the figures described below.

[0067] 9 shows a structure related to two adjacent dividing portions DV (first dividing portion DV1 and second dividing portion DV2) among a plurality of dividing portions DV. In the example shown in FIG. 9, the first dividing portion DV1 and the second dividing portion DV2 are formed by dividing portions SHE. Note that one or both of the first dividing portion DV1 and the second dividing portion DV2 may be formed by dividing portions ST instead of dividing portions SHE. A region R corresponding to one string STR is defined between the first dividing portion DV1 and the second dividing portion DV2.

[0068] In this embodiment, the multiple memory pillars MH are arranged so that the memory pillars MH are located at the corners and centers of multiple imaginary hexagons arranged in a hexagonal lattice pattern. In this embodiment, the multiple memory pillars MH are arranged in an arrangement structure in which five memory pillars MH are arranged in the Y direction (hereinafter referred to as a "five-array arrangement structure") in the region R between two adjacent dividing portions DV. Note that in this application, "multiple memory pillars arranged in a specific direction" is not limited to multiple memory pillars MH arranged linearly in the specific direction, but may also correspond to multiple memory pillars MH arranged in a staggered pattern along the specific direction. In other words, "multiple memory pillars arranged in the Y direction" means that the positions of the multiple memory pillars MH in the Y direction are different, and the positions of the multiple memory pillars MH in the X direction may be different from each other.

[0069] In this embodiment, a connection structure between a bit line set BLS including five bit lines BL (bit lines BL1 to BL5) adjacent in the X direction and five memory pillars MH (memory pillars MH1 to MH5) corresponding to the five bit lines BL constitutes one structural unit. The connection structure is repeated in the X direction for every five bit lines BL. The connection structure is also repeated in the Y direction for every region R. For this reason, one connection structure will be described in detail below.

[0070] 6.1 Memory pillar layout The five memory pillars MH include a first memory pillar MH1, a second memory pillar MH2, a third memory pillar MH3, a fourth memory pillar MH4, and a fifth memory pillar MH5. The first memory pillar MH1, the second memory pillar MH2, the third memory pillar MH3, the fourth memory pillar MH4, and the fifth memory pillar MH5 are arranged in this order in the Y direction.

[0071] In this embodiment, the first to fifth memory pillars MH1 to MH5 are arranged in a first column RW1 and a second column RW2 included in one column set RWS. The first column RW1 and the second column RW2 are two columns adjacent to each other in the X direction and each extending in the Y direction. The first to fifth memory pillars MH1 to MH5 are arranged alternately in the first column RW1 and the second column RW2. For example, the first memory pillar MH1, the third memory pillar MH3, and the fifth memory pillar MH5 are arranged in the first column RW1. The second memory pillar MH2 and the fourth memory pillar MH4 are arranged in the second column RW2. In this embodiment, the first to fifth memory pillars MH1 to MH5 partially overlap each other when viewed from the Y direction.

[0072] 6.2 Bit Line Arrangement The five bit lines BL include a first bit line BL1, a second bit line BL2, a third bit line BL3, a fourth bit line BL4, and a fifth bit line BL5, which are arranged in this order in the X direction.

[0073] <6.3 Connection structure> The first memory pillar MH1 overlaps the first bit line BL1 when viewed from the Z direction and is electrically connected to the first bit line BL1 via the contact VY. The second memory pillar MH2 overlaps the fourth bit line BL4 when viewed from the Z direction and is electrically connected to the fourth bit line BL4 via the contact VY. The third memory pillar MH3 overlaps the second bit line BL2 when viewed from the Z direction and is electrically connected to the second bit line BL2 via the contact VY. The fourth memory pillar MH4 overlaps the fifth bit line BL5 when viewed from the Z direction and is electrically connected to the fifth bit line BL5 via the contact VY. The fifth memory pillar MH5 overlaps the third bit line BL3 when viewed from the Z direction and is electrically connected to the third bit line BL3 via the contact VY.

[0074] As described above, each of the five memory pillars MH (MH1 to MH5) is electrically connected to a different bit line BL among the five bit lines BL (BL1 to BL5) included in one bit line set BLS. Hereinafter, the connection structure between the five memory pillars MH and the five bit lines BL described above will be referred to as a connection structure CSA. In this embodiment, the connection structure CSA is provided in each of the four regions R (regions R1 to R4). Note that the connection structure CSA provided in the first region R1 and the third region R3 and the connection structure CSA provided in the second region R2 and the fourth region R4 are arranged, for example, line-symmetrically with respect to an imaginary line extending in the Y direction or rotationally symmetrically with respect to an imaginary center provided at a position overlapping the dividing portion DV (see FIG. 10).

[0075] 10 is an enlarged cross-sectional view of the region surrounded by line F10 of the semiconductor memory device 1 shown in FIG. 8. In this embodiment, 20 memory pillars MH are lined up in the Y direction in the region between two adjacent dividing portions ST (dividing portions ST1, ST2). The 20 memory pillars MH are arranged alternately in a first row RW1 and a second row RW2. The 20 memory pillars MH include five memory pillars MH in a first group G1, five memory pillars MH in a second group G2, five memory pillars MH in a third group G3, and five memory pillars MH in a fourth group G4.

[0076] The five memory pillars MH of the first group G1 are arranged in the first region R1. Each of the five memory pillars MH of the first group G1 is electrically connected to a different bit line BL from each other among the five bit lines BL (BL1 to BL5). The five memory pillars MH of the second group G2 are arranged in the second region R2. Each of the five memory pillars MH of the second group G2 is electrically connected to a different bit line BL from each other among the five bit lines BL (BL1 to BL5). The five memory pillars MH of the third group G3 are arranged in the third region R3. Each of the five memory pillars MH of the third group G3 is electrically connected to a different bit line BL from each other among the five bit lines BL (BL1 to BL5). The five memory pillars MH of the fourth group G4 are arranged in the fourth region R4. Each of the five memory pillars MH of the fourth group G4 is electrically connected to a different bit line BL from each other among the five bit lines BL (BL1 to BL5).

[0077] In this embodiment, each of the first group G1 to the fourth group G4 includes a memory pillar MHS closest to the adjacent region R. As described above, a portion of the memory pillar MHS overlaps with the separating portion SHE when viewed from the Z direction. In this embodiment, the memory pillar MHS overlapping with the separating portion SHE when viewed from the Z direction is an electrically functional memory pillar MH connected to a bit line BL via a contact VY. That is, a memory cell transistor MT used to store data is formed at the intersection of the memory pillar MHS and the word line WL. In this embodiment, when viewed from the Z direction, the multiple (e.g., 20) memory pillars MH arranged between two separating portions ST and aligned in the Y direction are arranged at equal intervals, regardless of whether they are memory pillars MHS or not. When viewed from the Z direction, the multiple memory pillars MH are arranged at equal intervals, regardless of whether there is a separating portion SHE or not.

[0078] As described above, among the plurality of memory pillars MH, in the region R between the first dividing portion DV1 and the second dividing portion DV2 arranged adjacent to the first dividing portion DV1 in the Y direction, there are three or more memory pillars MH (for example, three memory pillars MH1, MH3, MH5) arranged in the first row RW1 extending in the Y direction, and two or more memory pillars MH (for example, two memory pillars MH2, MH4) arranged in the second row RW2 extending in the Y direction and adjacent to the first row RW1 in the X direction. The three or more memory pillars MH (for example, three memory pillars MH1, MH3, MH5) and the two or more memory pillars MH (for example, two memory pillars MH2, MH4) are arranged alternately in the Y direction. And the three or more memory pillars MH (for example, three memory pillars MH1, MH3, MH5) and the two or more memory pillars MH (for example, two memory pillars MH2, MH4) are electrically connected to different bit lines BL among the plurality of bit lines BL.

[0079] <A7. Structure related to bit line> Next, the structure related to the bit line BL will be described. Here, the connection structure between the bit line BL2 and the memory pillar MH connected to the bit line BL2 will be taken as an example for explanation. The bit line BL2 is an example of the "first bit line". The bit line BL3 is an example of the "second bit line". The memory pillar MH connected to the bit line BL2 is an example of the "first columnar body".

[0080] FIG. 11 is a cross-sectional view showing an enlarged view of the region surrounded by the F11 line of the semiconductor memory device 1 shown in FIG. 3. Note that FIG. 11 is shown upside down with respect to FIG. 3. As shown in FIG. 11, the memory cell array 11 has the plurality of bit lines BL, the plurality of contacts VY (only one is shown in FIG. 11), the insulating layer 80, the plurality of first insulating portions 91, the plurality of vias V1 (only one is shown in FIG. 11), and the second insulating portion 92 described above. <A7. Structure related to bit line>

[0081] <7.1 Bit line> First, the shape of the bit line BL will be described. The bit line BL is formed of, for example, a wiring material that can be processed by reactive ion etching (RIE). The bit line BL is formed of, for example, tungsten, molybdenum, chromium, or ruthenium.

[0082] In this embodiment, each bit line BL has a first end 101a and a second end 101b in a cross section along the X and Z directions. The first end 101a is the end on the side where the wiring 71 and the via V1 are located in the Z direction. The first end 101a is the end facing the opposite side from the stacked body 40. The first end 101a contacts a first layer portion 81 of the insulating layer 80 (described later) in the Z direction. On the other hand, the second end 101b is located on the opposite side from the first end 101a in the Z direction. The second end 101b is the end on the side where the contact VY and the memory pillar MH are located. The second end 101b is the end facing the stacked body 40. The second end 101b contacts the contact VY in the Z direction.

[0083] In this embodiment, the multiple bit lines BL are patterned by reactive ion etching from the side opposite to the stack 40 (the -Z direction side). Therefore, for each bit line BL, the width W1 in the X direction of the first end 101a of the bit line BL is smaller than the width W2 in the X direction of the second end 101b of the bit line BL. In a cross section along the X and Z directions, each bit line BL has a trapezoidal shape whose width in the X direction gradually increases toward the stack 40 (toward the memory pillar MH).

[0084] In a cross section along the X and Z directions, each bit line BL has a first side end 101c and a second side end 101d located on the opposite side of the first side end 101c in the X direction. The first side end 101c extends from the edge of the first end 101a on the +X direction side to the edge of the second end 101b on the +X direction side. The first side end 101c contacts a first insulating portion 91 (described below) in the X direction. The second side end 101d extends from the edge of the first end 101a on the -X direction side to the edge of the second end 101b on the -X direction side. The second side end 101d contacts the first insulating portion 91 at a position different from the first side end 101c.

[0085] <7.2 Contact> Next, the shape of the contact VY will be described. The contact VY includes a first portion 111 and a second portion 112, for example.

[0086] The first portion 111 is a portion of the contact VY that contacts the bit line BL. The first portion 111 has, for example, a first end 110a, a first side end 110c, and a second side end 110d.

[0087] The first end 110a contacts the second end 101b of the bit line BL in the Z direction. The first side end 110c extends from the edge of the first end 110a on the +X direction side toward the opposite side to the bit line BL. The second side end 110d extends from the edge of the first end 110a on the -X direction side toward the opposite side to the bit line BL.

[0088] In this embodiment, the first portion 111 of the contact VY is patterned by reactive ion etching together with the bit line BL. Therefore, in a cross section along the X and Z directions, the first portion 111 has a trapezoidal shape whose width in the X direction gradually increases toward the stack 40 (closer to the memory pillar MH). The width W3 in the X direction of the first end 110a is the same as the width W2 in the X direction of the second end 101b of the bit line BL. The width W3 in the X direction of the first end 110a is smaller than, for example, the maximum width W4 in the X direction of the second portion 112.

[0089] A first end 110c of the first portion 111 is processed by reactive ion etching to be integral with the first end 101c of the bit line BL and extends continuously with the first end 101c of the bit line BL. A second end 110d of the first portion 111 is processed by reactive ion etching to be integral with the second end 101d of the bit line BL and extends continuously with the second end 101d of the bit line BL.

[0090] On the other hand, the second portion 112 of the contact VY is provided between the first portion 111 and the contact CH. The second portion 112 is in contact with the contact CH. In a cross section along the X and Z directions, the second portion 112 has an inverted trapezoidal shape whose width in the X direction gradually decreases as it approaches the stack 40 (approaching the memory pillar MH). Between the second portion 112 of the contact VY and the first portion 111, there is a step 113 where the width of the contact VY in the X direction increases. In addition, the contact VY has a second end 110b in contact with the contact CH. The width W5 in the X direction of the second end 110b is greater than the width W3 in the X direction of the first end 110a.

[0091] 7.3 Insulating layer Next, the insulating layer 80 will be described. The insulating layer 80 is an insulating layer for suppressing the influence of misalignment, for example, when the via V1 is misaligned with respect to the bit line BL. The insulating layer 80 is disposed on the opposite side of the memory pillar MH with respect to the multiple bit lines BL. The insulating layer 80 has, for example, multiple first layer portions 81 and a second layer portion 82. Note that in FIG. 11, the first layer portions 81 and the second layer portions 82 are hatched differently for ease of explanation. However, the first layer portions 81 and the second layer portions 82 exist as a single unit, for example, containing the same material. Therefore, the boundary between the first layer portions 81 and the second layer portions 82 disappears, and they exist as a single insulating layer 80.

[0092] <7.3.1 First layer of insulating layer> The multiple first layer portions 81 are separated in the X direction. The multiple first layer portions 81 are provided corresponding to the multiple bit lines BL, and overlap the multiple bit lines BL when viewed from the Z direction. The first layer portions 81 are portions of the insulating layer 80 that are responsible for, for example, electrical insulation (voltage resistance). The first layer portions 81 are located on the -Z direction side of the corresponding bit lines BL. The first layer portions 81 are stacked on the bit lines BL. The first layer portions 81 extend in the Y direction along the surfaces of the bit lines BL. The multiple first layer portions 81 are arranged at intervals from one another in the X direction.

[0093] The first layer 81 includes, for example, an insulating material containing nitrogen. The insulating material is, for example, a film containing silicon and nitrogen (for example, SiN), a film containing silicon, carbon, and nitrogen (for example, SiCN), or a film containing silicon, oxygen, and nitrogen (for example, SiON). When the etching selectivity between the first insulating section 91 and the first layer 81, which will be described later, is taken into consideration, silicon nitride (SiN) or silicon carbonitride (SiCN) is preferable as the insulating material.

[0094] In this embodiment, the multiple first layer portions 81 are patterned by, for example, reactive ion etching together with the bit lines BL. Therefore, in a cross section along the X and Z directions, the first layer portions 81 have a trapezoidal shape whose width in the X direction gradually increases toward the side where the stacked body 40 (memory pillar MH) is located. In this embodiment, the first layer portion 81 (81-1) that overlaps with the bit line BL2 when viewed from the Z direction is an example of the "first portion of the insulating layer." The first layer portion 81 (81-2) that overlaps with the bit line BL3 when viewed from the Z direction is an example of the "second portion of the insulating layer."

[0095] <7.3.2 Second layer of insulating layer> The second layer 82 is a portion that functions as a stopper layer against the processing of a hole to form the via V1, for example. The second layer 82 is located on the -Z direction side with respect to the multiple first layer portions 81. In other words, the second layer 82 is located on the opposite side of the multiple first layer portions 81 from the multiple bit lines BL. The second layer 82 extends at least in the X direction so as to span the multiple first layer portions 81. In this embodiment, the second layer 82 extends along the X direction and the Y direction. The second layer 82 is an example of a "third portion of the insulating layer."

[0096] The second layer 82 includes, for example, the same insulating material as the first layer 81. That is, the second layer 82 includes, for example, a film containing silicon and nitrogen (for example, SiN), a film containing silicon, carbon, and nitrogen (for example, SiCN), or a film containing silicon, oxygen, and nitrogen (for example, SiON). In this embodiment, the first layer 81 and the second layer 82 are formed of the same material.

[0097] <7.4 First insulating part> The first insulating portion 91 is disposed on the +Z direction side of the insulating layer 80. The first insulating portion 91 is provided between adjacent bit lines BL in the X direction. The first insulating portion 91 includes a first portion 91a located between adjacent bit lines BL in the X direction, a second portion 91b located between multiple first layer portions 81 of the insulating layer 80 adjacent in the X direction, and a cavity portion (air gap) 91c provided inside the first insulating portion 91. The cavity portion (air gap) 91c is located between two adjacent bit lines BL in the X direction.

[0098] The second portion 91b of the first insulating portion 91 contacts the second layer portion 82 of the insulating layer 80 in the Z direction. The first insulating portion 91 includes, for example, an insulating material containing oxygen. This insulating material is, for example, a film containing silicon and oxygen (e.g., SiO2). The first insulating portion 91 is formed of a material different from that of the insulating layer 80.

[0099] <7.5 via> The via V1 is an electrical connection portion that electrically connects the wiring 71 and the bit line BL. The via V1 is a self-aligned via. The via V1 is disposed between the wiring 71 and the bit line BL in the Z direction and extends in the Z direction. The via V1 extends from the side of the insulating layer 80 opposite to the bit line BL toward the insulating layer 80. The via V1 is an example of a "conductor portion." The via V1 has, for example, a first portion 121 and a second portion 122.

[0100] When viewed from the Z direction, the first portion 121 is a portion of the via V1 that overlaps with the bit line BL. The first portion 121 penetrates the second layer portion 82 and the first layer portion 81 of the insulating layer 80 in the Z direction and contacts the bit line BL. The first portion 121 electrically connects the wiring 71 and the bit line BL. The first portion 121 is an example of a "first conductor portion."

[0101] The second part 122 is the part where the bit line BL is detached at the via V1 when viewed from the Z direction. The second part 122 is arranged side by side with the first part 121 in the X direction. The second part 122 penetrates the second layer portion 82 of the insulating layer 80 in the Z direction and contacts the first insulating portion 91. The end 122e on the +Z direction side of the second part 122 is located, for example, at the boundary B1 between the second layer portion 82 of the insulating layer 80 and the first insulating portion 91. A step 123 in the Z direction is formed between the first part 121 and the second part 122. The second part 122 is an example of a "second conductor part".

[0102] <7.6 Second insulating portion> The second insulating portion 92 is arranged on the -Z direction side with respect to the insulating layer 80. The second insulating portion 92 extends in the X direction and the Y direction along the second layer portion 82 of the insulating layer 80. The second insulating portion 92 includes, for example, an insulating material containing oxygen. This insulating material is, for example, a film containing silicon and oxygen (e.g., SiO2).

[0103] <A8. Manufacturing method> <8.1 Manufacturing method of semiconductor memory device> Next, a manufacturing method of the semiconductor memory device 1 will be described. FIG. 12 is a cross-sectional view for explaining a manufacturing method of the semiconductor memory device 1. Hereinafter, steps related to the formation of the dividing portion SHE, the contact CH, the contact VY, and the bit line BL will be described. Details of other manufacturing steps are described, for example, in Japanese Patent Application Laid-Open No. 2022-41054. This document is incorporated herein by reference in its entirety.

[0104] First, as shown in (a) in FIG. 12, a laminate 40A is formed by alternately laminating the insulating layer 201 and the insulating layer 42. The insulating layer 201 is a sacrificial layer that will be replaced by the conductive layer 41 in a substitution process described later. The insulating layer 201 is formed by, for example, a film containing silicon and nitrogen. Next, a hole for providing the memory pillar MH is formed in the laminate 40A, and the memory pillar MH is formed inside the hole.

[0105] Next, as shown in FIG. 12(b), dividing portions ST and SHE are formed. For example, grooves g for providing dividing portions ST are formed in the laminate 40A. Next, a replacement step is performed. That is, the insulating layer 201 is removed through the grooves g by wet etching. Next, the material for the conductive layer 41 is supplied into the space where the insulating layer 201 has been removed, and the conductive layer 41 is formed. Next, dividing portions ST are formed inside the grooves g. Next, grooves for providing dividing portions SHE are formed in the laminate 40A, and the dividing portions SHE are formed inside the grooves.

[0106] 12(c), the contact CH and the contact VY are formed. For example, an insulating layer 202 is laminated on the laminate 40. Next, a hole for providing the contact CH is formed in the insulating layer 202, and the contact CH is formed inside the hole. Next, an insulating layer 203 is laminated on the insulating layer 202 and the contact CH. Next, a hole for providing the contact VY is formed in the insulating layer 203, and the contact VY is formed inside the hole.

[0107] 12(d), bit lines BL are formed above the contacts VY. Thereafter, wiring sections 70 are formed, thereby completing the second chip 3. Then, the second chip 3 is turned upside down, and the first chip 2 and the second chip 3 are bonded together, thereby forming the semiconductor memory device 1.

[0108] <8.2 Manufacturing method for parts related to bit lines> Next, a method for manufacturing the portion related to the bit line BL will be described. FIG. 13 is a cross-sectional view for explaining a manufacturing method around the bit line BL. 13(a), a structure 210 is formed that includes a stacked body 40, a memory pillar MH, a contact CH, and a conductive portion VYA. The conductive portion VYA is a conductor portion in which the contact VY is formed by processing that will be described later.

[0109] Next, a metal layer 211 is formed on the structure 210 by chemical vapor deposition (CVD). The metal layer 211 is plate-shaped and extends in the X and Y directions. The metal layer 211 is a metal layer on which the bit lines BL will be formed in a later process. Next, an insulating layer 212 is formed on the metal layer 211. The insulating layer 212 extends in the X and Y directions. The insulating layer 212 is an insulating film on which the multiple first layer portions 81 of the insulating layer 80 will be formed in a later process. Next, a material such as amorphous silicon is formed on the insulating layer 212, and an insulating layer 213 that will serve as the base of a hard mask is formed.

[0110] Next, as shown in FIG. 13(b), the insulating layer 213 is subjected to a predetermined processing, so that a hard mask M corresponding to the arrangement of the bit lines BL is formed from the insulating layer 213.

[0111] 13(c), reactive ion etching is performed using a hard mask M to remove unnecessary portions of the metal layer 211 and the insulating layer 212. That is, the metal layer 211 is divided in the X direction by reactive ion etching, and a plurality of bit lines BL are formed from the metal layer 211. Furthermore, the insulating layer 212 is divided in the X direction together with the metal layer 211 by the reactive ion etching, and a plurality of first layer portions 81 of the insulating layer 80 are formed from the insulating layer 212. Furthermore, corners of the conductive portion VYA are removed by the reactive ion etching, and a contact VY is formed from the conductive portion VYA.

[0112] 13(d), an insulating material is supplied between the plurality of bit lines BL and the plurality of first layer portions 81 to form the insulating portion 220. The insulating portion 220 has a cavity portion 93c between adjacent bit lines BL.

[0113] 14(e), the upper end of the insulating section 220 is removed by planarization (CMP: Chemical Mechanical Polishing), thereby forming a plurality of first insulating sections 91 from the insulating section 220. As a result, the upper surface of the first insulating section 91 is positioned on the same plane as the upper surfaces of the plurality of first layer sections 81. As a result, a structure 230 including a plurality of bit lines BL, a plurality of first layer sections 81, and a first insulating section 91 is formed.

[0114] 14(f), a second layer 82 is formed so as to cover the upper surfaces of the plurality of first layer portions 81 and the upper surface of the first insulating portion 91. As a result, an insulating layer 80 is formed by the plurality of first layer portions 81 and the second layer portion 82.

[0115] 14(g), a second insulating portion 92 is formed on the insulating layer 80. The second insulating portion 92 is formed using, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4)).

[0116] Next, as shown in FIG. 14(h), a mask (not shown) is provided, and a hole H for providing a via V1 is formed in the second insulating portion 92. The hole H is formed, for example, by reactive ion etching. The etching to form the hole H is first performed under first conditions. The first conditions are etching conditions that remove the second insulating portion 92 but remove the insulating layer 80 less easily than the second insulating portion 92. As a result, a hole H1 is first formed that penetrates the second insulating portion 92 in the Z direction and reaches the surface S2 of the insulating layer 80.

[0117] 15(i), etching for forming the hole H is performed by switching the etching conditions from the first conditions to the second conditions. The second conditions are etching conditions that remove the insulating layer 80 but remove the first insulating portion 91 less easily than the insulating layer 80.

[0118] As a result, a hole H including a first portion Ha and a second portion Hb is formed. The first portion Ha is a portion that overlaps with the bit line BL within the hole H when viewed in the Z direction. The first portion Ha penetrates through the second layer portion 82 and the first layer portion 81 of the insulating layer 80 in the Z direction and reaches the surface of the bit line BL. The second portion Hb is a portion that is out of the bit line BL within the hole H when viewed in the Z direction. The second portion Hb penetrates through the second layer portion 82 of the insulating layer 80 in the Z direction and stays on the upper surface of the first insulating portion 91. There is a step Hs in the Z direction between the first portion Ha and the second portion Hb.

[0119] Next, as shown in (j) in FIG. 15, a mask (not shown) is provided, and a groove G for forming the wiring 71 is formed by the upper surface of the second insulating portion 92. The groove G is formed, for example, by reactive ion etching.

[0120] Next, as shown in (k) in FIG. 15, by supplying a conductive material into the groove G and the hole H, the wiring 71 and the via V1 are formed. At this time, a first portion 121 of the via V1 is formed in the first portion Ha of the hole H, and a second portion 122 of the via V1 is formed in the second portion Hb of the hole H.

[0121] <A9. Advantages> <9.1 Advantages of the five - column arrangement structure> First, the advantages of the five - column arrangement structure will be described. FIG. 16 is a diagram for explaining the advantages of the five - column method. (a) in FIG. 16 shows an arrangement structure of a four - column method which is a comparative example. The arrangement structure of the four - column method is an arrangement structure in which four memory pillars MH are arranged in the Y direction between two adjacent dividing parts DV (that is, the dividing part ST or the dividing part SHE). On the other hand, (b) in FIG. 16 shows the arrangement structure of the five - column method of the present embodiment. The arrangement structures of (a) and (b) in FIG. 16 have the same distance between two dividing parts ST and the same arrangement structure of a plurality of memory pillars MH.

[0122] Here, each block BLK is a storage unit defined between two adjacent separation portions ST. The block size (capacity of each block BLK) is defined by multiplying four elements: the number of strings STR, the number of stacked word lines WL, the multiplexing level (TLC, QLC, etc.), and the page size.

[0123] In order to increase the integration density of the semiconductor memory device 1, it is effective to increase the number of stacked word lines WL and the number of memory pillars MH (MH series) lined up in the Y direction between two adjacent dividing portions ST. On the other hand, increasing the number of stacked word lines WL and the number of MH series increases the block size. When the block size increases, the erase operation takes longer, making it difficult to increase the speed of the semiconductor memory device 1. Furthermore, when the block size increases, there is a possibility that the area required for overprovisioning (OP area) will be insufficient or the WAF (Write Amplification Factor) will increase.

[0124] Furthermore, as the number of stacked word lines WL increases, the parasitic capacitance of the word lines increases, which may increase the time required to drive and charge the word lines, resulting in a decrease in write and / or read performance. As the number of stacked word lines WL increases, the size of the semiconductor memory device 1 tends to increase in the X direction, which may make it difficult to package the semiconductor memory device 1.

[0125] Therefore, in this embodiment, a five-row layout structure is provided. The five-row layout structure allows for a smaller number of strings STR included in one block BLK than the four-row layout structure. Therefore, the five-row layout structure allows for a smaller block size than the four-row layout structure. Reducing the block size shortens the erase operation time, thereby increasing the speed of the semiconductor memory device 1. This improves the electrical characteristics of the semiconductor memory device 1. Furthermore, reducing the block size can prevent a shortage of the OP area and / or an increase in the WAF. From this perspective, the electrical characteristics of the semiconductor memory device 1 can be improved.

[0126] FIG. 17 is another diagram for explaining the advantages of the five-unit system. (a) in FIG. 17 shows a plane PL having a four-unit system arrangement structure, which is a comparative example. (b) in FIG. 17 shows a plane PL having a five-unit system arrangement structure of this embodiment. The plane PL is a unit of physical structure included in the memory cell array 11 as a configuration including multiple blocks BLK. The arrangement structures of (a) and (b) in FIG. 17 have the same number of memory cell transistors MT included in the plane PL.

[0127] In the five-series array configuration of this embodiment, if the number of memory cell transistors MT included in each string STR is the same as the number of memory cell transistors MT included in each string STR of the four-series array configuration, the length of the plane PL in the X direction (the length of the word lines WL in the X direction) is four-fifths shorter than that of the four-series array configuration. Reducing the length of the word lines WL in the X direction reduces the parasitic capacitance of the word lines WL. Therefore, in cases where the write and / or read performance of the semiconductor memory device 1 is rate-determined by the charging or propagation delay of the word lines WL, the write and / or read performance of the semiconductor memory device 1 can be improved. Furthermore, reducing the length of the plane PL in the X direction may facilitate packaging.

[0128] In this embodiment, the width W3 in the X direction of the first end 110a of the contact VY is the same as the width W2 in the X direction of the second end 101b of the bit line BL2. This configuration makes it easier to ensure a distance between the contact VY and the bit line BL even when misalignment occurs between the contact VY and the bit line BL and multiple bit lines BL are closely arranged in the X direction. Therefore, in a closely arranged structure of the bit lines BL corresponding to the five-line arrangement structure, it is possible to increase the breakdown voltage and improve the electrical characteristics of the semiconductor memory device 1.

[0129] In this embodiment, via V1 includes a first portion 121 that penetrates through the second layer portion 82 and the first layer portion 81 of the insulating layer 80 in the Z direction and contacts the bit line BL, and a second portion 122 that penetrates through the second layer portion 82 of the insulating layer 80 in the Z direction, contacts the first insulating portion 91, and has a step 123 between the first portion 121. According to such a configuration, when misalignment occurs between the via V1 and the bit line BL, even when a plurality of bit lines BL are densely arranged in the X direction, it becomes easier to provide a distance between the via V1 and the bit line BL. Therefore, in the dense arrangement structure of the bit lines BL corresponding to the five-in-one arrangement structure, the breakdown voltage resistance can be increased, and the electrical characteristics of the semiconductor memory device 1 can be improved.

[0130] In this embodiment, the first insulating portion 91 disposed between the bit lines BL includes a cavity portion (air gap) 91c located between a plurality of bit lines BL in the X direction. According to such a configuration, in the dense arrangement structure of the bit lines BL corresponding to the five-in-one arrangement structure, the parasitic capacitance generated in the bit lines BL can be reduced, and the electrical characteristics of the semiconductor memory device 1 can be improved.

[0131] <A10. Modified Example> Next, some modified examples of the first embodiment will be described. In each modified example, the configuration other than that described below is the same as the configuration of the first embodiment described above.

[0132] <10.1 First Modified Example> FIG. 18 is a cross-sectional view showing a part of the semiconductor memory device 1 of the first modified example. In this modified example, 17 memory pillars MH are arranged in the Y direction in the region between two adjacent divided portions ST (divided portions ST1, ST2). The 17 memory pillars MH are alternately arranged in the first row RW1 and the second row RW2. The 17 memory pillars MH include five memory pillars MH of the first group G1, five memory pillars MH of the second group G2, five memory pillars MH of the third group G3, and two dummy memory pillars MHD (dummy memory pillars MHD1, MHD2). In this modified example, the 17 memory pillars MH including the two dummy memory pillars MHD are arranged at equal intervals in the Y direction.

[0133] The dummy memory pillars MHD have the same configuration as the memory pillars MH, but are not electrically connected to the bit lines BL and are not used to store data. The dummy memory pillar MHD1 is disposed between the five memory pillars MH of the first group G1 and the five memory pillars MH of the second group G2 in the Y direction. When viewed from the Z direction, one separating portion SHE is disposed at a position overlapping with the dummy memory pillar MHD1. Similarly, the dummy memory pillar MHD2 is disposed between the five memory pillars MH of the second group G2 and the five memory pillars MH of the third group G3 in the Y direction. When viewed from the Z direction, one separating portion SHE is disposed at a position overlapping with the dummy memory pillar MHD2.

[0134] <10.2 Second Modification> FIG. 19 is a cross-sectional view showing a portion of a semiconductor memory device 1 of a second modified example. In this modified example, 21 memory pillars MH are lined up in the Y direction in the region between two adjacent separation portions ST (separation portions ST1, ST2). The 21 memory pillars MH are alternately arranged in a first row RW1 and a second row RW2. The 21 memory pillars MH include five memory pillars MH in a first group G1, five memory pillars MH in a second group G2, five memory pillars MH in a third group G3, five memory pillars MH in a fourth group G4, and one dummy memory pillar MHD. Each of the first group G1 to the fourth group G4 includes one or two memory pillars MHS. The memory pillars MHS partially overlap with the separation portion SHE when viewed from the Z direction, but are electrically functional memory pillars MH connected to bit lines BL via contacts VY. In this modification, 21 memory pillars MH, including one dummy memory pillar MHD and multiple memory pillars MHS, are arranged at equal intervals in the Y direction.

[0135] (Second embodiment) Next, the semiconductor memory device 1 of the second embodiment will be described. The semiconductor memory device 1 of the second embodiment is different from the first embodiment in that only three memory pillars MH are arranged in the Y direction in the region R between two adjacent divided portions DV. The configuration other than that described below is the same as that of the first embodiment.

[0136] <B1. Configuration of Semiconductor Memory Device> FIG. 20 shows a structure related to two adjacent divided portions DV (the first divided portion DV1 and the second divided portion DV2) among a plurality of divided portions DV. In the example shown in FIG. 20, the first divided portion DV1 and the second divided portion DV2 are formed by a dividing portion SHE. Note that one or both of the first divided portion DV1 and the second divided portion DV2 may be formed by a dividing portion ST instead of the dividing portion SHE. A region R corresponding to one string STR is defined between the first divided portion DV1 and the second divided portion DV2.

[0137] In the present embodiment, a plurality of memory pillars MH are arranged in an arrangement structure (hereinafter referred to as a "three-in-line arrangement structure") in which three memory pillars MH are arranged in the Y direction in the region R between two adjacent divided portions DV.

[0138] In the present embodiment, a connection structure between a bit line set BLS including three adjacent bit lines BL (bit lines BL1 to BL3) in the X direction and three memory pillars MH (memory pillars MH1 to MH3) corresponding to the three bit lines BL is one structural unit. Then, the connection structure repeatedly exists in the X direction for each of the three bit lines BL. Further, the connection structure repeatedly exists in the Y direction for each region R. Therefore, one connection structure will be described in detail below.

[0139] <1.1 Arrangement of Memory Pillars> The three memory pillars MH include a first memory pillar MH1, a second memory pillar MH2, and a third memory pillar MH3. The first memory pillar MH1, the second memory pillar MH2, and the third memory pillar MH3 are arranged in this order in the Y direction.

[0140] In this embodiment, the first to third memory pillars MH1 to MH3 are arranged separately in a first column RW1 and a second column RW2 included in one column set RWS. The first to third memory pillars MH1 to MH3 are arranged alternately in the first column RW1 and the second column RW2. For example, the first memory pillar MH1 and the third memory pillar MH3 are arranged in the first column RW1. The second memory pillar MH2 is arranged in the second column RW2. In this embodiment, the first to third memory pillars MH1 to MH3 partially overlap each other when viewed from the Y direction.

[0141] 1.2 Bit line layout The three bit lines BL include a first bit line BL1, a second bit line BL2, and a third bit line BL3. The first bit line BL1, the second bit line BL2, and the third bit line BL3 are arranged in this order in the X direction. In this embodiment, the pitch between the centers of the multiple bit lines BL in the X direction is, for example, 40 nm or more.

[0142] <1.3 Connection structure> The first memory pillar MH1 overlaps the second bit line BL2 when viewed from the Z direction and is electrically connected to the second bit line BL2 via the contact VY. The second memory pillar MH2 overlaps the third bit line BL3 when viewed from the Z direction and is electrically connected to the third bit line BL3 via the contact VY. The third memory pillar MH3 overlaps the first bit line BL1 when viewed from the Z direction and is electrically connected to the first bit line BL1 via the contact VY.

[0143] As described above, each of the three memory pillars MH (MH1 to MH3) is electrically connected to a different bit line BL among the three bit lines BL (BL1 to BL3) included in one bit line set BLS. Hereinafter, the connection structure between the three memory pillars MH and the three bit lines BL described above will be referred to as a connection structure CSB. In this embodiment, the connection structure CSB is provided in each of the multiple regions R.

[0144] FIG. 21 is a cross-sectional view showing a part of the semiconductor memory device 1 of the second embodiment. In this embodiment, in the region between two adjacent divided portions ST (divided portions ST1, ST2), 24 memory pillars MH are arranged in the Y direction. The 24 memory pillars MH are alternately arranged in the first row RW1 and the second row RW2. The 24 memory pillars MH include memory pillars MH divided into three each from the first group G1 to the eighth group G8.

[0145] In this embodiment, each of the first group G1 to the eighth group G8 includes a memory pillar MHS closest to the adjacent region R. As described above, a part of the memory pillar MHS overlaps the divided portion SHE when viewed from the Z direction. In this embodiment, the memory pillar MHS that overlaps the divided portion SHE when viewed from the Z direction is a memory pillar MH that is connected to the bit line BL via the contact VY and functions electrically.

[0146] As described above, the plurality of memory pillars MH are arranged as memory pillars MH arranged in the first row RW1 extending in the Y direction in the region R between the first divided portion DV1 and the second divided portion DV2 arranged adjacent to the first divided portion DV1 in the Y direction, and include only two or less memory pillars MH (for example, two memory pillars MH1, MH3), and as a memory pillar MH arranged in the second row RW2 extending in the Y direction and adjacent to the first row RW1 in the X direction, include one memory pillar MH2. The two or less memory pillars MH (for example, two memory pillars MH1, MH3) and the one memory pillar MH2 are alternately arranged in the Y direction. And the two or less memory pillars MH (for example, two memory pillars MH1, MH3) and the one memory pillar MH2 are electrically connected to different bit lines BL among the plurality of bit lines BL.

[0147] <B2. Advantages> FIG. 22 is another diagram for explaining the advantages of the triple arrangement. (a) in FIG. 22 shows a plane PL having an arrangement structure of a quadruple arrangement as a comparative example. (b) in FIG. 22 shows a plane PL having an arrangement structure of the triple arrangement of the present embodiment. The plane PL is a unit of the physical structure included in the memory cell array 11 configured to include a plurality of blocks BLK. The arrangement structures of (a) and (b) in FIG. 22 have the same number of memory cell transistors MT included in the plane PL.

[0148] Here, the writing performance and / or reading performance of the semiconductor memory device 1 may be limited by the charging and propagation delay of the bit line BL instead of the charging and propagation delay of the word line WL. In the triple arrangement structure of the present embodiment, when the number of memory cell transistors MT included in each string unit SU is made the same as the number of memory cell transistors MT included in each string unit SU of the quadruple arrangement, the length of the plane PL in the Y direction (the length of the bit line BL in the Y direction) becomes three-fourths shorter than that of the quadruple arrangement structure. If the length of the bit line BL in the X direction can be shortened, the parasitic capacitance of the bit line BL can be reduced. Therefore, when the writing performance and / or reading performance of the semiconductor memory device 1 is limited by the charging or propagation delay of the bit line BL, the writing performance and / or reading performance of the semiconductor memory device 1 can be improved. For this reason, the electrical characteristics of the semiconductor memory device 1 can be improved. Also, if the length of the plane PL in the Y direction can be shortened, it may be easier to enclose the package components.

[0149] <B3. Modified Example> Next, some modified examples of the second embodiment will be described. In each modified example, the configuration other than that described below is the same as the configuration of the second embodiment described above.

[0150] <3.1 First Modified Example> FIG. 23 is a cross-sectional view showing a portion of a semiconductor memory device 1 of a first modified example. In this modified example, 23 memory pillars MH are lined up in the Y direction in the region between two adjacent dividing portions ST (dividing portions ST1, ST2). The 23 memory pillars MH are arranged alternately in a first row RW1 and a second row RW2. The 23 memory pillars MH include memory pillars MH arranged in groups of three in the first group G1 to the sixth group G6, and five dummy memory pillars MHD. In this modified example, the 23 memory pillars MH including the five dummy memory pillars MHD are arranged at equal intervals in the Y direction.

[0151] <10.2 Second Modification> FIG. 19 is a cross-sectional view showing a portion of a semiconductor memory device 1 according to a second modification. In this modification, 25 memory pillars MH are arranged in the Y direction in the region between two adjacent separation portions ST (separation portions ST1, ST2). The 23 memory pillars MH are alternately arranged in the first row RW1 and the second row RW2. The 23 memory pillars MH include one dummy memory pillar MHD and three memory pillars MH arranged in each of the first group G1 to the eighth group G8. The three memory pillars MH included in each of the first group G1 to the eighth group G8 include one or two memory pillars MHS. The memory pillars MHS partially overlap the separation portion SHE when viewed from the Z direction, but are electrically functional memory pillars MH connected to the bit lines BL via contacts VY. In this modification, the 23 memory pillars MH, including one dummy memory pillar MHD and multiple memory pillars MHS, are arranged at equal intervals in the Y direction.

[0152] Several embodiments and modifications have been described above. However, the embodiments and modifications are not limited to the examples described above. For example, in the first embodiment, the number of memory pillars MH aligned in the Y direction in the region R between two adjacent dividing portions DV is not limited to five and may be six or more. Furthermore, in the second embodiment, the number of memory pillars MH aligned in the Y direction in the region R between two adjacent dividing portions DV is not limited to three and may be two.

[0153] According to at least one of the above-described embodiments, the semiconductor memory device includes a stacked body, a plurality of pillars, a plurality of bit lines, and a plurality of dividing portions. The plurality of dividing portions are arranged separately in the third direction. The plurality of dividing portions include a first dividing portion and a second dividing portion that are adjacent to each other among the plurality of dividing portions. The plurality of pillars includes, in a region between the first dividing portion and the second dividing portion, three or more pillars arranged in a first row extending in the third direction and two or more pillars arranged in a second row extending in the third direction and adjacent to the first row in the second direction. The three or more pillars and the two or more pillars are arranged alternately in the third direction. The three or more pillars and the two or more pillars are electrically connected to different bit lines among the plurality of bit lines. This configuration can improve electrical characteristics.

[0154] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0155] 1...Semiconductor memory device 40...Laminate 41...Conductive layer (gate electrode layer) 42...insulating layer 80...insulating layer 81...First layer 81-1...First layer part (first part) 81-2…1st layer part (2nd part) 82…Second layer part (third part) WL...word line BL...bit line MH...Memory pillar (columnar body) Domestic violence...Divided section DV1: First division DV2: Second division ST: Divided section SHE...Divided part VY…Contact V1…Via 111…Part 1 112…Second part

Claims

1. a stacked body including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked one layer at a time in a first direction; a plurality of pillars extending in the first direction within the stacked body, the pillars forming transistors at intersections with the plurality of gate electrode layers; a plurality of bit lines arranged on one side of the stacked body in the first direction, aligned in a second direction intersecting the first direction, and extending in a third direction intersecting the first direction and the second direction; a plurality of dividing portions that are arranged separately in the third direction, each extending in the first direction within the stacked body, and dividing one or more gate electrode layers including a lowest layer among the plurality of gate electrode layers in the third direction when the one side is downward; Equipped with the plurality of dividing portions include a first dividing portion and a second dividing portion that are adjacent to each other among the plurality of dividing portions, the plurality of columns include, in a region between the first dividing portion and the second dividing portion, three or more columns arranged in a first row extending in the third direction, and two or more columns arranged in a second row extending in the third direction and adjacent to the first row in the second direction, the three or more pillars and the two or more pillars are arranged alternately in the third direction, the three or more pillars and the two or more pillars are electrically connected to different bit lines among the plurality of bit lines. Semiconductor memory device.

2. the plurality of bit lines includes a first bit line; the first bit line has a first end facing away from the stack and a second end facing the stack; a width of the first end in the second direction is smaller than a width of the second end in the second direction; 2. The semiconductor memory device according to claim 1.

3. a contact disposed between the first bit line and a first pillar included in the plurality of pillars; the contact has an end that contacts the second end of the first bit line; a width of the end of the contact in the second direction is the same as a width of the second end of the first bit line in the second direction; 3. The semiconductor memory device according to claim 2.

4. a contact located between the first bit line and a first pillar included in the plurality of pillars; the contact includes a first portion in contact with the first bit line and a second portion provided between the first portion and the first columnar body; the first portion has a width in the second direction that increases toward the first columnar body, the second portion has a width in the second direction that decreases toward the first columnar body; 4. The semiconductor memory device according to claim 2.

5. an insulating layer overlapping the plurality of bit lines when viewed from the first direction; a via penetrating the insulating layer in the first direction; an insulating portion disposed between the plurality of bit lines; Furthermore, the plurality of bit lines include a first bit line and a second bit line located adjacent to the first bit line; the insulating layer includes a first portion overlapping the first bit line when viewed from the first direction, a second portion overlapping the second bit line when viewed from the first direction, and a third portion located on an opposite side of the first and second portions from the plurality of bit lines and extending at least in the second direction; the via includes a first conductor portion that penetrates the third portion and the first portion of the insulating layer in the first direction and is in contact with the first bit line, and a second conductor portion that penetrates the third portion of the insulating layer in the first direction and is in contact with the insulating portion, and has a step between itself and the first conductor portion; 3. The semiconductor memory device according to claim 1.

6. the insulating portion has a cavity portion located between the plurality of bit lines in the second direction; 6. The semiconductor memory device according to claim 5.

7. a stacked body including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked one layer at a time in a first direction; a plurality of pillars extending in the first direction within the stacked body, the pillars forming transistors at intersections with the plurality of gate electrode layers; a plurality of bit lines arranged on one side of the stacked body in the first direction, aligned in a second direction intersecting the first direction, and extending in a third direction intersecting the first direction and the second direction; a plurality of dividing portions that are arranged separately in the third direction, each extending in the first direction within the stacked body, and dividing one or more gate electrode layers including a lowest layer among the plurality of gate electrode layers in the third direction when the one side is downward; Equipped with the plurality of dividing portions include a first dividing portion and a second dividing portion that are adjacent to each other among the plurality of dividing portions, the plurality of columns include, in a region between the first dividing portion and the second dividing portion, only two or less columns as columns arranged in a first row extending in the third direction, and only one column as a column arranged in a second row extending in the third direction and adjacent to the first row in the second direction, the two or less pillars and the one pillar are arranged alternately in the third direction, the two or less pillars and the one pillar are electrically connected to different bit lines among the plurality of bit lines; Semiconductor memory device.

Images