Semiconductor circuit

Abstract

To provide a semiconductor circuit which uses a wide bandgap semiconductor and which can restrain ringing from being generated in a gate of a switching element.SOLUTION: A semiconductor circuit 1 comprises a switching circuit 10 having at least one switching element Q, ground wiring 50, and a current detection circuit 30 that is connected between the switching circuit 10 and the ground wiring 50. A denoising circuit 40 is connected in parallel relationship to the current detection circuit 30 between the switching circuit 10 and the ground wiring 50.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor circuits. [Background technology]

[0002] Semiconductor circuits using wide bandgap semiconductors are known (see, for example, Patent Document 1). Wide bandgap semiconductors are devices that can withstand high voltages, high power, and high frequencies, so semiconductor circuits using wide bandgap semiconductors are circuits with high voltages, high power, and high frequencies, and are used for a variety of applications. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-115706 Summary of the Invention [Problem to be solved by the invention]

[0004] However, semiconductor circuits using wide bandgap semiconductors are prone to loss and ringing due to parasitic inductance caused by their high-speed switching. Ringing occurs not only in the drain (collector) of the switching element but also in the source (emitter). Ringing that occurs in the source (emitter) also occurs in the gate through the capacitance of the switching element, causing the switching element to turn on incorrectly and potentially damaging the switching element. Gate ringing is particularly likely to occur in circuits where the impedance between the switching element and ground wiring is large (for example, in circuits where current detection is performed by connecting a current detection element to the source (emitter)). For this reason, reducing ringing that occurs in switching elements has been a challenge.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor circuit that can suppress ringing that occurs at the gate of a switching element. [Means for solving the problem]

[0006] [1] The semiconductor circuit of the present invention is a semiconductor circuit comprising a switching circuit having at least one switching element, a ground wiring, and a current detection circuit connected between the switching circuit and the ground wiring, characterized in that a noise removal circuit is connected between the switching circuit and the ground wiring in a parallel relationship to the current detection circuit.

[0007] [2] In the semiconductor circuit of the present invention, the noise removal circuit is preferably an RC series circuit in which a resistor and a capacitor are connected in series.

[0008] [3] In the semiconductor circuit of the present invention, it is preferable that the switching circuit is a circuit including a half-bridge circuit having a high-side switching element and a low-side switching element, and the noise removal circuit is connected between the low-side switching element and the ground wiring.

[0009] [4] In the semiconductor circuit of the present invention, the switching circuit is preferably a full-bridge circuit in which two of the half-bridge circuits are connected in parallel.

[0010] [5] In the semiconductor circuit of the present invention, it is preferable that the high-side switching element and the low-side switching element are both made of transistors.

[0011] [6] In the semiconductor circuit of the present invention, it is preferable that the high-side switching element is a diode, and the low-side switching element is a transistor.

[0012] [7] In the semiconductor circuit of the present invention, the switching circuit is preferably a circuit in which three or more of the half-bridge circuits are connected in parallel.

[0013] [8] In the semiconductor circuit of the present invention, it is preferable that the switching circuit is housed inside a package, and the current detection circuit and the noise elimination circuit are both arranged outside the package.

[0014] [9] In the semiconductor circuit of the present invention, the switching circuit and one of the resistor and the capacitor that constitute the RC series circuit are housed inside a package; The current detection circuit and the other of the resistor and the capacitor that constitute the RC series circuit may have a structure that is arranged outside the package.

[0015]

[10] In the semiconductor circuit of the present invention, the switching circuit and the noise removal circuit may both be housed inside a package, and the current detection circuit may be arranged outside the package.

[0016]

[11] In the semiconductor circuit of the present invention, the switching circuit, the noise elimination circuit, and the current detection circuit may all be housed in a single package. [Effects of the Invention]

[0017] According to the semiconductor circuit of the present invention, a noise removal circuit is connected between the switching circuit and the ground wiring in a parallel relationship to the current detection circuit, so that ringing occurring in the switching circuit (for example, between the source (emitter) of the switching circuit and the ground wiring) is suppressed, and ringing occurring in the gate of the switching element can be suppressed. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a diagram showing a semiconductor circuit 1 according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing a semiconductor circuit 1A according to a first modification of the first embodiment. [Figure 3]FIG. 10 is a diagram showing a semiconductor circuit 1B according to a second modification of the first embodiment. [Figure 4] FIG. 10 is a diagram showing a semiconductor circuit 1C according to a third modification of the first embodiment. [Figure 5] FIG. 2 is a diagram showing a semiconductor circuit 2 according to a second embodiment. [Figure 6] FIG. 10 is a diagram showing a semiconductor circuit 2A according to a first modification of the second embodiment. [Figure 7] FIG. 10 is a diagram showing a semiconductor circuit 2B according to a second modification of the second embodiment. [Figure 8] FIG. 10 is a diagram showing a semiconductor circuit 2C according to a third modification of the second embodiment. [Figure 9] FIG. 10 is a diagram showing a semiconductor circuit 3 according to a third embodiment. [Figure 10] FIG. 10 is a diagram showing a semiconductor circuit 3A according to a first modification of the third embodiment. [Figure 11] FIG. 10 is a diagram showing a semiconductor circuit 3B according to a second modification of the third embodiment. [Figure 12] FIG. 10 is a diagram showing a semiconductor circuit 3C according to a third modification of the third embodiment. [Figure 13] FIG. 10 is a diagram showing a semiconductor circuit 3D according to a fourth modification of the third embodiment. [Figure 14] FIG. 10 is a diagram showing a semiconductor circuit 3E according to a fifth modification of the third embodiment. [Figure 15] FIG. 10 is a diagram showing a semiconductor circuit 3F according to a sixth modification of the third embodiment. [Figure 16] FIG. 10 is a diagram showing a semiconductor circuit 4 according to a fourth embodiment. [Figure 17] FIG. 10 is a diagram showing a semiconductor circuit 5 according to a fifth embodiment. [Figure 18] 10 is a planar layout diagram showing a semiconductor circuit 3E according to a fifth modified example of the third embodiment. FIG. [Figure 19] FIG. 11 is a planar layout diagram showing a semiconductor circuit 3G according to a seventh modification of the third embodiment. [Figure 20] 13 is a planar layout diagram showing a semiconductor circuit 3H according to Modification 8 of Embodiment 3. FIG. [Figure 21]FIG. 10 is a planar layout diagram showing a semiconductor circuit 6 according to Test Example 2 (comparative example). [Figure 22] FIG. 10 is a diagram illustrating a simulation model in a test example. [Figure 23] FIG. 10 is a diagram showing simulation results in a test example. DETAILED DESCRIPTION OF THE INVENTION

[0019] The semiconductor circuit of the present invention will be described below based on the embodiments shown in the drawings. In the embodiments described below, components having substantially the same functions will be designated by the same reference numerals across the embodiments, even if their shapes are slightly different, and repeated description may be omitted. The embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the present invention.

[0020] [Embodiment 1] Fig. 1 is a diagram showing a semiconductor circuit 1 according to embodiment 1. As shown in Fig. 1, the semiconductor circuit 1 according to embodiment 1 is a semiconductor circuit including a switching circuit 10 having a transistor Q as a switching element, a ground wiring 50, and a current detection circuit 30 connected between the switching circuit 10 and the ground wiring 50. A noise removal circuit 40 is connected between the switching circuit 10 and the ground wiring 50 in a parallel relationship with the current detection circuit 30.

[0021] In the semiconductor circuit 1 according to the first embodiment, the switching circuit 10 uses a transistor Q made of a MOSFET as a switching element. The transistor Q is made of a wide bandgap semiconductor (for example, SiC, GaN, diamond, etc.).

[0022] In the semiconductor circuit 1 according to the first embodiment, the noise removal circuit 40 is an RC series circuit in which a resistor R and a capacitor C are connected in series.

[0023] In the semiconductor circuit 1 according to the first embodiment, reference numeral 12 denotes a gate terminal, reference numeral 14 denotes a power supply terminal, reference numeral 16 denotes a ground terminal, reference numeral 20 denotes a noise elimination circuit terminal, and reference numeral 24 denotes a source sense terminal. The noise elimination circuit terminal 20 and the source sense terminal 24 may be combined into one terminal. Reference numeral 60 denotes a package molded from molded resin.

[0024] In the semiconductor circuit 1 according to the first embodiment, the current detection circuit 30 is connected between the ground terminal 30 and the ground wiring 50 in an area outside the package 60. The noise elimination circuit 40 is also connected between the noise elimination circuit terminal 20 and the ground wiring 50 in an area outside the package 60.

[0025] [Effects of the First Embodiment] According to the semiconductor circuit 1 of embodiment 1, the noise removal circuit 40 is connected between the switching circuit 10 and the ground wiring 50 in a parallel relationship with the current detection circuit 30, so that ringing occurring in the switching circuit 10 (in this case, between the source S of the transistor Q and the ground wiring 50) is suppressed, and ringing occurring in the gate G of the switching element can be suppressed.

[0026] According to the semiconductor circuit 1 of the first embodiment, the noise removal circuit 40 is an RC series circuit in which a resistor R and a capacitor C are connected in series, and therefore with a relatively simple configuration, ringing occurring between the switching circuit 10 and the ground wiring 50 can be suppressed, and ringing occurring at the gate G of the switching element can be suppressed.

[0027] According to the semiconductor circuit 1 of embodiment 1, the current detection circuit 30 and the noise removal circuit 40 are arranged outside the package 60, which makes it easier to optimize the characteristics of the noise removal circuit 40 and more effectively suppresses ringing that occurs in the switching element.

[0028] [Modifications 1 to 3 of Embodiment 1] Fig. 2 is a diagram showing a semiconductor circuit 1A according to Modification 1 of Embodiment 1. Fig. 3 is a diagram showing a semiconductor circuit 1B according to Modification 2 of Embodiment 1. Fig. 4 is a diagram showing a semiconductor circuit 1C according to Modification 3 of Embodiment 1.

[0029] [Modification 1 of Embodiment 1] 2, the semiconductor circuit 1A according to the first modification of the first embodiment has a structure in which the switching circuit 10 and one of the resistor R and capacitor C (in this case, the resistor R) that constitute the RC series circuit of the noise removal circuit 40 are housed inside a package 60, and the current detection circuit 30 and the other of the resistor R and capacitor C (in this case, the capacitor C) that constitute the RC series circuit of the noise removal circuit 40 are arranged outside the package 60. In the semiconductor circuit 1A according to the first modification of the first embodiment, reference numeral 21 denotes a terminal located between the resistor R and capacitor C of the noise removal circuit 40.

[0030] According to the semiconductor circuit 1A of the first variant of the first embodiment, as described above, by accommodating either the resistor R or the capacitor C that constitutes the RC series circuit of the noise removal circuit 40 inside the package 60, the number of components that need to be externally attached to the package 60 is reduced, the wiring of the noise removal circuit 40 is shortened, the impedance is reduced, and the ringing that occurs in the gate G of the switching element can be more effectively suppressed.

[0031] [Modification 2 of Embodiment 1] 3, the semiconductor circuit 1B according to the second modification of the first embodiment has a structure in which the switching circuit 10 and the noise elimination circuit 40 are both housed inside a package 60, and the current detection circuit 30 is disposed outside the package 60. In the semiconductor circuit 1B according to the second modification of the first embodiment, reference numeral 22 denotes a terminal located between the noise elimination circuit 40 and the ground wiring 50.

[0032] According to the semiconductor circuit 1B of the second modification of the first embodiment, as described above, by accommodating the noise removal circuit 40 inside the package 60, none of the components constituting the noise removal circuit 40 are externally attached to the package 60, which further shortens the wiring of the noise removal circuit 40 and reduces the impedance, thereby more effectively suppressing the ringing occurring at the gate G of the switching element.

[0033] [Modification 3 of Embodiment 1] 4, the semiconductor circuit 1C according to the third modification of the first embodiment has a structure in which the switching circuit 10, the noise elimination circuit 40, and the current detection circuit 30 are all housed inside a single package 60. In the semiconductor circuit 1C according to the third modification of the first embodiment, reference numeral 22 denotes a terminal located between the noise elimination circuit 40 and the ground wiring 50.

[0034] The semiconductor circuit 1C according to the third modification of the first embodiment has the advantage that the mounting area is reduced and a more compact semiconductor circuit can be configured.

[0035] [Embodiment 2] 5 is a diagram showing a semiconductor circuit 2 according to a second embodiment. The semiconductor circuit 2 according to the second embodiment basically has the same configuration as the semiconductor circuit 1 according to the first embodiment, but the configuration of the switching circuit 10 is different from that of the semiconductor circuit 1 according to the first embodiment. That is, as shown in FIG. 5, the semiconductor circuit 2 according to the second embodiment uses a switching circuit formed of a half-bridge circuit having a high-side switching element (transistor QH) and a low-side switching element (transistor QL) as the switching circuit 10. The noise removal circuit 40 is connected between the low-side switching element (transistor QL) and the ground wiring 50.

[0036] In the semiconductor circuit 2 according to the second embodiment, the reference symbols 12H and 12L indicate gate terminals, the reference symbol 18 indicates a midpoint terminal, and the reference symbols 24H and 24L indicate source sense terminals. The noise removal circuit terminal 20 and the low-side source sense terminal 24L may be combined into one terminal. In this specification, the reference symbol H means the high side, and the reference symbol L means the low side.

[0037] According to the semiconductor circuit 2 of the second embodiment, the configuration of the switching circuit 10 is different from that of the semiconductor circuit 1 of the first embodiment. However, as in the case of the semiconductor circuit 1 of the first embodiment, a noise removal circuit 40 is connected between the switching circuit 10 and the ground wiring 50 in a parallel relationship to the current detection circuit 30. Therefore, similar to the effect of the semiconductor circuit 1 of the first embodiment, ringing occurring in the switching circuit 10 (in this case, between the source S of the transistor QL and the ground wiring 50) is suppressed, and ringing occurring in the gate G of the switching element can be suppressed.

[0038] Furthermore, according to the semiconductor circuit 2 of the second embodiment, the noise removal circuit 40 is an RC series circuit in which a resistor R and a capacitor C are connected in series. Therefore, similar to the effect of the semiconductor circuit 1 of the first embodiment, with a relatively simple configuration, ringing occurring between the switching circuit 10 and the ground wiring 50 can be suppressed, and ringing occurring at the gate G of the switching element can be suppressed.

[0039] Furthermore, according to the semiconductor circuit 2 of embodiment 2, the current detection circuit 30 and the noise removal circuit 40 are arranged outside the package 60, which makes it easier to optimize the characteristics of the noise removal circuit 40, similar to the effect of the semiconductor circuit 1 of embodiment 1, and makes it possible to more effectively suppress ringing that occurs in the switching element.

[0040] [Modifications 1 to 3 of Embodiment 2] Fig. 6 is a diagram showing a semiconductor circuit 2A according to Modification 1 of Embodiment 2. Fig. 7 is a diagram showing a semiconductor circuit 2B according to Modification 2 of Embodiment 2. Fig. 8 is a diagram showing a semiconductor circuit 2C according to Modification 3 of Embodiment 2.

[0041] [Modification 1 of Embodiment 2] A semiconductor circuit 2A according to a first modification of the second embodiment basically has the same configuration as the semiconductor circuit 2 according to the second embodiment, but the position of the noise removal circuit 40 is different from that of the semiconductor circuit 2 according to the second embodiment. That is, as shown in FIG. 6 , the semiconductor circuit 2A according to the first modification of the second embodiment has a structure in which the switching circuit 10 and one of the resistor R and the capacitor C (resistor R in this case) that constitute the RC series circuit of the noise removal circuit 40 are housed inside a package 60, and the current detection circuit 30 and the other of the resistor R and the capacitor C (capacitor C in this case) that constitute the RC series circuit of the noise removal circuit 40 are disposed outside the package 60. In the semiconductor circuit 2A according to the first modification of the second embodiment, reference numeral 21 denotes a terminal located between the resistor R and the capacitor C of the noise removal circuit 40.

[0042] According to the semiconductor circuit 2A of the first variant of the second embodiment, as described above, by accommodating either the resistor R or the capacitor C that constitutes the RC series circuit of the noise removal circuit 40 inside the package 60, the number of components that need to be externally attached to the package 60 is reduced, the wiring of the noise removal circuit 40 is shortened, the impedance is reduced, and the ringing that occurs in the gate G of the switching element can be more effectively suppressed.

[0043] [Modification 2 of Embodiment 2] 7, the semiconductor circuit 2B according to the second modification of the second embodiment has a structure in which the switching circuit 10 and the noise removal circuit 40 are both housed inside a package 60, and the current detection circuit 30 is disposed outside the package 60. In the semiconductor circuit 2B according to the second modification of the second embodiment, reference numeral 22 denotes a terminal located between the capacitor C of the noise removal circuit 40 and the ground wiring 50.

[0044] According to the semiconductor circuit 2B of the second variant of the second embodiment, as described above, by accommodating the noise removal circuit 40 inside the package 60, none of the components constituting the noise removal circuit 40 are externally attached to the package 60, the wiring of the noise removal circuit 60 is further shortened, the impedance is reduced, and the ringing occurring at the gate G of the switching element can be more effectively suppressed.

[0045] [Modification 3 of Embodiment 2] 8, a semiconductor circuit 2C according to a third modification of the second embodiment has a structure in which the switching circuit 10, the noise elimination circuit 40, and the current detection circuit 30 are all housed inside a single package 60. In the semiconductor circuit 2C according to the third modification of the second embodiment, reference numeral 22 denotes a terminal located between the capacitor C of the noise elimination circuit 40 and the ground wiring 50.

[0046] The semiconductor circuit 2C according to the third modification of the second embodiment has the advantage that the mounting area is reduced and a more compact semiconductor circuit can be configured.

[0047] [Embodiment 3] 9 is a diagram showing a semiconductor circuit 3 according to a third embodiment. The semiconductor circuit 3 according to the third embodiment basically has the same configuration as the semiconductor circuit 2 according to the second embodiment, but the configuration of the switching circuit 10 is different from that of the semiconductor circuit 2 according to the second embodiment. That is, as shown in FIG. 9, the semiconductor circuit 3 according to the third embodiment uses, as the switching circuit 10, a switching circuit formed of a full-bridge circuit in which two half-bridge circuits 10-1 and 10-2 are connected in parallel. The noise removal circuit 40 is connected between the low-side switching elements (transistors QL1 and QL2) and the ground wiring 50.

[0048] In the semiconductor circuit 3 according to the third embodiment, reference numerals 12H-1, 12H-2, 12L-1, and 12L-2 denote gate terminals, reference numerals 18-1 and 18-2 denote midpoint terminals, reference numerals 24H-1, 24H-2, 24L-1, and 24L-2 denote source sense terminals, and reference numerals QH1, QH2, QL1, and QL2 denote transistors (MOSFETs). The noise elimination circuit terminal 20 and the low-side source sense terminal 24L-1 may be combined into one terminal, and the noise elimination circuit terminal 20 and the low-side source sense terminal 24L-2 may be combined into one terminal.

[0049] According to the semiconductor circuit 3 of the third embodiment, the configuration of the switching circuit 10 is different from that of the semiconductor circuit 2 of the second embodiment, but the configuration other than the configuration of the switching circuit 10 is the same as that of the semiconductor circuit 2 of the second embodiment. Therefore, as in the semiconductor circuit 2 of the second embodiment, the noise removal circuit 40 is connected in parallel to the current detection circuit 30 between the switching circuit 10 and the ground wiring 50, and therefore, similar to the effect of the semiconductor circuit 2 of the second embodiment, ringing occurring in the switching circuit 10 (in this case, between the sources S of the transistors QL1 and QL2 and the ground wiring 50) is suppressed, and ringing occurring in the gates G of the switching elements can be suppressed.

[0050] Furthermore, according to the semiconductor circuit 3 of the third embodiment, the noise removal circuit 40 is an RC series circuit in which a resistor R and a capacitor C are connected in series. Therefore, similar to the effect of the semiconductor circuit 1 of the first embodiment, with a relatively simple configuration, ringing occurring between the switching circuit 10 and the ground wiring 50 can be suppressed, and ringing occurring at the gate G of the switching element can be suppressed.

[0051] Furthermore, according to the semiconductor circuit 3 of embodiment 3, the current detection circuit 30 and the noise removal circuit 40 are arranged outside the package 60, which makes it easier to optimize the characteristics of the noise removal circuit 40, similar to the effect of the semiconductor circuit 1 of embodiment 1, and makes it possible to more effectively suppress ringing that occurs in the switching element.

[0052] [Modifications 1 to 6 of Embodiment 3] FIG. 10 is a diagram showing a semiconductor circuit 3A according to a first modification of the third embodiment. FIG. 11 is a diagram showing a semiconductor circuit 3B according to a second modification of the third embodiment. FIG. 12 is a diagram showing a semiconductor circuit 3C according to a third modification of the third embodiment. FIG. 13 is a diagram showing a semiconductor circuit 3D according to a fourth modification of the third embodiment. FIG. 14 is a diagram showing a semiconductor circuit 3E according to a fifth modification of the third embodiment. FIG. 15 is a diagram showing a semiconductor circuit 3F according to a sixth modification of the third embodiment.

[0053] [Modification 1 of Embodiment 3] The semiconductor circuit 3A according to the first modification of the third embodiment basically has the same configuration as the semiconductor circuit 3 according to the third embodiment, but the position of the noise removal circuit 40 is different from that of the semiconductor circuit 3 according to the third embodiment. That is, as shown in Fig. 10 , the semiconductor circuit 3A according to the first modification of the third embodiment has a structure in which the switching circuit 10 and one of the resistor R and the capacitor C (in this case, the resistor R) that constitute the RC series circuit of the noise removal circuit 40 are housed inside a package 60, and the current detection circuit 30 and the other of the resistor R and the capacitor C (in this case, the capacitor C) that constitute the RC series circuit of the noise removal circuit 40 are arranged outside the package 60. In the semiconductor circuit 3A according to the first modification of the third embodiment, reference numeral 21 denotes a terminal located between the resistor R and the capacitor C of the noise removal circuit 40.

[0054] According to the semiconductor circuit 3A of the first variant of the third embodiment, as described above, by accommodating either the resistor R or the capacitor C that constitutes the RC series circuit of the noise removal circuit 40 inside the package 60, the number of components that need to be externally attached to the package 60 is reduced, the wiring of the noise removal circuit 40 is shortened, the impedance is lowered, it becomes easier to adjust and optimize the characteristics of the noise removal circuit 40, and the ringing that occurs in the gate G of the switching element can be more effectively suppressed.

[0055] [Modification 2 of Embodiment 3] 11 , the semiconductor circuit 3B according to the second modification of the third embodiment has a structure in which the switching circuit 10 and the noise elimination circuit 40 are both housed inside a package 60, and the current detection circuit 30 is disposed outside the package 60. In the semiconductor circuit 3B according to the second modification of the third embodiment, reference numeral 22 denotes a terminal located between the noise elimination circuit 40 and the ground wiring 50.

[0056] According to the semiconductor circuit 3B of the second variant of the third embodiment, as described above, by accommodating the noise removal circuit 40 inside the package 60, none of the components constituting the noise removal circuit 40 are externally attached to the package 60, the wiring of the noise removal circuit 40 is further shortened, the impedance is reduced, and the ringing occurring at the gate G of the switching element can be suppressed even more effectively.

[0057] [Modification 3 of Embodiment 3] 12, a semiconductor circuit 3C according to a third modification of the third embodiment has a structure in which the switching circuit 10, the noise elimination circuit 40, and the current detection circuit 30 are all housed inside a single package 60. In the semiconductor circuit 3C according to the third modification of the third embodiment, reference numeral 22 denotes a terminal located between the noise elimination circuit 40 and the ground wiring 50.

[0058] The semiconductor circuit 3C according to the third modification of the third embodiment has the effect of reducing the mounting area and enabling the configuration of a more compact semiconductor circuit.

[0059] [Modification 4 of Embodiment 3] A semiconductor circuit 3D according to a fourth modification of the third embodiment basically has the same configuration as the semiconductor circuit 3 according to the third embodiment, but the configurations of the current detection circuit and the noise removal circuit are different from those of the semiconductor circuit 3 according to the third embodiment. That is, as shown in Fig. 13, the semiconductor circuit 3D according to the fourth modification of the third embodiment includes, as current detection circuits, two current detection circuits (a first current detection circuit 30-1 and a second current detection circuit 30-2) provided corresponding to each half-bridge circuit. Also, as noise removal circuits, the semiconductor circuit 3D includes, as noise removal circuits, two noise removal circuits (a first noise removal circuit 40-1 and a second noise removal circuit 40-2) provided corresponding to each half-bridge circuit.

[0060] In the semiconductor circuit 3D according to the fourth modification of the third embodiment, the terminal 20-1 for the noise elimination circuit and the low-side source sense terminal 24L-1 may be shared as one terminal, and the terminal 20-2 for the noise elimination circuit and the low-side source sense terminal 24L-2 may be shared as one terminal.

[0061] As described above, the semiconductor circuit 3D according to the fourth modification of the third embodiment differs from the semiconductor circuit 3 according to the third embodiment in the configuration of the current detection circuit and the configuration of the noise removal circuit. However, since the noise removal circuits 40-1, 40-2 are arranged between the low-side switching elements (transistors QL1, QL2) and the ground wiring 50, ringing occurring in the switching circuit 10 (in this case, between the sources S of the transistors QL1, QL2 and the ground wiring 50) is suppressed, as in the semiconductor circuit 3 according to the third embodiment, and ringing occurring in the gates G of the switching elements can be suppressed.

[0062] [Modification 5 of Embodiment 3] A semiconductor circuit 3E according to Modification 5 of Embodiment 3 basically has the same configuration as the semiconductor circuit 3 according to Embodiment 3, but the configuration of the noise removal circuit differs from that of the semiconductor circuit 3 according to Embodiment 3. That is, as shown in Fig. 14, the semiconductor circuit 3E according to Modification 5 of Embodiment 3 includes, as noise removal circuits, two noise removal circuits (first noise removal circuits 40-1, 40-2) provided corresponding to each half-bridge circuit. In the semiconductor circuit 3E according to Modification 5 of Embodiment 3, the noise removal circuit terminal 20-1 and the low-side source sense terminal 24L-1 may be shared as a single terminal, and the noise removal circuit terminal 20-2 and the low-side source sense terminal 24L-2 may be shared as a single terminal.

[0063] As described above, the semiconductor circuit 3E according to the fifth modification of the third embodiment differs from the semiconductor circuit 3 according to the third embodiment in the configuration of the noise removal circuit. However, since the noise removal circuits 40-1, 40-2 are arranged between the low-side switching elements (transistors QL1, QL2) and the ground wiring 50, ringing occurring in the switching circuit 10 (in this case, between the sources S of the transistors QL1, QL2 and the ground wiring 50) is suppressed, as in the semiconductor circuit 3 according to the third embodiment, and ringing occurring in the gates G of the switching elements can be suppressed.

[0064] [Modification 6 of Embodiment 3] The semiconductor circuit 3F according to the sixth modification of the third embodiment basically has the same configuration as the semiconductor circuit 3 according to the third embodiment, but the configuration of the current detection circuit is different from that of the semiconductor circuit 3 according to the third embodiment. That is, as shown in Fig. 15, the semiconductor circuit 3F according to the sixth modification of the third embodiment includes, as current detection circuits, two current detection circuits (a first current detection circuit 30-1 and a second current detection circuit 30-2) provided corresponding to each half-bridge circuit.

[0065] As described above, the semiconductor circuit 3F according to the sixth variant of the third embodiment differs from the semiconductor circuit 3 according to the third embodiment in the configuration of the current detection circuit. However, since the noise removal circuit 40 is connected in parallel to the current detection circuits 30-1 and 30-2 between each low-side switching element (transistors QL1 and QL2) and the ground wiring 50, as in the semiconductor circuit 3 according to the third embodiment, ringing occurring in the switching circuit 10 (in this case, between the source S of the transistors QL1 and QL2 and the ground wiring 50) is suppressed, and ringing occurring in the gate of the switching element can be suppressed.

[0066] [Embodiment 4] 16 is a diagram showing a semiconductor circuit 4 according to a fourth embodiment. The semiconductor circuit 4 according to the fourth embodiment basically has the same configuration as the semiconductor circuit 3D according to the fourth modification of the third embodiment, but the configuration of the high-side switching element is different from that of the semiconductor circuit 3D according to the fourth modification of the third embodiment. That is, as shown in FIG. 16, the semiconductor circuit 4 according to the fourth embodiment uses two diodes (diodes DiH1 and DiH2) instead of two transistors (transistors QH1 and QH2) on the high-side side.

[0067] As described above, the semiconductor circuit 4 according to the fourth embodiment differs from the semiconductor circuit 3D according to the fourth modification of the third embodiment in the configuration of the high-side switching elements. However, between each low-side switching element (transistors QL1, QL2) and the ground wiring 50, a noise removal circuit 40-1 is connected in parallel to the current detection circuit 30-1, and a noise removal circuit 40-2 is connected in parallel to the current detection circuit 30-2. Therefore, as in the semiconductor circuit 3D according to the fourth modification of the third embodiment, ringing occurring in the switching circuit 10 (in this case, between the source S of the transistors QL1, QL2 and the ground wiring 50) is suppressed, and ringing occurring in the gate G of the switching element can be suppressed.

[0068] [Embodiment 5] 17 is a diagram showing a semiconductor circuit 5 according to embodiment 5. The semiconductor circuit 5 according to embodiment 5 basically has the same configuration as the semiconductor circuit 3 according to embodiment 3, but the configuration of the switching circuit 10 is different from the configuration of the semiconductor circuit 3 according to embodiment 3. That is, as shown in FIG. 17, the semiconductor circuit 5 according to embodiment 5 uses an inverter circuit in which three half-bridge circuits are connected in parallel as the switching circuit 10.

[0069] As described above, in the semiconductor circuit 5 according to the fifth embodiment, the configuration of the switching circuit 10 is different from that in the semiconductor circuit 3 according to the third embodiment. However, between each low-side switching element (transistors QL1, QL2, QL3) and the ground wiring 50, a noise removal circuit (first noise removal circuit 40-1) is connected in parallel to the current detection circuit (first current detection circuit 30-1), a noise removal circuit (second noise removal circuit 40-2) is connected in parallel to the current detection circuit (second current detection circuit 30-2), and a noise removal circuit (third noise removal circuit 40-3) is connected in parallel to the current detection circuit (third current detection circuit 30-3). As a result, as in the case of the semiconductor circuit 3 according to the third embodiment, ringing occurring in the switching circuit 10 (in this case, between the sources S of the transistors QL1, QL2, QL3 and the ground wiring 50) is suppressed, and ringing occurring in the gates G of the switching elements can be suppressed.

[0070] [Plane layout of Modification 5 of Embodiment 3] Fig. 18 is a planar layout diagram showing a semiconductor circuit 3E (see Fig. 14, but ground wiring is not shown in the figure) according to Modification 5 of Embodiment 3. In Fig. 18 and Figs. 19 to 21 described below, reference numeral 100 denotes an insulating substrate, reference numerals 110, 120, 130, and 140 denote wiring patterns, and reference numerals 400, 400A, 400B, and 400C denote circuit patterns.

[0071] In a semiconductor circuit 3E according to a fifth modification of the third embodiment, a first noise removal circuit 40-1 is connected to a noise removal circuit terminal 20-1 shared with a source sense terminal 24L-1 of a transistor QL1, and a second noise removal circuit 40-2 is connected to a noise removal circuit terminal 20-2 shared with a source sense terminal 24L-2 of a transistor QL2. A current detection circuit 30 is connected to a ground terminal 16.

[0072] The semiconductor circuit 3E according to the fifth modification of the third embodiment has the planar layout shown in FIG. 18, but noise removal circuits 40-1, 40-2 are connected in parallel to the current detection circuit 30 between each low-side switching element (transistors QL1, QL2) and the ground wiring 50 (not shown) (see FIG. 14). Therefore, as in the case of the semiconductor circuit 3 according to the third embodiment, ringing occurring in the switching circuit 10 (in this case, between the source S of the transistors QL1, QL2 and the ground wiring 50) is suppressed, and ringing occurring in the gate G of the switching element can be suppressed.

[0073] [Seventh Modification of the Third Embodiment] FIG. 19 is a planar layout diagram showing a semiconductor circuit 3G according to a seventh modification of the third embodiment. The semiconductor circuit 3G according to the seventh modification of the third embodiment basically has the same configuration as the semiconductor circuit 3E according to the fifth modification of the third embodiment, but the arrangement position of the noise removal circuits differs from that of the semiconductor circuit 3E according to the fifth modification of the third embodiment. That is, in the semiconductor circuit 3G according to the seventh modification of the third embodiment, the noise removal circuits 40-1 and 40-2 are arranged inside the package 60, as shown in FIG.

[0074] As described above, in the semiconductor circuit 3G according to the seventh modification of the third embodiment, the noise removal circuits 40-1 and 40-2 are arranged inside the package 60, but the noise removal circuits 40-1 and 40-2 are connected in parallel to the current detection circuit 30 between each low-side switching element (transistors QL1 and QL2) and the ground wiring 50 (not shown). Therefore, as in the case of the semiconductor circuit 3E according to the fifth modification of the third embodiment, ringing occurring in the switching circuit 10 (in this case, between the source S of the transistors QL1 and QL2 and the ground wiring 50) is suppressed, and ringing occurring in the gates of the switching elements can be suppressed.

[0075] Furthermore, according to the semiconductor circuit 3G of the seventh modification of the third embodiment, the noise removal circuits 40-1 and 40-2 are arranged inside the package 60, which further shortens the wiring of the noise removal circuits 40-1 and 40-2, thereby reducing the impedance and more effectively suppressing the ringing occurring at the gate of the switching element.

[0076] [Variation 8 of Embodiment 3] 20 is a planar layout diagram showing a semiconductor circuit 3H according to Modification 8 of Embodiment 3. In the semiconductor circuit 3H according to Modification 8 of Embodiment 3, the entire noise removal circuits 40-1 and 40-2 are arranged inside the package 60, but the present invention is not limited to this. As shown in FIG. 20, only a part of the noise removal circuits 40-1 and 40-2 (in this case, the resistor R) can also be arranged inside the package 60.

[0077] [Test example] In order to confirm the effects of the present invention, the following test examples were carried out.

[0078] 1. Semiconductor circuit used in the test example In the test examples, a semiconductor circuit 3E according to Modification 5 of Embodiment 3 was used as Test Example 1 (Example) (see FIGS. 14 and 18). Test Example 1 (Example) without the noise removal circuits 40-1 and 40-2 was used as Test Example 2 (Comparative Example) (see FIG. 21). FIG. 21 is a planar layout diagram showing a semiconductor circuit 6 according to Test Example 2 (Comparative Example).

[0079] 2. Test methods in test examples In each of the above-mentioned Test Example 1 (Example) and Test Example 2 (Comparative Example), the test was performed by simulating the drain-source voltage Vds, gate-source voltage Vgs, and drain-source current Id using a circuit simulator when a DC voltage of 400 V was applied between the ground wiring 50 (not shown) and the power supply terminals 14-1 and 14-2 and gate voltages for performing full-bridge operation were applied at appropriate timing to the gate terminals 12H-1, 12H-2, 12L-1, and 12L-2 of the four transistors QH1, QH2, QL1, and QL2.

[0080] 3. Test results in the test example FIG. 22 is a diagram illustrating a simulation model for a test example. In the diagram, symbol Ls1 indicates the inductance of the wiring of the current detection circuit, symbol Rsnt indicates the current detection resistor of the current detection circuit, symbol Ls2 indicates the wiring of the noise removal circuit, symbol Vgs indicates the gate-source voltage of transistor QL2, symbol Vds indicates the drain-source voltage of transistor QL2, symbol Vs indicates the source voltage of transistor QL2, and symbol Id indicates the drain current of transistor QL2. FIG. 23 is a diagram illustrating the simulation results for the test example. FIG. 23(A) is a diagram illustrating the simulation results for Test Example 1 (Example), and FIG. 23(B) is a diagram illustrating the simulation results for Test Example 2 (Comparative Example).

[0081] In Test Example 2 (Comparative Example), as can be seen from Figure 23(B), the noise frequency is approximately 125 MHz, and this harmonic component is superimposed on the switching waveform. The RC series circuit for noise removal forms a so-called first-order low-pass filter, so the cutoff frequency fc is given by the following equation. fc=1 / (2πRC) (1) Therefore, if the cutoff frequency is determined to be equal to or lower than the noise frequency, the resistance value R1 can be determined, and the capacitance C1 of the capacitor can be determined by the following equation. C=1 / (2πRfc) (2)

[0082] As can be seen from Figure 23(B), the noise frequency is approximately 125 MHz. For example, if the cutoff frequency is 100 MHz and the resistance value R1 is 1 ohm, then the capacitor capacitance C1 is 1.59 nF according to equation (2) above. If the resistance value R1 is 2 ohms, then the capacitor capacitance C1 is 0.79 nF according to equation (2) above. If the cutoff frequency is 50 MHz and the resistance value R1 is 1 ohm, then the capacitor capacitance C1 is 3.18 nF according to equation (2) above. If the resistance value R1 is 2 ohms, then the capacitor capacitance C1 is 1.59 nF according to equation (2).

[0083] The cutoff frequency must be lower than the noise frequency, and higher than the switching frequency of the bridge circuit. The closer the cutoff frequency is to the switching frequency, the slower the rise and fall of the switching waveform will be, so it is better to have a higher cutoff frequency. The cutoff frequency will be set between the noise frequency and the switching frequency, but these factors must be taken into consideration when deciding.

[0084] Figure 23(A) shows the simulation results when the cutoff frequency is set to 100 MHz. The upper graph in Figure 23(A) shows the drain-source voltage Vds, and the lower graph in Figure 23(A) shows the gate-source voltage Vgs and drain-source current Id. For Figure 23(B), the cutoff frequency is set to 100 MHz, and the resistance value R1 and capacitance C1 are determined (optimized) and the simulation results are shown.

[0085] As can be seen from a comparison between Figures 23(A) and 23(B), when a noise removal circuit is connected in parallel to the current detection circuit between the switching circuit and the ground wiring, as in Test Example 1 (Example), it was found that the ringing occurring in the switching circuit is suppressed more than in Test Example 2 (Comparative Example), and the ringing occurring in the gate of the switching element can be suppressed.

[0086] The present invention is not limited to the above-described embodiments, and any other modifications may be made without departing from the spirit of the present invention. Various modifications are possible within the scope of the present invention. For example, the following modifications are possible: is.

[0087] (1) The shape, number, size, position, etc. of the components in the semiconductor circuit of the present invention are not limited to those shown in the drawings, and may be changed as appropriate as long as the characteristics of the present invention are not impaired.

[0088] (2) In each embodiment, a MOSFET is used as a transistor, but the present invention is not limited to this. An IGBT may be used as a transistor. Good too.

[0089] (3) In each of the first modified examples, the resistor R and the capacitor C that constitute the RC series circuit of the noise removal circuit 40 are accommodated inside the package 60, and the capacitor C is disposed outside the package 60. However, the present invention is not limited to this. The resistor R and the capacitor C that constitute the RC series circuit of the noise removal circuit 40 may be accommodated inside the package 60, and the resistor R may be disposed outside the package 60. [Explanation of symbols]

[0090] 1,1A,1B,1C,2,2A,2B,2C,3,3A,3B,3C,3D,3E,3F,3G,3H,4,5...Semiconductor circuit, 6...Semiconductor circuit (comparative example), 10,10-1,10-2,10-3...Switching circuit, 12,12H ,12L,12H-1,12H-2,12H-3,12L-1,12L-2,12L-3...Gate terminal, 14,14-1,14-2...Power terminal, 16,16-1,16-2...Ground terminal, 18,18-1,18-2,18-3...Middle point terminal, 20, 20-1, 20-2... terminal for noise elimination circuit, 21... terminal for R / C connection, 22, 22-1, 22-2... terminal for RC terminal / ground wiring connection, 24H-1, 24H-2, 24L-1, 24L-2... source sense terminal, 30, 30-1, 30-2, 30-3... current detection circuit, 40, 40-1, 40-2, 40-3... noise elimination circuit, R... resistor, C... capacitor, 50... ground wiring, 60... package, 400, 400A, 400B... circuit pattern

Claims

1. A semiconductor circuit comprising: a switching circuit having at least one switching element; a ground wiring; and a current detection circuit connected between the switching circuit and the ground wiring, a noise removal circuit connected between the switching circuit and the ground wiring in parallel with the current detection circuit;

2. 2. The semiconductor circuit according to claim 1, wherein the noise removal circuit is an RC series circuit in which a resistor and a capacitor are connected in series.

3. the switching circuit is a circuit including a half-bridge circuit having a high-side switching element and a low-side switching element, 2. The semiconductor circuit according to claim 1, wherein the noise removal circuit is connected between the low-side switching element and the ground wiring.

4. 4. The semiconductor circuit according to claim 3, wherein the switching circuit is a full-bridge circuit in which two of the half-bridge circuits are connected in parallel.

5. 5. The semiconductor circuit according to claim 3, wherein the high-side switching element and the low-side switching element are both made of transistors.

6. 5. The semiconductor circuit according to claim 3, wherein the high-side switching element is a diode, and the low-side switching element is a transistor.

7. 4. The semiconductor circuit according to claim 3, wherein the switching circuit is a circuit in which three or more of the half-bridge circuits are connected in parallel.

8. The switching circuit is housed within a package; 2. The semiconductor circuit according to claim 1, wherein the current detection circuit and the noise removal circuit are both arranged outside the package.

9. the switching circuit and one of the resistor and the capacitor that constitute the RC series circuit are housed inside a package; 3. The semiconductor circuit according to claim 2, wherein the current detection circuit and the other of the resistor and the capacitor that constitute the RC series circuit are arranged outside the package.

10. the switching circuit and the noise elimination circuit are both housed inside a package; 2. The semiconductor circuit according to claim 1, wherein the current detection circuit has a structure disposed outside the package.

11. 2. The semiconductor circuit according to claim 1, wherein the switching circuit, the noise elimination circuit, and the current detection circuit are all housed in a single package.

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