A / d conversion circuit

Abstract

To provide an A / D conversion circuit or the like capable of sampling in high accuracy by an A / D converter in a case a high-speed A / D converter is connected after a pipeline stage.SOLUTION: An A / D conversion circuit 100 includes: a first pipeline stage 110b for outputting a first digital value in x bit by A / D conversion based on an input signal; a second pipeline stage 110c for outputting a second digital value in y bit smaller than the x bit by A / D conversion based on a first analog output signal of the first pipeline stage 110b; and an A / D converter for sampling a second analog output signal of the second pipeline stage 110c in a sampling period shorter than the sampling period of the first pipeline stage 110b and shorter than the sampling period of the second pipeline stage 110c, and for outputting a third digital value by performing A / D conversion based on the sampling result.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an A / D conversion circuit and the like. [Background technology]

[0002] Patent Document 1 discloses a pipelined A / D conversion circuit including a 4-bit bit block and a 1.5-bit bit block that share an amplifier. In Patent Document 1, of the two bit blocks that share the amplifier, the number of bits in the latter stage is smaller than the number of bits in the former stage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-054608 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 does not disclose a configuration in which an A / D converter that operates on a clock faster than the clock of the pipeline A / D conversion circuit is connected to the rear stage of the pipeline A / D conversion circuit, nor does it disclose an appropriate number of bits for each bit block in such a configuration. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to an A / D conversion circuit including a first pipeline stage that outputs a first digital value of x bits by A / D conversion based on an input signal, a second pipeline stage that outputs a second digital value of y bits smaller than the x bits by A / D conversion based on a first analog output signal of the first pipeline stage, and an A / D converter that samples the second analog output signal of the second pipeline stage in a sampling period that is shorter than the sampling period of the first pipeline stage and the sampling period of the second pipeline stage, performs A / D conversion based on the sampling result, and outputs a third digital value. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a first example of an A / D conversion circuit configuration. [Figure 2] 1 is an example timing chart illustrating the operation of a pipeline stage and a cyclic A / D converter. [Figure 3] 2 shows a second example of an A / D conversion circuit configuration. [Figure 4] 4 is an example timing chart illustrating the operation of a pipeline stage and a successive approximation type A / D converter. [Figure 5] A detailed example of the configuration of a successive approximation type A / D converter. [Figure 6] A detailed example of the first pipeline stage configuration. [Figure 7] A detailed example of the capacitor circuit configuration. [Figure 8] FIG. 1 is a diagram illustrating the operation of the first pipeline stage. [Figure 9] FIG. 10 is a diagram illustrating the operation of the encoder and switch group in the calculation and hold operation of a 2.5-bit pipeline stage. [Figure 10] Detailed configuration example of the second pipeline stage. [Figure 11] Detailed configuration example of the third pipeline stage. [Figure 12] FIG. 10 is a diagram illustrating the operation of the second and third pipeline stages. [Figure 13]FIG. 1 is a diagram illustrating the operation of the encoder and switch group in the calculation and hold operation of a 1.5-bit pipeline stage. [Figure 14] Detailed configuration example of the first stage of a cyclic A / D converter. [Figure 15] Detailed configuration example of the second stage of a cyclic A / D converter. [Figure 16] FIG. 2 is a diagram illustrating the operation of the first and second stages of the cyclic A / D converter. [Figure 17] 1 is an example of a timing chart illustrating the overall operation of an A / D conversion circuit. [Figure 18] FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0008] 1. A / D conversion circuit 1 shows a first configuration example of an A / D conversion circuit. The A / D conversion circuit 100 includes pipeline stages 110a, 110b, and 110c, a cyclic A / D converter 120, a flash A / D converter 130, and an adder 190.

[0009] The pipeline stage 110a samples the input voltage VIN to the A / D conversion circuit 100, A / D converts the sampled voltage, and outputs the A / D conversion result as a digital value DQa[2:0]. The pipeline stage 110a multiplies the difference between the sampled voltage and the voltage obtained by D / A converting the digital value DQa[2:0] by a gain and outputs the result. The digital value DQa[2:0] has a range of 2.5 bits. That is, the digital value DQa[2:0] can take on seven values: 000b, 001b, 010b, 011b, 100b, 101b, and 110b. The "b" at the end of the number indicates a binary number.

[0010] Pipeline stage 110b samples the output voltage of pipeline stage 110a, A / D converts the sampled voltage, and outputs the A / D converted result as a digital value DQb[2:0]. Pipeline stage 110b multiplies the difference between the sampled voltage and the voltage obtained by D / A converting digital value DQb[2:0] by a gain and outputs the result. Digital value DQb[2:0] has a range of 2.5 bits.

[0011] Pipeline stage 110c samples the output voltage of pipeline stage 110b, A / D converts the sampled voltage, and outputs the A / D conversion result as a digital value DQc[1:0]. Pipeline stage 110c multiplies the difference between the sampled voltage and the voltage obtained by D / A converting digital value DQc[1:0] by a gain and outputs the result. Digital value DQc[1:0] has a range of 1.5 bits, which is smaller than the 2.5-bit range of digital value DQb[2:0] of the previous stage. Digital value DQc[1:0] can take three values: 00b, 01b, and 10b.

[0012] The pipeline stages 110a, 110b, and 110c perform A / D conversion using the clock signal CKA as an operating clock signal, that is, the pipeline stages 110a, 110b, and 110c perform one A / D conversion per cycle of the clock signal CKA.

[0013] In the first cycle of A / D conversion, the cyclic A / D converter 120 A / D converts the output voltage of the pipeline stage 110c and outputs the result as digital values ​​DQd[2:0] and DQe[2:0]. In the second cycle of A / D conversion, the cyclic A / D converter 120 A / D converts the output voltage of the cyclic A / D converter 120 that has completed the first cycle of A / D conversion and outputs the result as digital values ​​DQd[2:0] and DQe[2:0]. Each of the digital values ​​DQd[2:0] and DQe[2:0] has a 2.5-bit range. By performing two cycles of A / D conversion, a total of 2.5 bits x 4 data is obtained.

[0014] Specifically, the cyclic A / D converter 120 includes a first stage 120d and a second stage 120e.

[0015] The first round of A / D conversion will be described. The first stage 120d samples the output voltage of the pipeline stage 110c, A / D converts the sampled voltage, and outputs the result of the A / D conversion as a digital value DQd[2:0]. The first stage 120d multiplies the difference between the sampled voltage and the voltage obtained by D / A converting the digital value DQd[2:0] by a gain, and outputs the result. The second stage 120e samples the output voltage of the first stage 120d, A / D converts the sampled voltage, and outputs the result of the A / D conversion as a digital value DQe[2:0]. The second stage 120e multiplies the difference between the sampled voltage and the voltage obtained by D / A converting the digital value DQe[2:0] by a gain, and outputs the result.

[0016] The second round of A / D conversion will now be described. The first stage 120d samples the output voltage of the second stage 120e, which has completed the first round of A / D conversion, performs A / D conversion on the sampled voltage, and outputs the result of the A / D conversion as a digital value DQd[2:0]. The rest of the process is the same as the first round of A / D conversion.

[0017] The cyclic A / D converter 120 performs A / D conversion using clock signals CKA and CKB as operating clock signals. The period of the clock signal CKB is half that of the clock signal CKA. The cyclic A / D converter 120 performs two A / D conversions based on the clock signal CKB per period of the clock signal CKA.

[0018] The flash A / D converter 130 A / D converts the output voltage of the cyclic A / D converter 120 that has completed the second round of A / D conversion, and outputs the result of the A / D conversion as a digital value DQf[2:0]. The flash A / D converter 130 includes a reference voltage generation circuit and multiple comparators. The reference voltage generation circuit generates multiple reference voltages and inputs each reference voltage to each comparator one by one. The comparators compare the input voltage to the flash A / D converter 130 with the reference voltage input to the comparator. The flash A / D converter 130 outputs the digital value DQf[2:0] based on the outputs of the multiple comparators.

[0019] The flash A / D converter 130 operates using the clock signal CKC as its operating clock. The period of the clock signal CKC is the same as the period of the clock signal CKA, but the phase of the clock signal CKC is different from the phase of the clock signal CKA. Specifically, the sampling timing of the flash A / D converter 130 based on the clock signal CKC is shifted by half a period from the sampling timing of the pipeline stage 110a based on the clock signal CKA.

[0020] The adder 190 adds the digital values ​​DQa[2:0], DQb[2:0], DQc[1:0], the first round DQd[2:0], the first round DQe[2:0], the second round DQd[2:0], the second round DQe[2:0], and DQf[2:0] to output the output digital value DOUT[15:0] of the A / D conversion circuit 100.

[0021] Figure 2 is an example timing chart explaining the operation of the pipeline stage and cyclic A / D converter. The phases of the clock signals CKA and CKB are synchronized at the falling edge. "Samp." means sampling operation, and "FB" means calculation and hold operation. The calculation and hold operation is the operation in which the D / A converter included in the pipeline stage D / A converts the digital value and calculates the difference between the sampling voltage and the D / A conversion result.

[0022] Pipeline stages 110a and 110c perform sampling operations while clock signal CKA is at high level and perform calculation and hold operations while clock signal CKA is at low level. Pipeline stage 110b performs sampling operations while clock signal CKA is at low level and performs calculation and hold operations while clock signal CKA is at high level.

[0023] The cyclic A / D converter 120 starts the first round of A / D conversion while the pipeline stage 110c is performing calculations and holding, and starts the second round of A / D conversion while the pipeline stage 110c is performing sampling operations.

[0024] The first stage 120d of the cyclic A / D converter 120 performs sampling while the clock signal CKB is at high level and performs calculation and holding while the clock signal CKB is at low level. The second stage 120e performs sampling while the clock signal CKB is at low level and performs calculation and holding while the clock signal CKB is at high level.

[0025] Hereinafter, the pipeline stage 110b two stages before the cyclic A / D converter 120 will be referred to as the first pipeline stage, and the pipeline stage 110c one stage before the cyclic A / D converter 120 will be referred to as the second pipeline stage. As described with reference to FIG. 1, the first pipeline stage 110b outputs a 2.5-bit digital value DQb[2:0], and the second pipeline stage 110c outputs a 1.5-bit digital value DQc[1:0], which is less than 2.5 bits. This allows the first stage 120d of the cyclic A / D converter 120 to sample the output voltage of the second pipeline stage 110c with high accuracy. This point will be described using FIG. 2 and other figures.

[0026] As shown in FIG. 2, the first pipeline stage 110b performs a sampling operation during a first period TA1. During a second period TA2 following the first period TA1, the first pipeline stage 110b performs an arithmetic and hold operation, and the second pipeline stage 110c performs a sampling operation. During a third period TA3 following the second period TA2, the second pipeline stage 110c performs an arithmetic and hold operation. Then, during the third period TA3, the first stage 120d of the cyclic A / D converter 120 performs a sampling operation. More specifically, the sampling period TB1 of the first stage 120d corresponds to the latter half of the third period TA3 divided by the clock signal CKB. The sampling period TB1 of the first stage 120d is shorter than the first period TA1, which is the sampling period of the first pipeline stage 110b, and the second period TA2, which is the sampling period of the second pipeline stage 110c.

[0027] In order for the first stage 120d to perform sampling with high accuracy, the output voltage of the second pipeline stage 110c needs to settle sufficiently by the end of the sampling period TB1, during which the sampling voltage of the first stage 120d is determined. According to this embodiment, the number of bits of the second pipeline stage 110c is small, which improves the settling accuracy.

[0028] Specifically, as will be described later with reference to Fig. 10, the first pipeline stage 110b includes a D / A converter MDACb that performs D / A conversion by switching capacitors. The D / A converter MDACb includes three positive and negative capacitor circuits CSMP1b to CSMP3b and three negative capacitor circuits CPMN1b to CSMN3b corresponding to 2.5 bits. Each capacitor circuit includes a capacitor CM shown in Fig. 7.

[0029] 11, the second pipeline stage 110c includes a D / A converter MDACc that performs D / A conversion by switching capacitors. The D / A converter MDACc includes one positive and one negative capacitor circuit CSMPc and CPMNc corresponding to 1.5 bits. Each capacitor circuit includes a capacitor CM shown in FIG. 7.

[0030] Each capacitor circuit acts as a load on the feedback path of the D / A converter during calculation and hold operations. The greater the number of bits in a pipeline stage, the greater the number of capacitor circuits, and therefore the greater the load on the feedback path. Therefore, the greater the number of bits in a pipeline stage, the lower the settling accuracy. According to this embodiment, the second pipeline stage 110c, which is located before the cyclic A / D converter 120, has a smaller number of bits, so the settling accuracy is higher, and the first stage 120d can sample with high accuracy even with a short sampling period TB1.

[0031] 3 shows a second configuration example of the A / D conversion circuit 100. The A / D conversion circuit 100 includes a first pipeline stage 110b, a second pipeline stage 110c, a successive approximation type A / D converter 140, and an adder 190.

[0032] The first pipeline stage 110b samples the input voltage VIN to the A / D conversion circuit 100, A / D converts the sampled voltage, and outputs the A / D conversion result as a digital value DQb[3:0]. The first pipeline stage 110b multiplies the difference between the sampled voltage and the voltage obtained by D / A converting the digital value DQb[3:0] by a gain and outputs the result. The digital value DQb[3:0] has a range of 3.5 bits. That is, the digital value DQb[3:0] can take on 15 values: 0000b, 0001b, 0010b, . . . , 1100b, 1101b, and 1110b.

[0033] The second pipeline stage 110c samples the output voltage of the first pipeline stage 110b, A / D converts the sampled voltage, and outputs the A / D conversion result as a digital value DQc[2:0]. The second pipeline stage 110c multiplies the difference between the sampled voltage and the voltage obtained by D / A converting the digital value DQc[2:0] by a gain and outputs the result. The digital value DQc[2:0] has a range of 2.5 bits, which is smaller than the 3.5-bit range of the digital value DQb[3:0] of the previous stage.

[0034] The first pipeline stage 110b and the second pipeline stage 110c perform A / D conversion using the clock signal CKA as an operating clock signal, i.e., the first pipeline stage 110b and the second pipeline stage 110c perform one A / D conversion per cycle of the clock signal CKA.

[0035] The successive approximation type A / D converter 140 samples the output voltage of the second pipeline stage 110c, A / D converts the sampled voltage by performing successive approximation on the sampled voltage, and outputs the result of the A / D conversion as a digital value DQg[6:0].

[0036] The successive approximation type A / D converter 140 operates using a clock signal CKD as an operating clock. The successive approximation type A / D converter 140 performs one A / D conversion by successive approximation based on the clock signal CKD per cycle of the clock signal CKA. The frequency of the clock signal CKD is higher than the frequency of the clock signal CKA so that successive approximation of the number of bits of the successive approximation type A / D converter 140 can be performed.

[0037] The adder 190 adds the digital values ​​DQb[3:0], DQc[2:0], and DQg[6:0] together to output the output digital value DOUT[11:0] of the A / D conversion circuit 100.

[0038] Figure 4 is an example timing chart explaining the operation of the pipeline stage and successive approximation A / D converter. Here, the frequency of the clock signal CKD is assumed to be 16 times the frequency of the clock signal CKA. "Samp." means sampling operation, "FB" means operation and hold operation, and "SAR" means successive approximation.

[0039] The first pipeline stage 110b performs a sampling operation while the clock signal CKA is at a low level, and performs an arithmetic and hold operation while the clock signal CKA is at a high level. The second pipeline stage 110c performs a sampling operation while the clock signal CKA is at a high level, and performs an arithmetic and hold operation while the clock signal CKA is at a low level.

[0040] The successive approximation A / D converter 140 starts a sampling operation during the period when the second pipeline stage 110c is performing calculations and holding, and performs successive approximation after the sampling operation is completed. The sampling operation is performed, for example, over a period of multiple clocks of the clock signal CKD. In the example of FIG. 4, the period when the second pipeline stage 110c is performing calculations and holding corresponds to eight clocks of the clock signal CKD. FIG. 4 shows an example in which the sampling operation is performed during the latter four clocks of the eight clocks. The successive approximation is performed one bit at a time per clock of the clock signal CKA, starting from the MSB side of the digital value DQg[6:0].

[0041] As explained in Fig. 3, the first pipeline stage 110b outputs a 3.5-bit digital value DQb[3:0], and the second pipeline stage 110c outputs a 2.5-bit digital value DQc[2:0], which is less than 3.5 bits. This allows the successive approximation type A / D converter 140 to sample the output voltage of the second pipeline stage 110c with high precision. The reason for this is the same as that explained in Fig. 2 of the first configuration example.

[0042] 5 shows a detailed configuration example of a successive approximation type A / D converter 140. The successive approximation type A / D converter 140 includes a sample-and-hold circuit 141, a D / A converter 142, a comparator 143, and a control circuit 144.

[0043] The sample-and-hold circuit 141 samples and holds the voltage VIS input to the successive approximation A / D converter 140 and outputs the held voltage VSH. The voltage VIS corresponds to the output voltage of the second pipeline stage 110c in FIG. 3. The D / A converter 142 D / A converts the successive approximation register value DREG from the control circuit 144 and outputs the D / A conversion result as a voltage VDAC. The comparator 143 compares the voltage VSH with the voltage VDAC and outputs the comparison result as a signal CPQ. The control circuit 144 updates the successive approximation register value DREG based on the signal CPQ and outputs the updated successive approximation register value DREG to the D / A converter 142. The control circuit 144 determines the successive approximation register value DREG bit by bit, starting from the MSB side down to the LSB, and outputs the successive approximation register value DREG determined up to the LSB as a digital value DQ. The digital value DQ corresponds to the digital value DQg[6:0] in FIG.

[0044] The configuration of the successive approximation A / D converter 140 is not limited to that shown in FIG. 5. For example, the D / A converter 142 may be a capacitor DAC and include the function of the sample-and-hold circuit 141. In this case, the capacitor DAC may sample and hold the voltage VIN and output the difference between the held voltage and a voltage obtained by D / A converting the successive approximation register value DREG. The comparator may compare the output voltage of the capacitor DAC with a reference voltage.

[0045] In this embodiment, the A / D conversion circuit 100 includes a first pipeline stage 110b, a second pipeline stage 110c, and an A / D converter. The first pipeline stage 110b performs A / D conversion based on an input signal to output a first digital value of x bits. The second pipeline stage 110c performs A / D conversion based on a first analog output signal of the first pipeline stage 110b to output a second digital value of y bits, which is smaller than the x bits. The A / D converter samples the second analog output signal of the second pipeline stage 110c during a sampling period that is shorter than the sampling period of the first pipeline stage 110b and the second pipeline stage 110c, performs A / D conversion based on the sampling result, and outputs a third digital value.

[0046] According to this embodiment, the second pipeline stage 110c outputs a second digital value of y bits, which is smaller than the x bits of the first digital value output by the first pipeline stage 110b. This reduces the load on the feedback path when the second pipeline stage 110c performs the calculation and hold operation, allowing the second pipeline stage 110c to quickly settle the sampling voltage of the A / D converter at the subsequent stage. This enables accurate sampling even when the A / D converter at the subsequent stage of the second pipeline stage 110c performs sampling in a short sampling period.

[0047] 1 and 3, the "input signal" corresponds to the signal based on the input voltage VIN. The "first analog output signal" corresponds to the signal based on the output voltage of the first pipeline stage 110b, and the "second analog output signal" corresponds to the signal based on the output voltage of the second pipeline stage 110c. The "first digital value" corresponds to the digital value DQb[2:0], and the "second digital value" corresponds to the digital value DQc[1:0]. In the example of FIG. 1, the "A / D converter" corresponds to the cyclic A / D converter 120, and the "third digital value" corresponds to the digital values ​​DQd[2:0] and DQe[2:0]. In the example of FIG. 3, the "A / D converter" corresponds to the successive approximation A / D converter 140, and the "third digital value" corresponds to the digital value DQg[6:0].

[0048] In this embodiment, the first pipeline stage 110b may perform a sampling operation during the first period TA1. During a second period TA2 after the first period TA1, the first pipeline stage 110b may perform an arithmetic and hold operation, and the second pipeline stage 110c may perform a sampling operation. During a third period TA3 after the second period TA2, the second pipeline stage 110c may perform an arithmetic and hold operation, and the A / D converter may perform a sampling operation.

[0049] According to this embodiment, in the second period, the second pipeline stage 110c can sample the first analog output signal output by the first pipeline stage 110b after performing an arithmetic and hold operation. In the third period, the A / D converter can sample the second analog output signal output by the second pipeline stage 110c after performing an arithmetic and hold operation. As described above, although the sampling period of the A / D converter is short, the small number of bits of the second pipeline stage 110c enables accurate sampling.

[0050] 1, the A / D converter may be a cyclic A / D converter 120. In this embodiment, during a period in which the first pipeline stage 110b and the second pipeline stage 110c perform one A / D conversion, the cyclic A / D converter 120 may perform a first round of A / D conversion in which the second analog output signal is A / D converted, and a second round of A / D conversion in which the analog output signal output by the cyclic A / D converter after the first round of A / D conversion is A / D converted again.

[0051] According to this embodiment, the cyclic A / D converter 120 performs multiple cyclic A / D conversions during the time it takes for a pipeline stage to perform one A / D conversion. Because the A / D conversion rate of the cyclic A / D converter 120 is thus higher than the A / D conversion rate of the pipeline stage, the sampling period of the cyclic A / D converter 120 is shorter than the sampling period of the pipeline stage. According to this embodiment, even in such a case, the cyclic A / D converter 120 can perform sampling with high accuracy.

[0052] 3, the A / D converter may be a successive approximation type A / D converter 140. In this embodiment, the successive approximation type A / D converter 140 may perform a sampling operation of sampling the second analog output signal and a successive approximation operation on the sampled second analog output signal during a period in which the first pipeline stage 110b and the second pipeline stage 110c perform one A / D conversion.

[0053] The successive approximation A / D converter 140 performs successive approximation on a bit-by-bit basis, and therefore the sampling period tends to be short in order to ensure the period for the successive approximation operation. According to this embodiment, even if the sampling period of the successive approximation A / D converter 140 is shortened, the successive approximation A / D converter 140 can perform sampling with high accuracy.

[0054] In this embodiment, x bits may be n+0.5 bits, where n is an integer equal to or greater than 1. y bits may be m+0.5 bits, where m is an integer equal to or greater than 1 and smaller than n.

[0055] According to this embodiment, the first pipeline stage 110b performs n+0.5-bit A / D conversion. The second pipeline stage 110c, which is located before the A / D converter, performs m+0.5-bit A / D conversion, which is smaller than n+0.5 bits. This improves the sampling accuracy of the A / D converter, as described above.

[0056] In this embodiment, the third digital value may be z bits, which is greater than x bits and y bits.

[0057] According to this embodiment, the A / D converter performs A / D conversion with a bit number greater than the bit number of the first pipeline stage 110b and the second pipeline stage 110c.

[0058] In this embodiment, the A / D conversion circuit 100 may also include a flash A / D converter 130 provided in the subsequent stage of the A / D converter.

[0059] According to this embodiment, by providing a flash A / D converter 130 in the subsequent stage, it is possible to ensure the conversion speed while increasing the overall number of conversion bits in the A / D conversion circuit 100. The conversion accuracy on the MSB side can be ensured by the preceding pipeline stage, while the conversion speed on the LSB side can be improved by the flash A / D converter 130 in the subsequent stage.

[0060] In this embodiment, the A / D conversion circuit 100 may also include an adder 190. The adder 190 may output an output digital value of the A / D conversion circuit 100 based on the first digital value, the second digital value, and the third digital value.

[0061] According to this embodiment, the output digital value of the A / D conversion circuit 100 can be calculated from the digital values ​​output by the first pipeline stage 110b, the second pipeline stage 110c, and the A / D converter. Note that the "output digital value" corresponds to the output digital value DOUT[15:0] in FIG. 1 or the output digital value DOUT[11:0] in FIG. 3.

[0062] 2. Detailed configuration example of pipeline stage, cyclic A / D converter, and adder An example of detailed configurations of the pipeline stages 110a to 110c, the cyclic A / D converter 120, and the adder 190 in FIG. 1 will be described.

[0063] 6 shows a detailed configuration example of the first pipeline stage 110a. The pipeline stage 110a includes a D / A converter MDACa, a sub A / D converter 111a, and an encoder 112a.

[0064] A positive input voltage VINP and a negative input voltage VINN are input to the pipeline stage 110a. The difference between the input voltages VINP and VINN corresponds to the input voltage VIN of the A / D conversion circuit 100 in FIG.

[0065] The sub-A / D converter 111a performs A / D conversion on the differential voltage (VINP-VINN) by comparison using a reference voltage VR, and outputs the A / D conversion result as a digital value DQa[2:0]. +VR to -VR corresponds to the full scale of the differential voltage (VINP-VINN). The sub-A / D converter 111a performs A / D conversion according to the following equation (1). The differential voltage (VINP-VINN) is represented as VIN. -VR≦VIN≦-5 / 8×VR:DQa[2:0]=000b, -5 / 8×VR <VIN≦-3 / 8×VR:DQa[2:0]=001b, -3 / 8×VR <VIN≦-1 / 8×VR:DQa[2:0]=010b, -1 / 8×VR <VIN≦+1 / 8×VR:DQa[2:0]=011b, +1 / 8×VR <VIN≦+3 / 8×VR:DQa[2:0]=100b, +3 / 8×VR <VIN≦+5 / 8×VR:DQa[2:0]=101b, +5 / 8×VR <VIN≦+VR :DQa[2:0]=110b ···(1)

[0066] The encoder 112a encodes the digital value DQa[2:0] into a control signal SWCNT. The control signal SWCNT is a signal that controls a group of switches SMG, which will be described later with reference to Fig. 7. Control of the switches SMB1 to SMB3 will be described later with reference to Fig. 9.

[0067] The D / A converter MDACa includes positive-side capacitor circuits CSMP1a, CSMP2a, and CSMP3a, negative-side capacitor circuits CSMN1a, CSMN2a, and CSMN3a, switches SFP1a, SFP2a, SFN1a, SFN2a, SSPa, and SSNa, capacitors CFPa and CFNa, and an operational amplifier OPa.

[0068] The capacitor circuits CSMP1a, CSMP2a, and CSMP3a are connected in parallel between the node of the input voltage VINP and a node NQPa connected to the positive input terminal of the operational amplifier OPa. The switch SFP1a and capacitor CFPa are connected in series between the node of the input voltage VINP and the node NQPa. The switch SFP2a is connected between the node between the switch SFP1a and the capacitor CFPa and the node of the positive output voltage VQPa. The switch SSPa is connected between the node NQPa and a ground node. The negative output terminal of the operational amplifier OPa is connected to the node of the positive output voltage VQPa. Note that since the D / A converter MDACa is a non-inverting amplifier circuit with respect to VIN, the output voltage VQPa is defined as positive.

[0069] The capacitor circuits CSMN1a, CSMN2a, and CSMN3a are arranged in parallel between the node of the input voltage VINN and a node NQNa connected to the negative input terminal of the operational amplifier OPa. The switch SFN1a and the capacitor CFNa are connected in series between the node of the input voltage VINN and the node NQNa. The switch SFN2a is connected between the node between the switch SFN1a and the capacitor CFNa and the node of the negative output voltage VQNa. The switch SSNa is connected between the node NQNa and a ground node. The positive output terminal of the operational amplifier OPa is connected to the node of the negative output voltage VQNa.

[0070] Fig. 7 shows a detailed configuration example of a capacitor circuit. The capacitor circuit CSM shown in Fig. 7 corresponds to each of the capacitor circuits CSMP1a, CSMP2a, CSMP3a, CSMN1a, CSMN2a, and CSMN3a in Fig. 6. The capacitor circuit CSM includes a capacitor CM, a switch SMA, and a switch group SMG. The switch group SMG includes switches SMB1, SMB2, and SMB3.

[0071] One end of switch SMA is connected to node NIN, and the other end is connected to node N1. One end of capacitor CM is connected to node N1, and the other end is connected to node NQ. Corresponding to FIG. 6, node NIN is the node of input voltage VINP, and node NQ is node NQPa. Alternatively, node NIN is the node of input voltage VINN, and node NQ is node NQNa.

[0072] One end of switch SMB1 is connected to a node of a positive reference voltage +VR, and the other end is connected to node N1. One end of switch SMB2 is connected to a node of 0V, which is the ground voltage, and the other end is connected to node N1. One end of switch SMB3 is connected to a node of a negative reference voltage -VR, and the other end is connected to node N1. Each of switches SMB1, SMB2, and SMB3 is controlled to be on or off by a control signal SWCNT.

[0073] 8 is a diagram illustrating the operation of the first pipeline stage. XCKA is the logically inverted signal of clock signal CKA. Circles indicate whether each element operates in response to clock signal CKA or XCKA.

[0074] When the clock signal CKA is at a high level, the pipeline stage 110a performs a sampling operation. Specifically, the switches SFP1a, SFN1a, SMA, SSPa, and SSNa are on. The switches SMB1, SMB2, and SMB3 of the switch group SMG are all off. The switches SFP2a and SFN2a are off. As a result, the input voltage VINP is sampled by the capacitors CM and CFPa of the capacitor circuits CSMP1a, CSMP2a, and CSMP3a. Also, the input voltage VINN is sampled by the capacitors CM and CFNa of the capacitor circuits CSMN1a, CSMN2a, and CSMN3a.

[0075] When the clock signal CKA is at a low level, the pipeline stage 110a performs an operation and hold operation. Specifically, the switches SFP1a, SFN1a, SMA, SSPa, and SSNa are off. The encoder 112a encodes the digital value DQa[2:0] and outputs the control signal SWCNT, and the switches SMB1, SMB2, and SMB3 of the switch group SMG are each controlled by the control signal SWCNT. The switches SFP2a and SFN2a are on. This forms a feedback path for the operational amplifier OPa via the capacitors CFPa and CFNa.

[0076] FIG. 9 is a diagram illustrating the operation of the encoder and switch group during the calculation and hold operations of a 2.5-bit pipeline stage. In FIG. 9, the "DQ[2:0]" column indicates each value of the digital value DQa[2:0]. The "CSMP1" column indicates the operation of the switch group SMG of the capacitor circuit CSMP1a for each value of the digital value DQa[2:0]. The same applies to the "CSMP2," "CSMP3," "CSMN1," "CSMN2," and "CSMN3" columns. "+VR" indicates that switch SMB1 is on and switches SMB2 and SMB3 are off. "0" indicates that switch SMB2 is on and switches SMB1 and SMB3 are off. "-VR" indicates that switch SMB3 is on and switches SMB1 and SMB2 are off.

[0077] By performing the above-described operations, the pipeline stage 110a outputs the output voltage VQa=VQPa-VQNa of the following equation (2) during the calculation and hold period: The capacitances of the capacitors CM, CFPa, and CFNa are the same. VQa = 4 × VIN - VDAC (2)

[0078] The voltage VDAC is the result of D / A conversion of the digital value DQa[2:0] by the D / A converter MDACa, and is as shown in the following equation (3). DQa[2:0]=000b:VDAC=0, DQa[2:0]=001b:VDAC=-VR, DQa[2:0]=010b:VDAC=-2×VR, DQa[2:0]=011b:VDAC=-3×VR, DQa[2:0]=100b:VDAC=-4×VR, DQa[2:0]=101b:VDAC=-5×VR, DQa[2:0]=110b:VDAC=-6×VR (3)

[0079] 10 shows a detailed configuration example of the second pipeline stage 110b. The pipeline stage 110b includes a D / A converter MDACb, a sub A / D converter 111b, and an encoder 112b.

[0080] The positive output voltage VQPa and the negative output voltage VQNa from the pipeline stage 110a are input to the pipeline stage 110b.

[0081] The sub A / D converter 111b A / D converts the differential voltage (VQPa-VQNa) by comparison using a reference voltage VR, and outputs the A / D conversion result as a digital value DQb[2:0]. Details of the A / D conversion can be obtained by replacing VIN with VQa=VQPa-VQNa and DQa[2:0] with DQb[2:0] in the above equation (1).

[0082] The encoder 112b encodes the digital value DQb[2:0] into the control signal SWCNT in the same manner as the encoder 112a in the pipeline stage 110a.

[0083] The D / A converter MDACb includes positive-side capacitor circuits CSMP1b, CSMP2b, and CSMP3b, negative-side capacitor circuits CSMN1b, CSMN2b, and CSMN3b, switches SFP1b, SFP2b, SFN1b, SFN2b, SSPb, and SSNb, and capacitors CFPb and CFNb.

[0084] The capacitor circuits CSMP1b, CSMP2b, and CSMP3b are provided in parallel between the node of the output voltage VQPa and the node NQPb. The switch SFP1b and the capacitor CFPb are connected in series between the node of the positive output voltage VQPa from the pipeline stage 110a and the node NQPb. The switch SFP2b is connected between the node between the switch SFP1b and the capacitor CFPb and the node of the positive output voltage VQPc. The switch SSPb is connected between the node NQPb and the ground node.

[0085] Capacitor circuits CSMN1b, CSMN2b, and CSMN3b are provided in parallel between the node of the output voltage VQNa and node NQNb. Switch SFN1b and capacitor CFNb are connected in series between the node of the positive output voltage VQNa from pipeline stage 110a and node NQNb. Switch SFN2b is connected between the node between switch SFN1b and capacitor CFNb and the node of the negative output voltage VQNc. Switch SSNb is connected between node NQNb and a ground node.

[0086] An example of the configuration of each of the capacitor circuits CSMP1b, CSMP2b, CSMP3b, CSMN1b, CSMN2b, and CSMN3b is as described with reference to FIG.

[0087] 11 shows a detailed configuration example of the third pipeline stage. The pipeline stage 110c includes a D / A converter MDACc, a sub A / D converter 111c, and an encoder 112c.

[0088] A positive output voltage VQPc and a negative output voltage VQNc are input to the pipeline stage 110c. The pipeline stages 110b and 110c share an operational amplifier OPc, and in the sampling operation of the pipeline stage 110c, the output voltages VQPc and VQNc in the operation and hold operation of the pipeline stage 110b are input to the pipeline stage 110c.

[0089] The sub-A / D converter 111c A / D converts the differential voltage (VQPc-VQNc) by comparison using a reference voltage VR, and outputs the A / D conversion result as a digital value DQc[2:0]. +VR to -VR corresponds to the full scale of the differential voltage (VQPc-VQNc). The sub-A / D converter 111c performs A / D conversion according to the following equation (4). The differential voltage (VQPc-VQNc) output by the pipeline stage 110b in the calculation and hold operations is denoted as VQb. -VR≦VQb≦-1 / 4×VR:DQc[1:0]=00b, -1 / 4×VR <VQb≦+1 / 4×VR:DQc[1:0]=01b, +1 / 4×VR <VQb≦+VR :DQc[1:0]=10b ···(4)

[0090] The encoder 112c encodes the digital value DQc[1:0] into a control signal SWCNT. Control of the switch group SMG by the control signal SWCNT will be described later with reference to FIG.

[0091] The D / A converter MDACc includes a positive-side capacitor circuit CSMPc, a negative-side capacitor circuit CSMNc, switches SFP1c, SFP2c, SFN1c, SFN2c, SSPc, SSNc, SP1c, SP2c, SN1c, and SN2c, capacitors CFPc and CFNc, and an operational amplifier OPc.

[0092] The capacitor circuit CSMPc is provided between the node of the output voltage VQPc and the node NQPc. The switch SFP1c and the capacitor CFPc are connected in series between the node of the output voltage VQPc and the node NQPc. The switch SFP2c is connected between the node between the switch SFP1c and the capacitor CFPc and the node of the positive output voltage VQPc. The switch SSPc is connected between the node NQPc and a ground node. The negative output terminal of the operational amplifier OPc is connected to the node of the positive output voltage VQPc. One end of the switch SP1c is connected to the node NQPb of the pipeline stage 110b, and the other end is connected to the positive input terminal of the operational amplifier OPc. One end of the switch SP2c is connected to the node NQPc, and the other end is connected to the positive input terminal of the operational amplifier OPc.

[0093] The capacitor circuit CSMNc is provided between the node of the output voltage VQNc and the node NQNc. The switch SFN1c and the capacitor CFNc are connected in series between the node of the output voltage VQNc and the node NQNc. The switch SFN2c is connected between the node between the switch SFN1c and the capacitor CFNc and the node of the negative output voltage VQNc. The switch SSNc is connected between the node NQNc and a ground node. The positive output terminal of the operational amplifier OPc is connected to the node of the negative output voltage VQNc. One end of the switch SN1c is connected to the node NQNb of the pipeline stage 110b, and the other end is connected to the negative input terminal of the operational amplifier OPc. One end of the switch SN2c is connected to the node NQNc, and the other end is connected to the negative input terminal of the operational amplifier OPc.

[0094] An example of the configuration of each of the capacitor circuits CSMPc and CSMNc is as described with reference to FIG.

[0095] FIG. 10 is a diagram illustrating the operation of the second and third pipeline stages.

[0096] When the clock signal CKA is at a low level, the pipeline stage 110b performs a sampling operation. Specifically, the switches SFP1b, SFN1b, SMA, SSPb, and SSNb of the pipeline stage 110b are on. The switches SMB1, SMB2, and SMB3 of the switch group SMG are all off. The switches SFP2b and SFN2b are off. Furthermore, the switches SP1c and SN1c of the pipeline stage 110c are off. As a result, the output voltage VQPa from the pipeline stage 110a is sampled onto the capacitors CM and CFPb of the capacitor circuits CSMP1b, CSMP2b, and CSMP3b. Furthermore, the output voltage VQNa from the pipeline stage 110a is sampled onto the capacitors CM and CFNb of the capacitor circuits CSMN1b, CSMN2b, and CSMN3b.

[0097] When the clock signal CKA is at a high level, the pipeline stage 110b performs the operation and hold operation. Specifically, the switches SFP1b, SFN1b, SMA, SSPb, and SSNb are off. The encoder 112b encodes the digital value DQb[2:0] and outputs the control signal SWCNT. The switches SMB1, SMB2, and SMB3 of the switch group SMG are controlled by the control signal SWCNT. The switches SFP2b and SFN2b are on. Furthermore, the switches SP1c and SN1c of the pipeline stage 110c are on. This forms a feedback path for the operational amplifier OPc via the capacitors CFPb and CFNb. At this time, the operational amplifier OPc functions as an amplifier for performing the operation and hold operation of the pipeline stage 110b. The output voltages VQPc and VQNc of the operational amplifier OPc are the output voltages during the operation and hold operation of the pipeline stage 110b.

[0098] Furthermore, when the clock signal CKA is at a high level, the pipeline stage 110c performs a sampling operation. Specifically, the switches SFP1c, SFN1c, SMA, SSPc, and SSNc of the pipeline stage 110c are on. The switches SMB1, SMB2, and SMB3 of the switch group SMG are all off. The switches SFP2c and SFN2c are off. Furthermore, the switches SP2c and SN2c are off. As a result, the output voltage VQPc during the calculation and hold operation of the pipeline stage 110b is sampled by the capacitors CM and CFPc of the capacitor circuit CSMPc. Furthermore, the output voltage VQNc during the calculation and hold operation of the pipeline stage 110b is sampled by the capacitors CM and CFNc of the capacitor circuit CSMNc.

[0099] When the clock signal CKA is at a low level, the pipeline stage 110c performs the operation and hold operation. Specifically, the switches SFP1c, SFN1c, SMA, SSPc, and SSNc are off. The encoder 112c encodes the digital value DQc[1:0] and outputs the control signal SWCNT. The switches SMB1, SMB2, and SMB3 of the switch group SMG are controlled by the control signal SWCNT. The switches SFP2c and SFN2c are on. In addition, the switches SP2c and SN2c are on. This forms a feedback path for the operational amplifier OPc via the capacitors CFPc and CFNc. At this time, the operational amplifier OPc functions as an amplifier for performing the operation and hold operation of the pipeline stage 110c. The output voltages VQPc and VQNc of the operational amplifier OPc are the output voltages during the operation and hold operation of the pipeline stage 110c.

[0100] FIG. 13 is a diagram illustrating the operation of the encoder and switch group in the calculation and hold operation of a 1.5-bit pipeline stage. In FIG. 13, the "DQ[1:0]" column indicates each value of the digital value DQc[1:0]. The "CSMP" column indicates the operation of the switch group SMG of the capacitor circuit CSMPc for each value of the digital value DQc[1:0]. The same applies to the "CSMN" column. The meanings of "+VR," "0," and "-VR" are as explained in FIG. 9.

[0101] By performing the above-described operations, the pipeline stage 110b outputs the output voltage VQb=VQPc-VQNc of the following equation (5) during the calculation and hold period. The capacitances of the capacitors CM, CFPb, and CFNb are the same. The voltage VDAC can be obtained by replacing DQa[2:0] with DQb[2:0] in the above equation (3). VQb = 4 × VQa - VDAC (5)

[0102] Furthermore, by performing the above-described operations, the pipeline stage 110c outputs the output voltage VQc=VQPc-VQNc of the following equation (6) during the calculation and hold period. The capacitances of the capacitors CM, CFPc, and CFNc are the same. VQc = 2 × VQb - VDAC (6)

[0103] The voltage VDAC is the result of D / A conversion of the digital value DQc[1:0] by the D / A converter MDACc, and is as shown in the following equation (7). DQc[1:0]=00b:VDAC=0, DQc[1:0]=01b:VDAC=-VR, DQc[1:0]=10b:VDAC=-2×VR (7)

[0104] Although the above example shows that the pipeline stages 110b and 110c share an amplifier, each of the pipeline stages 110b and 110c may be provided with an operational amplifier.

[0105] 14 shows a detailed configuration example of the first stage of the cyclic A / D converter. The first stage 120d includes a D / A converter MDACd, a sub-A / D converter 111d, an encoder 112d, and switches SP1d, SP2d, SN1d, and SN2d.

[0106] The positive output voltage VQPc and the negative output voltage VQNc of the pipeline stage 110c are input to the first stage 120d.

[0107] One end of switch SP2d is connected to the node of output voltage VQPc from pipeline stage 110c, and the other end is connected to node NIPd. One end of switch SP1d is connected to the node of output voltage VQPe from operational amplifier OPe of second stage 120e, and the other end is connected to node NIPd. One end of switch SN2d is connected to the node of output voltage VQNc from pipeline stage 110c, and the other end is connected to node NINd. One end of switch SN1d is connected to the node of output voltage VQNe from operational amplifier OPe of second stage 120e, and the other end is connected to node NINd.

[0108] The differential voltage between nodes NIPd and NINd is denoted as VNId. The sub-A / D converter 111d A / D converts the differential voltage VNId by comparison using a reference voltage VR, and outputs the A / D conversion result as a digital value DQd[2:0]. Details of the A / D conversion can be obtained by replacing VIN with VNId and DQa[2:0] with DQd[2:0] in the above equation (1).

[0109] The encoder 112d encodes the digital value DQd[2:0] into the control signal SWCNT in the same manner as the encoder 112a in the pipeline stage 110a.

[0110] The D / A converter MDACd includes positive-side capacitor circuits CSMP1d, CSMP2d, and CSMP3d, negative-side capacitor circuits CSMN1d, CSMN2d, and CSMN3d, switches SFP1d, SFP2d, SFN1d, SFN2d, SSPd, and SSNd, and capacitors CFPd and CFNd.

[0111] Capacitor circuits CSMP1d, CSMP2d, and CSMP3d are arranged in parallel between node NIPd and node NQPd. Switch SFP1d and capacitor CFPd are connected in series between node NIPd and node NQPd. Switch SFP2d is connected between the node between switch SFP1d and capacitor CFPd and the node of the positive output voltage VQPe. Switch SSPd is connected between node NQPd and a ground node.

[0112] Capacitor circuits CSMN1d, CSMN2d, and CSMN3d are arranged in parallel between node NINd and node NQNd. Switch SFN1d and capacitor CFNd are connected in series between node NINd and node NQNd. Switch SFN2d is connected between a node between switch SFN1d and capacitor CFNd and a node of a negative output voltage VQNe. Switch SSNd is connected between node NQNd and a ground node.

[0113] An example of the configuration of each of the capacitor circuits CSMP1d, CSMP2d, CSMP3d, CSMN1d, CSMN2d, and CSMN3d is as described with reference to FIG.

[0114] 15 shows a detailed configuration example of the second stage of the cyclic A / D converter. The second stage 120e includes a D / A converter MDACe, a sub A / D converter 111e, and an encoder 112e.

[0115] The positive output voltage VQPe and the negative output voltage VQNe are input to the second stage 120e. The first stage 120d and the second stage 120e share the operational amplifier OPe, and in the sampling operation of the second stage 120e, the output voltages VQPe and VQNe in the operation and hold operation of the first stage 120d are input to the second stage 120e.

[0116] The sub-A / D converter 111e performs A / D conversion on the differential voltage (VQPe-VQNe) by comparison using a reference voltage VR, and outputs the result of the A / D conversion as a digital value DQe[2:0]. The differential voltage (VQPe-VQNe) output by the first stage 120d in the calculation and hold operation is represented as VQd. Details of the A / D conversion performed by the sub-A / D converter 111e can be obtained by replacing VIN with VQd and DQa[2:0] with DQe[2:0] in the above equation (1).

[0117] The encoder 112e encodes the digital value DQe[2:0] into the control signal SWCNT in the same manner as the encoder 112a in the pipeline stage 110a.

[0118] The D / A converter MDACe includes positive-side capacitor circuits CSMP1e, CSMP2e, and CSMP3e, negative-side capacitor circuits CSMN1e, CSMN2e, and CSMN3e, switches SFP1e, SFP2e, SFN1e, SFN2e, SSPe, SSNe, SP1e, SP2e, SN1e, and SN2e, capacitors CFPe and CFNe, and an operational amplifier OPe.

[0119] The capacitor circuits CSMP1e, CSMP2e, and CSMP3e are connected in parallel between the node of the output voltage VQPe and the node NQPe. The switch SFP1e and the capacitor CFPe are connected in series between the node of the output voltage VQPe and the node NQPe. The switch SFP2e is connected between the node between the switch SFP1e and the capacitor CFPe and the node of the positive output voltage VQPe. The switch SSPe is connected between the node NQPe and a ground node. The negative output terminal of the operational amplifier OPe is connected to the node of the positive output voltage VQPe. One end of the switch SP1e is connected to the node NQPd of the first stage 120d, and the other end is connected to the positive input terminal of the operational amplifier OPd. One end of the switch SP2d is connected to the node NQPe, and the other end is connected to the positive input terminal of the operational amplifier OPe.

[0120] The capacitor circuits CSMN1e, CSMN2e, and CSMN3e are connected in parallel between the node of the output voltage VQNe and the node NQNe. The switch SFN1e and the capacitor CFNe are connected in series between the node of the output voltage VQNe and the node NQNe. The switch SFN2e is connected between the node between the switch SFN1e and the capacitor CFNe and the node of the negative output voltage VQNe. The switch SSNe is connected between the node NQNe and a ground node. The positive output terminal of the operational amplifier OPe is connected to the node of the negative output voltage VQNe. One end of the switch SN1e is connected to the node NQNd of the first stage 120d, and the other end is connected to the negative input terminal of the operational amplifier OPd. One end of the switch SN2d is connected to the node NQNe, and the other end is connected to the negative input terminal of the operational amplifier OPe.

[0121] An example of the configuration of each of the capacitor circuits CSMP1e, CSMP2e, CSMP3e, CSMN1e, CSMN2e, and CSMN3e is as described with reference to FIG.

[0122] FIG. 16 is a diagram illustrating the operation of the first and second stages of the cyclic A / D converter.

[0123] When the clock signal CKA is at a low level, switches SP1d and SN1d are off, switches SP2d and SN2d are on, and the pipeline stage 110c is performing an arithmetic and hold operation. The voltages at nodes NIPd and NINd of the first stage 120d are the output voltages VQPc and VQNc from the arithmetic and hold operation of the pipeline stage 110c. That is, when the clock signal CKA is at a low level, the cyclic A / D converter 120 performs a first round of A / D conversion using as input the output voltages VQPc and VQNc from the arithmetic and hold operation of the pipeline stage 110c.

[0124] When the clock signal CKA is at a high level, the switches SP1d and SN1d are on, and the switches SP2d and SN2d are off. The voltages at the nodes NIPd and NINd in the first stage 120d are the output voltages VQPe and VQNe resulting from the first round of A / D conversion by the cyclic A / D converter 120. That is, when the clock signal CKA is at a high level, the cyclic A / D converter 120 performs a second round of A / D conversion using as input the output voltages VQPe and VQNe resulting from the first round of A / D conversion by the cyclic A / D converter 120.

[0125] When the clock signal CKB is at a high level, the first stage 120d performs a sampling operation, and the second stage 120e performs an arithmetic and hold operation. When the clock signal CKB is at a low level, the first stage 120d performs an arithmetic and hold operation, and the second stage 120e performs a sampling operation. At this time, the operations of the first stage 120d and the second stage 120e are the same as those of the pipeline stages 110b and 110c. However, the first stage 120d and the second stage 120e use the clock signal CKB as their operating clock, and operate at a cycle that is half the operating cycle of the pipeline stages 110b and 110c.

[0126] Although the above example shows amplifier sharing between the first stage 120d and the second stage 120e of the cyclic A / D converter 120, an operational amplifier may be provided in each of the first stage 120d and the second stage 120e.

[0127] Consider the case where the first stage 120d of the cyclic A / D converter 120 samples the output voltage of the pipeline stage 110c in the above configuration. The pipeline stage 110c in FIG. 11 performs calculation and hold operations, and a feedback path for the operational amplifier OPc is formed via capacitors CFPc and CFNc. The capacitor circuits CSMPc and CSMNc act as loads on the feedback path. In this state, switches SP2d and SN2d are turned on in the first stage 120d of the cyclic A / D converter 120 in FIG. 14, and sampling begins. The operational amplifier OPc in the pipeline stage 110c charges the capacitor circuit CMP1d and other components of the first stage 120d, causing the sampling voltage to settle.

[0128] In this case, since the number of bits of the pipeline stage 110c is small, the number of capacitor circuits in the pipeline stage 110c is also small, and the load seen on the feedback path of the operational amplifier OPc is small. This allows the operational amplifier OPc to quickly settle the sampling voltage of the first stage 120d, enabling accurate sampling even if the sampling period of the first stage 120d is short.

[0129] FIG. 17 is an example of a timing chart illustrating the overall operation of the A / D conversion circuit shown in FIG.

[0130] The vertical dotted line indicates the timing at which the initial pipeline stage 110a determines the sampled value. The circles at the intersections of the vertical dotted line and the waveform of the input voltage VIN indicate the determined sampled value. The pipeline stage 110a performs sampling while the clock signal CKA is at a high level, and therefore determines the sampled value at the falling edge of the clock signal CKA.

[0131] The sampled values ​​are determined in time series at each falling edge of the clock signal CKA. The sampled values ​​in the time series are assigned numbers "k," "k+1," "k+2," ... in order. The waveform of each digital value is similarly numbered to indicate which sampled value the digital value corresponds to.

[0132] In the waveforms of the digital values ​​DQd[2:0] and DQe[2:0] that are the output of the cyclic A / D converter 120, "(1)" indicates the result of the A / D conversion for the first cycle, and "(2)" indicates the result of the A / D conversion for the second cycle.

[0133] The sub-A / D converter of each stage updates its digital value at the end of its sampling period. For example, the pipeline stage 110a performs sampling while the clock signal CKA is at a high level, so the sub-A / D converter 111a updates the digital value DQa[2:0] at the falling edge of the clock signal CKA. For example, the pipeline stage 110b performs sampling while the clock signal CKA is at a low level, so the sub-A / D converter 111a updates the digital value DQa[2:0] at the rising edge of the clock signal CKA. The flash A / D converter 130 updates the digital value DQf[2:0] at the falling edge of the clock signal CKC.

[0134] FIG. 18 is a diagram illustrating the operation of an adder. Each square represents one bit of a digital value. The left direction of the drawing is the most significant bit side. (k) indicates a digital value corresponding to the kth sampling value. (k(1)) indicates a digital value corresponding to the kth sampling value and is the A / D conversion result of the first cycle of the cyclic A / D converter 120. (k(2)) indicates a digital value corresponding to the kth sampling value and is the A / D conversion result of the second cycle of the cyclic A / D converter 120.

[0135] 18, the adder 190 obtains the output digital value DOUT[15:0] of the A / D conversion circuit 100 from the digital values ​​of each stage. Specifically, the adder 190 arranges DQf[0](k), DQf[1](k), and DQf[2](k) at the first, second, and third digits from the LSB, respectively, arranges DQe[0](k(2)), DQe[1(k(2))], and DQ3[2](k(2)) at the third, fourth, and fifth digits from the LSB, respectively, arranges each digital value thereafter in the same manner, and adds the arranged digital values.

[0136] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term with a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also within the scope of the present disclosure. Furthermore, the configurations and operations of the pipeline stages, cyclic A / D converters, flash A / D converters, successive approximation A / D converters, adders, A / D conversion circuits, and the like are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0137] 100...A / D conversion circuit, 110a...pipeline stage, 110b...first pipeline stage, 110c...second pipeline stage, 111a, 111b, 111c, 111d, 111e...sub A / D converter, 112a, 112b, 112c, 112d, 112e...encoder, 120...cyclic A / D converter, 120d...first stage, 120e...second stage, 130...flash type A / D converter, 140...comparison type A / D converter, 1 41...Sample-hold circuit, 142...D / A converter, 143...Comparator, 144...Control circuit, 190...Adder, DOUT[15:0], DOUT[11:0]...Output digital value, DQa, DQb, DQc, DQd, DQe, DQf, DQg...Digital value, MDACa, MDACb, MDACc, MDACd, MDACe...D / A converter, TA1...First period, TA2...Second period, TA3...Third period, TB1...Sampling period, VIN...Input voltage

Claims

1. a first pipeline stage that outputs an x-bit first digital value by A / D conversion based on an input signal; a second pipeline stage that performs A / D conversion based on the first analog output signal of the first pipeline stage to output a second digital value of y bits, which is smaller than the x bits; an A / D converter that samples the second analog output signal of the second pipeline stage during a sampling period that is shorter than the sampling period of the first pipeline stage and the sampling period of the second pipeline stage, performs A / D conversion based on the sampling result, and outputs a third digital value; An A / D conversion circuit comprising:

2. 2. The A / D conversion circuit according to claim 1, the first pipeline stage performs a sampling operation during a first period; In a second period after the first period, the first pipeline stage performs an operation and hold operation, and the second pipeline stage performs a sampling operation; In a third period after the second period, the second pipeline stage performs an arithmetic and hold operation, and the A / D converter performs a sampling operation.

3. 2. The A / D conversion circuit according to claim 1, 10. An A / D conversion circuit, wherein the A / D converter is a cyclic A / D converter.

4. 4. The A / D conversion circuit according to claim 3, the cyclic A / D converter performs a first cycle of A / D conversion to A / D convert the second analog output signal, and a second cycle of A / D conversion to A / D convert again the analog output signal output by the cyclic A / D converter after the first cycle of A / D conversion, during a period in which the first pipeline stage and the second pipeline stage perform one cycle of A / D conversion.

5. 2. The A / D conversion circuit according to claim 1, The A / D conversion circuit is characterized in that the A / D converter is a successive approximation type A / D converter.

6. 6. The A / D conversion circuit according to claim 5, the successive approximation type A / D converter performs a sampling operation of sampling the second analog output signal and a successive approximation operation on the sampled second analog output signal during a period in which the first pipeline stage and the second pipeline stage perform one A / D conversion.

7. 2. The A / D conversion circuit according to claim 1, The x bits are n+0.5 bits (n is an integer of 1 or more), The A / D conversion circuit is characterized in that the y bits are m+0.5 bits (m is an integer equal to or greater than 1 and smaller than n).

8. 2. The A / D conversion circuit according to claim 1, The A / D conversion circuit is characterized in that the third digital value is z bits, which is greater than the x bits and the y bits.

9. 2. The A / D conversion circuit according to claim 1, An A / D conversion circuit comprising a flash A / D converter provided in a subsequent stage of the A / D converter.

10. 10. The A / D conversion circuit according to claim 1, an adder that outputs an output digital value of the A / D conversion circuit based on the first digital value, the second digital value, and the third digital value;

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