Timer

Abstract

To provide a timer that shortens a time required for counting up and counting down a bit counter without increasing the clock frequency.SOLUTION: A timer includes: a bit counter that includes multiple bits and counts up or counts down a count value of the multiple bits in synchronization with a clock; and a division circuit that divides the multiple bits into M groups on the basis of at least a division permission signal that permits division of the multiple bits into M groups (M is a natural number greater than or equal to 1), a division position setting signal that sets a bit corresponding to a position at which the multiple bits are to be divided into the M groups, among the multiple bits, and a boundary verification signal that verifies the count up or count down of the count value at a boundary between the M groups. The M groups include the same number of bits, and the bit counter counts up or counts down the count values of the bits of the M groups in parallel in synchronization with the clock.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to timers. [Background technology]

[0002] In the case of timers used in safety mechanisms, in order to confirm that the timer is operating normally before actually using it, the technology disclosed in Patent Document 1 and elsewhere diagnoses the normality of the timer over a set time period set by the user. At this time, it is desirable to switch the clock quickly to shorten the diagnostic time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 6-282353 Summary of the Invention [Problem to be solved by the invention]

[0004] However, as the bit width of a timer becomes enormous, diagnostic time can become very long. For example, if a 32-bit timer counts up from 0 to expiration using a 48 MHz clock, it takes approximately 89 seconds. Even if a faster clock is used to address this issue, for example, one with twice the clock frequency, it still takes nearly 45 seconds, and if countdown diagnostics are also performed, the diagnostic time becomes even longer. Furthermore, if diagnostic time needs to be reduced beyond the maximum frequency built into the system, a dedicated oscillator circuit must be developed for diagnostics, which can increase development efforts. As such, conventional technology leaves room for improvement in terms of further reducing the time required for counting up and down all bit counters during timer diagnostics.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a timer that further reduces the time required for a bit counter to count up and down without increasing the clock frequency. [Means for solving the problem]

[0006] In order to solve the above problem, the timer disclosed herein comprises a bit counter that includes a plurality of bits and counts up or down a count value of the plurality of bits in synchronization with a clock; a division circuit that divides the plurality of bits into M groups based on at least a division permission signal that permits division of the plurality of bits into M groups (M is a natural number greater than or equal to 1), a division position setting signal that sets a bit among the plurality of bits corresponding to a position at which the bits are to be divided into the M groups, and a boundary verification signal that verifies the count up or count down of the count value at the boundary between the M groups, wherein the M groups include the same number of bits, and the bit counter counts up or counts down the count values ​​of the bits of the M groups in parallel in synchronization with the clock. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a configuration diagram of a timer 100 according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram for explaining the information set in the diagnostic mode register A, the timer bit division register B, and the count value write register C. [Figure 3] FIG. 3 is a diagram showing the configuration of the dividing circuit 10. [Figure 4A] FIG. 4A is a diagram for explaining the operation of the timer 100. In FIG. [Figure 4B] FIG. 4B is a diagram for explaining the operation of the timer 100. [Figure 4C] FIG. 4C is a diagram for explaining the operation of the timer 100. [Figure 5] FIG. 5 is a diagram for explaining the operation of the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0009] (Embodiment) 1 is a configuration diagram of a timer 100 according to an embodiment of the present disclosure. The timer 100 may be interpreted as a timer that divides the bits included in the bit counter 20 into any number equal to or greater than two, thereby dividing the number of bits included in the bit counter 20 into at least two or more groups, and increments the count values ​​of these groups in parallel. The timer 100 may include a diagnostic mode register A, a timer bit division register B, a count value write register C, a division circuit 10, and a bit counter 20.

[0010] For simplicity of explanation, the following describes a case where bits included in a 32-bit bit counter 20 are divided, but the number of bits of the bit counter 20 provided in the timer 100 is not limited to 32 bits and may be, for example, two or more bits, such as 8 bits, 16 bits, or 64 bits. The number of divisions described below is an example, and the number of divisions of the bits included in the bit counter 20 may be two or more.

[0011] (Diagnostic Mode Register A) The diagnostic mode register A may be interpreted as a register for setting the diagnostic mode transition signal Aa, the division enable signal Ab, the write enable signal Ac, and the count instruction signal Ad. The diagnostic mode register A may include N flip-flops (N is a natural number equal to or greater than 1).

[0012] The diagnostic mode transition signal Aa may be interpreted as a signal indicating that the bit counter 20 is to be transitioned to a mode for diagnosing the bit counter 20 .

[0013] The division permission signal Ab may be interpreted as a signal that permits division of the multiple bits included in the bit counter 20 into at least M groups (M is a natural number equal to or greater than 1). The division permission signal Ab may be enabled only when a diagnostic enable bit [0] (described later) is set to 1, that is, when the bit counter 20 has transitioned to a mode for diagnosing by the diagnostic mode transition signal Aa.

[0014] The write enable signal Ac may be interpreted as a signal that allows writing of a count value to the bit counter 20. The write enable signal Ac may be enabled only when a diagnostic enable bit [0] (described later) is set to 1, that is, when the bit counter 20 is in a diagnostic mode.

[0015] The count instruction signal Ad may be interpreted as a signal that instructs the bit counter 20 to start or stop counting up or down the count value. The count instruction signal Ad may be enabled only when a diagnostic enable bit [0] (described later) is set to 1, that is, when the bit counter 20 is in a diagnostic mode. A specific example of the configuration of the diagnostic mode register A will be described later.

[0016] (Timer bit division register B) The timer bit division register B may be interpreted as a register for setting the division position setting signal Ba. The division position setting signal Ba may be interpreted as a signal for setting a bit corresponding to a position for dividing a plurality of bits included in the bit counter 20 into M groups. The timer bit division register B may include a plurality of flip-flops. The division position setting signal Ba may be enabled only when the timer bit division enable bit [2] described later is set to 1, that is, when division of the bit counter 20 is permitted by the division permission signal Ab. A specific example of the configuration of the timer bit division register B will be described later.

[0017] (Count value write register C) The count value write register C may be interpreted as a register for setting the boundary verification signal Ca. The boundary verification signal Ca may be interpreted as a signal for verifying the count up or count down of the count value at the boundary between the M groups. For example, when the count up or count down of each of the M divided groups is stopped, the count value write register C may be set to any value (count value) of the bit to be verified in order to verify the count up or count down of the count value at each boundary between the M divided groups. The verification may be interpreted as, for example, confirming that carry is performed accurately at the boundary between a specific divided group and another group adjacent to that group. If there are multiple boundaries between adjacent groups, the verification may be performed for these multiple boundaries. For example, if a 32-bit bit counter 20 is divided into four, to verify that the count value at the boundary BD between bit [7] and bit [8] of the bit counter 20 accurately counts up or counts down, 0x000000FF is set and then incremented by one bit. As a result, if the bit value of the bit counter 20 changes to 0x00000100, it can be verified that the count value at the boundary portion BD between bits [7] and [8] of the bit counter 20 is counting up or down accurately. The count value write register C may include multiple flip-flops. The boundary verification signal Ca may be enabled only when the diagnostic mode register A[4] or write enable bit described below is set to 1, that is, when writing of the count value to the bit counter 20 is permitted by the write enable signal Ac. A specific example of the configuration of the count value write register C will be described later.

[0018] (divided circuit 10) The dividing circuit 10 may be interpreted as a circuit for dividing the plurality of bits included in the bit counter 20 into M groups. Specifically, the dividing circuit 10 may be interpreted as a circuit that divides the plurality of bits included in the bit counter 20 into M groups based on at least the above-mentioned division permission signal Ab, division position setting signal Ba, and boundary verification signal Ca, and counts up or down the count value in each of the M groups in parallel. A specific example of the configuration of the dividing circuit 10 will be described later.

[0019] (Bit counter 20) The bit counter 20 may be interpreted as a circuit that includes a plurality of bits and counts up or down a count value of the plurality of bits in synchronization with a clock. The bit counter 20 may include a plurality of flip-flops.

[0020] Next, with reference to FIG. 2, a specific example of the configuration of the diagnostic mode register A, the timer bit division register B, and the count value write register C will be described.

[0021] 2 is a diagram for explaining information to be set in each of the diagnostic mode register A, the timer bit division register B, and the count value write register C. Fig. 2 shows an example of the diagnostic mode register A, the timer bit division register B, and the count value write register C. Each register may have, for example, 32 bits.

[0022] (Diagnostic Mode Register A) The diagnostic mode register A may include, for example, a KEY bit (for example, [31:16]) and other bits (for example, [15:0]) excluding the KEY bit.

[0023] For example, by simultaneously writing 0xAA55 to the KEY bits [31:16] and the bit you want to write from bits [0] to [6], you can write a value to the diagnostic mode register A, but the value (0xAA55) at this time is not retained. This prevents writing to the register due to unintended access, etc.

[0024] Other bits [15:0] may include a diagnostic enable bit (e.g., [0]), a timer bit split enable bit (e.g., [2]), a write enable bit (e.g., [4]), and a count enable bit (e.g., [6]).

[0025] When the diagnostic enable bit [0] is set to 1, a diagnostic mode transition signal Aa is input to the division circuit 10. When the timer bit division enable bit [2] is set to 1, a division enable signal Ab is input to the division circuit 10. When the write enable bit [4] is set to 1, a write enable signal Ac is input to the division circuit 10. When the count enable bit [6] is set to 1, a count instruction signal Ad is input to the division circuit 10.

[0026] (Timer bit division register B) The timer bit division register B may include, for example, a bit (e.g., [31:1]) for setting the division position setting signal Ba, and other bits (e.g., [0]) excluding the bit. Note that if the bit counter 20 has one bit, the bit is not divided, so the other bit [0] may be interpreted as unusable.

[0027] (Count value write register C) The count value write register C may include a bit (e.g., [31:0]) that sets the boundary verification signal Ca. For example, if the 32 bits included in the bit counter 20 are equally divided into four groups, the boundaries of each group are set between bit [7] and bit [8], between bit

[15] and bit

[16] , and between bit

[23] and bit

[24] . Specifically, when verifying the boundary between bit [7] and bit [8], 0x000000FF is set in the count value write register C. Similarly, when verifying the boundary between bit

[15] and bit

[16] , 0x0000FFFF is set in the count value write register C. When verifying the boundary between bit

[23] and bit

[24] , 0x00FFFFFF is set in the count value write register C.

[0028] Next, the configuration of the division circuit 10 will be described with reference to Fig. 3. Fig. 3 is a configuration diagram of the division circuit 10. The division circuit 10 may include a diagnostic mode switching circuit 11, a timer bit division enable circuit 12, a timer bit division circuit 13, a write enable circuit 14, and a count enable circuit 15.

[0029] Each of these circuits may include a plurality of selectors. Each selector may be interpreted as a circuit that selects an input signal and outputs the selected signal.

[0030] (Diagnostic mode switching circuit 11) The diagnostic mode switching circuit 11 may be interpreted as a circuit for switching to a mode for diagnosing the bit counter 20. The selection signal input to the diagnostic mode switching circuit 11 may be interpreted as, for example, a diagnostic mode transition signal Aa. Specifically, when the diagnostic enable bit [0] is set to 1 and the diagnostic mode transition signal Aa is output, the selectors 11a, 11b, and 11c in the diagnostic mode switching circuit 11 input the diagnostic mode transition signal Aa as a selection signal.

[0031] When the selector 11a receives the count instruction signal Ad as an input signal, it inputs its output to the count enable circuit 15 according to the selection signal. When the output of the selector 11a is "1", counting (counting up or down of the count value) in the bit counter 20 starts, and when the output of the selector 11a is "0", counting stops.

[0032] When the selector 11b receives the division permission signal Ab as an input signal, it outputs the output to the timer bit division permission circuit 12 in response to the selection signal, thereby enabling the timer bit division permission circuit 12.

[0033] When the selector 11c receives the write permission signal Ac as an input signal, the selector 11c inputs its output to the write permission circuit 14 in response to a selection signal, thereby enabling the write permission circuit 14.

[0034] (Timer bit division permission circuit 12) The timer bit division permission circuit 12 may be interpreted as a circuit that allows a plurality of bits included in the bit counter 20 to be divided into at least M groups (M is a natural number equal to or greater than 1). The timer bit division permission circuit 12 may include a plurality of selectors (selector 12-1, selector 12-2, selector 12-31, etc.) that receive the output from selector 11b as a selection signal.

[0035] For example, when selector 12-1 receives division position setting signal B[1] as an input signal, it inputs its output to selector 13-1 of timer bit division circuit 13 in response to a selection signal. Similarly, when selector 12-2 receives division position setting signal B[2] as an input signal, it inputs its output to selector 13-2 of timer bit division circuit 13 in response to a selection signal. When selector 12-31 receives division position setting signal B

[31] as an input signal, it inputs its output to selector 13-31 of timer bit division circuit 13 in response to a selection signal.

[0036] (Timer bit division circuit 13) The timer bit division circuit 13 may be interpreted as a circuit for arbitrarily setting bits corresponding to positions for dividing a plurality of bits included in the bit counter 20 into M groups. The timer bit division circuit 13 may include a plurality of selectors (selector 13-1, selector 13-2, selector 13-31, etc.) that input the output from the timer bit division permission circuit 12 as a selection signal.

[0037] For example, when selector 13-1 receives the output from selector 12-1 as a selection signal, it selects either the bit value of counter [0] of bit counter 20 or the output of exclusive OR circuit 20-1 based on the selection signal, and inputs the selected output to selector 15-1 of count enable circuit 15.

[0038] The exclusive OR circuit 20-1 outputs the exclusive OR of the bit value of counter [1] of the bit counter 20 and the input 1. Specifically, when the bit value of counter [1] is 0, the exclusive OR circuit 20-1 outputs 1, and when the bit value of counter [1] is 1, the output is 0.

[0039] When the selector 13-2 receives the output from the selector 12-2 as a selection signal, it selects either the bit value of counter [1] of the bit counter 20 or the output of the exclusive OR circuit 20-2 based on the selection signal, and inputs the selected output to the selector 15-2 of the count enable circuit 15.

[0040] The exclusive OR circuit 20-2 outputs the exclusive OR of the bit value of counter [2] of the bit counter 20 and the input 1. Specifically, when the bit value of counter [2] is 0, the exclusive OR circuit 20-2 outputs 1, and when the bit value of counter [2] is 1, the output is 0.

[0041] When the selector 13-31 receives the output from the selector 12-31 as a selection signal, it selects either the bit value of the counter

[30] (not shown) of the bit counter 20 or the output of the exclusive OR circuit 20-31 based on the selection signal, and inputs the selected output to the selector 15-31 of the count enable circuit 15.

[0042] The exclusive OR circuit 20-31 outputs the exclusive OR of the bit value of counter

[31] of the bit counter 20 and the input 1. Specifically, when the bit value of counter

[31] is 0, the exclusive OR circuit 20-31 outputs 1, and when the bit value of counter

[31] is 1, the output is 0.

[0043] (Write enable circuit 14) The write permission circuit 14 may be interpreted as a circuit that permits writing of a count value to the bit counter 20. The write permission circuit 14 may include a plurality of selectors (selector 14-0, selector 14-1, selector 14-2, selector 14-31, etc.) that receive the output from the selector 11c as a selection signal.

[0044] For example, when selector 14-0 receives boundary verification signal C[0] as an input signal, it inputs its output to selector 15-0 of count enable circuit 15 in response to a selection signal. Similarly, when selector 14-1 receives boundary verification signal C[1] as an input signal, it inputs its output to selector 15-1 of count enable circuit 15 in response to a selection signal. When selector 14-2 receives boundary verification signal C[2] as an input signal, it inputs its output to selector 15-2 of count enable circuit 15 in response to a selection signal. When selector 14-31 receives boundary verification signal C

[31] as an input signal, it inputs its output to selector 15-31 of count enable circuit 15 in response to a selection signal.

[0045] (Count enable circuit 15) The count enable circuit 15 may include a plurality of selectors (selector 15-0, selector 15-1, selector 15-2, selector 15-31, etc.) that receive the output from the selector 11a as a selection signal.

[0046] For example, when selector 15-0 receives the output from selector 11a as a selection signal, it selects either the value of selector 14-0 or the output of exclusive OR circuit 30 based on the selection signal, and inputs the selected output to bit counter 20, thereby setting the bit value of counter [0] of bit counter 20 to 0 or 1.

[0047] The exclusive OR circuit 30 outputs the exclusive OR of the bit value of counter [0] of the bit counter 20 and the input 1. Specifically, when the bit value of counter [0] of the bit counter 20 is 0, the exclusive OR circuit 20-1 outputs 1, and when the bit value of counter [0] is 1, the output is 0.

[0048] When selector 15-1 receives the output from selector 11a as a selection signal, it selects either the value of selector 14-1 or the value of selector 13-1 based on the selection signal, and inputs the selected output to bit counter 20, thereby setting the bit value of counter [1] of bit counter 20 to 0 or 1.

[0049] When selector 15-2 receives the output from selector 11a as a selection signal, it selects either the value of selector 14-2 or the value of selector 13-2 based on the selection signal, and inputs the selected output to bit counter 20, thereby setting the bit value of counter [2] of bit counter 20 to 0 or 1.

[0050] When selector 15-3 receives the output from selector 11a as a selection signal, it selects either the value of selector 14-31 or the value of selector 13-31 based on the selection signal, and inputs the selected output to bit counter 20, thereby setting the bit value of counter

[31] of bit counter 20 to 0 or 1.

[0051] Next, the operation of the timer 100 will be described with reference to Figures 4A to 4C. Figures 4A to 4C are diagrams for explaining the operation of the timer 100.

[0052] First, 0xAA550005 is set in the diagnostic mode register A. This switches to diagnostic mode and enables division of the bit counter 20.

[0053] Next, 0X01010100 is set in the timer bit division register B. As a result, the number of bits (32 bits) included in the bit counter 20 is divided into four equal parts of 8 bits each (see FIG. 4A).

[0054] Next, 0xAA550405 is set in the diagnostic mode register A. This causes the bit counter 20 to start counting bit values ​​after transitioning to diagnostic mode and with division of the bit counter 20 permitted. In other words, the bit values ​​of the 8 bits contained in the four equal groups are counted up from 0 to 255.

[0055] At this time, as shown in Figure 4A, to verify the boundary areas BD ([7] → [8],

[15] →

[16] ,

[23] →

[24] ) between the four groups, the following settings are made.

[0056] 0xAA550011 is set in the diagnostic mode register A. This allows writing of the count value to the bit counter 20 while in the diagnostic mode.

[0057] Then, 0x000000FF is set in the count value write register C (see FIG. 4C). Furthermore, 0xAA550051 is set in the diagnostic mode register A. As a result, the bit counter 20 starts counting the bit values ​​in a state where the diagnostic mode has been entered and writing of the count value to the bit counter 20 is permitted. As shown in FIG. 4C, if the bit value of the bit counter 20 changes to 0x00000100 by incrementing 0x000000FF by one bit, it can be verified that the count value at the boundary portion BD between bits [7] and [8] of the bit counter 20 is counting up or down accurately.

[0058] Using the same procedure, it is possible to verify the boundary portion BD between bits

[15] and

[16] of the bit counter 20, and the boundary portion BD between bits

[23] and

[24] of the bit counter 20. In this case, verification of the three boundary portions BD is completed in a total of three clocks.

[0059] Figure 5 is a diagram for explaining the operation of the comparative example. In the conventional technology shown in Patent Document 1, as shown in Figure 5, if an oscillator circuit with a clock frequency twice the base clock frequency is used, the diagnostic time is reduced to 1 / 2, and if an oscillator circuit with a clock frequency four times the base clock frequency is used, the diagnostic time is reduced to 1 / 4. In this way, if it is desired to reduce the diagnostic time beyond the maximum frequency built into the system, it is necessary to develop an additional oscillator circuit for diagnosing the timer. However, this method requires the development of an oscillator circuit dedicated to diagnosing the timer, which can increase the number of development steps. For example, if the frequency is 10 times higher than the base clock frequency, the diagnostic time is reduced to 1 / 4. 7 It is not realistic to develop an oscillator circuit that is more than twice as large for diagnostic purposes.

[0060] In contrast, in the timer 100 of the present disclosure, if the diagnostic time using this method is 1, when it is divided into two, the diagnostic time is reduced to 1 / 65536, and when it is divided into four, the diagnostic time is reduced to 1 / 16843009 (see Figure 4B).

[0061] In addition, the following supplementary notes are provided in relation to the above description.

[0062] (Appendix 1) a bit counter including a plurality of bits, which counts up or down a count value of the plurality of bits in synchronization with a clock; a division circuit that divides the plurality of bits into M groups (M is a natural number equal to or greater than 1) based on at least a division permission signal that permits division of the plurality of bits into M groups, a division position setting signal that sets bits among the plurality of bits corresponding to positions at which the bits are divided into the M groups, and a boundary verification signal that verifies whether the count value is counted up or down at the boundary between the M groups; Equipped with the M groups each contain the same number of bits; The bit counter is a timer that counts up or down the count values ​​of M groups of bits in parallel in synchronization with the clock.

[0063] (Appendix 2) The dividing circuit comprises: 2. The timer of claim 1, wherein the timer divides the plurality of bits into the M groups based on the division permission signal, the division position setting signal, the boundary verification signal, a diagnostic mode transition signal indicating transition to a mode for diagnosing the bit counter, a write permission signal permitting writing of the count value to the bit counter, and a count instruction signal instructing start or stop of counting up or down the count value.

[0064] (Appendix 3) 3. The timer of claim 2, comprising: a register for setting the division permission signal, the diagnostic mode transition signal, the write permission signal, and the count instruction signal; a register for setting the division position setting signal; and a register for setting the boundary verification signal. [Explanation of symbols]

[0065] 10 division circuit 11 Diagnostic mode switching circuit 11a Selector 11b Selector 11c Selector 12 Timer bit division enable circuit 12-1 Selector 12-2 Selector 12-31 Selector 13 Timer bit division circuit 13-1 Selector 13-2 Selector 13-31 Selector 14 Write enable circuit 14-0 Selector 14-1 Selector 14-2 Selector 14-31 Selector 15 Count enable circuit 15-0 Selector 15-1 Selector 15-2 Selector 15-31 Selector 20-bit counter 20-1 Exclusive OR circuit 20-2 Exclusive OR circuit 20-31 Exclusive OR circuit 30 Exclusive OR circuit 100 Timers A Diagnostic Mode Register B Timer Bit Split Register C Count value write register

Claims

1. a bit counter including a plurality of bits, which counts up or down a count value of the plurality of bits in synchronization with a clock; a division circuit that divides the plurality of bits into M groups (M is a natural number equal to or greater than 1) based on at least a division permission signal that permits division of the plurality of bits into M groups, a division position setting signal that sets bits among the plurality of bits corresponding to positions at which the bits are divided into the M groups, and a boundary verification signal that verifies whether the count value is counted up or down at the boundary between the M groups; Equipped with the M groups each contain the same number of bits; The bit counter is a timer that counts up or down the count values ​​of M groups of bits in parallel in synchronization with the clock.

2. The dividing circuit comprises:

2. The timer according to claim 1, wherein the plurality of bits are divided into the M groups based on the division permission signal, the division position setting signal, the boundary verification signal, a diagnostic mode transition signal indicating transition to a mode for diagnosing the bit counter, a write permission signal permitting writing of the count value to the bit counter, and a count instruction signal instructing start or stop of counting up or down the count value.

3. 3. The timer according to claim 2, comprising: a register for setting the division enable signal, the diagnostic mode transition signal, the write enable signal, and the count instruction signal; a register for setting the division position setting signal; and a register for setting the boundary verification signal.

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