Process for manufacturing image sensor

Abstract

To provide a novel process for manufacturing an image sensor.SOLUTION: A process for manufacturing an image sensor according to the present invention includes preparing a base substrate (10) and a receiver substrate (1) including an active layer having a pixel (11) including a dope region (12) to collect charges, preparing a donor substrate (2) including a weak zone (200) defining a border with a single-crystal semiconductor layer (201), bonding the donor substrate (2) to the receiver substrate (1), detaching the donor substrate (2) along the weak zone (200) and transferring the semiconductor layer (201) to the receiver substrate (1), and finishing the transferred semiconductor layer (201). The finishing includes (i) thinning of the transferred layer by the sacrificial oxidation and the subsequent chemical etching, and (ii) smoothing of the transferred semiconductor layer by rapid annealing.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a process for making an image sensor. [Background technology]

[0002] The creation of an image sensor by three-dimensional (3D) integration involves successively stacking different layers comprising, in particular, photodiodes, each of which defines a pixel of the image sensor, components of a readout circuit for reading out the pixels, and interconnections between said components and the pixels.

[0003] For a description of image sensors formed by 3D integration, reference may be made, for example, to [Mansoorian 2009].

[0004] FIG. 1 shows an image sensor schematically in cross section.

[0005] The sensor a base substrate 10; an active layer comprising a plurality of pixels 11, each pixel comprising a doped region 12 suitable for collecting charge generated in each pixel, the pixels being separated from one another by electrical isolation trenches 13; one or more dielectric or electrically insulating layers 14, such as silicon nitride or silicon oxide; a silicon layer 22 comprising pixel readout circuitry components 25; Equipped with.

[0006] Interconnects 26 extend through layer 14 to electrically connect components 25 and pixels 11 .

[0007] However, 3D integration processes have significant limitations. Therefore, in traditional approaches that bond and consume sacrificial substrates, the process incurs the cost of consuming such substrates. For example, in approaches involving layer transfer using the SmartCut™ process, the thermal budget of successive steps must be controlled so as not to damage the active zone or pre-formed components. Generally speaking, and according to references available in the literature, a very high thermal budget tends to result in anomalous diffusion from the doped regions configured to collect photo-generated charge in the pixel, which may affect the performance of the sensor. Similarly, metal connections between sensor elements tend to be damaged by a very high thermal budget.

[0008] However, performing steps with a low thermal budget may be disadvantageous, particularly in terms of process duration and / or cost. Summary of the Invention

[0009] The objective of the present invention is to design a process for fabricating image sensors using 3D integration techniques in which the control of thickness of added layers is compatible with FDSOI type substrates, which process can be rapidly industrialized and cheap, while preventing the diffusion of dopants present in the charge collection regions and the doped layer of amorphous silicon.

[0010] An SOI ("semiconductor-on-insulator") substrate is a substrate comprising a semiconductor layer, for example made of silicon, on a substrate, with an electrically insulating layer interposed between the semiconductor layer and the substrate. In an FDSOI ("fully depleted semiconductor-on-insulator") substrate, the thickness of the semiconductor layer is thin enough to allow full depletion of the conduction channels of transistors formed in said layer. Such layers typically have a thickness of a few tens of nanometers.

[0011] To that end, the present invention proposes a process for producing an image sensor, the process comprising: providing a receiver substrate comprising a base substrate and an active layer comprising pixels, each pixel comprising a doped region for collecting charge generated in the pixel, said receiver substrate being free of metal interconnects; providing a donor substrate comprising a weakened zone defining a monocrystalline semiconductor layer; bonding the donor substrate to the receiver substrate; detaching the donor substrate along the weakened zone to transfer the semiconductor layer to a receiver substrate; Finishing the transferred semiconductor layer wherein the finishing process comprises (i) thinning the transferred layer by sacrificial oxidation followed by chemical etching, and (ii) smoothing the transferred semiconductor layer by at least one rapid anneal.

[0012] By "rapid anneal" herein is meant a heat treatment having a temperature ramp-up rate of greater than 10°C / sec, preferably on the order of 50°C / sec or even higher.

[0013] The fact that the receiver substrate comprises only doped zones and no metal interconnects allows for certain heat treatments to be tolerated in order to smooth the transferred semiconductor layer, but said heat treatments should have a sufficiently reasonable thermal budget so as not to result in diffusion of dopants present in the receiver substrate. Rapid annealing as performed in the present invention respects this constraint.

[0014] Furthermore, controlled chemical etching provides the thickness uniformity required for the target application. This uniformity of thickness is similar to that of FDSOI substrates, for which the measure of uniformity may be expressed, on the one hand, by the variability of the thickness of the transferred layer within one and the same substrate or wafer, with intra-wafer variability typically being 10 Å or less, and, on the other hand, by the variability of the average thickness of the transferred layer between different wafers, with inter-wafer variability typically being on the order of ±2 Å at most.

[0015] It is particularly advantageous that each rapid anneal is controlled to prevent diffusion of dopants from the doped regions of the pixel.

[0016] To that end, each rapid anneal may be carried out at a temperature between 1100° C. and 1250° C. for a duration between 15 and 60 seconds.

[0017] In some embodiments, the sacrificial oxidation and chemical etching are controlled to thin the transferred single crystal semiconductor layer to a thickness between 10 nm and 100 nm.

[0018] The chemical etching to thin the transferred monocrystalline semiconductor layer may be performed by wet etching, plasma dry etching, ion beam dry etching, or cluster ion beam dry etching.

[0019] In some embodiments, the process further includes, after finishing of the transferred monocrystalline semiconductor layer, forming readout circuitry components that read out pixels in or on the transferred semiconductor layer.

[0020] In some embodiments, the process further includes forming interconnects between the pixels and said components of the pixel readout circuitry after finishing of the transferred monocrystalline semiconductor layer.

[0021] In some embodiments, the process includes forming a weakened layer by implanting atomic species into the donor substrate.

[0022] In some embodiments, the finishing process comprises: (i) a first rapid annealing; (ii) sacrificial oxidation of the transferred layer to remove implant-related defects; (iii) a second rapid annealing; and (iv) Thinning of the transferred layer consecutively.

[0023] In some embodiments, the donor substrate further comprises a silicon oxide layer, preferably deposited by tetraethylorthosilicate (TEOS), on the monocrystalline semiconductor layer.

[0024] The donor substrate may further comprise one or more electrically insulating or semiconducting layers (or a stack of both of these types of layers) on the silicon oxide layer. In the case of semiconducting layers, the donor substrate may be crystalline or amorphous, doped (n+ or p+) or undoped.

[0025] In some embodiments, a silicon oxide layer, or a layer or stack of layers disposed on the silicon oxide layer, is deposited on the donor substrate prior to implantation.

[0026] In some embodiments, the receiver substrate further comprises one or more electrically insulating or semiconducting layers (or a stack of both of these types of layers) on the active layer. Preferably, at least one electrically insulating layer is a silicon oxide layer, and the semiconducting layers may be crystalline or amorphous, doped (n+ or p+) or undoped.

[0027] It is particularly advantageous for each rapid anneal to have a temperature ramp-up rate of greater than 10° C. / sec, preferably greater than or equal to 50° C. / sec.

[0028] Preferably, the smoothing does not include a heat treatment having a temperature ramp-up rate of less than 10° C. / sec.

[0029] In some embodiments, smoothing is performed individually for each structure comprising a semiconductor layer and a receiver substrate.

[0030] Further features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0031] [Figure 1] 1 is a schematic cross-sectional view of an image sensor; [Figure 2] 2A-2C are schematic cross-sectional views of a receiver substrate and a donor substrate used in a process for fabricating an image sensor according to an embodiment of the present invention; [Figure 3] 3 shows a schematic cross-sectional view of the receiver substrate and donor substrate of FIG. 2 after removal of the donor substrate along the weakened zone. [Figure 4] 4 shows a schematic cross-sectional view of an image sensor formed from the donor and receiver substrates of FIG. 3 after finishing of the transferred semiconductor layers and formation of readout circuitry and interconnects for reading out the pixels. [Figure 5] SIMS profiles of phosphorus concentration in an SOI structure comprising a phosphorus-doped layer following rapid annealing as performed in the present invention and thermal treatment as performed during the fabrication of FDSOI substrates. Reference numerals that are the same from one figure to the next indicate elements that are identical or perform the same function. For greater clarity of the figures, the various elements are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0032] The present invention proposes to fabricate an image sensor by transferring a thin layer from a donor substrate to a receiver substrate.

[0033] The receiver substrate comprises a base substrate and an active layer comprising a plurality of pixels.

[0034] The base substrate is generally a semiconductor substrate, for example of silicon, which serves inter alia as a mechanical carrier for the image sensor.

[0035] The active layer is a monocrystalline semiconductor layer of, for example, silicon or silicon germanium.

[0036] The pixels are separated from each other by electrical isolation trenches, known by the acronyms DTI for "deep trench isolation" or CDTI for "capacitor deep trench isolation."

[0037] Each pixel comprises a doped region suitable for collecting the charge generated at each pixel.

[0038] It is particularly advantageous for the receiver substrate to be free of metal interconnects between its components.

[0039] The fabrication of such a receiver substrate is within the capabilities of one skilled in the art, and therefore the process of fabricating the receiver substrate will not be described in detail herein.

[0040] The donor substrate comprises weakened zones that define the boundaries of the thin monocrystalline semiconductor layers. In some embodiments, the donor substrate may be a bulk substrate made of a single monocrystalline semiconductor material. Alternatively, the donor substrate may be a composite substrate made of at least two layers of different materials, including at least one monocrystalline semiconductor layer. The thin monocrystalline layer may be a layer of silicon or a layer of another semiconductor material.

[0041] The weakened zone is advantageously formed by implanting atomic species, such as hydrogen and / or helium atoms, into the donor substrate. It is within the ability of a person skilled in the art to determine the dose and energy for the implantation in order to form a weakened zone at a given depth in the donor substrate. During the implantation, the surface of the donor substrate may possibly be protected by a dielectric layer, such as a silicon oxide (SiO2) layer. Said layer may then be removed, for example by selective etching.

[0042] The donor substrate is then bonded to a receiver substrate, hi some embodiments, the bonding may be performed through a dielectric layer, such as a silicon oxide layer.

[0043] A fracture of the donor substrate is initiated at the site of the weakened zone, resulting in detachment of the donor substrate along the weakened zone, after which the semiconductor thin layer has been transferred to the receiver substrate.

[0044] This process is commonly known as the SmartCut™ process.

[0045] The final product comprising the receiver substrate and the thin semiconductor layer will be referred to herein as a wafer.

[0046] Since the transferred thin semiconductor layer exhibits a certain degree of roughness, a finishing process is performed on the wafer to smooth the layer while providing the required thickness uniformity.

[0047] To avoid causing dopant diffusion from the active layer, this entire finishing process is carried out using a reasonable thermal budget, lower than that typically used to fabricate FDSOI substrates. However, considering that the receiver substrate does not contain metal, it is not necessary to use low-temperature processes, such as those described in [Schwarzenbach 2019], which have the drawback of being long and complex.

[0048] The target thickness for the transferred semiconductor layer is between 10 nm and 100 nm, with a maximum variation of ±5 Å from the target value within each wafer and between different wafers produced using the process. This standard of uniformity is generally required for the fabrication of FDSOI substrates, but for FDSOI substrates with very high thermal histories, it cannot be obtained for the target image sensor using conventional finishing processes. In particular, finishing processes for FDSOI substrates typically include a "batch anneal" process, which is a long, high-temperature smoothing process advantageously performed in a furnace, allowing multiple substrates to be processed simultaneously (hence the term "batch"). Such "batch anneals" are typically performed at temperatures between 1150°C and 1200°C for a duration of several minutes, generally longer than 15 minutes. Furthermore, the temperature ramp-up in the furnace is relatively slow, on the order of a few degrees Celsius per minute, which contributes to increasing the thermal history experienced by the substrates. This smoothing allows the transferred semiconductor layer to be brought to a level of surface roughness compatible with transistor fabrication. However, such "batch annealing" has been shown to have the effect of reducing the thickness uniformity of the transferred semiconductor layer within one and the same wafer.

[0049] In particular, the finishing process carried out in the present invention comprises, on the one hand, thinning of the transferred layer by sacrificial oxidation followed by chemical etching, and, on the other hand, smoothing by one or more rapid annealings providing a thermal budget lower than that of a "batch anneal", said thermal budget being suitable for maintaining pixel integrity.

[0050] Regarding thinning, the process first involves oxidizing the transferred layer to form a thin layer of oxide on the surface of the layer. This oxide is preferably formed by thermal oxidation of the material of the semiconductor layer. In thermal oxidation, the transferred semiconductor layer is subjected to a heat treatment in an oxidizing atmosphere containing oxygen and / or water vapor, which results in the surface portion of the layer being consumed. By adjusting the conditions of this thermal oxidation (in particular, its duration, the atmosphere (dry or humid), its pressure, and its temperature), it is possible to adjust the thickness of the consumed transferred layer and therefore the degree to which the layer is thinned. The oxidation is carried out at a temperature below 1000°C, preferably 950°C or less, so as not to cause diffusion of dopants within the wafer. The duration of the oxidation is selected according to the thickness of the oxide to be formed, which depends on the initial thickness of the transferred layer and the target thickness of the layer. Such oxidation may be carried out simultaneously on one or several batches of wafers.

[0051] The thickness of the transferred layer, covered with an oxide layer, is then measured at a number of points distributed over the surface of the wafer, so that ellipsometric or reflectometric measurements give the thickness of the semiconductor layer.

[0052] A map of the thickness of the transferred semiconductor layer, obtained by ellipsometry or reflectometry, is used to define the treatment to be applied to said layer in order to make its thickness uniform. It is also possible to determine the average thickness of the semiconductor layer from the thicknesses measured at various points on the wafer.

[0053] This thickness map and / or this average thickness makes it possible to determine one or more areas of the transferred layer that exhibit an excess thickness relative to the target thickness and, as a result, must be subjected to thinning to improve the thickness uniformity of the transferred semiconductor layer.

[0054] Depending on the situation, the uniformity of interest may be "intra-wafer" uniformity (i.e., uniformity across the surface of one and the same structure, said structure generally taking the shape of a circular wafer) and / or "inter-wafer" uniformity (i.e., uniformity between all structures of all structures belonging to a production batch).

[0055] In the case of within-wafer uniformity, the measured thickness is compared at each point with a target thickness of the desired final product, said target thickness being equal to or less than the average thickness. In this case, the thinned area or areas are therefore the area or areas where the semiconductor layer thickness is greater than the target thickness, and the excess thickness or thicknesses correspond to the difference between the measured thickness and the target thickness. It is therefore here a question of one or more "local" excess thicknesses of the wafer.

[0056] In the case of wafer-to-wafer uniformity, the average thickness of the semiconductor layer measured at various measurement points is compared to a target average thickness. In this case, the wafer to be thinned is the wafer for which the average thickness of the semiconductor layer is greater than the target average thickness, and the excess thickness corresponds to the difference between these two average thicknesses. Therefore, it is here a question of the "overall" excess thickness of the wafer.

[0057] Of course, these uniformity requirements may be combined.

[0058] To thin these areas in a localized manner within a wafer and / or to thin the wafer globally, selective etching of the sacrificial oxide layer is first performed. For this purpose, an etchant suitable for etching the sacrificial oxide without attacking the semiconductor material of the layer is used. Typically, if the sacrificial oxide layer is made of silicon oxide and the transferred layer is made of silicon, a solution of hydrofluoric (HF) acid is used as the etchant. Of course, those skilled in the art will be able to select any other suitable etchant according to the respective materials of the sacrificial oxide layer and the semiconductor layer.

[0059] Once the sacrificial oxide layer is removed, a chemical etch of the semiconductor layer itself is performed.

[0060] In some embodiments, the etching is a wet etch, i.e., an etch in which the transferred semiconductor layer is exposed to an etching solution, which may be achieved by immersing the wafer in said solution or by spraying the etching solution onto the surface of the wafer by means of a nozzle, which may allow the etching to be localized to areas that must be thinned relative to other areas of the wafer.

[0061] This etching may be carried out at ambient temperature, ie, a temperature of the order of 20-25°C, or at a higher temperature, but below approximately 80°C.

[0062] In other embodiments, the etching may be plasma dry etching, ion beam dry etching (or RIE, for "reactive-ion etching"), or cluster ion beam dry etching (or GCIB etching, GCIB, for "gas cluster ion beam"). These steps do not involve a significant thermal budget.

[0063] The parameters of these various types of etching implementations allow the transferred semiconductor layer to be thinned in a global and / or localized manner.

[0064] Such a process for thinning an FDSOI substrate and making it uniform (improving the poor uniformity of the thickness of the transferred semiconductor layer caused by smoothing by "batch annealing") is described in French Patent Application Publication No. 2,991,099 filed by the applicant.

[0065] Regarding smoothing, smoothing is performed in the present invention by one or two high-temperature RTAs (RTA for "rapid thermal annealing"). Each anneal is typically performed at a temperature between 1100°C and 1250°C for a duration between 15 and 60 seconds, which allows for atomic reorganization at the surface of the transferred semiconductor layer, thus smoothing the surface. In contrast to "batch annealing," each rapid annealing is performed with a rapid temperature ramp-up on the order of tens of °C / second. Furthermore, while "batch annealing" is performed on multiple wafers simultaneously, rapid annealing is performed on each wafer individually.

[0066] The thermal budget performed in these annealing steps or steps is low enough to avoid diffusion of dopants within the wafer.

[0067] To obtain optimal surface conditions for the transferred layer, the process preferably includes two rapid annealing steps.

[0068] Therefore, unlike known processes for making FDSOI substrates, the smoothing performed in the present invention does not involve a "batch anneal." More generally, the smoothing does not involve a slow thermal process, i.e., a thermal process having a temperature ramp-up rate of less than 10°C / sec. Thus, pixel integrity is maintained during smoothing.

[0069] According to one preferred embodiment, the process includes two sacrificial oxidation steps, one between the first and second rapid annealing steps and one after the second rapid annealing step when two rapid annealing steps are performed. The first sacrificial oxidation advantageously allows for the removal of defects associated with weakened implants by oxidizing the surface region of the transferred layer and then removing the oxidized region, while the second sacrificial oxidation, followed by chemical etching of the transferred layer, allows for the uniform thinning of the transferred layer to the target thickness. The rapid annealing step is preferably performed before the thinning of the transferred layer to maintain the stability of the layer. It would be possible to envision omitting the first rapid annealing, but this would come at the expense of reduced roughness.

[0070] After finishing the transferred semiconductor layer, it is possible to fabricate the components of the pixel readout circuitry in or on this layer.

[0071] The components are further electrically connected to the pixels by interconnects, which may be made of metal but which, in the case of the transferred semiconductor layer, do not risk being damaged by it, given that they are formed after finishing processes.

[0072] To produce an image sensor, it may be useful to insert one or more further semiconducting and / or electrically insulating layers between the active layer and the semiconducting layer comprising the components of the readout circuitry.

[0073] These additional layers may be integrated into the image sensor in a variety of ways.

[0074] According to one embodiment, the further layers may be formed on the active layer of the receiver substrate before bonding the donor substrate. These layers may be formed, for example, by deposition. Whatever the chosen formation process, the formation process does not involve a thermal budget that would tend to diffuse dopants out of the active layer.

[0075] According to another embodiment, at least one of the further layers may be formed by deposition on the active layer of the receiver substrate, and at least one other of the further layers is formed by deposition on the monocrystalline semiconductor layer of the donor substrate before bonding of the substrates. As mentioned above, the deposition of each further layer on the active layer of the receiver substrate must be carried out with a thermal budget low enough not to result in diffusion of dopants.

[0076] According to yet another embodiment, the further layers are formed on the donor substrate. Preferably, the layers are formed by deposition before the implantation of atomic species that form the weakened zone, so that the thermal budget of these depositions does not run the risk of causing premature fracture of the donor substrate along the weakened zone. If the further layers are deposited after the formation of the weakened zone, the applied thermal budget would have to be limited in order to avoid such premature fracture.

[0077] FIG. 2 is a cross-sectional schematic diagram of a donor substrate and a receiver substrate prior to bonding of the two together in one embodiment of the present invention.

[0078] The receiver board 1 is a base substrate 10; an active layer comprising a plurality of pixels 11, each pixel comprising a doped region 12 suitable for collecting charge generated in each pixel, the pixels being separated from one another by electrical isolation trenches 13; a first further layer 15, for example a semiconductor layer, a second further layer 16, for example an electrically insulating layer; are continuously provided.

[0079] The donor substrate 2 comprises a weakened zone 200 that delimits a thin semiconductor layer 201 .

[0080] As mentioned above, layer 16, and possibly layer 15, can be formed on donor substrate 2 instead of receiver substrate 1. In this case, each layer involved is intended to be transferred to the receiver substrate using layer 201.

[0081] Referring to FIG. 3, the donor substrate is bonded to the receiver substrate, after which the donor substrate is detached along the weakened zone to transfer the semiconductor layer 201 to the receiver substrate 1 .

[0082] As shown diagrammatically, the surface S of the layer 201 after removal is rough.

[0083] Therefore, the finishing process described above is carried out.

[0084] Once the transferred monocrystalline semiconductor layer has been uniformly thinned to a target thickness, readout circuit components 25 are formed in or on the layer (see FIG. 4). Interconnects 26 between the components 25 and the pixels 11 are also formed.

[0085] 5 shows SIMS (secondary ion mass spectrometry) profiles of the phosphorus concentration in an SOI structure, comprising, from its surface, successively: an undoped monocrystalline silicon layer having a thickness of 42 nm, a silicon oxide layer having a thickness of 190 nm, a phosphorus-doped silicon layer extending to a depth of 3500 nm, and a base substrate made of intentionally undoped silicon, following two rapid anneals at 1200°C for 30 seconds (curve a) as performed in the present invention, and a thermal treatment at 1200°C for 5 minutes ("batch anneal") (curve b) as performed in the preparation of FDSOI substrates. The abscissa gives the depth from the surface of the SOI structure (in nm), and the ordinate the phosphorus concentration (at / cm 2 units).

[0086] The steep transition (substantially vertical slope) between the doped layer and the base substrate seen in curve a indicates that there was essentially no dopant diffusion during the rapid anneal. Conversely, the more gradual transition seen in curve b indicates dopant diffusion from the doped layer into the base substrate.

[0087] These curves therefore show the protective effect of one or more rapid anneals compared to conventional heat treatments on doped regions.

[0088] References [Mansoorian 2009]: Mansoorian, B., and D. Shaver, withSuntharalingam, V. et al., Lin Ping Ang. "A 4-side Tileable BackIlluminated 3D-integrated Mpixel CMOS Image Sensor." Solid-State CircuitsConference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International.2009. 38-39, 39a. [Schwarzenbach 2019]: W. Schwarzenbach et al, “Low TemperatureSmartCut TM "enables High Density 3D SoC Applications", Proc.ICICDT Conf., 17-19 June 2019 FR 2 991 099 [Explanation of symbols]

[0089] 1... receiver substrate, 2... donor substrate, 10... base substrate, 11... pixel, 12... doped region, 200... weakened zone, 201... single crystal semiconductor layer.

Claims

1. 1. A process for fabricating an image sensor, comprising: providing a receiver substrate (1) comprising a base substrate (10) and an active layer comprising pixels (11), each pixel comprising a doped region (12) for collecting charge generated in said pixel, said receiver substrate (1) being free of metal interconnects; providing a donor substrate (2) comprising a weakened zone (200) delimiting a monocrystalline semiconductor layer (201); bonding the donor substrate (2) to the receiver substrate (1); detaching the donor substrate (2) along the weakened zone (200) and transferring the semiconductor layer (201) to the receiver substrate (1); performing a finishing process on the transferred semiconductor layer (201); wherein the finishing process comprises (i) thinning the transferred layer by sacrificial oxidation followed by chemical etching, and (ii) smoothing the transferred semiconductor layer by at least one rapid annealing.

2. 2. The process of claim 1, wherein each rapid anneal is controlled to prevent diffusion of the dopant from the doped region (12) of the pixel (11).

3. 3. The process of claim 1 or 2, wherein each rapid anneal is carried out at a temperature between 1100°C and 1250°C for a duration between 15 and 60 seconds.

4. The process of any one of claims 1 to 3, wherein the sacrificial oxidation and the chemical etching are controlled to thin the transferred monocrystalline semiconductor layer (201) to a thickness between 10 nm and 100 nm.

5. The process of any one of claims 1 to 4, wherein the chemical etching that thins the transferred monocrystalline semiconductor layer (201) is performed by wet etching, plasma dry etching, ion beam dry etching, or cluster ion beam dry etching.

6. 6. The process of any one of claims 1 to 5, further comprising, after said finishing of said transferred monocrystalline semiconductor layer (201), forming readout circuitry components (25) for reading out said pixels in or on said transferred semiconductor layer (201).

7. 7. The process of claim 6, further comprising, after said finishing of said transferred monocrystalline semiconductor layer (201), forming interconnects between said pixels (11) and said components (25) of said pixel readout circuitry.

8. The process according to any one of the preceding claims, comprising forming the weakened zone (200) by implanting atomic species into the donor substrate (2).

9. The finishing treatment is (i) a first rapid annealing; (ii) sacrificial oxidation of the transferred layer to remove defects associated with the implant; (iii) a second rapid annealing; and (iv) the thinning of the transferred layer 9. The process of claim 8, comprising sequentially:

10. The process according to any one of the preceding claims, wherein the donor substrate (2) further comprises at least one electrically insulating layer (23) on the monocrystalline semiconductor layer (201).

11. The process of any one of claims 1 to 10, wherein the donor substrate (2) further comprises at least one semiconductor layer (24) on the monocrystalline semiconductor layer (201).

12. 12. The process of claim 10 or 11 in combination with claim 8, wherein the electrically insulating layer (23) or the semiconducting layer (24), respectively, is deposited on the donor substrate before the implantation.

13. The process according to any one of claims 1 to 9, wherein the receiver substrate (1) further comprises a semiconductor layer (15) on the active layer.

14. The process according to any one of claims 1 to 9 and 13, wherein the receiver substrate (1) further comprises an electrically insulating layer (16) on the active layer.

15. A process according to any one of claims 1 to 14, wherein each rapid annealing has a temperature ramp-up rate higher than 10°C / sec, preferably 50°C / sec or higher.

16. The process of any one of claims 1 to 15, wherein the smoothing does not include a heat treatment having a temperature ramp-up rate lower than 10°C / sec.

17. The process according to any one of the preceding claims, wherein the smoothing is carried out individually for each structure comprising the semiconductor layer (201) and the receiver substrate (1).

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