Semiconductor device

Abstract

To provide a semiconductor device using an oxide semiconductor, in which deterioration in ON-state current is suppressed.SOLUTION: A semiconductor device comprises an oxide semiconductor film serving as a semiconductor layer, a gate insulation film including silicon oxide on the oxide semiconductor film, a gate electrode overlapping with at least the oxide semiconductor film on the gate insulation film, and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. The oxide semiconductor film overlapping with at least the gate electrode includes a region in which silicon concentration from an interface between the oxide semiconductor film and the gate insulation film to the oxide semiconductor film is distributed at concentration of 1.1 atomic% or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in such electronic devices. Silicon-based semiconductor materials are widely known, but oxide semiconductor materials are also attracting attention. It has been done.

[0004] For example, indium (In), gallium (Ga), and nickel are used as the active layer of a transistor. A transistor using an amorphous oxide containing lead (Zn) has been disclosed (see Patent Document 1). ).

[0005] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. It also has high on-state characteristics (on-state current, etc.).

[0006] Regarding the oxide semiconductor used in such a transistor, It is insensitive to sodium, and there is no problem even if a considerable amount of metal impurities are contained in the film. "Inexpensive soda-lime glass, which contains a large amount of alkali metals such as ammonium, can also be used." It is also stated (see Non-Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Non-patent literature]

[0008] [Non-Patent Document 1] Kamiya, Nomura, and Hosono, "Physical Properties of Amorphous Oxide Semiconductors and Current Status of Device Development," Solid State Physics, September 2009, Vol. 44, pp. 621-633 Summary of the Invention [Problem to be solved by the invention]

[0009] However, the conventional technical understanding that oxide semiconductors are insensitive to impurities is not accepted. Therefore, the device structure and process of a transistor using an oxide semiconductor film are designed. The resistance of the source and drain regions increases, and the on-current decreases below the designed value. Problems occur.

[0010] In view of the above problem, one embodiment of the disclosed invention is a transistor including an oxide semiconductor film. Another object is to improve the performance of a semiconductor device that is configured using this transistor. For example, a decrease in on-state current of a transistor including an oxide semiconductor film can be suppressed. One of the objectives of the present invention is to improve the operating characteristics of a semiconductor device that is configured using such transistors. Let's say. [Means for solving the problem]

[0011] The present inventors have found that the oxide semiconductor film can be formed by adding impurities such as silicon to the oxide semiconductor film. It was found that the sheet resistance of the nitride semiconductor film increases.

[0012] To miniaturize a transistor using an oxide semiconductor film, the thickness of the oxide semiconductor film must be made as thin as possible. It is desirable to reduce the thickness (which can suppress, for example, short channel effects). In addition, in miniaturizing transistors, it is necessary to form a source region and a drain region in an oxide semiconductor film. In order to form the region in a self-aligned manner, the transistor structure is a top gate structure (staggered type). It is generally formed by the following structure.

[0013] In the top-gate structure, a gate insulating film is formed on an oxide semiconductor film. The sputtering method is used as one of the film formation methods. When formed by sputtering, the The element might be incorporated into the oxide semiconductor film.

[0014] Usually, the channel region is formed in the oxide semiconductor film near the interface with the gate insulating film. The constituent elements of the gate insulating film are incorporated into the oxide semiconductor film near the interface with the gate insulating film. When this is done, the region functions as a highly resistant oxide semiconductor film containing impurities such as silicon. This leads to a decrease in the on-state current and other degradation of the electrical characteristics of the transistor. This could be a factor in causing this.

[0015] In view of the above problem, in one embodiment of the disclosed invention, It suppresses impurities such as silicon from being absorbed into the vicinity.

[0016] That is, one embodiment of the present invention is a method for manufacturing a semiconductor device using an oxide semiconductor film and an oxide film containing silicon on the oxide semiconductor film. a gate insulating film including an oxide and a gate insulating film overlapping at least the oxide semiconductor film on the gate insulating film; a source electrode and a drain electrode electrically connected to the oxide semiconductor film; At least the oxide semiconductor film overlapping with the gate electrode is formed from the interface with the gate insulating film. A semiconductor device having a region in which the silicon concentration is distributed at a concentration of 1.1 atomic percent or less toward the semiconductor membrane. It is a location.

[0017] In the above structure, the thickness of the region from the interface with the gate insulating film is 5 nm or less. The concentration of silicon in the area other than the area is the same as that of silicon in the area. It is preferable that the concentration is smaller than the concentration.

[0018] In the above structure, the concentration of silicon contained in the region is preferably 0.83 It is desirable to set the content to 0.1 atomic % or less, more preferably 0.1 atomic % or less.

[0019] In the above-described configuration, the gate insulating film contains carbon, and the carbon concentration in the region is 1. .0×10 20 atoms / cm 3 It is preferable that the following be true:

[0020] In the above, the oxide semiconductor film may be crystalline or amorphous. It may have a fine structure. [Effects of the Invention]

[0021] One embodiment of the disclosed invention is a transistor including an oxide semiconductor film or a semiconductor device including the transistor. This makes it possible to improve the performance of the semiconductor device.

[0022] Another embodiment of the disclosed invention is a method for reducing the on-state current of a transistor including an oxide semiconductor film. and improve the operating characteristics of a semiconductor device formed by the transistor. can. [Brief explanation of the drawings]

[0023] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 9] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 13] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 15] FIG. 1 illustrates an example of the configuration of a semiconductor device. [Figure 16] FIG. 1 illustrates an example of the configuration of a semiconductor device. [Figure 17] FIG. 1 illustrates an example of the configuration of a semiconductor device. [Figure 18] FIG. 1 illustrates an example of the configuration of a semiconductor device. [Figure 19] FIG. 1 illustrates an example of the configuration of a semiconductor device. [Figure 20] FIG. 1 illustrates an example of the configuration of a semiconductor device. [Figure 21] FIG. 1 illustrates an example of the configuration of a semiconductor device. [Figure 22] 1A and 1B are diagrams illustrating electronic devices. [Figure 23] 10 is a graph showing measurement results according to an example of the present invention. [Figure 24] FIG. 10 is a diagram showing calculation results according to an embodiment of the present invention. [Figure 25] FIG. 10 is a diagram showing calculation results according to an embodiment of the present invention. [Figure 26] FIG. 10 is a diagram showing calculation results according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and any deviation from the spirit and scope of the present invention is not permitted. It will be readily understood by those skilled in the art that various modifications can be made to the form and details thereof. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0025] In the embodiments described below, the same parts or parts having similar functions are referred to as the same. Reference numerals may be used in common between different drawings, and repeated explanations may be omitted.

[0026] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0027] In addition, ordinal numbers such as "first," "second," and "third" in this specification may be used to avoid confusion of elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0028] In addition, in this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." " excludes those that include other components between the gate insulating layer and the gate electrode. do not have.

[0029] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0030] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification and the like, the terms "source" and "drain" may be used interchangeably. It shall be possible.

[0031] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0032] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. and explain.

[0033] <Configuration example of semiconductor device> 1(A) and 1(B) show a top-gate structure transistor as an example of a semiconductor device. 1A and 1B show examples of a plan view and a cross-sectional view of the capacitor. It is a cross-sectional view of the cross section of the dashed line AB in FIG. To avoid this, some of the components of the transistor 150 (such as the substrate 100) It has been omitted.

[0034] The transistor 150 shown in FIGS. 1A and 1B includes an insulating film 10 on a substrate 100. 2, the oxide semiconductor film 106, the gate insulating film 108, and a film overlapping at least the oxide semiconductor film. a gate electrode 110 overlapping the oxide semiconductor film 106 and a source electrode 114 electrically connected to the oxide semiconductor film 106; a and drain electrodes 114b.

[0035] The oxide semiconductor film 106 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Note that the thickness of the oxide semiconductor film 106 is greater than 5 nm and less than 200 nm. The thickness is preferably 10 nm or more and 30 nm or less.

[0036] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0037] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure in which the amorphous phase contains crystalline and amorphous parts. The crystal part must be small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the amorphous part contained in the CAAC-OS film were The boundary between the crystal and the CAAC-OS film is not clear. Therefore, the CAAC-OS film has no grain boundary. The resulting decrease in electron mobility is suppressed.

[0038] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 10° to 5°.

[0039] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0040] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0041] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. is small.

[0042] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions contained in the sputtering target cleave from the ab plane, forming a -b Peels off as flat or pellet-shaped sputtered particles with surfaces parallel to the plane In this case, the plate-like sputtered particles may be transferred to the substrate while maintaining their crystalline state. By reaching the plate, a CAAC-OS film can be formed.

[0043] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0044] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0045] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When a plate-shaped sputtering particle reaches the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0046] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0047] As an example of a sputtering target, an In-Ga-Zn-O compound target is The following are the results:

[0048] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified number of moles and then pressurized. By heat treatment at a temperature between 1000℃ and 1500℃, polycrystalline In-Ga -Zn-O compound target, where X, Y, and Z are any positive numbers. , the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2 :2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. This can be changed as appropriate depending on the kit.

[0049] As shown in FIG. 1B, the oxide semiconductor film 106 has an edge portion with a tapered angle of 20° to 50°. It is preferable that the film has a taper angle. For example, the oxide semiconductor film 106 is cut in a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The inclination angle between the side surface and the bottom surface of the oxide semiconductor film 106 is shown when observed from the edge of the oxide semiconductor film 106. If the portion is vertical, oxygen is easily released from the oxide semiconductor film 106, and oxygen vacancies are easily generated. The tapered edge of the oxide semiconductor film 106 can suppress the generation of oxygen vacancies. This can reduce the occurrence of leakage current in the transistor 150.

[0050] The oxide semiconductor used for the oxide semiconductor film 106 is at least indium (In). It is preferable that the material contains In or zinc (Zn). It is particularly preferable that the material contains In and Zn. and a stabilization method for reducing variations in electrical characteristics of a transistor using the oxide semiconductor. It is preferable to have gallium (Ga) as a stabilizer in addition to the above. It is preferable to use tin (Sn) as the stabilizer. Hf, Zr, Titanium, Scandium, Yt Lithium (Y), lanthanides (e.g., cerium (Ce), neodymium (Nd), gadolinium It is preferable that the metal oxide contains one or more selected from the group consisting of gallium (Gd), magnesium (Gd), and zinc (Gd).

[0051] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-Zr-Zn oxides In-Ti-Zn oxides, In-Sc-Zn oxides, In-Y-Zn oxides, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, I n-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In -Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In- Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Y b-Zn oxide, In-Lu-Zn ​​oxide, and quaternary metal oxides, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn oxides can be used.

[0052] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements may also be included.

[0053] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. Indicates one or more metal elements, or the above-mentioned stabilizer elements In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials expressed as follows may also be used.

[0054] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, In:Ga: In-Ga-Zn with an atomic ratio of Zn=1:3:2 or In:Ga:Zn=2:1:3 It is advisable to use a base oxide or an oxide having a composition close to that of the base oxide.

[0055] The gate insulating film 108 is preferably an oxide insulating film having sufficient withstand voltage and insulating properties. When the gate insulating film 108 has a single layer structure, it is preferable to use a film such as a silicon oxide film. An insulating film containing an oxide containing silicon may be used.

[0056] The gate insulating film 108 may have a stacked structure. In this case, gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxynitride are used. Aluminum oxide, yttrium oxide, lanthanum oxide, or silicon nitride oxide is used as the silicon oxide. In addition, hafnium oxide and hafnium silicate (HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate (HfSiO x N y (x >0, y>0), hafnium aluminate (HfAl x O y (x>0, y>0) etc. The high-k material can be stacked on silicon oxide. This can reduce the gate leakage current.

[0057] By using an oxide insulating film as the gate insulating film 108, the oxide insulating film can be heated. Since oxygen can be released by the above reaction, oxygen is supplied to the oxide semiconductor film 106. In particular, oxygen vacancies in the gate insulating film 106 can be compensated for. It is preferable that oxygen is present in the bulk of 8 in an amount exceeding the stoichiometric ratio. For example, the gate insulating film 108 may be made of SiO 2+α (However, α>0) It is preferable to use a silicon oxide film as the gate insulating film 108. By using the oxide semiconductor film 106 as a cathode, oxygen can be supplied to the oxide semiconductor film 106. The transistor 150 using the film 106 can have good transistor characteristics.

[0058] The above-mentioned "releasing oxygen by heat treatment" refers to the TDS (Thermal Dispersion Strength) Thermal desorption spectroscopy (TDA) was used to measure the release of oxygen molecules. Output is 1.0 x 10 18 molecule / cm 3 or more, preferably 3.0 × 10 19 molecule / cm 3 Below or more preferably 1.0 × 10 20 molecule / cm 3 This means that the above is the case.

[0059] However, when a silicon oxide film is used as the gate insulating film 108, Silicon or the like in the oxide semiconductor film 106 may be introduced as an impurity. When silicon or the like is introduced into the oxide semiconductor film 106 as an impurity, the oxide The resistance of the semiconductor film 106 increases.

[0060] In view of this, in the semiconductor device described in this embodiment, the gate insulating film 108 and the oxide semiconductor film 1 The purpose is to suppress impurities such as silicon that are trapped near the interface of the oxide semiconductor. In the conductive film 106, from the interface with the gate insulating film 108 toward the oxide semiconductor film 106 A region in which the silicon concentration is distributed at a concentration of 1.1 atomic % or less is formed. In this example, the region is referred to as region 106a. The concentration is more preferably 0.83 atomic % or less, and even more preferably 0.1 atomic % or less. The region 106a has a thickness of 5 nm or less from the interface with the gate insulating film 108. It is preferred that the .alpha.-

[0061] Note that the region other than the region 106a of the oxide semiconductor film 106 is denoted as a region 106b. The concentration of silicon contained in the region 106b is smaller than the concentration of silicon contained in the region 106a. It gets smaller.

[0062] Furthermore, if the gate insulating film 108 contains impurities such as carbon, this also interacts with the silicon. Similarly, there is a risk that the oxide semiconductor film 106 will be taken in as an impurity. The carbon concentration in 06a is 1.0×10 20 atoms / cm 3 Below, more preferably 1.0×10 19 atoms / cm 3 The following applies.

[0063] In this way, impurities such as silicon are taken into the region 106a of the oxide semiconductor film 106. By reducing the on-state current of the transistor 150 including the oxide semiconductor film 106, Therefore, the semiconductor device configured by the transistor 150 can suppress the decrease. The operation characteristics of the device can be improved. Alternatively, the performance of a semiconductor device including the transistor can be improved.

[0064] Note that details of the other components will be described later in the manufacturing method of the transistor 150. This will be explained with reference to FIGS. 2(A) to 3(D).

[0065] Note that an insulating film or a planarizing insulating film may be further provided on the transistor 150. .

[0066] An example of a manufacturing process of the transistor 150 shown in FIG. 1 will be described below with reference to FIGS. 2 and 3. explain.

[0067] <Fabrication process of the transistor 150> First, a substrate 100 having an insulating surface is prepared, and an insulating film 102 is formed on the substrate 100 ( See Figure 2(A).

[0068] There is no significant limitation on the substrate that can be used for the substrate 100 having an insulating surface. In either case, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as aluminoborosilicate glass and aluminoborosilicate glass, ceramic substrates, A substrate such as a quartz substrate or a sapphire substrate can be used. For example, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, silicon gate It is also possible to use a compound semiconductor substrate such as an arsenic substrate, an SOI substrate, or the like.

[0069] A flexible substrate may be used as the substrate 100. When a flexible substrate is used, A transistor including the oxide semiconductor film 106 may be directly formed on a substrate. A transistor including an oxide semiconductor film 106 is formed on a substrate, and then the substrate is peeled off and transferred to a flexible substrate. In order to separate and transfer the film from the formation substrate to the flexible substrate, the film may be formed by separating the film from the formation substrate and the oxide film. A peeling layer may be provided between the semiconductor film 106 and the transistor.

[0070] The insulating film 102 prevents the diffusion of impurities (such as hydrogen and moisture) from the substrate 100. The silicon nitride film, silicon oxide film, silicon nitride oxide film, or silicon oxynitride film It can be formed by a single layer structure or a laminated structure using one or more films selected from the By using an oxide insulating film as the insulating film 102, the insulating film 102 can be easily formed by heat treatment, which will be described later. Therefore, part of the oxygen in the oxide insulating film can be released. By supplying oxygen to the oxide semiconductor film 106, oxygen vacancies in the oxide semiconductor film 106 can be filled. It is preferable that oxygen exists in the insulating film 102 (in the bulk) in an amount exceeding at least the stoichiometric ratio. Preferably, the insulating film 102 is made of, for example, SiO 2+α (where α>0) It is preferable to use a silicon film. As a result, oxygen can be supplied to the oxide semiconductor film 106 by heat treatment as described above. Therefore, the transistor 150 including the oxide semiconductor film can have good transistor characteristics. It is possible.

[0071] Before forming the insulating film 102 on the substrate 100 or after forming the oxide semiconductor film 101 on the insulating film 102, Before depositing 06, reverse sputtering is performed by introducing argon gas to generate plasma. Powdery substances (particles, dust, etc.) adhering to the surface of the substrate 100 and the surface of the insulating film 102 It is preferable to remove the organic matter (also called a SiO2) and the organic matter. This method involves forming plasma near the substrate and modifying the surface of the substrate. Additionally, gases such as nitrogen, helium, and oxygen may be used.

[0072] In addition, when the oxide semiconductor film 106 is formed on the insulating film 102 in a later step, the oxide semiconductor In order to minimize the amount of hydrogen or water contained in the oxide semiconductor film 106, As a pretreatment for the film formation process of 6, an insulating film 102 is formed in a preheating chamber of a sputtering device. The substrate is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 100 and the insulating film 102 are removed. It is preferable that the exhaust means provided in the preheating chamber has the ability to exhaust moisture. High-power cryopumps and high-power sputter ion pumps (simply ions) It is effective to combine it with an inert gas. By removing impurities while introducing air, the desorption rate of moisture and other impurities that are difficult to desorb by exhaust alone is increased. The degree can be further increased.

[0073] Note that the insulating film 102 is not necessarily provided. When the thin substrate 100 is used, the insulating film 102 may not be provided.

[0074] Next, an oxide semiconductor film 106 is formed over the insulating film 102 (see FIG. 2B). The thickness of the semiconductor film 106 is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less. More preferably, the thickness is 1 nm or more and 10 nm or less, and even more preferably, the thickness is 3 nm or more and 7 nm or less. When the oxide semiconductor film 106 has the above thickness, the transistor 150 The short channel effect can be suppressed.

[0075] As described above, the oxide semiconductor film 106 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or The oxide semiconductor film is preferably in a CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor tor) membrane.

[0076] In this embodiment, an In—Ga—Zn-based oxide target is used for the oxide semiconductor film 106. The oxide semiconductor film 106 is formed by a sputtering method using a rare gas (typically In general, the gas is heated under an atmosphere of argon, oxygen, or a mixture of rare gas and oxygen. It can be formed by sputtering.

[0077] In order to form an In-Ga-Zn-O film as the oxide semiconductor film 106 by a sputtering method, The target is, for example, an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. The target has an atomic ratio of In:Ga:Zn=3:1:2, and the target has an atomic ratio of In:Ga:Zn=3:1:2. Oxide targets with an In:Ga:Zn=1:3:2 atomic ratio or In:Ga:Zn=2 However, the oxide semiconductor film 106 can be formed by using an oxide target with a composition of 1:1:3. The target is not limited to these target materials and compositions.

[0078] The relative density of the oxide target is 90% or more and 100% or less, preferably 95% or more and 95% or less. By using an oxide target with a high relative density, the oxide film formed is The compound semiconductor film 106 can be a dense film.

[0079] The sputtering gas used in forming the oxide semiconductor film 106 is hydrogen, water, a hydroxyl group, or It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0080] When a large amount of hydrogen is contained in the oxide semiconductor film 106, hydrogen is bonded to the oxide semiconductor. As a result, some of the hydrogen atoms become donors, generating electrons as carriers. The threshold voltage of the transistor is shifted in the negative direction. At 106, the hydrogen concentration is 5 x 10 18 atoms / cm 3 Less than 1x1 0 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 below, More preferably, 1 × 10 16 atoms / cm 3 It is desirable to do the following. The hydrogen concentration in the oxide semiconductor film was measured by secondary ion mass spectrometry (SIMS). It is measured by ion mass spectrometry (Ion Mass Spectrometry).

[0081] Note that when the oxide semiconductor film 106 contains an alkali metal or an alkaline earth metal, By bonding with the oxide semiconductor, carriers can be generated, Therefore, in the oxide semiconductor film 106, an alkali metal oxide is used. The concentration of alkali or alkaline earth metals is 1 x 10 18 atoms / cm 3Below, preferably 2×10 16 atoms / cm 3 It is desirable to do the following:

[0082] The oxide semiconductor film 106 was formed by holding the substrate 100 in a film formation chamber maintained under reduced pressure. At this time, the film may be formed while heating the substrate 100. The substrate temperature is set to 100° C. or higher and the distortion point of the substrate 100 or lower. By forming the oxide semiconductor film 106 from the oxide semiconductor film 106, impurities such as hydrogen and moisture contained in the oxide semiconductor film 106 can be prevented. The concentration of sulphuric acid can be reduced (this can also be expressed as dehydration treatment or dehydrogenation treatment). This is preferable because it reduces damage caused by sputtering. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the target. An oxide semiconductor film 106 is formed on the substrate 100. In order to remove residual moisture in the film formation chamber, Adsorption type vacuum pumps, such as cryopumps, ion pumps, and titanium sublimation pumps It is preferable to use a pump. The exhaust means is a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may be filled with, for example, hydrogen atoms. Compounds containing hydrogen atoms, such as water (HO) (and more preferably compounds containing carbon atoms) Since the gases such as hydrogen and moisture contained in the oxide semiconductor film 106 formed in the deposition chamber are exhausted, The concentration of impurities such as

[0083] After the oxide semiconductor film 106 is formed, the oxide semiconductor film 106 is subjected to heat treatment. The temperature of the heat treatment may be 300°C or higher and 700°C or lower, or lower than the strain point of the substrate. By carrying out this heat treatment, it is possible to remove excess hydrogen (including water and hydroxyl groups). be.

[0084] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, etc., and heating the object in a nitrogen atmosphere. The oxide semiconductor film 106 is heated to 450° C. for 1 hour. Do not allow it to come into contact with water or hydrogen.

[0085] Heat treatment equipment is not limited to electric furnaces, and may be heat conduction or heat radiation from a medium such as heated gas. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. or an inert gas such as nitrogen that does not react with the material to be treated by heat treatment. It is used.

[0086] For example, the heat treatment may involve placing the object to be treated in a heated inert gas atmosphere for several minutes. After heating, the object to be treated may be subjected to GRTA treatment, in which the object to be treated is removed from the inert gas atmosphere. GRTA treatment enables high-temperature heat treatment in a short time. It is possible to apply this method even under temperature conditions exceeding 1000 K. During the treatment, inert gas and oxygen are not used. Alternatively, the gas may be switched to one containing

[0087] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0088] Note that when the dehydration or dehydrogenation treatment is performed, the main component material of the oxide semiconductor film is There is a risk that some oxygen atoms are simultaneously released and reduced. Oxygen vacancies exist at the locations where the oxygen is removed, and the electrical characteristics of the transistor are affected by the oxygen vacancies. Therefore, when dehydration or dehydrogenation treatment is performed, It is preferable to supply oxygen into the oxide semiconductor film 106. By supplying oxygen, oxygen vacancies in the film can be compensated for.

[0089] As a method for filling the oxygen vacancies in the oxide semiconductor film 106, for example, After dehydration treatment (dehydrogenation treatment) of 06, high-purity oxygen gas and hypochlorous acid gas are added to the same furnace. Nitrogen dioxide gas, high purity nitrous oxide gas, or ultra dry air (CRDS (cavity ring die) The moisture content measured using a dew point meter using the wind laser spectroscopy method was 20 ppm (dew point equivalent). (Air temperature -55°C or less, preferably 1 ppm or less, more preferably 10 ppb or less) It is necessary to introduce oxygen gas or nitrous oxide gas that does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or less. or more, preferably 7N or more (i.e., impurity concentration in oxygen gas or nitrous oxide gas is 1pp m or less, preferably 0.1 ppm or less).

[0090] In addition, as a method for supplying oxygen into the oxide semiconductor film 106, In addition to the method of heating in an atmosphere, the oxide semiconductor film 106 may be heated by adding oxygen (at least oxygen radicals). By adding oxygen atoms, oxygen atoms, or oxygen ions, the oxide semiconductor film 10 Oxygen may be supplied into the layer 6. The oxygen addition method may include ion implantation, ion doping, etc. using methods such as plasma immersion ion implantation and plasma treatment. .

[0091] As described above, the oxide semiconductor film 106 after deposition is subjected to dehydration treatment (dehydrogenation treatment). Hydrogen or moisture is removed from the oxide semiconductor to purify it so that it contains as few impurities as possible. The oxide semiconductor, which is simultaneously reduced by the dehydration treatment (dehydrogenation treatment), Supplying oxygen, the main component material (this can also be expressed as over-oxygenation), compensates for oxygen deficiency. By this, the oxide semiconductor film 106 can be made i-type (intrinsic) or nearly i-type. By doing so, the Fermi level (Ef) of the oxide semiconductor film can be adjusted to the intrinsic Fermi level (Ef). Therefore, the oxide semiconductor film can be formed into a ternary oxide film. By using it in transistors, the threshold voltage Vth of the transistor caused by oxygen vacancies can be reduced. The fluctuation and the threshold voltage shift ΔVth can be reduced.

[0092] For this reason, dehydration treatment (dehydrogenation treatment) is performed before the step of supplying oxygen to the oxide semiconductor film 106. It is preferable to carry out the following.

[0093] By the way, oxygen has 17 O and 18 There are isotopes such as O, and their existence in nature The respective proportions of oxygen atoms are known to be approximately 0.037% and 0.204% of the total oxygen atoms. In other words, the concentrations of these isotopes in the oxide semiconductor film can be measured by a method such as SIMS. Therefore, by measuring these concentrations, it is possible to estimate the oxide semiconductor It may be possible to estimate the oxygen concentration in the conductive film more accurately. The measurement of the oxygen concentration can be used as a basis for determining whether oxygen has been intentionally added to the oxide semiconductor film. It can also be used as follows.

[0094] Note that in the above description, the oxide semiconductor film 106 is subjected to dehydrogenation treatment and peroxidation treatment before being processed into an island shape. However, one embodiment of the disclosed invention is not limited to this. This treatment may be performed after the oxide semiconductor film 106 is processed into an island shape.

[0095] Next, the oxide semiconductor film 106 is photolithographically separated into island-shaped oxide semiconductor films 10 6 (see FIG. 2C). The resist mask may be formed by an ink-jet method. When the oxidation method is used, no photomask is used, which reduces the manufacturing cost. The etching of the compound semiconductor film 106 may be dry etching or wet etching. Both may be used.

[0096] Here, as shown in FIG. 2C, the oxide semiconductor film 106 has an edge portion with a tilt angle of 20° to 50°. When the edge of the oxide semiconductor film 106 is perpendicular, the oxide semiconductor film 106 is easily oxidized. Oxygen is easily released from the oxide semiconductor film 106, which easily causes oxygen vacancies. By providing a tapered angle at the end of the transistor 150, the occurrence of oxygen vacancies is suppressed. This can reduce the occurrence of leakage current.

[0097] Next, an insulating film 107 for forming a gate insulating film 108 is formed on the oxide semiconductor film 106. Here, the thickness of the insulating film 107 is, for example, 1 nm to 50 nm. The insulating film 107 can be formed by, for example, sputtering. The film is formed by appropriately using the deposition method, MBE method, CVD method, pulsed laser deposition method, ALD method, etc. It is possible.

[0098] The insulating film 107 is preferably an oxide insulating film that has sufficient withstand voltage and insulating properties. When the insulating film 107 has a single layer structure, for example, a silicon film such as a silicon oxide film is used. An insulating film containing an oxide containing fluorine may be used.

[0099] The insulating film 107 may have a layered structure. Gallium, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride , yttrium oxide, lanthanum oxide, or silicon oxynitride is stacked on silicon oxide. In addition, hafnium oxide and hafnium silicate (HfSi x O y x>0, y >0), nitrogen-doped hafnium silicate (HfSiO x N y (x>0, y>0 )), hafnium aluminate (HfAl x O y(x>0, y>0) The high-k material can be stacked on silicon oxide. The leak current can be reduced.

[0100] Note that by using an oxide insulating film as the insulating film 107, similar to the insulating film 102, By the treatment, part of the oxygen in the oxide insulating film is released, and oxygen is introduced into the oxide semiconductor film 106. By supplying oxygen, oxygen vacancies in the oxide semiconductor film 106 can be filled. In this regard, the description of the insulating film 102 can be referred to, and the insulating film 107 is subjected to heat treatment. There is no particular limitation on the timing as long as it is after the insulating film 107 is formed.

[0101] In particular, the insulating film 107 (bulk) contains oxygen in an amount exceeding the stoichiometric ratio. For example, the insulating film 107 is preferably made of SiO 2+α (where α>0) It is preferable to use a silicon oxide film that can be formed by the insulating film 107. By using the oxide semiconductor film 106 as the oxide semiconductor film 106, oxygen can be supplied to the oxide semiconductor film 106. The transistor characteristics of the transistor 150 using the conductive film 106 can be improved. .

[0102] As described above, the insulating film 107 is an insulating film containing oxygen in an amount exceeding the stoichiometric ratio. In order to form the insulating film 107 as a film, it is preferable to form the insulating film 107 by a sputtering method. In addition, when the sputtering method is used, a film forming apparatus using high purity gas as described above is required. The film is formed by baking the substrate, evacuating impurities with an exhaust system, and preheating the substrate. By removing impurities such as hydrogen and moisture from the device as much as possible, the hydrogen and moisture in the insulating film 107 From this point of view, the concentration of the component can be kept low. It is preferable to form the film by sputtering.

[0103] Note that before the oxide semiconductor film 106 was formed, argon gas was introduced to generate plasma. The powdery substances (particles) adhering to the surface of the gate insulating film 108 are removed by reverse sputtering. It is preferable to remove the particles (also called dust or rubbish). This method involves forming plasma near the substrate and modifying the surface of the substrate. Alternatively, gases such as nitrogen, helium, and oxygen may be used.

[0104] As described above, when the insulating film 107 is formed using a sputtering apparatus, the insulating film 107 When a constituent element of the oxide semiconductor film 106, such as silicon, collides with the oxide semiconductor film 106, the element The contamination phenomenon may occur when the insulating film 1 In the oxide semiconductor film 106 near the interface with SiO 2 , specifically in the region 106a In the transistor described in this embodiment, the gate insulating film 108 Since a channel region is formed in the oxide semiconductor film 106 nearby, the gate insulating film 108 The constituent elements are mixed into the region as impurities, which can affect the on-state characteristics of the transistor ( For example, this can cause a decrease in on-state current. What kind of characteristic changes occur in the oxide semiconductor film 106 due to the inclusion of impurities such as silicon? The details of how this occurs will be explained in Example 1.

[0105] The above-described phenomenon of the constituent elements of the insulating film 107 being mixed into the oxide semiconductor film 106 is The oxide semiconductor film 106 may be formed in the vicinity of the interface with the insulating film 107. If the impact of the constituent elements on the oxide semiconductor film is weakened and an insulating film is formed, For example, the film-forming power of the device for forming the insulating film may be reduced. The insulating film is formed near the interface with the oxide semiconductor film 106, and then the film formation power is increased. An insulating film may be further formed on the insulating film 107. The deposition pressure of the deposition apparatus is increased to deposit an insulating film near the interface with the oxide semiconductor film 106, and After that, the film formation pressure may be lowered and an insulating film may be further formed to form the insulating film 107. In addition, the distance between the TSs of the device for forming the insulating film is increased to prevent the interface with the oxide semiconductor film 106 from being broken down. By forming an insulating film near the surface, and then narrowing the TS distance and forming another insulating film, An insulating film 107 may be formed.

[0106] For example, when the insulating film 107 is formed using a sputtering device, the specific power for film formation is The numerical value is 10 kW or less, preferably 1 kW or less, more preferably 500 W or less, and even more preferably 100 W or less. It is preferable that the power for forming the insulating film is set to 200 W or less. In addition, if the deposition power is too low, the sputtering equipment This makes it difficult to generate plasma inside the device, increasing the possibility that film formation processing will not be carried out normally. Therefore, the deposition power should be 5% or more of the maximum power that can be applied to the sputtering equipment used. The extent to which the film formation power should be reduced depends on the sputtering equipment. In consideration of the performance of the device and the thickness of the insulating film 107, the film can be formed normally and The time is within a range that does not have a significant effect on the manufacturing process (takt time) of the transistor 150. The implementer can select the optimum power value as appropriate within this range.

[0107] When the insulating film 107 is formed using a sputtering device, the specific number of the film formation pressure is The value is 0.4 Pa or more, preferably 1.0 Pa or more, and more preferably 2.0 Pa or more. It is more preferable that the pressure is 5.0 Pa or more. However, the quality of the film formed tends to deteriorate (for example, the film quality becomes sparse). It is desirable that the film formation pressure be 100 Pa or less. In this regard, in consideration of the properties required for the insulating film 107 (for example, field effect mobility, etc.), The operator can select the optimum pressure value as appropriate.

[0108] In addition, when the insulating film 107 is formed using a sputtering device, the specific distance between the TSs is The appropriate value is 30 mm or more, preferably 50 mm or more, and more preferably 100 mm or more. It is more preferable to set the distance between the TSs to 300 mm or more. The longer the distance between the TSs, the lower the deposition rate of the insulating film 107. The extent to which the distance between TSs should be widened depends on the film formation. The time is within a range that does not have a significant effect on the manufacturing process (takt time) of the transistor 150. The implementer can select the optimum inter-TS distance as appropriate within this range.

[0109] Note that in order to weaken the force with which elements constituting the insulating film 107 collide with the oxide semiconductor film 106, To achieve this, one of the conditions, deposition power, deposition pressure, or TS distance, is set within the above range. Alternatively, the insulating film 107 may be formed by setting a plurality of conditions within the above ranges. You may do so.

[0110] The sputtering device used was a magnetron sputtering device in which the target and the substrate to be deposited were placed approximately parallel to each other. When using a magnetron sputtering device (also simply called a magnetron sputtering device), In this case, the oxide semiconductor film 106 contains elements other than those constituting the insulating film 107, such as plasma and secondary electric Since the elements included in the insulating film 107 are collided with the oxide semiconductor film 106, the elements are very likely to be present in the oxide semiconductor film 106. Therefore, the sputtering equipment for forming the insulating film 107 is in a state where the insulating film 107 is easily mixed in. The equipment is a facing target sputtering device (such as a mirrortron sputtering device or a naturaltron sputtering device). The device has two targets. The substrate to be coated is placed in a space other than the space between the two targets. The target is placed almost perpendicular to the target. A high density plasma is generated between the target and the insulating film 107. The surface of the target is sputtered, and an insulating film 107 is formed on the substrate. Therefore, the substrate on which the film is to be formed is not directly exposed to plasma or secondary electrons (or or very little).

[0111] When the insulating film 107 is formed by a sputtering method in a rare gas atmosphere, Helium may be used instead of argon. Since argon has a larger atomic number than helium, Therefore, when argon ions collide with the oxide semiconductor film 106 near the interface with the insulating film 107, The bonds of the oxide semiconductor film 106 are broken, and the constituent elements of the insulating film 107 are released from the broken bonds. The rare gas ions may be mixed into the compound semiconductor film 106. This makes it possible to suppress the above-mentioned disconnection of bonds, and therefore the constituent elements of the insulating film 107 This can prevent the elements from being mixed into the oxide semiconductor film 106. In the vicinity of the interface with 6, the insulating film is formed in a helium atmosphere, and then the film formation chamber is The insulating film 107 may be formed by switching to an argon atmosphere and depositing an insulating film. This makes it possible to improve the speed at which the insulating film 107 is formed.

[0112] The insulating film 107 is formed by ALD (Atomic Layer Deposition). Alternatively, the oxide semiconductor film 106 may be formed by a method that causes less impact on the oxide semiconductor film 106, such as evaporation or coating.

[0113] As described above, the collision force of the elements forming the insulating film 107 with the oxide semiconductor film 106 is weakened. By forming the insulating film 107, the oxide semiconductor film 106 can be formed as described above. The silicon concentration is 1.1 atomic % from the interface with the insulating film 107 toward the oxide semiconductor film 106. and a region 106a in which the silicon concentration is distributed at a concentration lower than that of the region 106a. Here, the region 106b is a region of the oxide semiconductor film 106. The area other than 106a is the area other than 106a. The concentration of silicon contained in the area 106b is 0 It is more preferable that it is 0.1 atomic % or less.

[0114] In addition, by forming the oxide semiconductor film 106 in this manner, the oxide semiconductor contained in the insulating film 107 The incorporation of impurities such as carbon into the oxide semiconductor film 106 is also reduced. The carbon concentration in the region 106a is 1.0×10 20 atoms / cm 3 Below, more preferred Preferably 1.0 x 10 19atoms / cm 3 The following is the result.

[0115] In this way, impurities such as silicon are taken into the region 106a of the oxide semiconductor film 106. By reducing the on-state current of the transistor 150 including the oxide semiconductor film 106, Therefore, the semiconductor device configured by the transistor 150 can suppress the decrease. The operation characteristics of the device can be improved. Alternatively, the performance of a semiconductor device including the transistor can be improved.

[0116] In addition, the energy of the elements constituting the insulating film 107 colliding with the oxide semiconductor film 106 is weakened. By forming the insulating film 107, the elements constituting the oxide semiconductor film 106 are formed in the insulating film 107. This also prevents the oxide semiconductor film 106 from being mixed into the insulating film 107. Since highly conductive elements such as constituent metal elements are prevented from being mixed in, the insulating film 10 Therefore, it is possible to prevent a decrease in the resistivity of the gate insulating film 108 formed using the silicon nitride film 7.

[0117] Next, a gate electrode 110 (including wiring formed in the same layer) is formed on the insulating film 107. A conductive film 109 for forming the conductive film 109 is formed (see FIG. 3A). For example, molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, Metallic materials such as scandium or alloy materials containing these as the main component can be used. The conductive film used for the gate electrode may be formed using a conductive metal oxide. Metal oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide. (ZnO), indium tin oxide (In2O3-SnO2, sometimes abbreviated as ITO) Indium zinc oxide (In2O3-ZnO), or these metal oxide materials The gate electrode can be made of a material containing silicon or silicon oxide. The above-mentioned materials can be used to form a single layer or a laminated layer. It is possible to use various film formation methods such as evaporation, CVD, sputtering, and spin coating. It is possible.

[0118] Furthermore, a layer of the gate electrode 110 in contact with the gate insulating film is made of a metal oxide containing nitrogen, Specifically, nitrogen-containing In-Ga-Zn-O films, nitrogen-containing In-Sn-O films, and nitrogen-containing In-Ga-Zn-O films are used. In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen, An In-O film containing nitrogen or a metal nitride film (InN, SnN, etc.) can be used. These films have a work function of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the threshold voltage of the transistor is increased. This makes it possible to realize a so-called normally-off switching element.

[0119] Next, a resist mask is formed over the conductive film 109 by a photolithography process. Then, the gate electrode 110 and the gate insulating film 108 are formed by etching the resist. The mask is removed (see FIG. 3(B)). A resist mask for forming the film 108 may be formed by an ink-jet method. When the photomask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. The gate electrode 110 and the gate insulating film 108 are etched by dry etching. Either etching or wet etching may be used, or both may be used.

[0120] Next, the resistance of the oxide semiconductor film 106 is reduced by ion doping or ion implantation. The impurity ions 130 having a function of imparting a hydrogen atom to the oxide semiconductor film 106 are added to the oxide semiconductor film 106. The gate electrode 110 and the gate insulating film 108 function as a mask, so that the oxide semiconductor film A low resistance region 106c is formed in a self-aligned manner in 106 (see FIG. 3(C)). The impurity ions 130 include group 15 elements (typically phosphorus (P), arsenic (As), and and antimony (Sb), boron (B), aluminum (Al), nitrogen (N), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), salt One or more selected from the group consisting of silicon (Cl), titanium (Ti), and zinc (Zn) are used. The ion implantation method uses a mass separator that extracts only the necessary ions. Therefore, only the impurity ions 130 can be selectively added to the object. The amount of impurities (e.g., This is preferable because it reduces the amount of contamination by gases such as hydrogen. However, this does not include the ion doping method. The low-resistance region 106c is formed by the oxide semiconductor film 106 (first region 106a and the second region 106b) are implanted with impurity ions 130 to form the low resistance region 106 As shown in FIG. 3(C), the low resistance region 106c is not transformed into the region 106c. There are regions 106a and 106b.

[0121] Next, a source electrode and a drain electrode (formed in the same layer as this) are formed on the oxide semiconductor film 106. Conductive films are deposited to be used for the source and drain electrodes (including wiring). The film may be made of, for example, aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. a metal film containing an element selected from the group consisting of tin and tin, or a metal nitride film containing the above-mentioned elements as a component; (titanium nitride film, molybdenum nitride film, tungsten nitride film) and the like can be used. In addition, titanium, molybdenum, etc. may be applied to either or both of the upper and lower sides of the metal film such as aluminum or copper. High-melting metal films such as titanium nitride film, tungsten film, etc., or their metal nitride films (titanium nitride film, nitride film, etc.) A structure in which a layer of a molybdenum film, a tungsten nitride film, etc. is laminated may also be used. The conductive film used for the gate and drain electrodes may be formed of a conductive metal oxide. Metal oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (Z nO), indium tin oxide (In2O3-SnO2, abbreviated as ITO), The source and drain electrodes can be made of In2O3-ZnO. The conductive film used for the electrode can be formed as a single layer or a laminated layer using the above materials. The deposition method is not particularly limited, and may be a vapor deposition method, a CVD method, a sputtering method, a spin coating method, or the like. Various film formation methods can be used.

[0122] Then, a resist mask is formed on the conductive film by a photolithography process, and selective etching is performed. After etching to form the source electrode 114a and the drain electrode 114b, a resist mask is applied. The mask is removed to form the transistor 150 (see FIG. 3(D)). In the photolithography process, ultraviolet rays and KrF lasers are used for exposure when forming resist masks. It is preferable to use laser light or ArF laser light. The gap between the lower end of the source electrode 114a and the lower end of the drain electrode 114b is The channel length L of the transistor is determined. Therefore, exposure to light with a channel length L of less than 25 nm For example, extreme ultraviolet rays with extremely short wavelengths of several nm to several tens of nm are used. Resist mask shape in photolithography process using Ultraviolet Exposure with extreme ultraviolet light has high resolution and a large depth of focus. This allows the channel length L of the transistor to be formed later to be miniaturized, The operating speed can be increased.

[0123] Note that from the viewpoint of suppressing a decrease in the on-state current of the transistor 150, the oxide semiconductor film 10 6, the end of the portion overlapping with the gate electrode 110, and the source portion of the oxide semiconductor film 106. The gap between the end of the part in contact with the electrode 114a closest to the gate electrode (see FIGS. 3(D) and 1 The X portion of (A). In this specification, this portion is referred to as the "Loff width.") and The end of the oxide semiconductor film 106 overlapping with the gate electrode 110 and the oxide semiconductor film 1 The gap between the end of the part of the gate electrode 114b that is in contact with the drain electrode 114b and the end closest to the gate electrode (see FIG. 3(D) and the Y portion of FIG. 1(A). This portion is also referred to as the "Loff width" in this specification. It is preferable that the X and Y portions in FIG. 3(D) are as small as possible. As a method for reducing the size, for example, the formation of the source electrode 114a and the drain electrode 114b By using different photomasks, the Only one of the source electrode 114a and the drain electrode 114b is as close as possible to the gate electrode 110. Since alignment can be performed smoothly, the Loff width can be reduced.

[0124] In addition, from the viewpoint of reducing the tact time and cost of the transistor 150, photolithography is used. It is preferable to reduce the number of photomasks used in the process and the number of steps. As a method for reducing this, for example, a multi-layer exposure mask is used, which allows the transmitted light to have multiple intensities. The etching process can be performed using a resist mask formed by the multi-layer mask. The resist mask formed using the adjustment mask has a shape with multiple film thicknesses, and etching By performing this process, the shape can be further deformed, so multiple processes can be performed to create different patterns. Therefore, a single multi-tone mask can be used in the etching process. It is also possible to form resist masks corresponding to two or more different patterns. This reduces the number of exposure masks and the corresponding photolithography process. This makes it possible to simplify the process.

[0125] Note that when the conductive film is etched, the oxide semiconductor film 106 is etched and divided. However, it is desirable to optimize the etching conditions so that the conductive film alone does not It is difficult to achieve a condition in which the oxide semiconductor film 106 is etched without being etched at all. When the conductive film is etched, only a part of the oxide semiconductor film 106 is etched. For example, 5% to 50% of the thickness of the oxide semiconductor film 106 is etched to form a groove (a recess). ) may be formed as the oxide semiconductor film 106.

[0126] A conductive film used for the source electrode and the drain electrode (including wiring formed in the same layer as these) When an oxide semiconductor material is used as the source electrode 114a, the conductive film is etched to form the source electrode 114a. When the drain electrode 114b is formed, the oxide semiconductor film 106 is etched as much as possible. The oxide semiconductor film 106 is formed of an oxide semiconductor material that is more difficult to etch than the oxide semiconductor film 106. It is necessary to use as a conductive film.

[0127] When an oxide semiconductor material is used for the source electrode 114a and the drain electrode 114b, Depending on the material and film formation conditions of the semiconductor film 106, the source electrode 114a and the drain electrode 114b may The interface between the oxide semiconductor film 14b and the oxide semiconductor film 106 may become unclear. When this is the case, the source electrode 114a, the drain electrode 114b, and the oxide semiconductor film 106 In some cases, what can be called a mixed region or layer with the metal may be formed.

[0128] The conductive film used for the source electrode 114a and the drain electrode 114b is made of impurity ions. It is also possible to use conductive materials or semiconductor materials in which ions have been introduced to reduce the resistance.

[0129] The transistor 150 is formed by the above steps. The impurities (for example, For example, silicon, which is an element that constitutes the gate insulating film 108, is reduced. This can suppress a decrease in the on-state current of the transistor 150. The operating characteristics of the semiconductor device configured by the resistor 150 can be improved. A transistor using an oxide semiconductor film or a semiconductor including the transistor The performance of the device can be improved.

[0130] Alternatively, an insulating film may be provided over the transistor 150. The insulating film may be a gate insulating film. Since the same material and film formation method as the film 108 can be used, the above-mentioned gate insulating film 10 The aluminum oxide film is resistant to external influences such as moisture and hydrogen. Since it has a high effect of suppressing the penetration of impurities, an aluminum oxide film or It is desirable to form a laminated film including an aluminum oxide film, and more preferably, a film-tight film. The viscosity is 3.2g / cm 3 or more, preferably 3.6 g / cm 3 The above aluminum oxide film is used This prevents impurities such as moisture and hydrogen from penetrating the oxide semiconductor film 106. This can prevent the intrusion of

[0131] A planarization insulating film may be provided over the transistor 150. Apply an insulating material using a dispensing method or an inkjet method. The film may be formed by carrying out a hardening treatment (for example, a heat treatment or a light irradiation treatment) according to the material used. Examples of insulating materials include acrylic resin, polyimide resin, and poly It can be formed using organic resins such as amide resin, polyamide-imide resin, and epoxy resin. In addition, low-k materials, siloxane resins, and PSG (Lingara) It is possible to use materials such as BPSG (borophosphorus glass) and BPSG (borophosphorus glass). A planarization insulating film may be formed by laminating a plurality of insulating films. Since they often contain a large amount of metals, the insulating films mentioned above (e.g., aluminum oxide and aluminum oxide) It is preferable to form the film on a laminate film containing aluminum.

[0132] As described above, one embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor. Therefore, impurities contained in the oxide semiconductor film near the interface with the gate insulating film can be reduced. Another embodiment of the disclosed invention is a transistor including an oxide semiconductor film or a semiconductor device including the transistor. This can improve the performance of a semiconductor device constructed using the STAR.

[0133] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0134] (Embodiment 2) In this embodiment mode, a semiconductor device having a structure different from that of Embodiment Mode 1 and a manufacturing method of the semiconductor device will be described. One embodiment of this will be described with reference to FIGS.

[0135] <Configuration example of semiconductor device> 4(A) and 4(B) show a top-gate structure transistor as an example of a semiconductor device. 4A and 4B show examples of a plan view and a cross-sectional view of the capacitor. It should be noted that in FIG. 4(A), the cross section is not shown to avoid complication. In order to achieve this, some of the components of the transistor 650 (such as the substrate 100) are omitted. There are.

[0136] In the transistor 650 of this embodiment, the conductive film 602 is on the same plane as the insulating film 102 and is an insulating film. The transistor differs from the transistor described in the first embodiment in that it is provided adjacent to the film 102. There are.

[0137] Generally, a transistor using an oxide semiconductor film as an active layer has a conductive layer formed between the oxide semiconductor film and the active layer. Although the contact resistance tends to be high at the contact point with the film, the transistor with the above structure By this, the source electrode 114a and the drain electrode 114b are formed on the oxide semiconductor film 1 Since the oxide semiconductor film 106 is electrically connected not only on the front side but also on the back side, The contact resistance between the oxide semiconductor film 106 and the source electrode 114a and the drain electrode 114 The contact resistance of b can be reduced, and the variation in the contact resistance can be reduced. High-performance transistors with high on-state current and suppressed variations in threshold voltage Therefore, this structure is one of the structures suitable for a transistor using an oxide semiconductor. It can be said that.

[0138] <Manufacturing process of transistor 650> 5A to 5E, an example of a manufacturing process of the transistor 650 shown in FIG. 4 will be described. We will explain about this.

[0139] First, a conductive film is formed on the substrate 100, and a resist is formed on the conductive film by a photolithography process. A resist mask is formed, and selective etching is performed to form a conductive film 602. The mask is removed (see FIG. 5(A)). The material used for the conductive film 602 is the same as that described above. The gate electrode 110 and the source electrode 114a (or the drain electrode 114b) in the above-described embodiment The explanation can be taken into consideration.

[0140] Next, the insulating film 102 is formed over the substrate 100 and the conductive film 602 (see FIG. 5(B)). Here, the surface of the insulating film 102 is set at a position higher than the surface of the conductive film 602. It is preferable that the surface of the conductive film 602 and the insulating film 10 be planarized by a planarization treatment described later. 2 can be made substantially flush with each other. When the insulating film 106 was formed, the oxide semiconductor film was broken due to a step between the conductive film 602 and the insulating film 102. Therefore, the oxide semiconductor film 106 can be made extremely thin. Therefore, planarization is an effective method for miniaturizing transistors. can.

[0141] Next, the insulating film 102 is subjected to a planarization process to make its surface approximately flush with the surface of the conductive film 602. The insulating film 102 is formed by planarizing the insulating film 102 (see FIG. 5(C)). Chemical Mechanical Polishin It is preferable to use a CMP (chemical mechanical polishing) process. A method of flattening a surface by using a combination of chemical and mechanical processes based on a standard surface. Generally, a polishing cloth is attached to the polishing stage, and a slide is placed between the workpiece and the polishing cloth. The polishing stage and the workpiece are rotated or swung while supplying the abrasive. The surface of the workpiece is polished by a chemical reaction between the slurry and the surface of the workpiece, and by a polishing cloth and the workpiece. This is a method of polishing the surface of a workpiece by mechanical polishing.

[0142] The CMP process may be performed once or multiple times. If polishing is to be performed, first polishing should be performed at a high polishing rate, followed by finishing polishing at a low polishing rate. By combining polishing processes with different polishing rates in this way, it is possible to The flatness of the surface 602 and the surface of the insulating film 102 can be further improved.

[0143] In addition, dry etching or the like can be applied as planarization treatment of the insulating film 102. The etching gas may be chlorine, boron chloride, silicon chloride, or carbon tetrachloride. Chlorine-based gas, fluorine-based gas such as carbon tetrafluoride, sulfur fluoride or nitrogen fluoride, oxygen, etc. For example, reactive ion etching (RIE) can be used. on Etching) method, ICP (Inductively Coupled Plasma) SMA etching method, ECR (Electron Cyclotron Resona nce) etching method, parallel plate (capacitively coupled) etching method, magnetron plasma etching method, dual frequency plasma etching method, helicon wave plasma etching method, etc. Dry etching can be used. In particular, silicon nitride or nitride is used as the insulating film 102. When inorganic insulating materials containing a lot of nitrogen, such as silicon oxide, are included, CMP alone is not sufficient. Inorganic insulating materials containing a lot of nitrogen can be difficult to remove, so dry etching or other methods may be used. It is preferable to use them in combination.

[0144] In addition, plasma treatment or the like can be applied as planarization treatment of the insulating film 102. In plasma treatment, an inert gas, such as argon gas, is introduced into a vacuum chamber, and the target material is heated. The principle is the same as that of the plasma dry etching method. However, by using an inert gas, it can be processed in a normal sputtering chamber. This plasma treatment is a simple method in which ions of an inert gas are irradiated onto the surface to be treated. This is a treatment in which the surface is irradiated with light and the fine irregularities on the surface are flattened by the sputtering effect. Therefore, in this specification, this plasma treatment is also referred to as "reverse sputtering."

[0145] The conductive film 602 and the insulating film 102 are formed in an island shape as shown in FIG. 5(D). In addition, in FIG. 5C, the conductive film 602 has an edge that narrows toward the surface. As shown in Figure 5(E), the edge becomes thinner as it approaches the surface. Alternatively, the groove may be formed in a so-called reverse tapered shape, in which the groove width is wider.

[0146] For the subsequent steps, please refer to Figures 2(A) to 3(D) and the explanations of the drawings. Just do it.

[0147] Through the above steps, the transistor 650 illustrated in FIG. In addition to the features described in the first embodiment, the transistor 650 has the following characteristics: The contact resistance between the oxide semiconductor film 106 and the source electrode 114a and the contact resistance between the oxide semiconductor film 106 and the drain electrode 114b are Since the contact resistance of 14b can be reduced and the variation in the contact resistance can be reduced, To create a high-performance transistor with high current and suppressed variations in threshold voltage Therefore, the operating characteristics of the semiconductor device configured by the transistor 650 can be Furthermore, a transistor including an oxide semiconductor film or a transistor using the oxide semiconductor film can be improved. The performance of the semiconductor device constructed by the resistor can be improved. In addition, the surface of the conductive film 602 and the surface of the insulating film 102 can be made substantially flush with each other. The film 106 can be made extremely thin, making it suitable for miniaturizing transistors. It can be said to be one of the following.

[0148] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0149] (Embodiment 3) In this embodiment mode, a semiconductor device having a structure different from that of the above-described embodiment mode and a method for manufacturing the semiconductor device will be described. One embodiment of the method will be described with reference to FIGS.

[0150] <Configuration example of semiconductor device> 6(A) and 6(B) show a top-gate structure transistor as an example of a semiconductor device. 6A and 6B show examples of a plan view and a cross-sectional view of the capacitor. 6(A) is a cross-sectional view of the cross section G-H in FIG. 6(A). In order to achieve this, some of the components of the transistor 850 (such as the substrate 100) are omitted. There are.

[0151] The transistor 850 shown in FIGS. 6A and 6B includes an insulating film 10 2, the oxide semiconductor film 106, the insulating film 107, and a film overlapping at least with the oxide semiconductor film The gate electrode 110, the interlayer insulating film 800, the interlayer insulating film 802, the insulating film 107, the interlayer insulating film The insulating film 800 and the interlayer insulating film 802 are electrically connected to the oxide semiconductor film 106 through the openings. The transistor has a source electrode 114a and a drain electrode 114b connected to it.

[0152] In the transistor 850, the insulating film 107 is formed to cover the oxide semiconductor film 106. The source electrode 114a and the drain electrode 114b are formed between the insulating film 107 and the interlayer insulating film. 800 and the oxide semiconductor film 106 through the openings in the interlayer insulating film 802. This is different from the structure of the transistor described in the above embodiment in that:

[0153] The transistor 850 has a structure in which the insulating film 107 covers the oxide semiconductor film 106. This can prevent impurities such as moisture from entering the oxide semiconductor film 106. When the compound ions 130 are added to the oxide semiconductor film 106, the insulating layer 130 is not formed on the oxide semiconductor film 106. The insulating film 107 prevents damage ( For example, the occurrence of lattice defects in the oxide semiconductor film 106 can be reduced.

[0154] Also, the transistor 850 is configured such that the source electrode 114a and the drain electrode 114b are insulated. The oxide semiconductor film 107 is exposed through the openings in the interlayer insulating film 800 and the interlayer insulating film 802. By forming the oxide semiconductor film 106, The oxide semiconductor film 106 is then subjected to etching treatment (for example, etching gas during dry etching). The parts exposed to gases and plasmas, and etching agents during wet etching, etc. Since only the openings are formed in the insulating film 107, the interlayer insulating film 800, and the interlayer insulating film 802, Therefore, contamination of transistor 850 (e.g., The etching gas used in dry etching reacts with the metal element of the oxide semiconductor film 106. The resulting metal compound may be conductive, so that the source electrode 114a and the drain electrode This can suppress the leakage path of the source electrode 114b. The electrode 114a and the drain electrode 114b are formed so as to overlap with the gate electrode 110. However, the source electrode 114a and the gate electrode 110, and the drain electrode 114b and the gate electrode There is an interlayer insulating film between the layers 110, so they are not electrically connected. The source electrode 114a and the drain electrode 114b are formed as close to the gate electrode 110 as possible. Therefore, this structure is suitable for miniaturizing transistors.

[0155] <Manufacturing process of transistor 850> An example of a manufacturing process of the transistor 850 shown in FIG. 6 will be described with reference to FIGS. 7A to 8C. do.

[0156] First, an insulating film 102, an oxide semiconductor film 106, and an insulating film 107 are formed on a substrate 100. (See FIG. 7(A)). This process is shown in FIGS. 2(A) to 2(D) and the drawings. This can be done by taking into consideration the explanation provided in the previous section.

[0157] Next, a gate electrode 110 is formed on the insulating film 107, and an oxide film is formed on the gate electrode 110 as a mask. Impurity ions 130 are added to the oxide semiconductor film 106 to form a low resistance layer in the oxide semiconductor film 106. The resist region 106c is formed in a self-aligned manner (see FIG. 7(B)). This can be done by referring to Figures 3(A) to 3(C) and the explanations of the drawings.

[0158] Next, an interlayer insulating film 800 and an interlayer insulating film 810 are formed on the insulating film 107 and the gate electrode 110. 02 is formed (see FIG. 7(C)).

[0159] The interlayer insulating film 800 is made of the same material and formed by the same method as the gate insulating film 108. Therefore, the details of the gate insulating film 108 described in the above embodiment should be taken into consideration. The aluminum oxide film prevents impurities such as moisture and hydrogen from entering from the outside. Since the insulating film has a high effect of preventing the formation of a thin film, an aluminum oxide film or an aluminum oxide film is preferably used as the insulating film. It is desirable to form a laminated film containing 3 Below It is desirable to use the aluminum oxide film above. This prevents impurities such as moisture and hydrogen from being generated. can be prevented from entering the oxide semiconductor film 106.

[0160] The interlayer insulating film 802 is formed by a method such as spin coating, printing, dispensing, or inkjet printing. Apply an insulating material using a coating method, etc., and then perform a hardening process (for example, For example, the insulating material may be formed by heat treatment or light irradiation treatment. Examples of the resin include acrylic resin, polyimide resin, polyamide resin, and polyamideimide resin. It can be formed using organic resins such as oil and epoxy resin. low-k materials), siloxane resin, PSG (phosphor glass), BPSG (phosphor boron glass) It should be noted that a plurality of insulating films made of these materials can be stacked. Since the interlayer insulating film contains a relatively large amount of impurities such as moisture, It is preferable to form the film on the surface of the insulating film (for example, aluminum oxide or a laminated film containing aluminum oxide). Desirable.

[0161] In this embodiment, a laminated structure of the interlayer insulating film 800 and the interlayer insulating film 802 is formed. Only one of them may be formed.

[0162] Next, the insulating film 107 in the region overlapping with the oxide semiconductor film, the interlayer insulating film 800, and the interlayer insulating film After forming an opening in at least a part of the film 802, the oxide semiconductor film Forming a source electrode 114a and a drain electrode 114b electrically connected to 106 (See Figure 8(A)).

[0163] The insulating film 107, the interlayer insulating film 800, and the interlayer insulating film 802 are etched by dry etching. Either etching or wet etching may be used, or both may be used. During the etching treatment, the oxide semiconductor film 106 is etched so as not to be divided. However, it is desirable to optimize the etching conditions. Only the interlayer insulating film 802 is etched, and the oxide semiconductor film 106 is not etched at all. It is difficult to achieve the condition that the oxide semiconductor film 106 is not etched. Only a part of the oxide semiconductor film 106 is etched, for example, by 5% to 50% of the thickness of the oxide semiconductor film 106. In some cases, the oxide semiconductor film 106 is etched to have a groove (depression).

[0164] The process of forming the source electrode 114a and the drain electrode 114b is shown in FIG. After this step, the source electrode 114a The drain electrode 114b and the interlayer insulating film 802 may be subjected to a planarization process. As a result, when a transistor is stacked on the transistor 850, , the surface to be formed (that is, the source electrode 114a, the drain electrode 114b and the interlayer insulating film 80 The surface of 2) is highly flat, which makes it easy to fabricate transistors. In this regard, the planarization treatment method described in the above embodiment can be referred to.

[0165] Through the above steps, the transistor 850 illustrated in FIG. 6B can be manufactured. In addition to the features described in the first embodiment, the transistor 850 has the following features: This damage to the oxide semiconductor film 106 (for example, lattice defects in the oxide semiconductor film 106) In addition, as described above, the oxide semiconductor film 106 can reduce the occurrence of defects. The area exposed to the etching process can be limited, so the damage to the transistor caused by the etching process can be minimized. Therefore, the semiconductor formed by the transistor 850 can be prevented from being polluted. The operation characteristics of the device can be improved. This can improve the performance of the semiconductor device that is configured using the transistor. As described above, a part of the source electrode 114a and the drain electrode 114b is connected to the gate electrode. Even if the source electrode 114a and the drain electrode 110 are overlapped with each other, they are not electrically connected. The drain electrode 114b can be formed as close as possible to the gate electrode 110, This structure is suitable for miniaturizing the sintered capacitor.

[0166] Also, as shown in FIG. 8B, even in the case of a structure in which a conductive film 602 is included in an insulating film 102, By using the structure of the transistor 850 shown in FIG. When forming openings in the interlayer insulating film 800 and the interlayer insulating film 802, the oxide in the openings Even if the semiconductor film 106 is over-etched and disappears, the source The electrode 114a and the drain electrode 114b are electrically connected to the sidewalls of the oxide semiconductor film 106. In addition to being electrically connected to the oxide semiconductor film 106 through the conductive film 602, Therefore, good contact resistance can be maintained even during over-etching. Therefore, it is particularly suitable for the case where the oxide semiconductor film 106 is thin (that is, for miniaturization of transistors). It can be said to be a structure.

[0167] (Fourth embodiment) In this embodiment mode, a semiconductor device having a structure different from that of the above-described embodiment mode and a method for manufacturing the semiconductor device will be described. One embodiment of the method will be described with reference to FIGS.

[0168] <Configuration example of semiconductor device> 9(A) and 9(B) show a top-gate structure transistor as an example of a semiconductor device. 9A and 9B show examples of a plan view and a cross-sectional view of the capacitor. 9(A) is a cross-sectional view of the IJ cross section. In order to achieve this, some of the components of the transistor 1150 (such as the substrate 100) are omitted. are.

[0169] The transistor 1150 shown in FIGS. 9A and 9B includes an insulating film 1 02, an oxide semiconductor film 106, a gate insulating film 108, and at least an oxide semiconductor film The gate electrode 110, the insulating film 1101, the sidewall insulating film 1102, and the oxide semiconductor The semiconductor device has a source electrode 114a and a drain electrode 114b electrically connected to the film 106. do.

[0170] The transistor 1150 has an insulating film 1101 on the gate electrode 110 and a The sidewall insulating film 1102 is provided on the side surface, and the source electrode 114a and the drain electrode The electrode 114b is provided in contact with the sidewall insulating film 1102, which is the same as the above embodiment. This differs from the transistor structure described in

[0171] The transistor 1150 is a transistor having a structure similar to that of the transistor 1150 described later. The conductive film used as the source electrode 114a and the drain electrode 114b is 6. After forming on the insulating film 1101 and the sidewall insulating film 1102, the conductive film is subjected to a planarization process. By removing a part of the conductive film by polishing, the source electrode 114a and drain electrode 114b. There is no need to use a photolithography process to form the electrode 114b, and the accuracy of the exposure machine and the photo It is possible to make the Loff width very small without being affected by misalignment of the mask. Therefore, a decrease in the on-state current of the transistor 1150 can be suppressed. This structure is one suitable for miniaturizing transistors.

[0172] <Manufacturing process of transistor 1150> An example of a manufacturing process of the transistor 1150 shown in FIG. 9 will be described with reference to FIGS. 10 and 11. I will explain.

[0173] First, an insulating film 102, an oxide semiconductor film 106, and an insulating film 107 are formed on a substrate 100. (See FIG. 10(A)). This process is shown in FIGS. 2(A) to 2(D) and the drawings. This can be done by taking into consideration the explanation of the face.

[0174] Next, a conductive layer for forming the gate electrode 110 (including wiring formed in the same layer) is formed. The insulating film 1100 for forming the film 109 and the insulating film 1101 is formed (FIG. 10( The insulating film 1100 is made of the same material and composition as the gate insulating film 108. Since the film forming method can be used, the gate insulating film 108 described in the above embodiment can be formed. The contents can be taken into consideration.

[0175] Next, the conductive film 109 and the insulating film 1100 are processed into an island shape by a photolithography process. Then, a gate electrode 110 and an insulating film 1101 are formed (see FIG. 10(C)). A resist mask for forming the port electrode 110 and the insulating film 1101 is formed by ink jet printing. If the resist mask is formed by the ink-jet method, a photomask can be used. Since no insulating film is used, the manufacturing cost can be reduced. The etching may be dry etching or wet etching, or both.

[0176] In this embodiment, the conductive film 109 and the insulating film 1100 are processed after being formed. A gate electrode 110 and an insulating film 1101 are formed, and then a sidewall insulating film 1102 is formed. In order to explain the process in the order of the steps, the insulating film 1101 and the sidewall insulating film 1102 are separated as shown in FIG. 9(B). Although the insulating film 1101 and the sidewall insulating film 1102 are described as components of the same film, In order to make the insulating film 1101 and the sidewall insulating film 1102 the same film, first, After the gate electrode 110 is formed, the insulating film 1101 and the sidewall insulating film 1102 are formed. The insulating film may be formed so as to cover the gate electrode 110 .

[0177] Next, the resistance of the oxide semiconductor film 106 is reduced by ion doping or ion implantation. The impurity ions 130 having a function of imparting a hydrogen atom to the oxide semiconductor film 106 are added to the oxide semiconductor film 106. The gate electrode 110 and the insulating film 1101 function as a mask, so that the oxide semiconductor film 10 A low resistance region 106c is formed in a self-aligned manner in the semiconductor substrate 6 (see FIG. 11(A)).

[0178] Next, an insulating film is formed using the same material and method as the insulating film 102, and the insulating film is etched. The sidewall insulating film 1102 is formed by the anisotropic etching of the insulating film. By performing a highly efficient etching process, it is possible to form the film in a self-aligned manner. It is preferable to use an etching method. The etching gas used in the dry etching method is For example, trifluoromethane, octafluorocyclobutane, tetrafluoromethane, etc. Examples of fluorine-containing gases include etching gases containing rare gases or hydrogen. Dry etching is also suitable. It is preferable to use the RIE method.

[0179] Then, after forming the sidewall insulating film 1102, the gate electrode 110, the insulating film 1101 and the sidewall insulating film 1102 are The insulating film 107 is processed using the wall insulating film 1102 as a mask to form the gate insulating film 108. (See FIG. 11(B)). The gate insulating film 1102 can be formed in the same process as the sidewall insulating film 1102. A photo insulating film 108 may be formed.

[0180] In this embodiment, immediately after the formation of the gate electrode 110 and the insulating film 1101, The gate electrode 110 and the insulating film 1101 are used as masks to form a thin film in the oxide semiconductor film 106. The impurity ions 130 were added to the gate electrode 110 after the sidewall insulating film 1102 was formed. The insulating film 1101 and the sidewall insulating film 1102 are used as masks to form a thin film in the oxide semiconductor film 106. Impurity ions 130 may be added.

[0181] Next, a source electrode is formed on the oxide semiconductor film 106, the insulating film 1101, and the sidewall insulating film 1102. The electrode 114a and the drain electrode 114b (including wiring formed in the same layer) are formed. A conductive film 1104 for forming the insulating film 802 is formed on the conductive film 1104 ( See FIG. 11C.) Note that the conductive film 1104 can be formed using, for example, aluminum or chromium. a metal film containing an element selected from the group consisting of copper, tantalum, titanium, molybdenum, and tungsten; or metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, titanium nitride film, etc.) Also, the underside or underside of a metal film such as aluminum or copper can be used. The upper surface or both surfaces are covered with a high melting point metal film such as titanium, molybdenum, or tungsten. These metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) are stacked The conductive film used for the source electrode and the drain electrode may have a conductive The conductive metal oxide may be indium oxide (In2O 3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3 -SnO2, abbreviated as ITO), and indium zinc oxide (In2O3-ZnO) The conductive film used for the source electrode and the drain electrode can be formed by simply using the above materials. The method for forming the film is not particularly limited, and examples thereof include vapor deposition and CVD. Various film formation methods such as a sputtering method and a spin coating method can be used. The interlayer insulating film 802 may be made of the same material and film formation as those described in Embodiment Mode 3. The method can be considered.

[0182] Next, the conductive film 1104 is subjected to planarization treatment from the top surface, and the insulating film 1101 and the sidewall insulating film 1102 are removed. At least a portion of the conductive film 1104 on the insulating film 1102 and at least a portion of the interlayer insulating film By removing the film 802, the conductive film 1104 is formed at least on the insulating film 1100 or on the sidewall insulating film. The gate electrode 114a is separated by an insulating film 1102, and the source electrode 114a and the drain electrode 114b are 110 is sandwiched between the two layers (see FIG. 12(A)). The details of the planarization treatment for the insulating film 102 described in the first embodiment can be taken into consideration. Cut.

[0183] The planarization treatment is performed not only on the conductive film 1104 and the interlayer insulating film 802 but also on the insulating film 1103. This may be performed on the insulating film 1101 or the sidewall insulating film 1102.

[0184] In FIG. 12(A), the surfaces of the source electrode 114a and the drain electrode 114b and the insulating layer The surfaces of the insulating film 1101 and the interlayer insulating film 802 are located on the same plane. When polishing the source electrode 114a, the drain electrode 114b, and the insulating film 1101, The source electrode 114a, the drain electrode 114b, the insulating film 1101, and the interlayer insulating film 8 When the polishing speed of the source electrode 114a and the drain electrode 114b is different, The surface of the insulating film 1101 and the surface of the interlayer insulating film 802 are different in height, and a step may occur. For example, the surfaces of the source electrode 114a and the drain electrode 114b are formed on the insulating film 1101. The surface may be lower than the surface (concave).

[0185] Through the above steps, the transistor 1150 illustrated in FIG. 12A can be manufactured. In addition to the features described in the first embodiment, the transistor 1150 has the following features: Therefore, the transistor 1150 can suppress a decrease in the on-state current of the transistor 1150. The oxide semiconductor film can be formed by the above-described method. The present invention aims to improve the performance of a transistor using the present invention or a semiconductor device including the transistor. In addition, the source electrode 114a and the drain electrode 114b can be formed using a photolithography method. There is no need to use a lithography process, and the accuracy of the exposure machine and the alignment error of the photomask are not affected. It is possible to make the Loff width very small without being affected by This structure is suitable for this purpose.

[0186] An insulating film may be provided over the transistor 1150. The insulating film may be a gate insulating film. Since the same material and film formation method as the insulating film 108 can be used, the above-mentioned gate insulating film 1 Please refer to the contents of 08. The aluminum oxide film prevents moisture from entering from the outside. Since it has a high effect of suppressing the above, aluminum oxide film or aluminum oxide film is used as the insulating film. It is desirable to form a laminated film including a silicon film, and more preferably, the film density is 3.2 g / cm. m 3 or more, preferably 3.6 g / cm 3 It is desirable to use the above aluminum oxide film. Note that the insulating film may be formed before the transistor 1150 is formed. After forming the wall insulating film 1102, the conductive film 1104, the insulating film, and the interlayer insulating film 802 are formed in this order. In the case of the structure of FIG. 9(B), a film may be formed on the surface of the insulating film, and then a planarization process such as CMP may be performed. In this case, even if impurities such as moisture or hydrogen are mixed into the interlayer insulating film 802, This is preferable because these impurities can be prevented from reaching the oxide semiconductor film 106.

[0187] As shown in FIG. 12B, the transistor 1150 has a conductive film 60 in the insulating film 102. 2. The transistor 1150 may have the structure shown in FIG. As a result, the source electrode 114a and the drain electrode 114b are formed on the oxide semiconductor film 106. Since the oxide semiconductor film 106 is electrically connected not only on the front side but also on the back side, and the contact resistance between the oxide semiconductor film 106 and the source electrode 114a and the contact resistance between the oxide semiconductor film 106 and the drain electrode 114b. This reduces the contact resistance and the variation in the contact resistance. To create a high-performance transistor with high current and suppressed variations in threshold voltage Therefore, this structure is considered to be one of the suitable structures for a transistor using an oxide semiconductor. I can say it.

[0188] (Embodiment 5) In this embodiment mode, a semiconductor device having a structure different from that of the above-described embodiment mode and a method for manufacturing the semiconductor device will be described. One embodiment of the method will be described with reference to FIGS.

[0189] <Configuration example of semiconductor device> 13(A) and 13(B) show a top-gate transistor as an example of a semiconductor device. 13A and 13B show examples of a plan view and a cross-sectional view of a resistor. is a cross-sectional view of the KL cross section in FIG. 13(A). To avoid this, some of the components of the transistor 1350 (e.g., the substrate 100) etc.) are omitted.

[0190] The transistor 1350 shown in FIGS. 13A and 13B is formed on a substrate 100 with an insulating layer. the oxide semiconductor film 102, the oxide semiconductor film 106, and a source The electrode 114a, the drain electrode 114b, the gate insulating film 108, and at least an oxide It has a gate electrode 110 that overlaps with the semiconductor film.

[0191] The transistor 1350 has a gate insulating film 108 formed over the entire oxide semiconductor film 106. This is different from the structure of the transistor described in the above embodiment in that:

[0192] As in the above-described embodiment, the gate insulating film is formed only on a part of the oxide semiconductor film 106. In this structure, even if the gate insulating film 108 is a film that releases oxygen by heat treatment, Oxygen (excess oxygen in the gate insulating film 108) is released from the edge of the gate insulating film 108. Therefore, the effect of reducing oxygen vacancies in the oxide semiconductor film 106 may be small.

[0193] However, as described in this embodiment, the gate insulating film 106 is formed over the entire surface of the oxide semiconductor film 106. By forming the film 108, oxygen released by the heat treatment is absorbed into the gate insulating film. Since the light is not emitted from the end of 108, the above problem can be solved.

[0194] <Manufacturing process of transistor 1350> An example of a manufacturing process of the transistor 1350 shown in FIGS. 13A to 13C will be described with reference to FIGS. 14A to 14C. .

[0195] First, an insulating film 102 and an oxide semiconductor film 106 are formed on a substrate 100 (FIG. 14(A)). (See FIG. 2(A) to FIG. 2(C) and the explanations of the drawings.) This can be done by taking into consideration the contents of the above-mentioned embodiment.

[0196] Next, the source electrode 114a and the drain electrode 114b in contact with the oxide semiconductor film 106 are The oxide semiconductor film 106, the source electrode 114a, and the drain electrode 114b are formed. The gate insulating film 108 is formed on the source electrode 114a (see FIG. 14(B)). The formation of the drain electrode 114b is described with reference to FIG. 3(D) and the description of the drawing. The gate insulating film 108 may be formed by the method shown in FIG. 2D and the description of the drawing. Just do it.

[0197] In this embodiment, the source electrode 114a and the drain electrode 114b are formed on the oxide semiconductor film 106. In order to form the gate insulating film 108 after forming the electrode 114b, the first region 106a The formation position is different from that of the above-described embodiment, and the oxide semiconductor film 106 and the gate insulating film 10 8 are formed in the area where they are in direct contact.

[0198] Next, a gate electrode 110 is formed on the gate insulating film 108 in a region overlapping with the oxide semiconductor film 106. (See FIG. 14(C)). This step is similar to that shown in FIG. 3(B) and the description of the drawing. This should be done taking into consideration the details.

[0199] Through the above steps, a transistor 1350 illustrated in FIG. 14C can be manufactured. In addition to the features described in the first embodiment, the transistor 1350 has the following features: When the insulating film 108 is a film that releases oxygen by heat treatment, the gate insulating film 1 Since oxygen released from the oxygen ion source 8 can be efficiently added to the oxide semiconductor film 106, The effect of reducing oxygen vacancies can be enhanced.

[0200] (Sixth embodiment) In this embodiment, the transistors described in any of Embodiments 1 to 5 are used. It is a semiconductor that can retain its memory contents even when power is not supplied and has no limit on the number of times it can be written. An example of the body device will be described with reference to the drawings.

[0201] 15A and 15B show an example of the structure of a semiconductor device. FIG. 15A shows a cross-sectional view of the semiconductor device. FIG. 15(B) shows a plan view of the semiconductor device, and FIG. 15(C) shows a circuit diagram of the semiconductor device. Here, FIG. 15(A) corresponds to the cross section at KL and MN in FIG. 15(B). .

[0202] The semiconductor device shown in FIGS. 15(A) and 15(B) has a transistor using a first semiconductor material in the lower part. A transistor 1760 is provided on the upper surface of the semiconductor substrate 1762, and a transistor 1762 is provided on the upper surface of the semiconductor substrate 1762. The transistor 1762 may be the transistor shown in the above embodiment. The following structure can be applied. Here, the transistor 1150 of the fourth embodiment is used. Here is an example of what happened.

[0203] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used can easily operate at high speed. The properties of the charge storage capacitor allow it to retain charge for a long period of time.

[0204] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can also be used. In order to maintain the resistance, the transistor 1762 described in Embodiment 4 using an oxide semiconductor is In addition to using it for semiconductor devices, specific information on semiconductor devices, such as the materials used in semiconductor devices and their structures, is also provided. The configurations need not be limited to those shown here.

[0205] The transistor 1760 in FIG. 15A is made of a semiconductor material (e.g., silicon). a channel forming region 1716 provided in a substrate 1700 including the channel forming region 1716; The impurity region 1720 is provided so as to sandwich the impurity region 1720. a gate insulating film 1708 provided on the semiconductor region 1724 and the channel forming region 1716; and a gate electrode 1710 provided on the gate insulating film 1708. Therefore, there are cases where the semiconductor device does not explicitly have a source electrode or a drain electrode, but for convenience, such a case is In some cases, the transistor is called a transistor including the state. In order to explain this, the source and drain regions are referred to as the source electrode and drain electrode. That is, in this specification, the term "source electrode" includes the source region. It can be found.

[0206] An element isolation insulating layer 1706 is provided on the substrate 1700 so as to surround the transistor 1760. An insulating layer 1728 and an insulating layer 1730 are provided to cover the transistor 1760. In the transistor 1760, the sidewalls of the gate electrode 1710 are An insulating layer (sidewall insulating layer) is provided to form impurity regions 17 including regions with different impurity concentrations. It can also be 20.

[0207] The transistor 1760 using a single crystal semiconductor substrate can operate at high speed. By using the transistor as a readout transistor, it is possible to improve the readout of information. Two insulating films are formed to cover the transistor 1760. As a process before forming the transistor 1762 and the capacitance element 1764, the two insulating layers are P treatment is performed to form a planarized insulating layer 1728 and an insulating layer 1730, and at the same time, gate electrodes The top surface of the pole 1710 is exposed.

[0208] The insulating layer 1728 and the insulating layer 1730 are typically formed of a silicon oxide film, a silicon oxynitride film, or Aluminum oxide film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, An inorganic insulating film such as a silicon nitride oxide film or an aluminum nitride oxide film can be used. The insulating layers 1728 and 1730 are formed by using a plasma CVD method, a sputtering method, or the like. It can be formed.

[0209] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric-constant materials (low-k materials) can also be used. When organic materials are used, the insulating layer can be formed by wet methods such as spin coating and printing. 1728, and an insulating layer 1730 may be formed.

[0210] In this embodiment, the insulating layer 1728 is a silicon nitride film, and the insulating layer 1730 is a silicon nitride film. A silicon oxide film is used as the insulating film.

[0211] On the surface of the insulating layer 1730, a region where the oxide semiconductor film 1744 is to be formed is subjected to planarization treatment. In this embodiment, the surface is sufficiently flattened by a polishing process (for example, a CMP process). On the insulating layer 1730 (preferably the average surface roughness of the insulating layer 1730 surface is 0.15 nm or less) An oxide semiconductor film 1744 is formed on the insulating film 1744 .

[0212] The transistor 1762 shown in FIG. 15A includes an oxide semiconductor in a channel formation region. Here, the oxide semiconductor film 1744 included in the transistor 1762 As described in the above embodiment, impurities such as moisture and hydrogen are removed as much as possible. It is desirable that the material is purified. Also, oxygen deficiency is sufficiently compensated. By using such an oxide semiconductor, a transistor with extremely excellent off-state characteristics can be obtained. You can get resistor 1762.

[0213] The transistor 1762 has an extremely small off-state current, and therefore, by using this transistor, It is possible to retain the stored contents for a long time, i.e., no refresh operation is required. Alternatively, it is possible to provide a semiconductor memory device in which the frequency of refresh operations is extremely low. Therefore, power consumption can be reduced sufficiently.

[0214] The transistor 1762 is fabricated by forming a gate electrode 1748, an insulating film 1737, and a The conductive film provided on the sidewall insulating film 1736a and the sidewall insulating film 1736b is subjected to chemical mechanical polishing. The electrode film 1 which functions as a source electrode and a drain electrode is removed by a process. 742a and an electrode film 1742b are formed.

[0215] Therefore, the transistor 1762 can reduce the Loff width. This makes it possible to improve the on-characteristics of the starter 1762.

[0216] The conductive layer on the gate electrode 1748 in the process of forming the electrode film 1742a and the electrode film 1742b In the process of removing the conductive film, an etching process using a resist mask is not used. Therefore, in the manufacturing process of a semiconductor device, it is possible to accurately perform precise processing. It is possible to manufacture transistors with fine structures with little variation in characteristics with high yield. can.

[0217] An interlayer insulating film 1735 and an insulating film 1750 are formed over the transistor 1762 as a single layer or a stacked layer. In this embodiment, an aluminum oxide film is used as the insulating film 1750. The aluminum oxide film is applied at a high density (film density 3.2 g / cm 3 More than 3.6g, preferably cm 3 By using a voltage of 100 V or more, the transistor 1762 can have stable electrical characteristics. This can be done.

[0218] In addition, the electrode film of the transistor 1762 is A conductive layer 1753 is provided in the region overlapping with the electrode film 1742a. The interlayer insulating film 1735, the insulating film 1750, and the conductive layer 1753 form the capacitance element 17 That is, the electrode film 1742a of the transistor 1762 is The conductive layer 1753 serves as one electrode of the capacitor 1764. If capacitance is not required, the capacitor element 1764 may be omitted. The capacitor 1764 may be provided separately above the transistor 1762. good.

[0219] An insulating film 1752 is provided over the transistor 1762 and the capacitor 1764. On the insulating film 1752, a transistor 1762 and another transistor are connected. Although not shown in FIG. 15(A), the wiring 1756 , formed in openings formed in the interlayer insulating film 1735, the insulating film 1750, the insulating film 1752, etc. The electrode is electrically connected to the electrode film 1742b through an electrode formed thereon. The oxide semiconductor film 1744 of the transistor 1762 is provided so as to overlap with at least part of the oxide semiconductor film 1744 of the transistor 1762. It is preferable that

[0220] In FIG. 15(A) and FIG. 15(B), a transistor 1760 and a transistor 176 2 is provided so as to overlap at least a part of the source of the transistor 1760. The oxide semiconductor film 1744 is provided so as to partly overlap with the source region or the drain region. In addition, it is preferable that the transistor 1762 and the capacitor 1764 are The capacitor element 1764 is provided so as to overlap at least a part of the capacitor element 1764. The conductive layer 1753 at least partially overlaps the gate electrode 1710 of the transistor 1760. By adopting such a planar layout, Since the occupied area can be reduced, high integration can be achieved.

[0221] The electrode film 1742b and the wiring 1756 are electrically connected to each other. 756 may be directly contacted, or an insulating layer may be formed between the electrode film 1742b and the wiring 1756. An electrode may be provided on the membrane, and the reaction may be carried out via the electrode. stomach.

[0222] Next, an example of a circuit configuration corresponding to FIGS. 15(A) and 15(B) is shown in FIG. 15(C).

[0223] In FIG. 15C, the first wiring (1st Line) and the source of the transistor 1760 The source electrode is electrically connected to the second wiring (2nd Line) and the transistor 176. The drain electrode of the third wiring (3rd Line ) and one of the source electrode and the drain electrode of the transistor 1762 are electrically connected. The fourth line and the gate electrode of the transistor 1762 are electrically connected to each other. The gate electrode of the transistor 1760 and the gate electrode of the transistor 17 One of the source electrode and the drain electrode of the capacitor 1762 is electrically connected to the other electrode of the capacitor 1764. , and one of the electrodes of the capacitor 1764 is electrically connected to the fifth wiring (5th Line). are actively connected.

[0224] In the semiconductor device shown in FIG. 15C, the potential of the gate electrode of the transistor 1760 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0225] The writing and retention of data will be explained. First, the potential of the fourth wiring is applied to the transistor The potential is set to turn on the transistor 1762, and the transistor 1762 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 1760 and the capacitor 176 4. That is, a predetermined charge is applied to the gate electrode of the transistor 1760. Here, the charge that gives two different potential levels (hereafter referred to as Low level) is Then, the fourth The potential of the wiring is set to a potential at which the transistor 1762 is turned off. 62 is turned off, the charge applied to the gate electrode of the transistor 1760 is retained (retained).

[0226] Since the off-state current of the transistor 1762 is extremely small, the gate voltage of the transistor 1760 The charge on the pole is maintained for a long period of time.

[0227] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, Then, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 1760 The second wiring has a different potential depending on the amount of charge held in the transistor electrode. If the transistor 1760 is an n-channel type, a high level is applied to the gate electrode of the transistor 1760. Apparent threshold V for a given Bell charge th_H is a transistor 1760 The apparent threshold voltage V when a low-level charge is applied to the gate electrode of th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 1760 is The term "fifth wiring" refers to the potential of the fifth wiring required to turn on the transistor. The potential of the wiring is V th_H and V th_L By setting the potential V0 between For example, in writing, the charge applied to the gate electrode of 760 can be determined. When the h level charge is applied, the potential of the fifth wire is V0 (>V th_H ) and If a low level charge is applied, the transistor 1760 is in the "on state." In this case, the potential of the fifth wire is V0( <V th_L ) even if the transistor 1760 Therefore, by observing the potential of the second wiring, The information can be read out.

[0228] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode Regardless of the voltage, transistor 1760 is in the "off" state, i.e., V th_H Alternatively, a smaller potential may be applied to the fifth wiring. The potential at which transistor 1760 is in the "on" state, i.e., V th_L Larger power Just give the position to the fifth wire.

[0229] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0230] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0231] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0232] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0233] (Embodiment 7) In this embodiment, the transistors described in Embodiments 1 to 5 are used. It is possible to retain memory contents even when power is not supplied, and there is no limit to the number of times it can be written. Regarding the semiconductor device having a different structure from that shown in the sixth embodiment, the structure shown in FIGS. 17 will be used for explanation.

[0234] FIG. 16(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 16(B) shows an example of a semiconductor device. First, the semiconductor device shown in FIG. 16A will be described, followed by The semiconductor device shown in FIG. 16B will be described below.

[0235] In the semiconductor device shown in FIG. 16A, the bit line BL and the source of the transistor 1762 The gate electrode or drain electrode of the transistor 1762 is electrically connected to the word line WL. The gate electrode is electrically connected to the source electrode or drain electrode of the transistor 1762. The first terminal of the capacitor 1764 is electrically connected.

[0236] Next, data is written and read into the semiconductor device (memory cell 1850) shown in FIG. The case where holding is performed will be described.

[0237] First, the potential of the word line WL is set to a potential at which the transistor 1762 is turned on. This causes the potential of the bit line BL to rise to the level of the capacitance element 17 Then, the potential of the word line WL is applied to the first terminal of the transistor 64 (write). The transistor 1762 is turned off by the potential Thus, the potential of the first terminal of the capacitor 1764 is held (retained).

[0238] The transistor 1762 including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 1762 is turned off, the capacitor 1764 The potential of the first terminal (or the charge stored in the capacitor 1764) is kept low for an extremely long time. It is possible to maintain the

[0239] Next, the reading of information will be described. When the transistor 1762 is turned on, the floating The bit line BL in the free state and the capacitance element 1764 are electrically connected, and the bit line BL and the capacitance element 17 The charge is redistributed between the bit line B and the bit line 64. As a result, the potential of the bit line BL changes. The change in the potential of L is determined by the potential of the first terminal of the capacitance element 1764 (or the capacitance element 1764 It takes on different values ​​depending on the charge stored in the

[0240] For example, the potential of the first terminal of the capacitor 1764 is V, the capacitance of the capacitor 1764 is C, and the bit The capacitance component of the bit line BL (hereinafter also referred to as bit line capacitance) is CB. If the previous potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is is (CB×VB0+C×V) / (CB+C). Therefore, the state of the memory cell 1850 is As a state, the potential of the first terminal of the capacitance element 1764 is in two states of V1 and V0 (V1>V0). If the potential V1 is held, the potential of the bit line BL (=CB×VB0 +C×V1) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained ( =CB×VB0+C×V0) / (CB+C)).

[0241] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0242] As described above, in the semiconductor device shown in FIG. 16A, the off-state current of the transistor 1762 is extremely low. Since the capacitance is small, the charge stored in the capacitance element 1764 can be maintained for a long time. In other words, the refresh operation becomes unnecessary or the refresh operation This makes it possible to reduce the frequency of this extremely low, thereby significantly reducing power consumption. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. It is Noh.

[0243] Next, the semiconductor device shown in FIG. 16B will be described.

[0244] The semiconductor device shown in FIG. 16B has a memory cell shown in FIG. 16A as a memory circuit thereon. The memory cell arrays 1851a and 1851b each have a plurality of memory cells 1850. In order to operate the memory cell array 1851 (memory cell arrays 1851a and 1851b), The peripheral circuit 1853 is a circuit for storing the memory cell array 1 851 is electrically connected to the

[0245] By using the configuration shown in FIG. 16B, the peripheral circuit 1853 is connected to the memory cell array 18 51 (memory cell arrays 1851a and 1851b) can be provided directly below the semiconductor device. The semiconductor device can be made smaller.

[0246] The transistor provided in the peripheral circuit 1853 is the same as the transistor 1762 in Embodiment 6. It is more preferable to use different semiconductor materials. For example, silicon, germanium, silicon Congenerium germanium, silicon carbide, or gallium arsenide can be used. It is preferable to use a conductor. Alternatively, an organic semiconductor material may be used. A transistor using a conductive material can operate at a sufficiently high speed. The resistors are ideal for various circuits (logic circuits, driver circuits, etc.) that require high-speed operation. It is possible to do this.

[0247] In the semiconductor device shown in FIG. 16B, two memory cell arrays 1851 (memory Although the configuration in which the cell array 1851a and the memory cell array 1851b are stacked is illustrated, However, the number of stacked memory cells is not limited to this. It is also possible to do so.

[0248] Next, the specific configuration of the memory cell 1850 shown in FIG. 16(A) will be described with reference to FIG. 17. Give an explanation.

[0249] 17A and 17B show an example of the configuration of a memory cell 1850. 17(A) and 17(B) show a cross-sectional view of the memory cell 1850, and a plan view of the memory cell 1850, respectively. 17(A) corresponds to the cross section at OP and QR in FIG. 17(B).

[0250] The transistor 1762 shown in FIGS. 17A and 17B is the same as that described in Embodiments 1 to 3. The same configuration as that shown in the fourth embodiment can be used.

[0251] An insulating film 1750 is provided over the transistor 1762 as a single layer or a stacked layer. , in a region overlapping with the electrode film 1742a of the transistor 1762 via the insulating film 1750. A conductive layer 1753 is provided, and an electrode film 1742a, an interlayer insulating film 1735, and an insulating film The insulating film 1750 and the conductive layer 1753 form a capacitor element 1764. The electrode film 1742a of the transistor 1762 functions as one electrode of the capacitor 1764. The conductive layer 1753 functions as the other electrode of the capacitor 1764 .

[0252] An insulating film 1752 is provided over the transistor 1762 and the capacitor 1764. On the insulating film 1752, a memory cell 1850 and an adjacent memory cell 1850 are formed. Wiring 1756 is provided for connection. Although not shown, the wiring 1756 is formed by an insulating film. 1750, an insulating film 1752, an interlayer insulating film 1735, and the like. It is electrically connected to the electrode film 1742b of the transistor 1762. However, if there is another conductive film in the opening, A layer is provided, and the wiring 1756 and the electrode film 1742b are electrically connected via the other conductive layer. Note that the wiring 1756 corresponds to the bit line BL in the circuit diagram of FIG. do.

[0253] In FIGS. 17A and 17B, the electrode film 1742b of the transistor 1762 is It can also function as the source electrode of a transistor included in an adjacent memory cell. By adopting such a planar layout, the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0254] By adopting the planar layout shown in FIG. 17(A), the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0255] As described above, the memory cells formed in multiple layers on the upper side are transistors using oxide semiconductors. The transistor using an oxide semiconductor has a low off-state current. Therefore, by using this, it is possible to retain the stored contents for a long period of time. This allows the frequency of refresh operations to be reduced significantly, resulting in sufficient power consumption. can be reduced to

[0256] In this way, transistors using materials other than oxide semiconductors (in other words, transistors with sufficiently high speed operation) The peripheral circuits are made up of transistors that can be operated with an oxide semiconductor. In a broader sense, it is a transistor with a sufficiently small off-state current. This makes it possible to realize a semiconductor device with unprecedented features. By forming the gate and memory circuits in a stacked structure, the integration of the semiconductor device can be increased.

[0257] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0258] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0259] (Embodiment 8) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, an An example of application to a portable device such as a child book will be described with reference to FIGS.

[0260] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following: The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: do.

[0261] In a normal SRAM, one memory cell is composed of a transistor 2001 as shown in FIG. The X decoder is composed of six transistors, ie, transistors 2001 to 2006. 2007 and Y decoder 2008. Transistor 2003 and transistor Transistor 2005, transistor 2004 and transistor 2006 form an inverter, However, since one memory cell consists of six transistors, However, the drawback is that the cell area is large. When the minimum dimension of the design rule is F, the SR The memory cell area of ​​AM is usually 100 to 150F 2 For this reason, SRAM is bit-wise The unit price is the highest among all types of memory.

[0262] On the other hand, in a DRAM, the memory cell is made up of transistors 2011 as shown in FIG. , and a storage capacitor 2012, which are connected to an X decoder 2013 and a Y decoder 20 Each cell is composed of one transistor and one capacitor. The area of ​​a DRAM memory cell is usually 10F 2 The following is true: However, D RAM needs to be constantly refreshed and consumes power even when not being rewritten. do.

[0263] However, the memory cell area of ​​the semiconductor device described in the previous embodiment is 10F 2 Before and after , and frequent refresh is not required. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0264] A block diagram of the portable device is shown in Fig. 19. The portable device shown in Fig. 19 includes an RF circuit 2101, an analog Log baseband circuit 2102, digital baseband circuit 2103, battery 210 4, power supply circuit 2105, application processor 2106, flash memory 211 0, a display controller 2111, a memory circuit 2112, a display 2113, It consists of a touch sensor 2119, a voice circuit 2117, a keyboard 2118, etc. The display 2113 includes a display unit 2114, a source driver 2115, and a gate driver 2116. The application processor 2106 is composed of a CPU 2107 , a DSP 2108, and an interface 2109 (also referred to as IF). Generally, the memory circuit 2112 is composed of an SRAM or a DRAM. By employing the semiconductor device described in the embodiment, writing and reading of information can be performed. The data is stored at high speed, can be stored for a long period of time, and consumes a sufficient amount of power.

[0265] FIG. 20 shows a display in which the semiconductor device described in the previous embodiment is incorporated in a memory circuit 2250 of the display. The memory circuit 2250 shown in FIG. 3, consisting of a switch 2254, a switch 2255 and a memory controller 2251 The memory circuit stores image data (input image data) input from the signal line. The data (stored image data) stored in the memory 2252 and the memory 2253 is read out. a display controller 2256 for controlling the display; A display 2257 is connected to display the signal from 256.

[0266] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 225 via the switch 2254. 2. The image data stored in the memory 2252 (stored image data A) is , a switch 2255, and a display controller 2256. 57 and displayed.

[0267] If there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. In this case, the memory 2252 is connected to the display controller 2256 via the switch 2255. is read from

[0268] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 2253 via the switch 2254. During this time, the stored image data A is periodically transferred from the memory 2252 via the switch 2255. New image data (stored image data B) is stored in the memory 2253. When this is complete, the stored image data B is read out from the next frame of the display 2257. The display 22 is connected to the display 22 via a switch 2255 and a display controller 2256. The stored image data B is sent to the memory 57 and displayed. This continues until sufficient image data is stored in memory 2252.

[0269] In this way, the memory 2252 and the memory 2253 alternately write image data and store image data. By reading out the data, the display 2257 is displayed. The memory 2252 and the memory 2253 are not limited to separate memories, but may be one memory. The semiconductor device described in the above embodiment may be used as a memory 2252 and a memory By adopting the memory 2253, it is possible to write and read information at high speed and for a long period of time. This allows for storage and retention of data, and also allows for a sufficient reduction in power consumption.

[0270] Figure 21 shows a block diagram of an electronic book. Figure 21 shows a battery 2301, a power supply circuit 2302, and , microprocessor 2303, flash memory 2304, audio circuit 2305, keyboard a memory circuit 2307; a touch panel 2308; a display 2309; It is configured by a display controller 2310.

[0271] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 2307 in FIG. The role of the memory circuit 2307 is to temporarily store the contents of the book. An example of a feature is when a user uses the highlight feature. When reading an e-book, you may want to mark a specific part. The highlighting function is called the highlight function, and it allows you to change the display color, underline, make the text bold, etc. The purpose is to differentiate the user from the surroundings by making the text smaller or changing the font. This is a function that stores and retains information from specified locations. If you want to store this information for a long period of time, It may be copied to the flash memory 2304. In this case, the same as in the previous embodiment By adopting the semiconductor device described above, writing and reading of information can be improved. This allows for high speed, long-term storage, and sufficient reduction in power consumption.

[0272] As described above, the portable device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for high-speed readout, long-term memory retention, and low power consumption. A portable device with reduced noise is realized.

[0273] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0274] (Embodiment 9) The semiconductor device disclosed in this specification and the like can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras cameras such as digital cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices) (c), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the liquid crystal display device described in the above embodiment include: I will explain.

[0275] FIG. 22(A) shows a notebook personal computer, which includes a main body 2501 and a housing 250 2, a display unit 2503, a keyboard 2504, etc. By applying the semiconductor device shown in the figure, a highly reliable notebook-type personal computer can be manufactured. The computer may be a

[0276] FIG. 22(B) shows a personal digital assistant (PDA), which has a main body 2511 including a display unit 2513 and a An external interface 2515 and operation buttons 2514 are provided. The stylus 2512 is an accessory of the device. This makes it possible to provide a highly reliable personal digital assistant (PDA).

[0277] FIG. 22C shows an example of an electronic book. For example, an electronic book 2520 is housed in a housing 25 It consists of two housings, housing 2521 and housing 2523. 3 is integrated with a shaft portion 2522, and performs opening and closing operations around the shaft portion 2522. With this configuration, it is possible to operate like a paper book.

[0278] The housing 2521 incorporates a display unit 2525, and the housing 2523 incorporates a display unit 2527. The display unit 2525 and the display unit 2527 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display (display 2525 in FIG. 22(C)) and An image can be displayed on the display unit (display unit 2527 in FIG. 22(C)). By applying the semiconductor device shown in the form of It is possible.

[0279] FIG. 22C shows an example in which an operation unit and the like are provided in the housing 2521. For example, The housing 2521 includes a power supply 2526, operation keys 2528, a speaker 2529, etc. The operation keys 2528 can be used to turn pages. The surface may be provided with a keyboard, a pointing device, etc. On the back and sides, there are external connection terminals (earphone terminal, USB terminal, etc.), storage media insertion port, etc. Furthermore, the electronic book 2520 may have a function as an electronic dictionary. A similar configuration may also be used.

[0280] The electronic book 2520 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0281] FIG. 22(D) shows a smartphone, which includes a housing 2530, a button 2531, and a micro A phone 2532, a display unit 2533 equipped with a touch panel, a speaker 2534, and a camera. The camera lens 2535 is provided, and the camera functions as a mobile phone. By applying the semiconductor device shown in the figure, a highly reliable smartphone can be achieved. can be done.

[0282] The display direction of the display unit 2533 changes appropriately depending on the usage mode. It has a camera lens 2535 on the same surface as the speaker, so video calls are possible. The speaker 2534 and microphone 2532 are not limited to voice calls, but can also be used for video calls, recording, playback, etc. It is possible to have live

[0283] In addition, the external connection terminal 2536 can be connected to various cables such as an AC adapter and a USB cable. It is possible to charge the device and to communicate data with a personal computer, etc. A recording medium can be inserted into an external memory slot (not shown) to store and transfer larger amounts of data. It can handle.

[0284] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0285] FIG. 22(E) shows a digital video camera, which includes a main body 2541, a display unit 2542, an operation screen, and a touch panel. The above embodiment is configured with a switch 2543, a battery 2544, etc. By applying the semiconductor device shown in the above, a highly reliable digital video camera can be obtained. can be done.

[0286] Figure 22(F) shows an example of a television device. The television device 2550 includes: A display unit 2553 is built into the housing 2551. The display unit 2553 displays images. In this case, the housing 2551 is supported by a stand 2555. By applying the semiconductor device shown in the above embodiment, reliability can be improved. This can result in a highly functional television device 2550.

[0287] The television device 2550 can be operated using an operation switch provided on the housing 2551 or a separate remote control. This can be done by a remote control operator. A display unit for displaying the output information may be provided.

[0288] The television device 2550 is configured to include a receiver, a modem, etc. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0289] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination. [Example]

[0290] In this example, an oxide semiconductor film containing silicon was fabricated. The results of the resistance measurement and X-ray photoelectron spectroscopy (XPS) The results of composition analysis using ion spectroscopy are explained below.

[0291] In this example, different concentrations of SiO2 (0 wt%, 2 wt%, 5 wt%) were added. The sputtering was performed on the target with different gas flow rates (oxygen 33%, oxygen 100%). Then, an oxide semiconductor film was formed on a glass substrate to prepare a sample.

[0292] The sputtering target is IG with an atomic ratio of In:Ga:Zn=1:1:1. ZO target and IGZO target with In:Ga:Zn=1:1:1 [atomic ratio] A target containing 2% by weight of SiO2 and a target containing In:Ga:Zn=1:1:1 [atomic ratio] The IGZO target was prepared by adding 5 wt% of SiO2.

[0293] For each target, the gas flow rate was O2 = 10 sccm or Ar / O2 = 10 The oxide semiconductor film was formed by sputtering at a flow rate of 1000µm / 500µm. Other deposition conditions were the same for all samples: substrate temperature: 200°C, deposition power: 100W (DC power The deposition pressure was 0.4 Pa and the film thickness was 100 nm.

[0294] In other words, the sample was formed in a 100% oxygen atmosphere using a target without SiO2 added. The film was formed in a 100% oxygen atmosphere using a target containing 2% by weight of SiO2. Sample M was grown in a 100% oxygen atmosphere using a target containing 5% by weight of SiO2. Sample N was deposited in an atmosphere of 33% oxygen using a target without SiO2 added. The filmed sample was placed in an atmosphere of 33% oxygen using a target containing 2% by weight of SiO2. Sample P was deposited in an atmosphere of 33% oxygen using a target containing 5% by weight of SiO2. Sample Q was prepared by deposition in an ambient atmosphere.

[0295] Furthermore, Samples L to Q are introduced into an electric furnace using a resistance heating element and subjected to heat treatment. The heat treatment was carried out in a N2 atmosphere at 450°C for 1 hour, followed by O Heating was carried out at 2 atmospheres for 1 hour.

[0296] The sheet resistance of Samples L to Q was measured after the above treatment. The measurement results of the sheet resistance of samples L to Q are shown in the graph of FIG. The vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the SiO2 concentration in the target (wt% ) is taken.

[0297] From the graph in Figure 23, as the SiO2 concentration in the target increases, the oxide semiconductor film The sheet resistance also tends to increase. For sample L and sample O, the sheet resistance was 8×10 5 Ω / □~1×10 6 About Ω / □ The sheet resistance was such that it could be used as an active layer for a transistor or the like. Even in samples M and P, where the SiO2 concentration in the target was 2 wt%, the sheet resistance is 1×10 6 Ω / □~3×10 6 It is about Ω / □ and is used as an active layer for transistors, etc. However, the SiO2 concentration in the target was 5 wt. % of samples N and Q, the sheet resistance was greater than the upper limit of measurement, and the transistor When such a material is used as an active layer, the on-current may decrease.

[0298] In this way, the SiO2 concentration in the target used to form the oxide semiconductor film of the transistor For example, if the SiO2 concentration in the target is about 2 wt% or less, good.

[0299] Furthermore, in this example, the oxide semiconductor film was grown under the same conditions as in Sample M and Sample N. The sample was prepared by depositing the above on a silicon substrate, and the composition was analyzed using XPS.

[0300] The sputtering target is IG with an atomic ratio of In:Ga:Zn=1:1:1. ZO target with 2 wt% SiO2 added and In:Ga:Zn=1: A target with 1:1 atomic ratio of IGZO and 5% by weight of SiO2 was used. Used.

[0301] The film formation conditions were: gas flow rate: O2 = 10 sccm, substrate temperature: 200°C, film formation power: 100 W (DC power supply), film formation pressure: 0.4 Pa, film thickness: 15 nm.

[0302] That is, a film was formed in a 100% oxygen atmosphere using a target containing 2% by weight of SiO2. Sample R was grown in a 100% oxygen atmosphere using a target containing 5% by weight of SiO2. Sample S was prepared by film deposition.

[0303] The composition of Sample R and Sample S was analyzed using XPS. The silicon concentration in the oxide semiconductor film of sample S is 1.1 atomic %. The silicon concentration in the film was 2.6 atomic %. The silicon concentration in the oxide semiconductor film using this target was 1.1 atomic %. The silicon concentration in the oxide semiconductor film using a target with 5 wt% O2 added was 2. It was 6 atom %.

[0304] As described above, due to mixing or the like, a semiconductor film is formed in the vicinity of the interface with the gate insulating film. When impurities such as silicon are mixed in, the resistance of the channel formation region increases, and the transistor Therefore, the on-state current of the oxide semiconductor film near the interface with the gate insulating film may decrease. In the meantime, it is important to reduce the silicon concentration as described above. [Example]

[0305] As described in the first embodiment, the oxide semiconductor film used in the above embodiment is a C It is preferable to use an AAC-OS film, but silicon may be mixed into the CAAC-OS film. There is a concern that the crystal structure of the CAAC-OS film may change due to this.

[0306] In this example, an oxide semiconductor film having high crystallinity such as a CAAC-OS film was used. The researchers calculated the concentration of silicon required to destroy the crystal structure of the oxide semiconductor film. The results will be explained below.

[0307] In the calculations in this example, the "classical molecular dynamics method" was used as the calculation method. We used "SCIGRESS-ME" from Tsushin Co., Ltd.

[0308] In addition, a single-crystal structure model of InGaZnO4 with 1680 atoms was used as a film with high crystallinity. The density of the model was 6.36 g / cm 3 Yes do.

[0309] Then, for the above model, under constant temperature and pressure conditions (pressure: 1 atm, temperature: 300°C), In this structure, two In atoms, two Ga atoms, two Zn atoms, and eight oxygen atoms are replaced by Si atoms. A sample containing 3 In atoms, 3 Ga atoms, and Zn atoms (hereinafter referred to as sample A) A sample in which 3 atoms and 12 oxygen atoms were replaced with Si atoms (hereinafter referred to as sample B) The initial structure and the structure after 2 nsec were calculated for each of the molecules.

[0310] The Si substituted in sample A accounts for 0.83 atomic % (0. 52 wt %, and the Si substituted in Sample B was 1.25 atomic % (0.7 9% by weight.

[0311] First, the structure of sample A and the structure of sample B in the initial state (0 nsec) are shown in Figure 2. 4(A) and 24(B), and in FIG. 24(C), In atoms, Ga atoms, Zn atoms, A sample in which the O atoms and Si atoms were not replaced (hereinafter referred to as sample C) The structure of the

[0312] As can be seen from Figure 24, in the initial state, both Sample A and Sample B have the same characteristics as Sample C. It is confirmed that the film has high crystallinity.

[0313] Next, Figure 25 shows the crystal state of Sample A and Sample B after 2 nsec. explain.

[0314] First, Figure 25(A) shows the crystalline state of sample A after 2 nsec. To investigate whether the structure has crystallinity, the radial distribution function g(r ) was sought.

[0315] The above-mentioned "radial distribution function g(r)" is the function of the distribution of other atoms at a distance r from a certain atom. is a function that represents the probability density of atoms existing in the r) approaches 1.

[0316] The calculation results of the radial distribution function for sample A are shown in Figure 25(B). The horizontal axis is the distance r (nm) and the vertical axis is the radial distribution function g (r). The dashed line represents the radial distribution function of sample A, and the dashed line represents the radial distribution function of sample C.

[0317] From Figure 25(B), the radial distribution function of sample A after 2 nsec is As with the radial distribution function, there is order (or peak) even when r (nm) becomes long-range. This suggests that the crystallinity is maintained.

[0318] Similarly, Fig. 26(A) shows the crystalline state of sample B after 2 nsec, and Fig. 26(B) shows the crystalline state of sample B after 2 nsec. The calculation results of the radial distribution function g(r) for this structure are shown below. The solid line in Figure 26(B) indicates The line represents the radial distribution function of sample B, and the dashed line represents the radial distribution function of sample C. be.

[0319] As shown in FIG. 26(A), the structure of sample B after 2 nsec is the same as that shown in FIG. 24(B). It is clear that the structure has changed compared to the initial structure of sample B. do.

[0320] Also, looking at Figure 26(B) which shows the radial distribution function of sample B after 2 nsec, r As the distance (nm) increases, the order disappears and the line becomes flat (the peak disappears). This means that the crystallinity is not maintained (i.e., amorphous). This suggests that the cellular membrane is becoming more and more dense.

[0321] In this specification, in a semiconductor device using an oxide semiconductor film as a semiconductor layer, The silicon concentration is 1.1 atomic % or less from the interface with the insulating film toward the oxide semiconductor film. However, the results of this example show that the semiconductor layer When an oxide semiconductor film with high crystallinity such as a CAAC-OS film is used as the The silicon concentration is 0.83 atomic % or less from the interface with the gate insulating film toward the oxide semiconductor film. It was confirmed that a structure having a region in which the concentration is distributed at 1000 ppm or more is more preferable. [Explanation of symbols]

[0322] 100 boards 102 insulating film 106 Oxide semiconductor film 106a area 106b area 106c low resistance area 107 Insulating film 108 Gate insulating film 109 Conductive film 110 gate electrode 114a Source electrode 114b Drain electrode 130 impurity ions 150 transistors 602 Conductive film 650 transistors 800 Interlayer insulating film 802 Interlayer insulating film 850 transistors 1100 insulating film 1101 insulating film 1102 Sidewall insulating film 1104 Conductive film 1150 transistor 1350 transistor 1700 boards 1706 Element isolation insulating layer 1708 Gate insulating film 1710 Gate electrode 1716 Channel formation region 1720 Impurity region 1724 Intermetallic compound area 1728 Insulating layer 1730 Insulation layer 1735 Interlayer insulating film 1736a Sidewall insulating film 1736b Sidewall insulating film 1737 insulating film 1742a Electrode membrane 1742b Electrode membrane 1744 Oxide semiconductor film 1748 Gate electrode 1750 insulating film 1752 insulating film 1753 Conductive layer 1756 Wiring 1760 transistors 1762 transistors 1764 Capacitor 1850 memory cells 1851 Memory Cell Array 1851a Memory Cell Array 1851b memory cell array 1853 Peripheral Circuit 2001 transistor 2002 Transistor 2003 Transistor 2004 Transistor 2005 Transistor 2006 Transistor 2007 X Decoder 2008 Y decoder 2011 Transistor 2012 holding capacity 2013 X Decoder 2014 Y Decoder 2101 RF circuit 2102 Analog Baseband Circuit 2103 Digital Baseband Circuit 2104 Battery 2105 Power supply circuit 2106 Application Processor 2107 CPU 2108 DSP 2109 Interface 2110 flash memory 2111 Display Controller 2112 Memory Circuit 2113 Display 2114 Display section 2115 Source Driver 2116 Gate Driver 2117 Audio Circuit 2118 keyboard 2119 Touch Sensor 2250 memory circuit 2251 memory controller 2252 memory 2253 memory 2254 Switch 2255 Switch 2256 display controller 2257 Display 2301 Battery 2302 Power supply circuit 2303 microprocessor 2304 flash memory 2305 Audio Circuit 2306 Keyboard 2307 Memory Circuit 2308 Touch Panel 2309 Display 2310 Display Controller 2501 Main Unit 2502 chassis 2503 Display section 2504 keyboard 2511 Main Unit 2512 Stylus 2513 Display section 2514 Operation button 2515 External Interface 2520 e-books 2521 Case 2522 Shaft 2523 Case 2525 Display section 2526 Power supply 2527 Display section 2528 Operation Key 2529 Speaker 2530 chassis 2531 Button 2532 Microphone 2533 Display section 2534 Speaker 2535 Camera Lens 2536 External connection terminal 2541 Main Unit 2542 Display section 2543 Operation switch 2544 Battery 2550 Television Equipment 2551 Case 2553 Display section 2555 Stand

Claims

1. an oxide semiconductor film; a gate insulating film on the oxide semiconductor film; a gate electrode on the gate insulating film overlapping at least the oxide semiconductor film; the oxide semiconductor film contains indium oxide, the gate insulating film includes silicon oxide; the oxide semiconductor film has a first region and a second region, the first region is located closer to the gate insulating film than the second region, the concentration of silicon contained in the first region is 0.83 atomic % or less and is higher than the concentration of silicon contained in the second region; The concentration of carbon contained in the first region is 1.0×10 ２０ atoms / cm ３ The semiconductor device is as follows:

2. In claim 1, The semiconductor device, wherein the first region is present in a range of 5 nm or less in thickness from the interface with the gate insulating film.

3. In claim 1 or claim 2, The semiconductor device, wherein the gate electrode has an In—O film containing nitrogen.

Images