Control system

The control system reallocates arithmetic processes and adjusts operating frequencies to maintain consistent calculation results and controlled movement by minimizing time discrepancies and movement restrictions due to abnormal cores.

JP2025139145APending Publication Date: 2025-09-26DENSO CORP +2
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Patent Information

Application Number
JP2024037928
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-03-12
Publication Date
2025-09-26

AI Technical Summary

Technical Problem

In control systems with multiple processor cores, reallocating arithmetic processes due to an abnormality in one core increases calculation time and movement of a moving body, potentially preventing desired calculation results at specific intervals.

Method used

A control system that reallocates arithmetic processes to normal cores, calculates a reduced movement upper limit based on post-allocation processing periods, and adjusts operating frequencies to minimize time differences, ensuring consistent calculation results and controlled movement.

Benefits of technology

The system maintains consistent calculation results and controlled movement by reducing the movement amount and processing time discrepancies, preventing excessive restrictions during abnormal core conditions.

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Abstract

To restrain calculation processing from becoming unable to acquire the calculation result at a desired distance interval in a control system.SOLUTION: A control system comprises a plurality of processor cores PC1-PC4, an abnormality diagnosis part 310, an assignment part 320 which executes reassignment so as to execute calculation processing, which is assigned to an abnormal core, on a normal core if it is diagnosed that there is an abnormality in some of the plurality of processor cores, a movement upper limit calculation part 340 which calculates a movement upper limit corresponding to an abnormality occurrence state of each processor core, and an actuator control part 420 which controls an actuator by using the calculation result obtained in the calculation processing so as to move a movable body with a movement amount related parameter of the movement upper limit or less. The movement upper limit calculation part calculates the movement upper limit so that the movement upper limit, when a processing period after reassignment is a first period, becomes lower than the movement upper limit when the processing period after assignment is a second period shorter than the first period.SELECTED DRAWING: Figure 1
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Description

[Technical Field]

[0001] The present disclosure relates to control systems. [Background technology]

[0002] Conventionally, a system has been known in which multiple processor cores execute multiple arithmetic processes in parallel (for example, Patent Document 1). In the control system described in Patent Document 1, if an abnormality occurs in one of the multiple processor cores, the system continues to operate by reallocating the arithmetic process that was assigned to the core in which the abnormality occurred to other cores that are not experiencing an abnormality. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-305317 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the technology described in Patent Document 1 is used in a control system that controls an actuator for moving a moving body using environmental information, which is information about the external environment, the time required for the calculation processing in the core to which the calculation processing is reallocated will increase, and the amount of movement of the moving body while the calculation processing is being executed will increase, which may make it impossible to obtain the calculation results of the calculation processing at the desired distance intervals. [Means for solving the problem]

[0005] The present disclosure can be realized in the following forms.

[0006] According to one aspect of the present disclosure, there is provided a control system (10) for controlling an actuator (40) for moving a moving body (V1) by using environmental information, which is information about an external environment. The control system includes a plurality of processor cores (PC1 to PC4) for executing arithmetic processing by using the environmental information, an abnormality diagnosis unit (310) for diagnosing the presence or absence of an abnormality in each of the processor cores, an allocation unit (320) for reallocating, when some of the plurality of processor cores are diagnosed as having an abnormality, the arithmetic processing assigned to the abnormal core, which is the processor core diagnosed as having an abnormality, to a normal core, which is a processor core diagnosed as having no abnormality, so that the arithmetic processing assigned to the abnormal core is executed by the normal core, which is the processor core diagnosed as having no abnormality, and an allocation unit (320) for controlling the actuator (40) for moving a moving body (V1) in accordance with the occurrence status of the abnormality in each of the processor cores. and an actuator control unit (420) that controls the actuator using the calculation results of the calculation process so as to move the moving body with the movement amount-related parameter that is equal to or less than the movement amount, wherein the movement upper limit calculation unit calculates the movement upper limit when a post-allocation processing period, which is the processing period of the calculation process after the reallocation, is a first period, so that the movement upper limit is lower than the movement upper limit when the post-allocation processing period is a second period that is shorter than the first period.

[0007] According to this aspect of the control system, the upper limit of movement is calculated so that the upper limit of movement when the post-allocation processing period is a first period is lower than the upper limit of movement when the post-allocation processing period is a second period that is shorter than the first period, and the actuator is controlled to move the moving body with a movement amount-related parameter that is equal to or less than the upper limit of movement. Therefore, when an abnormality occurs and the post-allocation processing period increases, the allowable upper limit of the movement amount-related parameter, which is a parameter related to the movement amount of the moving body, can be reduced to suppress an increase in the movement amount of the moving body during execution of the calculation processing, and it can be suppressed that the calculation results of the calculation processing cannot be obtained at the desired distance interval.

[0008] According to another aspect of the present disclosure, there is provided a control system (10a) that controls an actuator (40) for moving a moving body (V1) by utilizing environmental information that is information about an external environment. This control system includes a plurality of processor cores (PC1 to PC4) that execute arithmetic processing using the environmental information; an abnormality diagnosis unit (310) that diagnoses the presence or absence of an abnormality in each of the processor cores; an allocation unit (320) that, when it is diagnosed that some of the plurality of processor cores have an abnormality, executes a reallocation of the arithmetic processing to a normal core, that is, a processor core that has been diagnosed as having an abnormality, so that the arithmetic processing that was assigned to the abnormal core, that is, the processor core that has been diagnosed as having an abnormality, is executed by the normal core, that is, the processor core that has been diagnosed as having no abnormality; a frequency calculation unit that calculates a post-allocation operating frequency that is the operating frequency of the normal core after the reallocation in accordance with the occurrence status of an abnormality in each of the processor cores; and an actuator control unit (420) that controls the actuator using the calculation results of the arithmetic processing, wherein the frequency calculation unit calculates the post-allocation operating frequency so as to minimize the difference between the processing time required to execute the arithmetic processing using the normal core and the processing time required to execute the arithmetic processing using all of the plurality of processor cores, and when it is diagnosed that some of the plurality of processor cores have an abnormality, the normal core executes the arithmetic processing at the post-allocation operating frequency.

[0009] According to this control system, the post-allocation operating frequency is calculated so as to minimize the difference between the processing time required to execute the arithmetic processing using the normal cores and the processing time required to execute the arithmetic processing using all of the multiple processor cores. If an abnormality is diagnosed, the normal cores execute the arithmetic processing at the post-allocation operating frequency. Therefore, even if there are many abnormal cores and the processing load of the arithmetic processing on the normal cores increases, the time required for the arithmetic processing can be prevented from increasing and the inability to obtain the arithmetic processing results at the desired intervals can be prevented. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of a control system according to a first embodiment. [Figure 2] 4 is a flowchart showing the procedure of an abnormality handling process according to the first embodiment. [Figure 3] FIG. 10 is a block diagram showing the configuration of a control system according to a second embodiment. [Figure 4] 10 is a flowchart showing the procedure of an abnormality handling process according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] A. First embodiment: A-1. System Configuration: A control system 10 of this embodiment shown in FIG. 1 is mounted on a vehicle V1 and controls the vehicle V1. In this embodiment, the vehicle V1 is a vehicle equipped with an engine. The vehicle V1 is also capable of automatic driving and is configured to be able to switch between automatic driving and manual driving. "Automatic driving" refers to driving in which engine control, braking control, and steering control are performed automatically on behalf of the occupant. "Manual driving" refers to driving in which the occupant performs operations for engine control (pressing the accelerator pedal), braking control (pressing the brake pedal), and steering control (turning the steering wheel). Note that the vehicle V1 is not limited to a vehicle equipped with an engine, and may also be an electric vehicle, a hybrid vehicle, or a fuel cell vehicle.

[0012] As shown in FIG. 1, a vehicle V1 is equipped with a control system 10, a vehicle state acquisition unit 20, an environmental information acquisition unit 30, and an actuator 40.

[0013] The vehicle state acquisition unit 20 acquires vehicle state information. "Vehicle state information" means information relating to the vehicle state of the vehicle V1. "Vehicle state" means the driving state of the vehicle V1, such as the traveling speed, position, and attitude of the vehicle V1. The vehicle state acquisition unit 20 is, for example, a vehicle speed sensor, a yaw rate sensor, an acceleration sensor, etc. The vehicle state acquisition unit 20 outputs the acquired vehicle state to the control system 10.

[0014] The environmental information acquisition unit 30 acquires environmental information. "Environmental information" means information about the external environment of the vehicle V1, and includes, for example, information about the presence or absence of targets, other vehicles, pedestrians, etc., around the vehicle V1. The environmental information acquisition unit 30 is, for example, a camera, LiDAR, millimeter-wave radar, etc., mounted on the vehicle V1. In this embodiment, the environmental information acquisition unit 30 is configured as a camera and acquires captured images of the surroundings of the vehicle V1 as the environmental information. The environmental information acquisition unit 30 outputs the acquired captured images to the control system 10. Note that, when the environmental information acquisition unit 30 is configured as a LiDAR, the environmental information acquisition unit 30 acquires point cloud data indicating targets around the vehicle V1 as the environmental information.

[0015] The actuator 40 is an actuator for driving the vehicle V1. In this embodiment, the actuator 40 includes an engine 41, a brake mechanism 42, and a steering mechanism 43. The brake mechanism 42 is made up of a group of devices related to brake control, such as sensors, motors, valves, and pumps. The steering mechanism 43 is made up of a group of devices related to steering, such as a power steering motor. The engine 41, the brake mechanism 42, and the steering mechanism 43 are driven to perform the operations of the vehicle V1, i.e., driving, steering, and braking. The actuator 40 may also include a group of devices for operating accessories, including various lamps.

[0016] The control system 10 acquires vehicle state information and environmental information from the vehicle state acquisition unit 20 and the environmental information acquisition unit 30. The control system 10 executes arithmetic processing using the acquired vehicle state information and environmental information from the vehicle state acquisition unit 20 and the environmental information acquisition unit 30, and controls the actuator 40 using the results of the arithmetic processing to cause the vehicle V1 to travel. In this embodiment, the control system 10 includes a state recognition processor 100, an environment recognition processor 200, an abnormality monitoring processor 300, a vehicle control processor 400, a RAM 500, and a ROM 600. The state recognition processor 100, the environment recognition processor 200, the abnormality monitoring processor 300, the vehicle control processor 400, the RAM 500, and the ROM 600 are connected to each other via a bus. Note that while FIG. 1 illustrates one RAM 500 and one ROM 600 as storage devices, the control system 10 may include multiple RAMs corresponding to each processor, and may also include a cache memory.

[0017] The state recognition processor 100 functions as a vehicle state recognition unit 110 by expanding a program pre-stored in the ROM 600 into the RAM 500 and executing the program. The vehicle state recognition unit 110 acquires vehicle state information from the vehicle state acquisition unit 20 and identifies the vehicle state of the vehicle V1.

[0018] The environment recognition processor 200 is configured as a multi-core processor having processor cores PC1 to PC4. The processes in the processor cores PC1 to PC4 can be executed in parallel with each other. In the following description, the processor cores will also be simply referred to as "cores." By expanding a program pre-stored in the ROM 600 into the RAM 500 and executing it, the processor core PC1 functions as an image recognition unit 211 and a signal response unit 221, the processor core PC2 functions as an image recognition unit 212 and a signal response unit 222, the processor core PC3 functions as an image recognition unit 213 and a signal response unit 223, and the processor core PC4 functions as an image recognition unit 214 and a signal response unit 224.

[0019] The image recognition unit 211 acquires environmental information from the environmental information acquisition unit 30, and executes arithmetic processing using the environmental information, thereby identifying the external environment of the vehicle V1 as a result of the arithmetic processing. In this embodiment, the image recognition unit 211 executes arithmetic processing using a neural network model to identify the external environment of the vehicle V1. The image recognition unit 211 executes a series of arithmetic processing after the environmental information acquisition unit 30 acquires the environmental information. The processing in the image recognition units 212 to 214 is similar to that in the image recognition unit 211, and therefore a description thereof will be omitted. Note that the processing in the image recognition units 211 to 214 may be arithmetic processing using different neural network models, or arithmetic processing using the same neural network model may be executed in at least two of the image recognition units 211 to 214.

[0020] The signal response unit 221 outputs a signal to the anomaly monitoring processor 300, which will be described later, depending on whether or not an abnormality has occurred in the processor core PC1. More specifically, when an abnormality has occurred, the signal response unit 221 outputs an abnormality notification signal to the anomaly monitoring processor 300, notifying the occurrence of the abnormality. Furthermore, the signal response unit 221 may periodically output a watchdog pulse to the anomaly monitoring processor 300 while the processor core PC1 is operating normally. The processing in the anomaly monitoring processor 300 that has received the abnormality notification signal or watchdog pulse will be described later.

[0021] Furthermore, the signal response unit 221 receives a reset signal, which will be described later, when the reset signal is output from the abnormality monitoring processor 300. When the reset signal is received, the image recognition unit 211 restarts the calculation process.

[0022] The signal response units 222 to 224 execute the same processing as the signal response unit 221 in the processor cores PC2 to PC4, respectively.

[0023] The abnormality monitoring processor 300 functions as an abnormality diagnosis unit 310, an allocation unit 320, a period calculation unit 330, and an upper speed limit calculation unit 340 by expanding a program pre-stored in the ROM 600 into the RAM 500 and executing it.

[0024] The abnormality diagnosis unit 310 diagnoses whether or not an abnormality exists in each of the processor cores PC1 to PC4 of the environment recognition processor 200. More specifically, when the abnormality diagnosis unit 310 receives the abnormality notification signal, it diagnoses that an abnormality has occurred in the core having the signal response unit that output the abnormality notification signal, and outputs a reset signal to the signal response unit that output the signal. Furthermore, when the abnormality diagnosis unit 310 does not receive the watchdog pulse even after a preset time has elapsed, it determines that an abnormality has occurred in the core having the signal response unit whose output has been interrupted, and outputs a reset signal to the signal response unit whose output has been interrupted. Furthermore, the abnormality diagnosis unit 310 outputs information indicating an abnormal core, which is a core among the processor cores PC1 to PC4 in which an abnormality has occurred (hereinafter also referred to as "abnormal core information") to the allocation unit 320 at predetermined intervals. Note that when an abnormality has not occurred in any of the processor cores PC1 to PC4, the abnormality diagnosis unit 310 outputs abnormal core information indicating that no abnormality has occurred in any of the processor cores PC1 to PC4. In the following description, any of the processor cores PC1 to PC4 in which no abnormality has occurred will also be referred to as a "normal core."

[0025] In the following description, a state in which at least some of the processor cores PC1 to PC4 are diagnosed as having an abnormality is referred to as an “abnormal state.” Furthermore, a state in which none of the processor cores PC1 to PC4 are diagnosed as having an abnormality is referred to as a “normal state.”

[0026] When some of the processor cores PC1 to PC4 are diagnosed as having an abnormality, the allocation unit 320 reallocates arithmetic processes to normal cores. In this embodiment, the allocation unit 320 allocates arithmetic processes with higher priorities, which are preset for each arithmetic process, to normal cores with shorter total processing times. The "total processing time" refers to the total processing time for each normal core of the allocated arithmetic processes. This allows arithmetic processes with higher priorities to be preferentially allocated, and also prevents arithmetic processes from being allocated unevenly to some normal cores.

[0027] The allocation unit 320 also calculates the maximum processing time. The "maximum processing time" refers to the longest total processing time among the total processing times for each core. After completing the reallocation, the allocation unit 320 calculates the longest total processing time among the total processing times of each normal core as the maximum processing time.

[0028] The period calculation unit 330 calculates a post-allocation processing period. The "post-allocation processing period" refers to the processing period of the arithmetic processing in the normal core after reallocation. The "processing period" refers to the time required to complete a series of arithmetic processing. In this embodiment, the period calculation unit 330 calculates the post-allocation processing period as a value obtained by multiplying the processing period in a normal state (hereinafter also referred to as the "normal processing period") by n so that the post-allocation processing period is equal to or greater than the maximum processing time of the normal core. For example, if the normal processing period is "100 milliseconds" and the maximum processing time after reallocation is "150 milliseconds," the period calculation unit 330 calculates the post-allocation processing period as "200 milliseconds," which is double the normal processing period, so that the post-allocation processing period is equal to or greater than the maximum processing time after reallocation.

[0029] The upper speed limit calculation unit 340 calculates the upper speed limit, which is the allowable upper limit of the traveling speed of the vehicle V1, depending on the occurrence status of an abnormality in the processor cores PC1 to PC4. In this embodiment, the upper speed limit calculation unit 340 calculates the upper speed limit of the vehicle V1 using the allocated post-processing period calculated by the period calculation unit 330. More specifically, the upper speed limit calculation unit 340 calculates the upper speed limit by multiplying the value obtained by dividing the normal processing period by the allocated post-processing period by the upper speed limit in a normal state (hereinafter also referred to as the "normal speed limit"). Note that the normal processing period and the upper speed limit are identified through experiments and simulations and are set in advance. For example, if the normal speed limit is "100 km / h," the normal processing period is "100 milliseconds," and the allocated post-processing period is "200 milliseconds," the upper speed limit calculation unit 340 calculates the upper speed limit to be "50 km / h."

[0030] As described above, in this embodiment, the speed upper limit calculation unit 340 calculates the speed upper limit so as to reduce the speed upper limit in accordance with an increase in the post-allocation processing cycle. As a result, even if an abnormality occurs and the time required for the calculation processing in the normal core increases, an increase in the traveling speed of the vehicle V1 during the calculation processing can be suppressed, and the movement amount of the vehicle V1 during the calculation processing can be suppressed. Therefore, it is possible to suppress the inability to acquire the external environment, which is the calculation result of the calculation processing, at the desired distance interval. The speed upper limit calculation unit 340 corresponds to the "movement upper limit calculation unit" in this disclosure.

[0031] The vehicle control processor 400 loads a program stored in advance in the ROM 600 into the RAM 500 and executes the program, thereby functioning as a route planning unit 410 and a vehicle control unit 420. The route planning unit 410 creates a planned route, which is a planned travel route for the vehicle V1, based on the recognition result of the vehicle state by the vehicle state recognition unit 110 and the recognition result of the environment around the vehicle V1 by the image recognition units 211 to 214.

[0032] The vehicle control unit 420 controls the actuator 40 so as to make the vehicle V1 travel along the created planned route. As described above, the planned route is created using the external environment of the vehicle V1 output as the calculation result of the calculation process. That is, the vehicle control unit 420 controls the actuator 40 so as to make the vehicle V1 travel using the calculation result of the calculation process. The vehicle control unit 420 corresponds to the "actuator control unit" in this disclosure. Furthermore, the vehicle control unit 420 controls the actuator 40 so that the traveling speed of the vehicle V1 is equal to or less than the upper speed limit in normal conditions or the upper speed limit in an abnormal state set by the upper speed limit calculation unit 340. In this embodiment, the vehicle control unit 420 outputs a control signal to the actuator 40 instructing the traveling speed to be equal to or less than the upper speed limit, and the actuator 40 drives in accordance with the control signal, thereby realizing control of the vehicle V1 in accordance with the upper speed limit.

[0033] A-2. Abnormality Response Procedure: The abnormality handling process shown in FIG. 2 starts when the allocation unit 320 receives abnormality core information from the abnormality diagnosis unit 310.

[0034] In step S2, the allocation unit 320 uses the abnormal core information to determine whether the abnormal core is the same core as when the previous abnormality occurred. If it is determined that the abnormal core is the same core as when the previous abnormality occurred (step S2: Yes), in other words, if there is no change in the state of the abnormality in the environment recognition processor 200, the abnormality response process ends.

[0035] If it is determined that the core is not the same as the one at the time of the previous abnormality (step S2: No), in other words, if the abnormality has occurred in at least some cores that are different from the core at the time of the previous abnormality, the allocation unit 320 stops processing in all processor cores PC1 to PC4 in step S4, and reallocates the calculation processing to the normal core in step S6.

[0036] In step S8, the allocation unit 320 calculates and outputs the maximum processing time after reallocation as described above.

[0037] In step S10, the cycle calculation unit 330 uses the maximum processing time to calculate the post-allocation processing cycle as described above.

[0038] In step S12, the cycle calculation unit 330 determines whether the cycle ratio is equal to or less than a predetermined threshold. The "cycle ratio" refers to the ratio of the post-allocation processing cycle to the normal processing cycle. In this embodiment, the cycle calculation unit 330 determines whether the cycle ratio is equal to or less than 400%. Note that the threshold is not limited to 400%, and may be set arbitrarily depending on the degree to which the upper speed limit reduction is allowed.

[0039] If it is determined that the cycle ratio is equal to or less than the threshold value (step S12: Yes), the cycle calculation unit 330 outputs the post-allocation processing cycle in step S14.

[0040] In step S16, the upper speed limit calculation unit 340 uses the post-allocation processing period to calculate and output the upper speed limit as described above.

[0041] In step S18, vehicle control unit 420 controls the vehicle in accordance with the planned route created by route planning unit 410 and so as not to exceed the calculated upper speed limit. Thereafter, the abnormality response process ends.

[0042] If it is determined in step S12 that the period ratio is greater than the threshold value (step S12: No), in step S20, the period calculation unit 330 outputs an autonomous driving stop signal that instructs to stop the autonomous driving of the vehicle V1. In this embodiment, the period calculation unit 330 outputs a predetermined value that is not normally output, such as "processing period 0 milliseconds," as the autonomous driving stop signal.

[0043] If steps S14 to S18 are executed even when it is determined that the period ratio is greater than the threshold, vehicle control is executed according to an excessively reduced upper speed limit, and the traveling of vehicle V1 is excessively restricted. In this embodiment, if it is determined that the period ratio is greater than the threshold, the period calculation unit 330 outputs an automatic driving stop signal in step S20, so that it is possible to prevent vehicle control from being executed in such a state where the upper speed limit has been excessively reduced.

[0044] In step S22, the automatic driving is stopped. In this embodiment, the route planning unit 410 receives the automatic driving stop signal and stops creating the planned route. When the creation of the planned route is stopped, the vehicle control unit 420 is no longer able to perform automatic driving along the planned route, and automatic driving is stopped. Thereafter, the abnormality response processing ends. Note that after the automatic driving is stopped, the vehicle may be shifted to manual driving by the occupant, or the traveling of the vehicle V1 itself may be stopped.

[0045] In parallel with the above-mentioned steps S8 to S22, in step S24, the image recognition unit of the healthy core resumes the arithmetic processing in accordance with the reallocated arithmetic processing allocation, after which the anomaly handling processing ends.

[0046] When the above-described process is repeatedly executed, if the abnormality in at least one of the processor cores PC1 to PC4 is resolved, reallocation is performed according to the abnormality occurrence status of each core after the abnormality is resolved, and the periodic ratio and upper speed limit are reset. That is, if the abnormality in at least one abnormal core is resolved, the vehicle control unit 420 resumes controlling the actuator 40 to move the vehicle V1 at a traveling speed equal to or lower than the upper speed limit calculated according to the abnormality occurrence status after recovery. Therefore, when the abnormality in at least one abnormal core is resolved, it is possible to prevent the vehicle V1 from continuing to be excessively restricted in its traveling. Furthermore, even if the abnormality occurrence status of each core changes, it is possible to continue controlling the vehicle V1 in accordance with the upper speed limit if the periodic ratio is equal to or lower than the threshold value.

[0047] According to the control system 10 of the first embodiment described above, the upper speed limit is calculated so as to reduce the upper speed limit as the post-allocation processing period increases, and the vehicle V1 is caused to travel at a speed equal to or less than the upper speed limit. Therefore, even if an abnormality occurs and the post-allocation processing period increases, an increase in the movement amount of the vehicle V1 during the execution of the calculation processing can be suppressed, and it is possible to suppress the inability to acquire the external environment as the calculation result of the calculation processing at desired distance intervals.

[0048] Furthermore, the upper rate limit calculation unit 340 calculates the upper rate limit using the processing cycle calculated by the cycle calculation unit 330, and therefore can calculate an appropriate upper rate limit according to the post-allocation processing cycle.

[0049] Furthermore, the allocation unit 320 allocates multiple arithmetic processes to multiple normal cores so that arithmetic processes with higher pre-set priorities for each arithmetic process are allocated to normal cores with shorter total processing times, thereby enabling preferential allocation of arithmetic processes with higher priorities and preventing arithmetic processes from being allocated unevenly to some normal cores.

[0050] Furthermore, if it is determined that the period ratio is greater than the threshold value, the period calculation unit 330 outputs an automatic driving stop signal, and the vehicle control unit 420 stops control of the actuator 40, thereby preventing vehicle control from being performed in a state where the upper speed limit is excessively reduced.

[0051] Furthermore, when the abnormality is resolved in at least one of the multiple processor cores PC1 to PC4, the vehicle control unit 420 resumes controlling the actuator 40 to move the vehicle V1 at a speed that is equal to or lower than the upper speed limit calculated in accordance with the abnormality occurrence status of each processor core PC1 to PC4 after the abnormality is resolved, thereby preventing the vehicle V1 from continuing to be excessively restricted in its travel when the abnormality is resolved in at least one abnormal core.

[0052] B. Second embodiment: The control system 10a of the second embodiment differs from the control system 10 of the first embodiment in that it has an abnormality monitoring processor 300a instead of the abnormality monitoring processor 300, and in that it executes the abnormality response processing shown in Fig. 4 instead of the abnormality response processing shown in Fig. 2. The device configuration and other procedures in the abnormality response processing of the control system 10a of the second embodiment are the same as those of the control system 10 of the first embodiment, so the same configurations and procedures are denoted by the same reference numerals and detailed descriptions thereof will be omitted.

[0053] As shown in FIG. 3, the abnormality monitoring processor 300 a functions as an abnormality diagnosis unit 310 , an allocation unit 320 , and a frequency calculation unit 350 .

[0054] The frequency calculation unit 350 calculates the post-allocation operating frequency according to the occurrence status of an abnormality in the processor cores PC1 to PC4. The "post-allocation operating frequency" refers to the operating frequency of the normal cores after reallocation. If the abnormality diagnosis unit 310 diagnoses that some of the multiple processor cores have an abnormality, the normal cores execute arithmetic processing at the post-allocation operating frequency. In this embodiment, the frequency calculation unit 350 calculates the operating frequency so as to minimize the difference between the processing time required to execute arithmetic processing using the normal cores and the processing time required to execute arithmetic processing using all of the processor cores PC1 to PC4.

[0055] For example, if the operating frequency in the normal state (hereinafter also referred to as the "normal operating frequency") is "1 GHz," the maximum processing time in the normal state is "100 milliseconds," and the maximum processing time after reallocation is "200 milliseconds," the frequency calculation unit 350 calculates the operating frequency as "2 GHz." In this case, although the maximum processing time after reallocation is twice as long as that in the normal state, the normal core executes arithmetic processing at an operating frequency twice as long as that in the normal state, so the time required for arithmetic processing after reallocation is the same as that in the normal state. In this way, in this embodiment, even if the processing load of arithmetic processing in the normal core increases, it is possible to prevent an increase in the time required for arithmetic processing and to prevent an inability to acquire the external environment as the calculation result of arithmetic processing at a desired distance interval.

[0056] As shown in Figure 4, the abnormality response processing of this embodiment differs from the abnormality response processing of the first embodiment in that steps S12a to S16a are executed instead of steps S12 to S18 and step S24 in the abnormality response processing shown in Figure 2.

[0057] In step S10a, the frequency calculation unit 350 calculates the post-allocation operating frequency as described above using the maximum processing time.

[0058] In step S12a, the frequency calculation unit 350 determines whether the frequency ratio is equal to or less than a predetermined threshold. The "frequency ratio" refers to the ratio of the post-allocation operating frequency to the normal operating frequency. In this embodiment, the cycle calculation unit 330 determines whether the frequency ratio is equal to or less than 400%. Note that the threshold is not limited to 400%, and may be set arbitrarily according to the upper limit of the operating frequency predetermined as a specification of the processor cores PC1 to PC4.

[0059] If it is determined that the frequency ratio is equal to or less than the threshold value (step S12a: Yes), in step S14a, the cycle calculation unit 330 outputs the post-allocation operating frequency.

[0060] In step S16a, the image recognition unit in the healthy core resumes its calculation process at the allocated operating frequency, after which the abnormality handling process ends.

[0061] If it is determined in step S12a that the frequency ratio is greater than the threshold value (step S12a: No), the above-described steps S20 and S22 are executed, and the abnormality handling process ends.

[0062] In this embodiment, in step S20, the frequency calculation unit 350 outputs the above-mentioned automatic operation stop signal. In this embodiment, the frequency calculation unit 350 outputs a predetermined value that is not normally output, such as "operating frequency 0 GHz," as the automatic operation stop signal.

[0063] When the above-described process is repeatedly executed, if the abnormality in at least one of the processor cores PC1 to PC4 is resolved, reallocation is performed according to the abnormality occurrence status of each core after the abnormality is resolved, and the post-allocation operating frequency is reset. That is, if the abnormality in at least one abnormal core is resolved, the normal core resumes executing arithmetic processing at the post-allocation operating frequency calculated according to the abnormality occurrence status after the abnormality is resolved. Therefore, when the abnormality in at least one abnormal core is resolved, it is possible to prevent the state in which arithmetic processing is executed at an operating frequency higher than necessary and to prevent excessive processing load on the normal core. Furthermore, even if the abnormality occurrence status of each core changes, it is possible to continue arithmetic processing at the post-allocation operating frequency as long as the frequency ratio is equal to or less than a threshold.

[0064] According to the control system 10a of the second embodiment described above, when an abnormality is resolved in at least one of the multiple processor cores PC1 to PC4, the normal core resumes executing arithmetic processing at the post-allocation operating frequency calculated in accordance with the abnormality occurrence situation after the abnormality is resolved. Therefore, when an abnormality is resolved in at least one abnormal core, it is possible to prevent the state in which arithmetic processing is executed at an operating frequency higher than necessary from continuing, and it is possible to prevent the processing load on the normal core from becoming excessive.

[0065] C. Other Embodiments: (C1) In the above embodiment, the multiple arithmetic processes are executed by four processor cores PC1 to PC4 of the environment recognition processor 200 configured as a multi-core processor, but the present disclosure is not limited to this. The multiple arithmetic processes may be executed by multiple processor cores of different processors. For example, the multiple arithmetic processes may be executed by two multi-core processors each having two processor cores, or by four single-core processors. Note that in these embodiments, the number of processor cores in the control system 10 is not limited to "4" and may be any number equal to or greater than two. Such embodiments also achieve the same effects as the above embodiment.

[0066] (C2) In the above embodiment, in step S24 of the abnormality response processing, the route planning unit 410 receives the automatic driving stop signal, but the present disclosure is not limited to this. The automatic driving stop signal may be received by the vehicle control unit 420 or the image recognition units 211-214, and processing for stopping automatic driving may be executed. In a configuration in which the vehicle control unit 420 receives the automatic driving stop signal, the vehicle control unit 420 does not execute control of the actuator 40 even if the route planning unit 410 has created a planned route, thereby stopping automatic driving. Furthermore, in a configuration in which the image recognition units 211-214 receive the automatic driving stop signal, the image recognition units 211-214 do not execute calculation processing even if they acquire environmental information, thereby preventing the route planning unit 410 from creating a planned route, and automatic driving is stopped as in the above embodiment. In these configurations as well, automatic driving can be stopped when the automatic driving stop signal is output.

[0067] (C3) In the above embodiment, the control system 10 is realized as a single ECU having the state recognition processor 100, the environment recognition processor 200, the abnormality monitoring processor 300, and the vehicle control processor 400, but the present disclosure is not limited to this. The control system 10 may be realized by multiple ECUs, for example, an ECU having the state recognition processor 100, an ECU having the environment recognition processor 200, an ECU having the abnormality monitoring processor 300, and an ECU having the vehicle control processor 400. Even in such a configuration, the same effects as those of the above embodiment can be achieved.

[0068] (C4) In the above embodiment, the allocation unit 320 allocates arithmetic processes to healthy cores in descending order of priority, which is set in advance for each arithmetic process. However, the present disclosure is not limited to this. The allocation unit 320 may reallocate arithmetic processes to obtain an allocation pattern with the shortest maximum processing time after reallocation. For example, the allocation unit 320 sequentially calculates and compares the maximum processing times for multiple allocation patterns to identify the allocation pattern with the shortest maximum processing time. Note that the allocation unit 320 is not limited to the allocation pattern with the shortest maximum processing time, and may reallocate arithmetic processes to obtain any allocation pattern that does not maximize the maximum processing time, such as the allocation pattern with the second smallest maximum processing time. This configuration can prevent the maximum processing time from increasing after reallocation compared to a configuration in which reassignment is performed to obtain an allocation pattern with the longest maximum processing time.

[0069] The allocation unit 320 may also allocate arithmetic processing to the normal cores in accordance with an allocation pattern that is predetermined depending on the pattern of abnormality occurrence in the processor cores PC1 to PC4. This configuration makes it possible to easily perform reallocation.

[0070] (C5) In the above embodiment, the speed upper limit calculation unit 340 calculates the speed upper limit using the processing period calculated by the period calculation unit 330. However, the present disclosure is not limited to this. For example, the speed upper limit calculation unit 340 may calculate the speed upper limit using the maximum processing time after reallocation so that the speed upper limit decreases as the maximum processing time increases. Furthermore, the speed upper limit calculation unit 340 may calculate the speed upper limit using the number of abnormal cores so that the speed upper limit decreases as the number of abnormal cores increases. Because an increase in the maximum processing time or the number of abnormal cores increases the post-allocation processing period, calculating the speed upper limit using the maximum processing time or the number of abnormal cores can indirectly calculate the speed upper limit in response to an increase in the post-allocation processing period. If the processing period is not used to calculate the speed upper limit, the control system 10 may not need to include the period calculation unit 330. According to this embodiment, since calculation of the processing period is unnecessary, the control system 10 can avoid complex processing and easily calculate the speed upper limit.

[0071] Furthermore, if the speed upper limit calculation unit 340 calculates the speed upper limit using the maximum processing time or the number of abnormal cores after reallocation instead of the processing period, step S12 in the abnormality response process may determine whether the maximum processing time is equal to or less than a predetermined threshold or whether the number of abnormal cores is equal to or less than a predetermined threshold, instead of determining whether the period ratio is equal to or less than a predetermined threshold. If steps S14 to S18 described above are executed even if it is determined that the maximum processing time is greater than the threshold or the number of abnormal cores is greater than the threshold, vehicle control will be executed according to an excessively reduced speed upper limit, and the traveling of the vehicle V1 will be excessively suppressed. Therefore, by executing the above-described determination, it is possible to prevent vehicle control from being executed with an excessively reduced speed upper limit, as in the above embodiment.

[0072] Similarly, in 10a of the second embodiment, in step S12a of the abnormality response processing, instead of determining whether "the frequency ratio is equal to or less than a predetermined threshold value," a determination may be made as to whether "the maximum processing time is equal to or less than a predetermined threshold value" or "whether the number of abnormal cores is equal to or less than a predetermined threshold value."

[0073] (C6) In the above embodiment, the "control system" in the present disclosure is realized as the control system 10 of the vehicle V1, but the present disclosure is not limited thereto. The "control system" in the present disclosure may be realized as any system that controls an actuator using environmental information. For example, the "control system" in the present disclosure may be realized as a system that inspects the appearance of an object, such as a product, while transporting the object using a conveyor. In this embodiment, the conveyor corresponds to the "moving body" in the present disclosure, and the motor that drives the conveyor corresponds to the "actuator" in the present disclosure. In such a system, if an abnormality is detected in a core that executes arithmetic processing for inspection, the arithmetic processing is reallocated to a normal core, and the upper limit of the conveyor feed speed is reduced. As in the above embodiment, this embodiment can reduce the amount of conveyor movement during execution of the arithmetic processing, even if an abnormality occurs and the time required for arithmetic processing in a normal core increases, thereby preventing the inspection results from being unable to be executed at desired intervals.

[0074] Furthermore, the "control system" in the present disclosure may be realized as, for example, a system that acquires the external environment using a camera or the like and controls a robot arm. In this embodiment, the robot arm corresponds to the "moving body" in the present disclosure, and the motor that drives the robot arm corresponds to the "actuator" in the present disclosure. In such a system, if an abnormality is diagnosed in a core that executes arithmetic processing for controlling the robot arm, the arithmetic processing is reallocated to a normal core, and the upper limit of the movement speed of the robot arm is reduced. In this embodiment, as in the above embodiment, even if an abnormality occurs and the time required for arithmetic processing in the normal core increases, an increase in the movement amount of the robot arm during execution of the arithmetic processing can be suppressed, and the inability to acquire the external environment as the calculation result of the arithmetic processing at desired distance intervals can be suppressed.

[0075] (C7) In the above embodiment, vehicle control unit 420 outputs a control signal instructing the traveling speed to actuator 40, but the present disclosure is not limited to this. Vehicle control unit 420 may output a control signal instructing, for example, the amount of movement or acceleration from the current position to actuator 40. That is, generally, vehicle control unit 420 may output a control signal instructing a movement amount-related parameter, which is a parameter related to the amount of movement of vehicle V1.

[0076] In a configuration in which the vehicle control unit 420 controls the actuator 40 using a control signal indicating the amount of movement from the current position, the control system 10 may include, instead of the speed upper limit calculation unit 340, a movement amount upper limit calculation unit that calculates an upper limit of the amount of movement that is the allowable upper limit of the amount of movement during execution of the calculation process, depending on the occurrence of an abnormality in the processor cores PC1 to PC4. In this configuration, the movement amount corresponds to the "movement amount-related parameter" in this disclosure, the movement amount upper limit corresponds to the "upper limit of movement" in this disclosure, and the movement amount upper limit calculation unit corresponds to the "upper limit of movement" in this disclosure. In this configuration, the movement speed may exceed the upper limit of the speed in the above embodiment as long as the movement amount during execution of the calculation process is equal to or less than the upper limit of the amount of movement. This configuration also makes it possible to suppress the amount of movement of the vehicle V1 during execution of the calculation process, thereby preventing the external environment, which is the calculation result of the calculation process, from being unable to be acquired at desired distance intervals.

[0077] Furthermore, in a configuration in which the vehicle control unit 420 controls the actuator 40 using a control signal indicating acceleration, the control system 10 may include, instead of the speed upper limit calculation unit 340, an acceleration upper limit calculation unit that calculates an acceleration upper limit, which is an allowable upper limit of acceleration, depending on the occurrence of an abnormality in the processor cores PC1 to PC4. In this configuration, the acceleration corresponds to the "travel amount-related parameter" in this disclosure, the acceleration upper limit corresponds to the "travel upper limit" in this disclosure, and the acceleration upper limit calculation unit corresponds to the "travel upper limit calculation unit" in this disclosure. This configuration also makes it possible to suppress an increase in the traveling speed of the vehicle V1 during execution of the calculation process, and to suppress the travel amount of the vehicle V1 during execution of the calculation process. This makes it possible to suppress the inability to acquire the external environment, which is the calculation result of the calculation process, at desired distance intervals.

[0078] (C8) In the above embodiment, the processor cores PC1 to PC4 execute arithmetic processing using a neural network model, but the present disclosure is not limited to this. The processor cores PC1 to PC4 may execute any arithmetic processing that does not use a neural network model.

[0079] The present disclosure is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit thereof. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention section can be appropriately replaced or combined to solve some or all of the above-described problems or achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be appropriately deleted.

[0080] The control system 10 and methods described herein may be implemented by a special-purpose computer configured with a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the control system 10 and methods described herein may be implemented by a special-purpose computer configured with a processor configured with one or more dedicated hardware logic circuits. Alternatively, the control system 10 and methods described herein may be implemented by one or more special-purpose computers configured with a processor and memory programmed to perform one or more functions in combination with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory storage medium. [Explanation of symbols]

[0081] 10, 10a... control system, 40... actuator, 310... abnormality diagnosis unit, 320... allocation unit, 340... upper speed limit calculation unit, 350... frequency calculation unit, 420... vehicle control unit, PC1 to PC4... processor core

Claims

1. A control system (10) for controlling an actuator (40) for moving a moving body (V1) by utilizing environmental information, which is information about an external environment, comprising: a plurality of processor cores (PC1 to PC4) that execute arithmetic processing using the environmental information; an abnormality diagnosis unit (310) for diagnosing whether or not there is an abnormality in each of the processor cores; an allocation unit (320) that, when a part of the plurality of processor cores is diagnosed as having an abnormality, executes reallocation of the arithmetic processing to the normal cores so that the arithmetic processing assigned to the abnormal cores, which are the processor cores diagnosed as having an abnormality, is executed by the normal cores, which are the processor cores diagnosed as not having an abnormality; a movement upper limit calculation unit (340) that calculates a movement upper limit, which is an allowable upper limit of a movement amount related parameter, which is a parameter related to the movement amount of the moving body, in response to the occurrence state of an abnormality in each of the processor cores; an actuator control unit (420) that controls the actuator using the calculation result of the calculation processing so as to move the moving body with the movement amount related parameter that is equal to or less than the movement upper limit; Equipped with the movement upper limit calculation unit calculates the movement upper limit when a post-allocation processing period, which is a processing period of the calculation process after the reallocation, is a first period, so that the movement upper limit is lower than the movement upper limit when the post-allocation processing period is a second period that is shorter than the first period. Control system.

2. 2. The control system of claim 1, the movement amount related parameter includes a movement speed of the moving object; the movement upper limit calculation unit calculates, as the movement upper limit, a speed upper limit that is an allowable upper limit of the movement speed; the actuator control unit controls the actuator using a calculation result of the calculation processing so as to move the moving body at the moving speed that is equal to or less than the upper speed limit; the movement upper limit calculation unit calculates the speed upper limit when the post-allocation processing period is the first period so that the speed upper limit is lower than the speed upper limit when the post-allocation processing period is the second period. Control system.

3. 3. The control system of claim 2, the actuator is an actuator for driving a vehicle, the movement upper limit calculation unit calculates an upper limit of a traveling speed of the vehicle as the speed upper limit; Control system.

4. 4. A control system according to any one of claims 1 to 3, Further provided is a period calculation unit (330) for calculating the post-allocation processing period, the movement upper limit calculation unit calculates the movement upper limit by using the post-allocation processing period; Control system.

5. 4. A control system according to any one of claims 1 to 3, the plurality of processor cores execute, as the arithmetic processing, arithmetic processing that utilizes a neural network model; Control system.

6. 4. A control system according to any one of claims 1 to 3, When allocating a plurality of the arithmetic processes to a plurality of the normal cores, the allocation unit executes the reallocation so as to allocate the arithmetic process having a higher priority, which is preset for each of the arithmetic processes, to the normal core having a smaller total processing time, which is the sum of the processing times of the arithmetic processes allocated to each of the normal cores. Control system.

7. 4. A control system according to any one of claims 1 to 3, When allocating a plurality of the arithmetic processes to a plurality of the normal cores, the allocation unit performs the reallocation so as to obtain an allocation pattern in which a maximum processing time, which is the longest total processing time, is smaller among total processing times, which are the sum of processing times of the arithmetic processes allocated to each of the normal cores. Control system.

8. 4. A control system according to any one of claims 1 to 3, the allocation unit performs the reallocation in accordance with a preset allocation pattern. Control system.

9. 4. A control system according to any one of claims 1 to 3, the actuator control unit stops control of the actuator when a cycle ratio, which is a ratio of the post-allocation processing cycle to a normal processing cycle, which is a processing cycle of the arithmetic processing in a normal state, is higher than a predetermined threshold value. Control system.

10. 4. A control system according to any one of claims 1 to 3, when the abnormality in at least one of the plurality of processor cores is resolved, the actuator control unit resumes controlling the actuator so as to move the moving body with the movement amount related parameter equal to or less than the movement upper limit calculated in accordance with the occurrence state of the abnormality in each of the processor cores after the abnormality is resolved. Control system.

11. 4. A control system according to any one of claims 1 to 3, The environmental information is a captured image acquired by a camera. Control system.

12. 4. A control system according to any one of claims 1 to 3, The environmental information is point cloud data acquired by LiDAR, Control system.

13. A control system (10a) for controlling an actuator (40) for moving a moving body (V1) by utilizing environmental information that is information about an external environment, a plurality of processor cores (PC1 to PC4) that execute arithmetic processing using the environmental information; an abnormality diagnosis unit (310) for diagnosing whether or not there is an abnormality in each of the processor cores; an allocation unit (320) that, when a part of the plurality of processor cores is diagnosed as having an abnormality, executes reallocation of the arithmetic processing to the normal cores so that the arithmetic processing assigned to the abnormal cores, which are the processor cores diagnosed as having an abnormality, is executed by the normal cores, which are the processor cores diagnosed as not having an abnormality; a frequency calculation unit (350) that calculates a post-allocation operating frequency, which is an operating frequency of the normal core after the reallocation, in response to an abnormality occurrence state of each of the processor cores; an actuator control unit (420) that controls the actuator using the calculation result of the calculation processing; Equipped with the frequency calculation unit calculates the post-allocation operating frequency so as to reduce a difference between a processing time required to execute the arithmetic processing using the normal core and a processing time required to execute the arithmetic processing using all of the plurality of processor cores; When a part of the plurality of processor cores is diagnosed as having an abnormality, the normal core executes the arithmetic processing at the post-allocation operating frequency. Control system.

14. 14. The control system of claim 13, the plurality of processor cores execute, as the arithmetic processing, arithmetic processing that utilizes a neural network model; Control system.

15. 14. The control system of claim 13, When allocating a plurality of the arithmetic processes to a plurality of the normal cores, the allocation unit executes the reallocation so as to allocate the arithmetic process having a higher priority, which is preset for each of the arithmetic processes, to the normal core having a smaller total processing time, which is the sum of the processing times of the arithmetic processes allocated to each of the normal cores. Control system.

16. 14. The control system of claim 13, When allocating a plurality of the arithmetic processes to a plurality of the normal cores, the allocation unit performs the reallocation so as to obtain an allocation pattern in which a maximum processing time, which is the longest total processing time, is smaller among total processing times, which are the sum of processing times of the arithmetic processes allocated to each of the normal cores. Control system.

17. 14. The control system of claim 13, the allocation unit performs the reallocation in accordance with a preset allocation pattern. Control system.

18. 14. The control system of claim 13, the actuator control unit stops control of the actuator when a frequency ratio, which is a ratio of the post-allocation operating frequency to a normal operating frequency, which is an operating frequency of the processor core in a normal state, is higher than a predetermined threshold value. Control system.

19. 14. The control system of claim 13, when an abnormality is resolved in at least one of the plurality of processor cores, the normal core resumes executing the arithmetic processing at the post-allocation operating frequency calculated in accordance with the occurrence state of the abnormality in each of the processor cores after the abnormality is resolved; Control system.

20. 14. The control system of claim 13, The environmental information is a captured image acquired by a camera. Control system.

21. 14. The control system of claim 13, The environmental information is point cloud data acquired by LiDAR, Control system.

22. A control system according to any one of claims 13 to 21, comprising: The actuator is an actuator for driving a vehicle. Control system.

Citation Information

Patent Citations

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