Multilayer connection structure and manufacturing method thereof, semiconductor device

Abstract

To provide a multilayer connection structure and a manufacturing method thereof, and a semiconductor device.SOLUTION: A multilayer connection structure includes: a laminated structure; a plurality of interconnection through holes arranged at intervals in a horizontal direction; and interconnection conductors HL1 to HL4 filled in the interconnection through holes. The multilayer connection structure further includes: a plurality of lead film layers 1a to 1e; and at least one insulating film layer 2a to 2f. Each of the lead film layers and the insulating film layers are alternately arranged along a vertical direction Z, include at least actual lead pattern portions, and expose the actual lead pattern portion of the at least one lead film layer. Positions of the lead film layers in which the actual lead pattern portion 11 correspondingly exposed by the at least two interconnection through holes are located are not exactly the same, and each of the interconnection through holes penetrates through at least all the film layers on the lowermost lead film layer in at least the laminated structure.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a multilayer interconnect structure, a manufacturing method thereof, and a semiconductor device. [Background technology]

[0002] Currently, semiconductor technology is rapidly developing, and semiconductor components in semiconductor devices are becoming increasingly dense, leading to an ever-increasing number of lead film layers in interconnection structures, which in turn leads to increasingly complex connections between lead film layers and lead-out methods, resulting in significant manufacturing costs and wasted production capacity. Summary of the Invention

[0003] The embodiments of the present invention provide a multilayer connection structure, a manufacturing method thereof, and a semiconductor device that can not only realize connections between interconnection conductors and corresponding lead film layers, but also reduce manufacturing costs and waste of production capacity.

[0004] A first aspect of the present application provides a multi-layer connection structure, a laminated structure, a plurality of interconnect through-holes spaced apart in a horizontal direction, and interconnect conductors filling the interconnect through-holes; the laminated structure includes a plurality of lead film layers and at least one insulating film layer, the lead film layers and the insulating film layers are alternately arranged along a vertical direction, and each of the lead film layers includes at least an actual lead pattern portion; The interconnection through hole exposes an actual lead pattern portion of at least one of the lead film layers, and the positions of the lead film layers on which the actual lead pattern portions correspondingly exposed by at least two of the interconnection through holes are located are not exactly the same, and each of the interconnection through holes penetrates at least all film layers above the lowest lead film layer in the laminated structure.

[0005] In an exemplary embodiment of the present disclosure, the top surfaces of any of the interconnect through holes are flush with one another.

[0006] In exemplary embodiments of the present disclosure, the top surface of the interconnect conductor is flush with the top surface of the laminate structure; and / or The insulating film layer is provided in a plurality of layers, and the uppermost layer of the laminated structure is the insulating film layer; and / or The lead film layer is provided in three or more layers.

[0007] In an exemplary embodiment of the present disclosure, at least one of the lead film layers above the lowest lead film layer in the laminated structure further includes a dummy pattern portion separated from the actual lead pattern portion, and in the same lead film layer, a lower end surface of the dummy pattern portion is flush with a lower end surface of the actual lead pattern portion, and an upper end surface of the dummy pattern portion is flush with an upper end surface of the actual lead pattern portion; The dummy pattern portion overlaps at least one of the interconnection through-holes in the vertical direction and is exposed.

[0008] In an exemplary embodiment of the present disclosure, each of the interconnection through holes penetrates a pattern portion of each of the lead film layers above the lowest lead film layer along a vertical direction, and the pattern portion through which the interconnection through hole penetrates along a vertical direction includes the actual lead pattern portion and / or the dummy pattern portion.

[0009] In an exemplary embodiment of the present disclosure, the lower end surfaces of any of the interconnect through holes are flush with one another; The interconnection through-holes penetrate the pattern portion of the lowermost lead film layer, or The lower ends of the interconnection through holes are embedded in the pattern portion of the lowermost lead film layer.

[0010] In an exemplary embodiment of the present disclosure, the vertical orthogonal projection of at least one of the interconnect through holes is located entirely within one pattern portion of each of the lead film layers; and / or a vertical orthogonal projection of at least one of the interconnection through holes overlaps with at least one pattern portion located in the lead film layer of the same layer; and / or At least one pattern portion is exposed by a plurality of the interconnection through holes.

[0011] A second aspect of the present application provides a semiconductor device, comprising a substrate and at least one multilayer connection structure according to any one of the preceding claims formed on the substrate.

[0012] A third aspect of the present application provides a method for manufacturing a multilayer connection structure, the method comprising: forming a laminated structure by alternately arranging lead film layers and insulating film layers on a substrate along a vertical direction, the lead film layers being provided in a plurality of layers, the insulating film layer being provided in at least one layer, and each of the lead film layers including at least an actual lead pattern portion; forming a topmost film layer of the laminated structure, and then performing a patterning process on the laminated structure using an etching process to form a plurality of interconnection through-holes spaced apart in a horizontal direction, the interconnection through-holes penetrating at least all film layers above the bottommost lead film layer in the laminated structure and exposing actual lead pattern portions of at least one of the lead film layers, and the positions of the lead film layers where the actual lead pattern portions correspondingly exposed by at least two of the interconnection through-holes are located are not exactly the same; and filling each of the interconnect through holes with a conductive material to form an interconnect conductor in each of the interconnect through holes.

[0013] In an exemplary embodiment of the present disclosure, at least one of the lead film layers further includes a dummy pattern portion separated from the actual lead pattern portion, the interconnection through-holes pass through the pattern portions of each of the lead film layers above the bottom lead film layer along a vertical direction, and the pattern portion through which the interconnection through-holes pass along a vertical direction includes the actual lead pattern portion and / or the dummy pattern portion; The step of forming a lead film layer including the actual lead pattern portion and the dummy pattern portion includes: forming a conductive film on the substrate; The method includes the step of simultaneously forming the actual lead pattern portion and the dummy pattern portion by performing a patterning process on the conductive film.

[0014] In an exemplary embodiment of the present disclosure, the interconnection through-holes penetrate through pattern portions of each of the lead film layers above the lowest lead film layer along a vertical direction, and the pattern portions through which the interconnection through-holes penetrate along a vertical direction include the actual lead pattern portion and / or the dummy pattern portion; The step of forming a lead film layer including the actual lead pattern portion and the dummy pattern portion includes: forming a conductive film on the substrate; performing a patterning process on the conductive film using a single patterning process to simultaneously form a portion of the actual lead pattern portion and at least one intermediate pattern portion, and the intermediate pattern portion and the actual lead pattern portion are separated from each other; and performing a patterning process on the intermediate pattern portion using a single patterning process to simultaneously form another portion of the actual lead pattern portion and the dummy pattern portion.

[0015] The technical solutions provided by the embodiments of the present invention have at least the following advantages:

[0016] In the present invention, all of the interconnect through holes in the multilayer connection structure penetrate all of the film layers above the bottom lead film layer in the laminate structure. That is, the interconnect conductors corresponding to all of the interconnect through holes in the multilayer connection structure of the present invention are formed after the top film layer of the laminate structure is manufactured. This design facilitates simultaneous manufacturing of different types of interconnect conductors in the multilayer connection structure. Compared with structural solutions that require individual manufacturing of different types of interconnect conductors, the design solution for the multilayer connection structure of the present invention can reduce the manufacturing cost of the multilayer connection structure and reduce waste of production capacity. [Brief explanation of the drawings]

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without any creative efforts. [Figure 1a] 1A-1C show schematic diagrams of multi-layer interconnect structures shown in different related arts. [Figure 1b] 1A-1C show schematic diagrams of multi-layer interconnect structures shown in different related arts. [Figure 2] 1A and 1B show structural schematic diagrams of multi-layer connection structures according to different embodiments of the present invention; [Figure 3] 1A and 1B show structural schematic diagrams of multi-layer connection structures according to different embodiments of the present invention; [Figure 4] 1A and 1B show structural schematic diagrams of multi-layer connection structures according to different embodiments of the present invention; [Figure 5] 1A and 1B show structural schematic diagrams of multi-layer connection structures according to different embodiments of the present invention; [Figure 6] 1 shows a schematic diagram of a laminate structure after perforation processing according to one embodiment of the present invention. [Figure 7] 1 shows a schematic structural diagram of a laminated structure including an actual lead pattern portion and a dummy pattern portion according to an embodiment of the present invention; [Figure 8] 8 shows a schematic diagram of the laminated structure shown in FIG. 7 after hole opening treatment. [Figure 9] 1 shows a structural schematic diagram of a multi-layer connection structure according to another embodiment of the present invention; [Figure 10] 1A and 1B are schematic diagrams illustrating the planar relationship between interconnection conductors and pattern portions according to different embodiments of the present invention; [Figure 11] 1A and 1B are schematic diagrams illustrating the planar relationship between interconnection conductors and pattern portions according to different embodiments of the present invention; [Figure 12] 1A and 1B are schematic diagrams illustrating the planar relationship between interconnection conductors and pattern portions according to different embodiments of the present invention; [Figure 13] 1A and 1B are schematic diagrams illustrating the planar relationship between interconnection conductors and pattern portions according to different embodiments of the present invention; [Figure 14] 1 shows a structural schematic diagram of a multi-layer connection structure according to another embodiment of the present invention; [Figure 15] 1 shows a structural schematic diagram of a multi-layer connection structure according to another embodiment of the present invention; [Figure 16] 3A-3D show structural schematic diagrams corresponding to different steps when manufacturing a multi-layer connection structure according to an embodiment of the present invention; [Figure 17] 3A-3D show structural schematic diagrams corresponding to different steps when manufacturing a multi-layer connection structure according to an embodiment of the present invention; [Figure 18] 3A-3D show structural schematic diagrams corresponding to different steps when manufacturing a multi-layer connection structure according to an embodiment of the present invention; [Figure 19] 3A-3D show structural schematic diagrams corresponding to different steps when manufacturing a multi-layer connection structure according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0018]

[0023] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings. However, exemplary embodiments may be embodied in various forms and should not be construed as being limited to the examples set forth herein. Rather, these embodiments are provided so that the present invention will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art.

[0019] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present application. However, those skilled in the art will understand that the technical solutions of the present application may be implemented without one or more of the specific details, or may employ other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the present application.

[0020] The present application will be described in more detail below in conjunction with the accompanying drawings and specific examples. It should be noted that the technical features contained in the various embodiments of the present application described below can be combined with each other as long as they are not mutually contradictory. The embodiments described below with reference to the drawings are illustrative and are intended to explain the present application, and should not be construed as limiting the present application.

[0021] With the continuous development of semiconductor technology, semiconductor components are becoming increasingly dense in semiconductor devices, which leads to increasingly complex interconnections between lead film layers and between lead film layers and other circuits, resulting in an ever-increasing variety of interconnect conductors required for three-dimensional stacking processes.

[0022] It should be understood that an interconnect conductor refers to a conductive structure used to connect different conductive components; for example, an interconnect conductor can provide connections between different lead film layers, between different leads within each lead film layer, between a lead film layer and an external operating circuit, etc.

[0023] Furthermore, interconnect conductors that realize connections between different lead film layers and interconnect conductors that realize connections between lead film layers and external operating circuits can be defined as interconnect conductors of vertical interconnects, and interconnect conductors that realize connections between different leads within each lead film layer can be defined as interconnect conductors of horizontal interconnects.

[0024] In semiconductor devices, the interconnect conductors of vertical interconnects include many types. When the leads connected to the interconnect conductors of multiple vertical interconnects are located on different lead film layers, this means that the types of the interconnect conductors of these multiple vertical interconnects are different. This will be explained specifically with reference to the stacked structure shown in Figure 1a. In Figure 1a, there are four types of interconnect conductors of vertical interconnects in the stacked structure, namely, first interconnect conductor HL1, second interconnect conductor HL2, third interconnect conductor HL3, and fourth interconnect conductor HL4. The first interconnection conductor HL1 connects the corresponding leads 10 in the first lead film layer 1a and the second lead film layer 1b, the second interconnection conductor HL2 connects the corresponding leads 10 in the first lead film layer 1a and the third lead film layer 1c, one end of the third interconnection conductor HL3 is connected to the corresponding lead 10 in the first lead film layer 1a, and the other end of the third interconnection conductor HL3 extends in a direction away from the first lead film layer 1a, penetrates the laminated structure, and can be drawn out to connect to an external operating circuit (not shown), and one end of the fourth interconnection conductor HL4 is connected to the corresponding lead 10 in the fourth lead film layer 1d, and the other end of the fourth interconnection conductor HL4 extends in a direction away from the fourth lead film layer 1d, penetrates the laminated structure, and can be drawn out to connect to an external operating circuit (not shown).

[0025] It should be noted that Figure 1a is used only to illustrate the existence of multiple types of interconnect conductors of vertical interconnects in a laminate structure, and this does not mean that the laminate structure must include the interconnect conductors of vertical interconnects of the type shown in Figure 1a. That is, the laminate structure may include all types of interconnect conductors of vertical interconnects shown in Figure 1a, may include some types of interconnect conductors of vertical interconnects shown in Figure 1a, or may not include all types of interconnect conductors of vertical interconnects shown in Figure 1a. Different types of interconnect conductors of vertical interconnects are designed according to specific product requirements. Furthermore, the number of interconnect conductors of vertical interconnects, the number of lead film layers, the number of leads in a lead film layer, etc. are not limited to those shown in Figure 1a and can be designed according to actual conditions.

[0026] 1a, the interconnect conductor of the vertical interconnect is usually designed between two structures to be connected, so that the interconnect conductor of different types of vertical interconnect needs to be manufactured separately, so that when the lead film layer becomes denser and denser and more types of interconnect conductor of the vertical interconnect are required, the manufacturing cost becomes higher and the production capacity is wasted.

[0027] Furthermore, if the number of layers in the lead film layer 1 is relatively large and there are leads 10 on both adjacent layers that need to be connected by interconnect conductors HL for vertical interconnections, as shown in Figure 1b, for example, the interconnect conductors HL for vertical interconnections on each layer need to be manufactured separately.When manufacturing the interconnect conductors HL corresponding to each layer, holes need to be made in each layer (these holes are for accommodating the interconnect conductors), which increases the number of processes according to the number of layers in the lead film layer 1 and also increases the manufacturing cost.

[0028] To solve this technical problem, an embodiment of the present invention provides a multilayer interconnection structure applicable to semiconductor devices. Here, the multilayer interconnection structure may include a stacked structure, which may include multiple lead film layers and multiple insulating film layers, with the lead film layers and insulating film layers alternately arranged in the vertical direction. That is, the stacked structure may include a structure in which lead film layers, insulating film layers, lead film layers, insulating film layers, etc. are alternately stacked. Here, the multilayer interconnection structure may further include multiple interconnection through-holes spaced apart in the horizontal direction and interconnection conductors filled in each interconnection through-hole. The multiple interconnection conductors of the multilayer interconnection structure may include, but are not limited to, different types of interconnection conductors. The multiple interconnection conductors of the multilayer interconnection structure may include interconnection conductors of the same type, but whether they have the same type of interconnection conductors can be designed according to actual circumstances.

[0029] Hereinafter, a multilayer connection structure according to an embodiment of the present invention will be described in detail with reference to the drawings.

[0030] Referring to Figure 2, the laminated structure may include a first insulating film layer 2a, a first lead film layer 1a, a second insulating film layer 2b, a second lead film layer 1b, a third insulating film layer 2c, a third lead film layer 1c, a fourth insulating film layer 2d, a fourth lead film layer 1d, a fifth insulating film layer 2e, a fifth lead film layer 1e, and a sixth insulating film layer 2f, which are sequentially laminated along the vertical direction Z.

[0031] In the laminated structure of the present invention, the bottom layer (i.e., the first layer formed) may be an insulating layer, such as the first insulating layer 2a shown in FIG. 2, or may insulate the bottom lead layer (e.g., the first lead layer 1a shown in FIG. 2) from other external circuits and protect the bottom lead layer, but is not limited thereto. The bottom layer may be a lead layer to facilitate connection with other circuit structures, and specific designs may be made according to actual needs. The top layer (the last layer to be formed) may be an insulating layer, such as the sixth insulating layer 2f shown in FIG. 2, or may insulate the top lead layer (e.g., the fifth lead layer 1e shown in FIG. 2) from other external circuits and protect the top lead layer, but is not limited thereto. The top layer may be a lead layer to facilitate connection with other circuit structures, and specific designs may be made according to actual needs.

[0032] The insulating film layer is not limited to the above-mentioned multiple layers, and when the lead film layer has two layers, the insulating film layer may be one layer located between the two lead film layers. When the lead film layer has two layers, the insulating film layer may be provided in multiple layers, and may be designed according to the specific situation, for example, alternately arranged in the order of insulating film layer, lead film layer, insulating film layer, lead film layer, or alternately arranged in the order of lead film layer, insulating film layer, lead film layer, insulating film layer, or alternately arranged in the order of insulating film layer, lead film layer, insulating film layer, lead film layer, insulating film layer.

[0033] In some other embodiments, the lead film layers may be three or more layers, for example, but not limited to, five layers as shown in Figure 2, and may be three, four, or more than five layers. By providing three or more lead film layers, it is possible to realize diversity in the interconnect structure design and increase the interconnect density. Applying the interconnect structure of the present invention to the wiring of a three-dimensional memory structure can reduce the manufacturing cost of the wiring of the three-dimensional memory structure.

[0034] In the embodiment of the present invention, it is to be understood that each lead film layer may include at least a plurality of pattern portions, and the material of the pattern portions may be a conductive material, i.e., the pattern portions themselves may be conductive. For example, the material of the pattern portions may include, but is not limited to, one or more metallic conductive materials such as aluminum, copper, tungsten, etc., and may also be other non-metallic conductive materials such as graphite, or semiconductor materials such as silicon, etc., which will not be further described herein.

[0035] The plurality of pattern portions of each lead film layer may include at least an actual lead pattern portion 11, which refers to a portion that is actually used in a circuit structure to realize a function such as signal transmission. For example, the actual lead pattern portion 11 in the lead film layer may include one or more of a word line, a bit line, a capacitor plate, a ground line, a bridge line, a gate, a source electrode, and a drain electrode, but is not particularly limited thereto and may be designed according to actual needs.

[0036] Furthermore, the number and arrangement of the actual lead pattern portions 11 in each lead film layer can be designed according to the actual situation, and therefore detailed explanations thereof will be omitted here.

[0037] In some embodiments, each lead film layer may include, in addition to the conductive pattern portion, an insulating separator 12, which may be formed in an area of ​​the lead film layer where electrical conductivity is not required. For example, the insulating separator 12 may be formed in the gap between adjacent pattern portions so that the pattern portions of each lead film layer achieve insulating separation at specific positions, or the insulating separator 12 may be formed at the edge positions of the entire lead film layer.

[0038] Of these, the upper surface of the insulating separation portion 12 can be made flush with the upper surface of the pattern portion, thereby ensuring the flatness of the surface of the lead film layer, making it easier to carry out the subsequent film layer process and ensuring the flatness of the subsequent film layer formation.

[0039] For example, the material of the insulating isolation portion 12 may be the same as, but is not limited to, the material of the insulating film layer, and may be different from, and in the embodiments of the present invention, the material of the insulating film layer and the insulating isolation portion 12 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, etc., and may be, but is not limited to, a low-k (low dielectric constant) dielectric material to reduce crosstalk between adjacent lead film layers and interconnect conductors, and other insulating materials may also be used.

[0040] In the multilayer connection structure of the present invention, each interconnection conductor can be connected to the actual lead pattern portion 11 of at least one lead film layer according to an actual design, and it should be noted that the positions of the lead film layers on which the actual lead pattern portions 11 to which at least two interconnection conductors are connected are located are not exactly the same. That is, the multilayer connection structure of the present invention includes interconnection conductors of different types of vertical interconnections. For example, in some embodiments, referring to FIG. 2, in the multilayer connection structure, the number of lead film layers on which the actual lead pattern portions 11 to which the first interconnection conductor HL1, the second interconnection conductor HL2, the third interconnection conductor HL3, and the fourth interconnection conductor HL4 are connected are the same, but the positions are partially different. That is, the number of lead film layers on which the actual lead pattern portions 11 to which the first interconnect conductor HL1, the second interconnect conductor HL2, the third interconnect conductor HL3, and the fourth interconnect conductor HL4 are connected are all two, and the actual lead pattern portions to which the first interconnect conductor HL1 is connected include the actual lead pattern portion 11 located on the first lead film layer 1a and the actual lead pattern portion 11 located on the second lead film layer 1b, and the actual lead pattern portion to which the second interconnect conductor HL2 is connected includes the actual lead pattern portion 11 located on the first lead film layer 1a. 2, the first interconnection conductor HL1, the second interconnection conductor HL2, the third interconnection conductor HL3, and the fourth interconnection conductor HL4 include an actual lead pattern portion 11 located on the first lead film layer 1a and an actual lead pattern portion 11 located on the third lead film layer 1c, the actual lead pattern portion to which the third interconnection conductor HL3 corresponds and connects includes an actual lead pattern portion 11 located on the first lead film layer 1a and an actual lead pattern portion 11 located on the fourth lead film layer 1d, and the actual lead pattern portion to which the fourth interconnection conductor HL4 corresponds and connects includes an actual lead pattern portion 11 located on the first lead film layer 1a and an actual lead pattern portion 11 located on the fifth lead film layer 1e. That is, in the multilayer connection structure shown in FIG. 2, the first interconnection conductor HL1, the second interconnection conductor HL2, the third interconnection conductor HL3, and the fourth interconnection conductor HL4 are different types of interconnection conductors.

[0041] In another embodiment, as shown in FIG. 3, the multilayer connection structure includes interconnect conductors in which the corresponding connecting actual lead pattern portions 11 are located on the same number of lead film layers but at completely different positions, such as the first interconnect conductor HL1 and the second interconnect conductor HL2; interconnect conductors in which the corresponding connecting actual lead pattern portions 11 are located on different number of lead film layers and at completely different positions, such as the third interconnect conductor HL3 and the fourth interconnect conductor HL4; and interconnect conductors in which the corresponding connecting actual lead pattern portions 11 are located on different number of lead film layers and at partially different positions, such as the first interconnect conductor HL1 and the third interconnect conductor HL3, the first interconnect conductor HL1 and the fourth interconnect conductor HL4, or the second interconnect conductor HL2 and the fourth interconnect conductor HL4.

[0042] It should be noted that the multilayer connection structure of the present invention is not limited to the designs shown in FIGS. 2 and 3, and other designs are possible according to actual needs, and no excessive examples are shown here.

[0043] In a specific implementation of the present invention, in a multilayer connection structure, each interconnection conductor penetrates at least all film layers above the bottom lead film layer of the laminated structure. That is, each interconnection conductor extends from the top end of the laminated structure (the end farthest from the substrate required in the manufacturing process) to the bottom end of the laminated structure (the end closest to the substrate required in the manufacturing process), penetrating at least all film layers above the bottom lead film layer of the laminated structure. It should be understood that all film layers referred to herein include insulating film layers and lead film layers, and that when each interconnection conductor penetrates at least all film layers above the bottom lead film layer of the laminated structure, each interconnection conductor can be connected to a corresponding actual lead pattern portion 11 in the corresponding lead film layer. That is, if an interconnection conductor and a corresponding actual lead pattern portion in the corresponding lead film layer are not separated in orthogonal projection, the interconnection conductor is considered to be connected to the corresponding actual lead pattern portion in the corresponding lead film layer.

[0044] 2 and 3, the first interconnect conductor HL1, the second interconnect conductor HL2, the third interconnect conductor HL3, and the fourth interconnect conductor HL4 can penetrate all film layers above the bottom lead film layer (i.e., the first lead film layer 1a). In other words, the first interconnect conductor HL1, the second interconnect conductor HL2, the third interconnect conductor HL3, and the fourth interconnect conductor HL4 can penetrate the sixth insulating film layer 2f, the fifth lead film layer 1e, the fifth insulating film layer 2e, the fourth lead film layer 1d, the fourth insulating film layer 2d, the third lead film layer 1c, the third insulating film layer 2c, the second lead film layer 1b, and the second insulating film layer 2b.

[0045] Here, each interconnection conductor in the multilayer connection structure needs to penetrate all film layers above the bottom lead film layer in the laminated structure to connect with the actual lead pattern portion 11 in the corresponding lead film layer. Therefore, all interconnection conductors in the multilayer connection structure of the present invention are formed after the topmost film layer of the laminated structure is completed. This design facilitates simultaneous manufacturing of different types of interconnection conductors in the multilayer connection structure. Compared with the structural solution shown in FIG. 1a, in which different types of interconnection conductors need to be manufactured individually, and the structural solution of FIG. 1b, in which the multilayer interconnection conductors are manufactured layer by layer, the design solution for the multilayer connection structure of the present invention can reduce the manufacturing cost of the multilayer connection structure and reduce wasted production capacity.

[0046] It should be noted that each interconnect conductor is not limited to penetrating all film layers above the bottom lead film layer in the laminate structure, but may also penetrate the bottom lead film layer. For example, as shown in Fig. 4, the first interconnect conductor HL1, the second interconnect conductor HL2, the third interconnect conductor HL3, and the fourth interconnect conductor HL4 penetrate the sixth insulating film layer 2f, the fifth insulating film layer 1e, the fifth insulating film layer 2e, the fourth insulating film layer 1d, the fourth insulating film layer 2d, the third lead film layer 1c, the third insulating film layer 2c, the second lead film layer 1b, and the second insulating film layer 2b, and also penetrate the first lead film layer 1a (i.e., the bottom lead film layer). However, without being limited thereto, each interconnect conductor may also extend into the first lead film layer 1a, as shown in Figs. 2 and 3, in addition to penetrating all film layers above the first lead film layer 1a in the laminate structure. Alternatively, each interconnection conductor may penetrate only all film layers above the first lead film layer 1a in the laminate structure, but may not penetrate the first lead film layer 1a, and may extend only to the top surface of the first lead film layer 1a, i.e., just contact the top surface of the first lead film layer 1a, as shown in FIG. 5.

[0047] In some embodiments, the orthogonal projection of the interconnect conductor of the present invention in the vertical direction Z can be located within the actual lead pattern portion 11 to which the interconnect conductor corresponds. As described above, since the interconnect conductor penetrates at least all film layers above the lowest lead film layer, if the actual lead pattern portion 11 to which the interconnect conductor corresponds includes the actual lead pattern portion 11 located on the lowest lead film layer, the interconnect conductor will at least penetrate the actual lead pattern portion 11 to which the interconnect conductor corresponds and which is located on the lowest lead film layer. That is, the present invention uses the penetration method to actually bring the interconnect conductor into contact with the corresponding actual lead pattern portion 11 located on the lowest lead film layer, thereby realizing connection between the interconnect conductor and the corresponding actual lead pattern portion 11 located on the lowest lead film layer. This reduces the difficulty of connecting the interconnect conductor and the actual lead pattern portion 11 and increases the contact area between the interconnect conductor and the actual lead pattern portion 11, thereby ensuring connection reliability between the interconnect conductor and the actual lead pattern portion 11.

[0048] 3, the first interconnection conductor HL1 penetrates the actual lead pattern portion 11 of the fourth lead film layer 1d and the second lead film layer 1b correspondingly, thereby realizing a connection between the actual lead pattern portion 11 of the fourth lead film layer 1d and the actual lead pattern portion 11 of the second lead film layer 1b. The second interconnection conductor HL2 penetrates the actual lead pattern portion 11 of the third lead film layer 1c correspondingly and extends to the actual lead pattern portion 11 of the first lead film layer 1a, thereby realizing a connection between the actual lead pattern portion 11 of the third lead film layer 1c and the actual lead pattern portion 11 of the first lead film layer 1a. The third interconnection conductor HL3 penetrates the actual lead pattern portion 11 of the fourth lead film layer 1d, and the top surface of the third interconnection conductor HL3 can be connected to other external operating circuits, thereby realizing the connection between the actual lead pattern portion 11 of the fourth lead film layer 1d and other external operating circuits. The fourth interconnection conductor HL4 penetrates the actual lead pattern portions 11 of the fifth lead film layer 1e, the third lead film layer 1c, and the second lead film layer 1b, and extends to the actual lead pattern portion 11 of the first lead film layer 1a, thereby realizing the connection between the fifth lead film layer 1e, the third lead film layer 1c, the second lead film layer 1b, and the actual lead pattern portion 11 of the first lead film layer 1a.

[0049] When the actual lead pattern portion to which the interconnection conductor is connected includes an actual lead pattern portion 11 located in the lowest lead film layer, the interconnection conductor may penetrate the actual lead pattern portion 11 of the lowest lead film layer as shown in Fig. 4, or may not completely penetrate the actual lead pattern portion 11 of the lowest lead film layer but may only extend into the actual lead pattern portion 11 of the lowest lead film layer as shown in Figs. 2 and 3. Either connection method can increase the contact area between the interconnection conductor and the actual lead pattern portion 11 of the lowest lead film layer and ensure stable contact between them, but is not limited thereto. As shown in Fig. 5, the interconnection conductor may extend only to the upper surface of the actual lead pattern portion 11 of the lowest lead film layer, i.e., it just comes into contact with the upper surface of the actual lead pattern portion 11 of the lowest lead film layer to realize connection between the interconnection conductor and the actual lead pattern portion 11 of the lowest lead film layer.

[0050] In the present invention, the interconnect conductors are formed as follows: First, interconnect through holes are formed in corresponding regions of the laminated structure. For example, as shown in FIG. 6, a first interconnect through hole ZJ1, a second interconnect through hole ZJ2, a third interconnect through hole ZJ3, and a fourth interconnect through hole ZJ4 can be formed in corresponding regions of the laminated structure. Next, a conductive material is filled into the interconnect through holes to form interconnect conductors in each interconnect through hole. For example, as shown in FIG. 2, a first interconnect conductor HL1 can be formed in the first interconnect through hole ZJ1, a second interconnect conductor HL2 can be formed in the second interconnect through hole ZJ2, a third interconnect conductor HL3 can be formed in the third interconnect through hole ZJ3, and a fourth interconnect conductor HL4 can be formed in the fourth interconnect through hole ZJ4.

[0051] Since the interconnection conductor of the present invention needs to penetrate at least all film layers above the bottom lead film layer of the laminated structure, when designing the interconnection through holes of the multi-layer connection structure, the present invention requires providing multiple interconnection through holes spaced apart horizontally, with each interconnection through hole penetrating at least all film layers above the bottom lead film layer of the laminated structure and exposing the actual lead pattern portion 11 of at least one lead film layer.

[0052] Specifically, as shown in Figure 6, the first interconnection through hole ZJ1 exposes the actual lead pattern portions 11 of the first lead film layer 1a and the second lead film layer 1b, the second interconnection through hole ZJ2 exposes the actual lead pattern portions 11 of the first lead film layer 1a and the third lead film layer 1c, the third interconnection through hole ZJ3 exposes the actual lead pattern portions 11 of the first lead film layer 1a and the fourth lead film layer 1d, and the fourth interconnection through hole ZJ4 exposes the actual lead pattern portions 11 of the first lead film layer 1a and the fifth lead film layer 1e.Therefore, when a conductive material is filled into the interconnection through holes in a subsequent process to form an interconnection conductor, the conductive material formed in the interconnection through hole can come into contact with the corresponding exposed actual lead pattern portions 11. That is, for example, as shown in Figures 2 and 6, a connection between the interconnection conductor and the corresponding actual lead pattern portion 11 is realized.

[0053] Since the interconnect conductor is formed by filling the interconnect through-hole with a conductive material, the design of the interconnect conductor, such as its extension length, shape, and area, is all related to the design of the interconnect through-hole. That is, the design of the interconnect through-hole is consistent with the design of the interconnect conductor. For example, if it is desired that the interconnect conductor not only penetrate all the film layers above the lowest lead film layer in the laminate structure but also penetrate the lowest lead film layer, the interconnect through-hole must be designed to penetrate not only all the film layers above the lowest lead film layer in the laminate structure but also the lowest lead film layer. If it is desired that the interconnect conductor not only penetrate all the film layers above the lowest lead film layer in the laminate structure but also extend into the lowest lead film layer, the interconnect through-hole must be designed to penetrate not only all the film layers above the lowest lead film layer in the laminate structure but also extend into the lowest lead film layer, but examples will not be given here.

[0054] In some embodiments, interconnect through-holes corresponding to different types of interconnect conductors can be simultaneously formed using a one-time molding process. For example, after forming the topmost film layer of a laminated structure, a single etching process can be used to pattern the laminated structure to form multiple horizontally spaced interconnect through-holes required for the laminated structure. Because the interconnect conductors are of different types, the interconnect through-holes corresponding to the different types of interconnect conductors are also different. Specifically, the positions on the lead film layer at which the actual lead pattern portions 11 corresponding to the interconnect through-holes of the different types of interconnect conductors are located along the vertical direction Z are not exactly the same. For example, the positions on the lead film layer at which the actual lead pattern portions 11 corresponding to the first interconnect through-hole ZJ1, the second interconnect through-hole ZJ2, the third interconnect through-hole ZJ3, and the fourth interconnect through-hole ZJ4 shown in FIG. 6 are located are partially different. As a result, the number of processes can be reduced, thereby lowering manufacturing costs.

[0055] The one-time molding process refers to a process technology that can complete the entire molding process in one operation during the manufacturing of interconnect through holes. The one-time molding process of the present invention can not only manufacture interconnect through holes corresponding to the same type of interconnect conductor at one time, but also manufacture interconnect through holes corresponding to different types of interconnect conductor at one time, thereby reducing processing time and costs, improving production efficiency, and ensuring processing precision and quality.

[0056] When multiple interconnect through-holes required for a multi-layer connection structure are simultaneously fabricated in a single etching process, the etching process conditions (including the gases used in etching, process parameters, etc.) can be adaptively adjusted according to the etching depth and the material of the etched film layer, but the etching process is still performed continuously or quasi-continuously, so even if the etching process conditions are adaptively adjusted at various stages of the etching process, it is still within the scope of a single etching process.

[0057] For example, in the embodiments of the present disclosure, the interconnect through-holes described in the embodiments of the present disclosure can be formed by performing a hole-opening process on the stacked structure using an etching process, where the etching process can be anisotropic etching or even dry etching, but is not limited thereto. As long as the pattern density is the same, other etching manufacturing methods can be used while ensuring the etching accuracy of the interconnect through-holes.

[0058] Here, since the positions of the lead film layers where the actual lead pattern portions 11 to which different types of interconnect conductors are connected are located are not exactly the same, when interconnect through holes for different types of interconnect conductors are manufactured by a one-time molding process, the laminated film layers through which the interconnect through holes corresponding to the different types of interconnect conductors penetrate along the vertical direction Z are different.

[0059] For example, in some embodiments, the number of pattern portions in stacked film layers through which interconnect through holes corresponding to different types of interconnect conductors penetrate along the vertical direction Z are not exactly the same. As shown in Figure 3, the pattern portions through which the first interconnect through hole ZJ1 and the second interconnect through hole ZJ2 penetrate are two actual lead pattern portions 11, the pattern portion through which the third interconnect through hole ZJ3 penetrates is one actual lead pattern portion 11, and the pattern portion through which the fourth interconnect through hole ZJ4 penetrates is four actual lead pattern portions 11. Because the total number of film layers through which each interconnect through hole penetrates along the vertical direction Z is the same, if the numbers of pattern portions through which each interconnect through hole penetrates along the vertical direction Z are not exactly the same, the numbers of insulating isolation portions 12 through which each penetrates will also not be exactly the same.

[0060] In another embodiment, the number of pattern portions in the stacked film layers through which interconnection through holes corresponding to different types of interconnection conductors penetrate along the vertical direction Z is the same, but the positions of the lead film layers are not exactly the same. For example, as shown in Figure 6, the number of insulating isolation portions 12 and actual lead pattern portions 11 through which the first interconnection through hole ZJ1, the second interconnection through hole ZJ2, the third interconnection through hole ZJ3, and the fourth interconnection through hole ZJ4 penetrate along the vertical direction Z is the same, but the positions of the lead film layers where the actual lead pattern portions 11 are located are different. That is, the stacked film layers through which the first interconnection through hole ZJ1 passes include, arranged from top to bottom, the sixth insulating film layer 2f, the insulating isolation portion 12 of the fifth lead film layer 1e, the fifth insulating film layer 2e, the insulating isolation portion 12 of the fourth lead film layer 1d, the fourth insulating film layer 2d, the insulating isolation portion 12 of the third lead film layer 1c, the third insulating film layer 2c, the actual lead pattern portion 11 of the second lead film layer 1b, and the second insulating film layer 2b. The stacked film layers through which the second interconnection through hole ZJ2 penetrates include, arranged from top to bottom, the sixth insulating film layer 2f, the insulating isolation portion 12 of the fifth lead film layer 1e, the fifth insulating film layer 2e, the insulating isolation portion 12 of the fourth lead film layer 1d, the fourth insulating film layer 2d, the actual lead pattern portion 11 of the third lead film layer 1c, the third insulating film layer 2c, the insulating isolation portion 12 of the second lead film layer 1b, and the second insulating film layer 2b. The stacked film layers through which the third interconnection through hole ZJ3 penetrates include, arranged from top to bottom, the sixth insulating film layer 2f, the insulating isolation portion 12 of the fifth lead film layer 1e, the fifth insulating film layer 2e, the actual lead pattern portion 11 of the fourth lead film layer 1d, the fourth insulating film layer 2d, the insulating isolation portion 12 of the third lead film layer 1c, the third insulating film layer 2c, the insulating isolation portion 12 of the second lead film layer 1b, and the second insulating film layer 2b. The stacked film layers through which the fourth interconnection through hole ZJ4 passes include, arranged from top to bottom, the sixth insulating film layer 2f, the actual lead pattern portion 11 of the fifth lead film layer 1e, the fifth insulating film layer 2e, the insulating isolation portion 12 of the fourth lead film layer 1d, the fourth insulating film layer 2d, the insulating isolation portion 12 of the third lead film layer 1c, the third insulating film layer 2c, the insulating isolation portion 12 of the second lead film layer 1b, and the second insulating film layer 2b.

[0061] Here, it can be understood that the etching rate is not constant with respect to the etching depth of the hole, and that the deeper the hole, the slower the etching rate under the same process conditions. Furthermore, interconnection through-holes corresponding to different types of interconnect conductors penetrate through different stacked film layers along the vertical direction Z. That is, the number and / or positions of the patterned portions are not identical, and the materials of the patterned portions and the insulating isolation portions 12 are different. Therefore, when interconnection through-holes for different types of interconnect conductors are manufactured by an etching process, the film layers through which the interconnection through-holes corresponding to different types of interconnect conductors penetrate are not completely identical, and therefore some of the manufactured interconnection through-holes are likely to have different etching depths at the same time. As a result, the interconnection through-holes corresponding to different types of interconnect conductors are likely to ultimately cause under-etching or over-etching problems, which are likely to cause serious etching load effects, making etching control difficult and affecting yield.

[0062] In some embodiments, when different types of interconnect through holes required for a multilayer connection structure are simultaneously fabricated in a single etching process, the etching process conditions (including the gases used for etching, process parameters, etc.) can be adaptively adjusted according to the etching depth and the material of the etched film layer. However, since the etching process is still performed continuously or quasi-continuously, adaptive adjustments of the etching process conditions at various stages of the etching process are within the scope of a single etching process. In this etching process, when etching the same lead film layer, if two interconnect through holes penetrate different materials of the film layers—for example, if one of the two interconnect through holes penetrates a pattern portion and the other of the two interconnect through holes penetrates an insulating isolation portion 12—the different materials of the pattern portion and the insulating isolation portion 12 result in different etching rates for the pattern portion and the insulating isolation portion 12. As a result, when one interconnect through hole in this lead film layer is completely etched, the other interconnect through hole will have an over-etching or under-etching defect. This defect accumulates as the number of film layers in the stacked structure increases and the etching depth of the interconnect through holes increases, affecting yield.

[0063] To solve the above problem, embodiments of the present invention utilize dummy pattern portions 13 when manufacturing a multilayer interconnect structure including different types of interconnect conductors, ensuring that the stacked film layers through which interconnect through holes corresponding to each interconnect conductor penetrate along the vertical direction Z are identical. That is, because the number and arrangement of pattern portions within the stacked film layers are identical, uniformity of each interconnect through hole during the etching process is ensured. That is, the problem of under-etching or over-etching of some interconnect through holes is alleviated, the etching load effect is improved, the difficulty of etching control is reduced, and the processing yield is improved.

[0064] Specifically, the pattern portion of at least one lead film layer located above the lowest lead film layer in the laminated structure may include a dummy pattern portion 13 in addition to the actual lead pattern portion 11. The dummy pattern portion 13 is exposed to at least one interconnection through-hole in the vertical direction Z so that the dummy pattern portion 13 is connected to the interconnection conductor in at least one interconnection through-hole in the vertical direction Z. In other words, the interconnection conductor can be connected to the dummy pattern portion 13 by passing through the dummy pattern portion 13 located above the lowest lead film layer. Note that the dummy pattern portion 13 in this embodiment refers to a pattern portion that is not related to the circuit function of the multilayer interconnection structure, and its main role in the design of the entire multilayer interconnection structure is to ensure the uniformity and consistency of etching of each interconnection through-hole.

[0065] Here, in order to avoid problems of leakage and short circuit, the dummy pattern portion 13 needs to be separated from the actual lead pattern portion 11 located on the same lead film layer. Specifically, the dummy pattern portion 13 and the actual lead pattern portion 11 can be separated by an insulating separation portion 12 so that the dummy pattern portion 13 and the actual lead pattern portion 11 are insulated from each other.

[0066] In some embodiments, as shown in FIG. 14, the first interconnection conductor HL1 and the second interconnection conductor HL2 are connected via the actual lead pattern portion 11 of the first lead film layer 1a, and the actual lead pattern portion 11 of the second lead film layer 1b connected to the first interconnection conductor HL1 is disconnected from the dummy pattern portion 13 of the second lead film layer 1b connected to the second interconnection conductor HL2, but this is not limited thereto, and the first interconnection conductor HL1 and the second interconnection conductor HL2 may be connected via the actual lead pattern portion 11 of the first lead film layer 1a. When the dummy pattern portion 13 of the second lead film layer 1b connected to the second interconnecting conductor HL2 is connected to another dummy pattern portion 13 via the first interconnecting conductor HL1, the actual lead pattern portion 11 of the second lead film layer 1b connected to the first interconnecting conductor HL1 can be connected to the dummy pattern portion 13 of the second lead film layer 1b connected to the second interconnecting conductor HL2, thereby forming the dummy pattern portion 13 of the second lead film layer 1b connected to the second interconnecting conductor HL2 as an actual pattern portion. By designing the actual pattern portion in this manner, the effect of reducing impedance due to parallel connection can be obtained, and at the same time, it is not necessary to cut the dummy pattern portion 13 of the second lead film layer 1b connected to the second interconnecting conductor HL2 and the actual lead pattern portion 11 of the second lead film layer 1b connected to the first interconnecting conductor HL1 through a patterning process, thereby reducing the difficulty and cost of the process.

[0067] In an embodiment of the present invention, the dummy pattern portion 13 and the actual lead pattern portion 11 of the lead film layer where it is located can be manufactured simultaneously. For example, after forming a conductive material film that uniformly covers the entire surface, the dummy pattern portion 13 and the actual lead pattern portion 11 can be formed simultaneously by patterning the conductive material film. This not only makes the dummy pattern portion 13 and the actual lead pattern portion 11 made of the same material, but also makes the film thickness of the dummy pattern portion 13 the same as that of the actual lead pattern portion 11. Specifically, in this embodiment, in the same lead film layer, the bottom end surface of the dummy pattern portion 13 can be made flush with the bottom end surface of the actual lead pattern portion 11, and the top end surface of the dummy pattern portion 13 (the end surface farthest from the substrate required in the manufacturing process) can be made flush with the top end surface of the actual lead pattern portion 11, thereby ensuring the flatness of the entire lead film layer and the flatness of film layers formed thereafter.

[0068] In this embodiment, each interconnection through hole penetrates the pattern portion of each lead film layer above the lowest lead film layer along the vertical direction Z, and the pattern portion through which the interconnection through hole penetrates along the vertical direction actually includes a lead pattern portion 11 and / or a dummy pattern portion 13, so that each interconnection conductor penetrates the pattern portion of each lead film layer above the lowest lead film layer along the vertical direction Z, and the pattern portion through which the interconnection conductor penetrates along the vertical direction Z actually includes a lead pattern portion 11 and / or a dummy pattern portion 13.

[0069] For example, first, a laminated structure is designed according to the actual situation, and the design of the lead film layers in the laminated structure can be referred to in Figure 7. The first lead film layer 1a has actual lead pattern portions 11 in the first area A1, the second area A2, the third area A3, and the fourth area A4, respectively; the second lead film layer 1b has actual lead pattern portions 11 in the first area A1, and dummy pattern portions 13 in the second area A2, the third area A3, and the fourth area A4, respectively; the third lead film layer 1c has actual lead pattern portions 11 in the second area A2, and dummy pattern portions 13 in the first area A1, the third area A3, and the fourth area A4, respectively. A dummy pattern portion 13 is provided in each of the first region A1, the second region A2, and the fourth region A4; the fourth lead film layer 1d has an actual lead pattern portion 11 provided in the third region A3, and has dummy pattern portions 13 provided in each of the first region A1, the second region A2, and the fourth region A4; the fifth lead film layer 1e has an actual lead pattern portion 11 provided in the fourth region A4, and has dummy pattern portions 13 provided in each of the first region A1, the second region A2, and the third region A3.

[0070] After forming a laminated structure as shown in Figure 7, a hole-opening process can be performed on the laminated structure shown in Figure 7 to form a first interconnection through hole ZJ1 located in the first region A1, a second interconnection through hole ZJ2 located in the second region A2, a third interconnection through hole ZJ3 located in the third region A3, and a fourth interconnection through hole ZJ4 located in the fourth region A4. Referring to Figure 8, the first interconnection through hole ZJ1, the second interconnection through hole ZJ2, the third interconnection through hole ZJ3, and the fourth interconnection through hole ZJ4 can penetrate the pattern portions of each lead film layer above the lowest lead film layer along the vertical direction Z. That is, the first interconnection through hole ZJ1, the second interconnection through hole ZJ2, the third interconnection through hole ZJ3, and the fourth interconnection through hole ZJ4 sequentially penetrate the pattern portions of the fifth lead film layer 1e, the fourth lead film layer 1d, the third lead film layer 1c, and the second lead film layer 1b along the vertical direction Z, and the pattern portions through which the first interconnection through hole ZJ1, the second interconnection through hole ZJ2, the third interconnection through hole ZJ3, and the fourth interconnection through hole ZJ4 penetrate along the vertical direction Z include an actual lead pattern portion 11 and a dummy pattern portion 13.

[0071] Furthermore, the pattern portions through which the first interconnect through hole ZJ1, the second interconnect through hole ZJ2, the third interconnect through hole ZJ3, and the fourth interconnect through hole ZJ4 penetrate along the vertical direction Z are not limited to including the actual lead pattern portion 11 and the dummy pattern portion 13 as described above, but may include only the actual lead pattern portion 11 or only the dummy pattern portion 13, and the specific design can be made based on the actual situation, as long as it is ensured that the placement positions of the pattern portions in the laminated film layer through which each interconnect through hole penetrates along the vertical direction Z are exactly the same.

[0072] After manufacturing the first interconnect through hole ZJ1, the second interconnect through hole ZJ2, the third interconnect through hole ZJ3, and the fourth interconnect through hole ZJ4 as shown in Figure 8, the first interconnect through hole ZJ1, the second interconnect through hole ZJ2, the third interconnect through hole ZJ3, and the fourth interconnect through hole ZJ4 are filled with a conductive material to form the first interconnect conductor HL1, the second interconnect conductor HL2, the third interconnect conductor HL3, and the fourth interconnect conductor HL4, respectively, as shown in Figure 9, and the first interconnect conductor HL1, the second interconnect conductor HL2, the third interconnect conductor HL3, and the fourth interconnect conductor HL4 penetrate the pattern portions of the fifth lead film layer 1e, the fourth lead film layer 1d, the third lead film layer 1c, and the second lead film layer 1b along the vertical direction Z. Preferably, the first interconnect through hole ZJ1, the second interconnect through hole ZJ2, the third interconnect through hole ZJ3, and the fourth interconnect through hole ZJ4 are completely filled with conductive material, thereby reducing the interconnect impedance and improving the interconnect reliability.

[0073] In an embodiment of the present invention, all of the interconnection through-holes in the multilayer connection structure penetrate all of the film layers above the bottom lead film layer in the stacked structure. That is, all of the interconnection through-holes in the multilayer connection structure of the present invention are formed after the top film layer of the stacked structure is manufactured. This design facilitates simultaneous manufacturing of different types of interconnection conductors in the multilayer connection structure. Compared with a structural solution that requires individual manufacturing of different types of interconnection conductors, the design solution for the multilayer connection structure of the present invention can reduce the number of processes and masks, thereby reducing the manufacturing cost of the multilayer connection structure and reducing waste of production capacity.

[0074] Since all of the interconnect through holes are formed after the topmost film layer of the laminated structure is manufactured, it can be seen that in this embodiment, the top surfaces of all of the interconnect through holes are flush with each other. As shown in Figure 8, the top surfaces of the first interconnect through hole ZJ1, the second interconnect through hole ZJ2, the third interconnect through hole ZJ3, and the fourth interconnect through hole ZJ4 are flush with each other.

[0075] In addition, in the embodiment of the present invention, the design of the dummy pattern portion 13 allows the stacked film layers through which each interconnection through-hole penetrates along the vertical direction Z to be completely identical, thereby ensuring that the stop positions of each interconnection through-hole are the same. For example, as shown in FIG. 8, the stop positions of each interconnection through-hole are located in the pattern portion of the first lead film layer 1a, thereby mitigating the problem of under-etching or over-etching of some interconnection through-holes and ensuring that the stop positions of each interconnection conductor are the same. For example, as shown in FIG. 9, the stop positions of each interconnection conductor are located in the pattern portion of the first lead film layer 1a, thereby further ensuring contact between the interconnection conductor and the corresponding actual lead pattern portion 11.

[0076] In some embodiments, each interconnection through-hole is not limited to penetrating the pattern portion of each lead film layer above the lowest lead film layer along the vertical direction Z, but may also penetrate the pattern portion of the lowest lead film layer. In this way, if the pattern portion of the lowest lead film layer through which the interconnection conductor penetrates is the actual lead pattern portion 11, the contact area between the interconnection conductor and the actual lead pattern portion 11 in the lowest lead film layer can be increased, thereby ensuring contact stability and conductivity between the interconnection conductor and the actual lead pattern portion 11 in the lowest lead film layer. That is, the interconnection conductor of the present invention is not limited to penetrating the pattern portion of each lead film layer above the lowest lead film layer along the vertical direction Z, but may also penetrate the pattern portion of the lowest lead film layer. It should be noted that the pattern portion of the lowest lead film layer through which the interconnection conductor penetrates may be, but is not limited to, the actual lead pattern portion 11, and may also be a dummy pattern portion, and may be determined according to actual design requirements. When the etching rate of the pattern portion is slower than the etching rate of the insulating film layer 2 and the insulating isolation portion 12, it is possible to avoid excessive etching depth of the interconnection through hole corresponding to the interconnection conductor damaging the film layer below the laminated structure, compared to providing the pattern portion of the lowest lead film layer through which the interconnection conductor penetrates as a dummy pattern portion and providing the pattern portion of the lowest lead film layer through which the interconnection conductor penetrates as the insulating isolation portion 12.

[0077] In some other embodiments, the stop position of each interconnection through-hole may be located within the pattern portion of the lowest lead film layer. That is, the bottom end of each interconnection conductor (the end closest to the substrate required in the manufacturing process) may be embedded within the pattern portion of the lowest lead film layer. This increases the contact area between the interconnection conductor and the actual lead pattern portion 11 of the lowest lead film layer, ensuring contact stability and conductivity between the interconnection conductor and the actual lead pattern portion 11 of the lowest lead film layer.

[0078] In other embodiments, each interconnect through hole may stop on the top surface of the pattern portion of the lowest lead film layer so that the bottom end surface of each interconnect conductor (the end surface closest to the substrate required in the manufacturing process) is just in contact with the top surface of the pattern portion of the lowest lead film layer.

[0079] Here, the multilayer connection structure in which the dummy pattern portion 13 is designed in the present invention is not limited to the embodiments shown in Figures 7 to 9, and the number of lead film layers, the connection relationship of the actual lead pattern portion 11 between each lead film layer, the layout design of the pattern portion in each lead film layer, etc. can also be changed according to actual needs.

[0080] In other embodiments of the present invention, multiple stacked structures may be provided, and multiple stacked structures may be prepared sequentially and stacked along the vertical direction Z, in which at least some of the interconnect through holes / pattern portions are connected to form a larger interconnected structure.

[0081] In some embodiments, as shown in Figures 2-5 and 9, the lower end surfaces of any interconnect through holes can be flush with one another, and the upper end surfaces of any interconnect through holes can be flush with one another. As a result, the lower end surfaces of each interconnect conductor can be flush with one another, and the upper end surfaces of any interconnect conductors can be flush with one another. In other words, the extension length, extension start position, and extension stop position of each interconnect conductor are all the same, so that each interconnect conductor can be reliably connected to the corresponding actual lead pattern portion.

[0082] In some embodiments, as shown in Figures 2-5 and 9, the top surface of the interconnect conductor can be flush with the top surface of the laminated structure, ensuring flatness of the entire multilayer connection structure and facilitating designs such as lamination with other film layer structures.

[0083] In some embodiments, the orthogonal projection of at least one interconnect through hole in the vertical direction Z is positioned completely within one pattern portion of each lead film layer, and if design requirements are met, the outer diameter of the interconnect conductor (i.e., the diameter of the interconnect through hole corresponding to the interconnect conductor) may be equal to the width of the corresponding pattern portion, or, for example, the outer diameter of the interconnect conductor HL shown in FIG. 10 is the same as the width of the corresponding actual lead pattern portion 11, but is not limited thereto, and may be smaller than the width of the corresponding actual lead pattern, or, for example, the outer diameter of the interconnect conductor HL shown in FIG. 11 is smaller than the width of the corresponding actual lead pattern. This ensures that the material etched when each portion of the interconnect through hole located on the same horizontal plane passes through the lead film layer is the same, i.e., the material of the pattern portion, thereby ensuring uniformity in the opening of the interconnect through hole. Furthermore, this design also prevents the interconnect conductor from coming into contact with the actual lead pattern portion 11 that does not need to be connected, which could result in a short circuit or leakage.

[0084] In this embodiment, the horizontal plane refers to a plane perpendicular to the vertical direction Z.

[0085] In another embodiment, if design requirements are met, the diameter of the interconnect through-hole corresponding to the interconnect conductor may be larger than the width of the corresponding pattern portion. For example, the outer diameter of the interconnect conductor HL shown in FIG. 12 is larger than the width of the corresponding actual lead pattern portion 11. As a result, the diameter of the interconnect through-hole can be enlarged, thereby reducing the difficulty in pattern alignment and etching process control.

[0086] In some embodiments, the vertical projection of at least one interconnect conductor overlaps with multiple pattern portions located on the same lead film layer, and such a design can reduce the difficulty of processing interconnect through holes corresponding to the interconnect conductor. For example, if multiple pattern portions located on the same lead film layer include multiple actual lead pattern portions 11 that need to be bridged, as shown in Figure 13, the actual lead pattern portion 11 on the left needs to cross the central dummy pattern portion 13 to connect with the actual lead pattern portion 11 on the right, and an interconnect conductor HL is used to bridge them.

[0087] In some embodiments, at least one pattern portion may be connected to multiple interconnect conductors, and this pattern portion may be an actual lead pattern portion 11 or a dummy pattern portion 13. For example, as shown in Fig. 14, the first lead film layer 1a may include an actual lead pattern portion 11, which spans the first area A1 and the second area A2 and is simultaneously connected to the first interconnect conductor HL1 and the second interconnect conductor HL2. The third lead film layer 1c may include an actual lead pattern portion 11, which spans the second area A2 and the third area A3 and is simultaneously connected to the second interconnect conductor HL2 and the third interconnect conductor HL3. The fourth lead film layer 1d may include a dummy pattern portion 13, which spans the first area A1 and the second area A2 and is simultaneously connected to the first interconnection conductor HL1 and the second interconnection conductor HL2. Therefore, if design requirements are met, the number of pattern portions in each lead film layer can be reduced, and the requirements for patterning accuracy in the patterning process of the lead film layer can be relaxed, thereby reducing the cost of the patterning process.

[0088] In addition, in the multilayer connection structure of the present invention, the pattern portions connected to the multiple interconnection conductors are not limited to the positions shown in Figure 14, and the number connected to the interconnection conductors is not limited to two but may be three, four, etc., and may vary depending on specific design conditions.

[0089] In another embodiment, the multilayer connection structure of the present invention may include, in addition to the above-mentioned interconnect conductors having actual functions in the circuit, dummy conductors XN spaced apart from the interconnect conductors, as shown in FIG. 15. Here, the dummy conductors XN are molded together with the first interconnect conductor HL1, the second interconnect conductor HL2, and the third interconnect conductor HL3 shown in FIG. 15, and the upper and lower ends of the dummy conductors XN are flush with the upper and lower ends of the first interconnect conductor HL1, the second interconnect conductor HL2, and the third interconnect conductor HL3, respectively. The number and arrangement order of pattern portions in the stacked film layer through which the dummy conductors XN pass are exactly the same as those of the interconnect conductors. In summary, the main difference between the dummy conductors XN and the interconnect conductors is that at least one of the pattern portions connected by the interconnect conductors is an actual lead pattern portion 11, while all of the pattern portions connected by the dummy conductors XN are dummy pattern portions 13. The dummy conductors XN do not have an actual conductive function in the entire multilayer connection structure. The use of interconnect through holes corresponding to the dummy conductors XN can make the density of interconnect through holes in each region uniform, thereby avoiding defects in the etching shape caused by changes in etching density when etching the interconnect through holes. After filling to form the dummy conductors XN, the stability of the structure can be improved. The arrangement of the dummy conductors XN and the patterns of the pattern parts connected to them can achieve other non-conductive functions, such as shielding crosstalk between interconnected devices, but this is not particularly limited in the present invention.

[0090] An embodiment of the present invention further provides a manufacturing method for manufacturing the multi-layer connection structure described in any of the previous embodiments. The manufacturing method of this embodiment may include the following steps:

[0091] In step S100, lead film layers 1 and insulating film layers 2 are alternately arranged on a substrate 3 along the vertical direction Z to form a laminated structure, where, for example, as shown in FIG. 16, multiple lead film layers 1 are provided, and at least one insulating film layer 2 is provided, and each lead film layer 1 includes at least an actual lead pattern portion 11; however, it should be understood that the laminated structure of this embodiment is not limited to FIG. 16 and can be appropriately adjusted according to actual design requirements.

[0092] In step S200, after forming the topmost film layer of the laminated structure, a plurality of interconnection conductors HL are formed, as in the multilayer connection structure shown in Fig. 17, and the interconnection conductors HL penetrate all film layers above at least the bottommost lead film layer 1 of the laminated structure and connect with the actual lead pattern portion 11 of at least one lead film layer 1, and the number and / or positions of the lead film layers 1 where the actual lead pattern portions 11 to be connected correspondingly for at least two interconnection conductors HL are located are not all the same. It should be understood that the multilayer connection structure of this embodiment is not limited to that shown in Fig. 17 and can be appropriately adjusted according to actual design requirements.

[0093] In some embodiments, in step S200, forming a plurality of interconnect conductors HL may specifically include the following steps.

[0094] In step S201, an etching process is used to pattern the laminated structure to form a plurality of spaced-apart interconnection through-holes ZJ, such as the intermediate structure for opening interconnection through-holes in the laminated structure shown in Fig. 18, where the interconnection through-holes ZJ penetrate at least all film layers above the bottommost lead film layer 1 in the laminated structure and expose the actual lead pattern portion 11 of at least one lead film layer 1, and the positions of the lead film layer 1 where the actual lead pattern portions 11 exposed by at least two interconnection through-holes ZJ are located are not exactly the same. It should be understood that the intermediate structure of this embodiment is not limited to that shown in Fig. 18 and can be adjusted according to actual design requirements.

[0095] In step S202, a conductive material is filled into each of the interconnection through holes ZJ to form interconnection conductors HL in each of the interconnection through holes ZJ. A specific structure can be seen in FIG.

[0096] For example, in step S202, a conductive material film DT may be formed first, which includes a conductive material filled in each interconnect through-hole ZJ and also includes a conductive material covering the top surface of the laminate structure, as shown in Fig. 19. Then, as shown in Fig. 17, the conductive material on the top surface of the laminate structure is removed to form a plurality of interconnect conductors HL arranged at intervals, but is not limited thereto, and the conductive material on the top surface of the laminate structure does not need to be completely removed, and a portion may be retained to allow bridging of the plurality of interconnect conductors.

[0097] In some embodiments, in order to ensure the uniformity of the interconnection through holes, a dummy pattern portion 13 separated from the actual lead pattern portion 11 can be designed in at least one lead film layer 1, as shown in FIG. 16, and as shown in FIG. 18, the interconnection through hole ZJ penetrates the pattern portion of each lead film layer 1 above the bottom lead film layer 1 along the vertical direction Z, and the pattern portion through which the interconnection through hole ZJ penetrates along the vertical direction Z includes the actual lead pattern portion 11 and / or the dummy pattern portion 13.

[0098] In one embodiment, the steps of forming the lead film layer 1 including the actual lead pattern portion 11 and the dummy pattern portion 13 include the following steps.

[0099] In step S1001, a conductive film is formed on a substrate 3.

[0100] In step S1002, the conductive film is subjected to a patterning process, thereby forming the actual lead pattern portion 11 and the dummy pattern portion 13 at the same time.

[0101] In another embodiment, the step of forming the lead film layer 1 including the actual lead pattern portion 11 and the dummy pattern portion 13 includes the following steps.

[0102] In step S1003, a conductive film is formed on the substrate 3.

[0103] In step S1004, a patterning process is performed on the conductive film using a single patterning process to simultaneously form a portion of the actual lead pattern portion 11 and at least one intermediate pattern portion, and the intermediate pattern portion and the actual lead pattern portion 11 are separated from each other.

[0104] In step S1005, a patterning process is performed on the intermediate pattern portion using one patterning process, thereby forming another portion of the actual lead pattern portion 11 and the dummy pattern portion 13 at the same time.

[0105] An embodiment of the present invention also provides a semiconductor device, which may be, but is not limited to, a DRAM (Dynamic Random Access Memory), and may be other types of structures, such as a FEOL (Front End Of Line) semiconductor structure or a BEOL (Back End Of Line) semiconductor structure, examples of which are not provided herein.

[0106] 17, the semiconductor device may include a substrate 3 and at least one multi-layer connection structure, and the multi-layer connection structure may be formed on the substrate 3. The design scheme of this multi-layer connection structure may refer to the content described in any of the previous embodiments and will not be repeated here. In some embodiments, the semiconductor substrate may include a substrate 3 and multiple multi-layer connection structures, and the multiple multi-layer connection structures may be horizontally distributed on the substrate 3, or multiple multi-layer connection structures may be vertically stacked and formed on the substrate 3, depending on design requirements.

[0107] The vertical direction Z may be perpendicular or nearly perpendicular to the substrate 3 in order to reduce the difficulty in manufacturing the multi-layer connection structure.

[0108] In some embodiments, the substrate 3 may be a semiconductor substrate, but is not limited thereto and may be other types of substrate 3, which can be determined according to the specific circumstances.

[0109] In addition, the orthogonal projection of the multilayer connection structure onto the substrate 3 in this embodiment can completely cover the substrate 3, but is not limited to this, and can also be orthogonal projection onto a localized area of ​​the substrate 3, depending on the design requirements.

[0110] Additionally, terms such as "first," "second," "third," and "fourth" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or quantity of the indicated technical features. Thus, a feature qualified by "first," "second," "third," or "fourth" may explicitly or implicitly include one or more of that feature. In the description of this application, "plurality" means two or more unless otherwise expressly qualified.

[0111] In the description herein, the use of terms such as "some embodiments," "exemplary," and the like means that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. In the present specification, schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine different embodiments or examples and features of different embodiments or examples described herein, as long as they are not mutually inconsistent.

[0112] Although the embodiments of the present application have been shown and described above, the above embodiments are illustrative and should not be construed as limitations of the present application. Those skilled in the art can change, modify, substitute and alter the above embodiments within the scope of the present application, and therefore, it is understood that all changes or modifications made in accordance with the claims and descriptions of the present application should be included within the patent scope of the present application. [Explanation of symbols]

[0113] 1, lead film layer; 1a, first lead film layer; 1b, second lead film layer; 1c, third lead film layer; 1d, fourth lead film layer; 1e, fifth lead film layer; 10, lead; 11, actual lead pattern portion; 12, insulating isolation portion; 13, dummy pattern portion; 2, insulating film layer; 2a, first insulating film layer; 2b, second insulating film layer; 2c, third insulating film layer; 2d, fourth insulating film layer; 2e, fifth insulating film layer; 2f, sixth insulating film layer; 3, substrate; A1, first region; A2, second region; A3, third region; A4, fourth region; DT, conductor material film; HL, interconnect conductor; HL1, first interconnect conductor; HL2, second interconnect conductor; HL3, third interconnect conductor; HL4, fourth interconnect conductor; Z, vertical direction; ZJ, interconnect through hole; ZJ1, first interconnect through hole; ZJ2, second interconnect through hole; ZJ3, third interconnect through hole; ZJ4, fourth interconnect through hole.

Claims

1. a laminated structure, a plurality of interconnect through-holes spaced apart in a horizontal direction, and interconnect conductors filling the interconnect through-holes; the laminated structure includes a plurality of lead film layers and at least one insulating film layer, the lead film layers and the insulating film layers are alternately arranged along a vertical direction, and each of the lead film layers includes at least an actual lead pattern portion; The interconnection through-holes expose actual lead pattern portions of at least one of the lead film layers, and the positions of the lead film layers where the actual lead pattern portions correspondingly exposed by the at least two interconnection through-holes are located are not exactly the same, and each of the interconnection through-holes penetrates at least all film layers above the bottommost lead film layer in the laminate structure. A multilayer connection structure characterized by:

2. The top surfaces of any of the interconnection through holes are flush with one another. The multilayer connection structure according to claim 1 .

3. the top surface of the interconnect conductor is flush with the top surface of the laminate structure; and / or The insulating film layer is provided in a plurality of layers, and the uppermost layer of the laminated structure is the insulating film layer; and / or The lead film layer is provided in three or more layers.

3. The multilayer connection structure according to claim 2.

4. At least one of the lead film layers above the lowest lead film layer in the laminated structure further includes a dummy pattern portion separated from the actual lead pattern portion, and in the same lead film layer, a lower end surface of the dummy pattern portion is flush with a lower end surface of the actual lead pattern portion, and an upper end surface of the dummy pattern portion is flush with an upper end surface of the actual lead pattern portion; The dummy pattern portion overlaps at least one of the interconnection through-holes in the vertical direction and is exposed. The multilayer connection structure according to claim 1 .

5. Each of the interconnection through holes penetrates a pattern portion of each of the lead film layers above the lowermost lead film layer along a vertical direction, and the pattern portion through which the interconnection through hole penetrates along a vertical direction includes the actual lead pattern portion and / or the dummy pattern portion.

5. The multilayer connection structure according to claim 4.

6. the lower end surfaces of any of the interconnection through holes are flush with one another; The interconnection through-holes penetrate the pattern portion of the lowermost lead film layer, or The lower end of the interconnection through hole is embedded in the pattern portion of the lowermost lead film layer.

6. The multilayer connection structure according to claim 5.

7. a vertical orthogonal projection of at least one of the interconnection through-holes is located entirely within one pattern portion of each of the lead film layers; and / or a vertical orthogonal projection of at least one of the interconnection through holes overlaps with at least one pattern portion located in the lead film layer of the same layer; and / or At least one pattern portion is exposed by a plurality of the interconnection through holes.

6. The multilayer connection structure according to claim 5.

8. A semiconductor device comprising a substrate and at least one multilayer connection structure according to any one of claims 1 to 7 formed on the substrate.

9. forming a laminated structure by alternately arranging lead film layers and insulating film layers on a substrate along a vertical direction, the lead film layers being provided in a plurality of layers, the insulating film layer being provided in at least one layer, and each of the lead film layers including at least an actual lead pattern portion; forming a topmost film layer of the laminated structure, and then performing a patterning process on the laminated structure using an etching process to form a plurality of interconnection through-holes spaced apart in a horizontal direction, the interconnection through-holes penetrating at least all film layers above the bottommost lead film layer in the laminated structure and exposing actual lead pattern portions of at least one of the lead film layers, and the positions of the lead film layers where the actual lead pattern portions correspondingly exposed by at least two of the interconnection through-holes are located are not exactly the same; and filling each of the interconnect through-holes with a conductive material to form an interconnect conductor in each of the interconnect through-holes. A method for manufacturing a multilayer connection structure.

10. at least one of the lead film layers further includes a dummy pattern portion separated from the actual lead pattern portion, the interconnection through-holes pass through the pattern portions of each of the lead film layers above the bottommost lead film layer along a vertical direction, and the pattern portion through which the interconnection through-holes pass along a vertical direction includes the actual lead pattern portion and / or the dummy pattern portion; The step of forming a lead film layer including the actual lead pattern portion and the dummy pattern portion includes: forming a conductive film on the substrate; and forming the actual lead pattern portion and the dummy pattern portion simultaneously by performing a patterning process on the conductive film.

10. The method for manufacturing a multilayer connection structure according to claim 9.

11. the interconnection through-holes pass through pattern portions of the lead film layers above the bottom lead film layer along a vertical direction, and the pattern portions through which the interconnection through-holes pass along a vertical direction include the actual lead pattern portion and / or the dummy pattern portion; The step of forming a lead film layer including the actual lead pattern portion and the dummy pattern portion includes: forming a conductive film on the substrate; performing a patterning process on the conductive film using a single patterning process to simultaneously form a portion of the actual lead pattern portion and at least one intermediate pattern portion, and the intermediate pattern portion and the actual lead pattern portion are separated from each other; and performing a patterning process on the intermediate pattern portion using a single patterning process to simultaneously form another portion of the actual lead pattern portion and the dummy pattern portion.

11. The method for manufacturing a multilayer connection structure according to claim 10.

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