Semiconductor module

Abstract

To provide a semiconductor module that uses a hard resin that is compatible with high heat resistance while improving the reliability of an insulating substrate.SOLUTION: A semiconductor module 1 includes an insulating substrate 22 arranged on a base 2 via a substrate joint, a circuit wiring pattern 20 formed on the upper surface of the insulating substrate, a conductor layer formed on the lower surface of the insulating substrate 22, a semiconductor chip 23 arranged on the circuit wiring pattern 20 via a chip joint, and a sealing resin provided on the upper surface of the base 2 for sealing the insulating substrate 22 and the semiconductor chip 23, and at least one of the circuit wiring pattern 20 and the conductor layer has an uneven end face which is an end face with a shape having repeated unevenness, and the positions of the end faces are different from each other in a protruding direction of the convex parts of the uneven end face.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the structure of a semiconductor module, and more particularly to a technique that is effective when applied to an insulating substrate structure used in a semiconductor module having a power semiconductor chip such as an IGBT. [Background technology]

[0002] In recent years, there has been growing demand for semiconductor modules containing power semiconductor chips such as IGBTs (Insulated Gate Bipolar Transistors) as power control devices installed in power generation systems such as wind power generation, railways, and even electric and hybrid vehicles. As a result, the development of modular structures that achieve compact size and high power density is becoming increasingly important. On the other hand, semiconductor modules containing power semiconductor chips such as IGBTs undergo temperature changes due to heat generation from the chips depending on the operating conditions used. This temperature change generates thermal stress in the internal structure of the semiconductor module, accelerating the deterioration of each component. For this reason, a temperature cycle test is conducted as one of the reliability evaluation tests for semiconductor modules to evaluate their resistance to thermal stress caused by temperature changes. In the temperature cycle test, the temperature of the entire semiconductor module is changed to evaluate the durability against thermal stress of each component (chip, insulating substrate, solder, bonding wire, sealing resin, etc.) with different linear expansion coefficients, as well as the reliability of the joints between components.

[0003] Furthermore, as background art in this technical field, there are technologies such as those disclosed in Patent Documents 1 and 2. Figure 1 and the abstract of Patent Document 1 state that "deterioration in quality can be suppressed along with the occurrence of thermal stress. In a side cross-sectional view of the semiconductor device 10, the position of the first end face 15a1 of the conductive pattern 15a is located between the position of the outermost end 16a1 of the dimple 16a and the position of the innermost end 16b2 of the dimple 16b. Therefore, even if thermal stress occurs in the ceramic circuit board 13 in response to a temperature change in the semiconductor device 10, the multiple dimples 16a, 16b mitigate deformation of the ceramic circuit board 13 due to the temperature change. Therefore, cracking of the ceramic circuit board 13 and peeling of the metal plate 16 and the conductive pattern 15a can be prevented."

[0004] The abstract of Patent Document 2 states that the problem is "to provide a semiconductor module with improved breakdown voltage at a lower cost," and as a solution, it states that "the semiconductor module of the present invention comprises an insulating substrate having a front surface and a back surface and having circuit patterns on the front surface and back surface, a semiconductor element bonded to the circuit pattern on the front surface, and a base plate bonded to the circuit pattern on the back surface. The distance between the insulating substrate and the base plate is longer than the thickness of the circuit pattern on the front surface. This makes it possible to improve the breakdown voltage of the semiconductor module at a lower cost." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 167509 [Patent Document 2] Japanese Patent Application Publication No. 2017-135144 Summary of the Invention [Problem to be solved by the invention]

[0006] Currently, semiconductor modules with power semiconductor chips mainly have a mounting structure in which a power semiconductor chip such as an IGBT is bonded to a ceramic insulating substrate with chip-bonding solder, the insulating substrate is then bonded to a base made of copper or the like with substrate-bonding solder, and a resin case is fixed to the top surface of the base. The resin case surrounds the power semiconductor chip and insulating substrate, and the inside of the case is filled with sealing resin. During temperature cycle testing, thermal stress occurs in each component that makes up a semiconductor module, primarily due to differences in the linear expansion coefficients of the base, insulating substrate, chip, and encapsulating resin, which can cause damage. There is a strong demand for high heat resistance in semiconductor modules, and hard resins with high heat resistance are increasingly being used for encapsulating resins. However, as described below, when hard resins are used, it has been found that the thermal stress generated in the insulating substrate increases during temperature cycle testing, potentially causing cracks in the insulating substrate.

[0007] FIG. 11A is a plan view of a conventional semiconductor module 101, and FIG. 11B is a cross-sectional view taken along line XIB-XIB in FIG. 11A . FIG. 11C is an enlarged view of the insulating substrate and its vicinity in FIG. 11B . In FIG. 11A , the sealing resin 126 disposed inside the case 107 is omitted to illustrate the internal structure of the semiconductor module. The sealing resin 126 is a hard resin. In the conventional semiconductor module 101 shown in FIGS. 11A and 11B , a circuit wiring pattern 120 is formed on the upper surface of an insulating substrate 122, and a semiconductor chip 123 is joined to the upper surface of the circuit wiring pattern 120 via a chip joint 125. A conductor layer 121 is formed on the lower surface of the insulating substrate 122 and is joined to the base 102 by solder at a substrate joint 124. As shown in FIG. 11B , the end faces of the circuit wiring pattern 120 and the conductor layer 121 generally coincide with each other in the x-direction in the figure. The x direction is the longitudinal direction of the semiconductor module 101.

[0008] During the temperature cycle test of this semiconductor module, if interfacial peeling P10 occurs between the sealing resin 126 and the insulating substrate 122, between the sealing resin 126 and the conductor layer 121, between the sealing resin 126 and the base 102, or between the sealing resin 126 and the substrate joint 124, as shown in FIG. 11C , shrinkage S10 of the sealing resin 126 occurs in the direction indicated by the white arrow during the cooling process of the temperature cycle test, and bending deformation D10 occurs in the base region R10 of the insulating substrate. Furthermore, as described above, because the end faces of the circuit wiring pattern 120 and the conductor layer 121 are aligned in the x-direction, stress concentration occurs in the base region R10 of the insulating substrate. Therefore, the inventors have found that cracks may occur in the insulating substrate 122. Furthermore, a thermal stress analysis simulating the temperature cycle test confirmed that the stress generated in the base region R10 of the insulating substrate increases as described above. As explained above, it has been found that a problem with semiconductor modules that use hard resins with high heat resistance is that when temperatures fluctuate, such as during temperature cycle tests, the influence of thermal stress increases the bending stress that occurs in the base region of the insulating substrate, which can lead to cracks in the insulating substrate.

[0009] The problem to be solved by the present invention is to provide a semiconductor module having a power semiconductor chip, which uses a hard resin that realizes high heat resistance while improving the reliability of the insulating substrate. [Means for solving the problem]

[0010] In order to achieve the above object, the semiconductor module of the present invention comprises an insulating substrate placed on a base via a substrate joint, a circuit wiring pattern formed on the upper surface of the insulating substrate, a conductor layer formed on the lower surface of the insulating substrate, a semiconductor chip placed on the circuit wiring pattern via a chip joint, and a sealing resin provided on the upper surface side of the base for sealing the insulating substrate and the semiconductor chip, wherein at least one of the circuit wiring pattern and the conductor layer has an uneven end face which is an end face with a shape having repeated unevenness, and the positions of the end faces are different from each other in the protruding direction of the convex parts of the uneven end face. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a semiconductor module having a power semiconductor chip, which uses a hard resin that is resistant to high heat, while improving the reliability of the insulating substrate. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view illustrating an outline of a semiconductor module according to an embodiment; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3A] FIG. 2 is a plan view illustrating an outline of a circuit board of the semiconductor module according to the embodiment. [Figure 3B] FIG. 2 is a bottom view illustrating an outline of a circuit board of the semiconductor module according to the embodiment. [Figure 4A] FIG. 3B is a cross-sectional view taken along line IVA-IVA in FIG. 3A. [Figure 4B] FIG. 3B is a cross-sectional view taken along line IVB-IVB in FIG. 3A. [Figure 5A] 10 is a plan view illustrating an example of the positional relationship between the uneven end faces of the circuit wiring pattern and the conductor layer and the end face of the insulating substrate. FIG. [Figure 5B] 10 is a plan view illustrating an example of the positional relationship between the uneven end faces of the circuit wiring pattern and the conductor layer and the end face of the insulating substrate. FIG. [Figure 6A] 1A to 1C are cross-sectional views illustrating examples of the shapes of the end faces of circuit wiring patterns and conductor layers formed by an etching process. [Figure 6B] 1A to 1C are cross-sectional views illustrating examples of the shapes of the end faces of circuit wiring patterns and conductor layers formed by an etching process. [Figure 7] FIG. 10 is a plan view illustrating an outline of a circuit board according to a first modified example. [Figure 8A] FIG. 8 is a cross-sectional view taken along line VIIIA-VIIIA in FIG. 7. [Figure 8B] FIG. 8 is a cross-sectional view taken along line VIIIB-VIIIB in FIG. [Figure 9]FIG. 10 is a plan view illustrating an outline of a circuit board according to a second modified example. [Figure 10A] FIG. 10 is a cross-sectional view taken along line XA-XA in FIG. 9. [Figure 10B] FIG. 10 is a cross-sectional view taken along line XB-XB in FIG. 9. [Figure 11A] FIG. 10 is a plan view illustrating an outline of a semiconductor module according to a conventional example. [Figure 11B] FIG. 11B is a cross-sectional view taken along line XIB-XIB in FIG. 11A. [Figure 11C] FIG. 11C is an enlarged view of a portion of FIG. 11B. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings. Note that in the drawings, some components may be omitted and the size, shape, and positional relationship of each component may be exaggerated. Furthermore, expressions such as upper and lower surfaces are examples of relative positional relationships and do not limit the direction of use. In each drawing, embodiment, and modified example, the same or similar components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0014] [Semiconductor module] A semiconductor module 1 according to an embodiment will be described with reference to FIGS. 1 to 6B. FIG. 1 is a plan view illustrating an outline of the semiconductor module 1 according to the embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3A is a plan view illustrating an outline of a circuit board 10. FIG. 3B is a bottom view illustrating an outline of the circuit board 10. FIG. 4A is a cross-sectional view taken along line IVA-IVA in FIG. 3A. FIG. 4B is a cross-sectional view taken along line IVB-IVB in FIG. 3A. FIGS. 5A and 5B are plan views illustrating the positional relationship between the irregular end faces of the circuit wiring pattern and the conductor layer and the end face of the insulating substrate. FIGS. 6A and 6B are cross-sectional views illustrating the shapes of the circuit wiring pattern and the conductor layer formed by an etching process. Note that in FIG. 1, a sealing resin 26 (described later) is omitted in order to illustrate the internal structure of the semiconductor module. 1 and 2, the semiconductor module 1 includes a base 2, an insulating substrate 22, a circuit wiring pattern 20, a conductor layer 21, a semiconductor chip 23, a chip bonding portion 25, and a substrate bonding portion 24. Here, the circuit wiring pattern 20 and the conductor layer 21 have uneven end surfaces. Each component of the semiconductor module 1 will be described below.

[0015] The base 2 is a plate-shaped member made of a metal or composite material such as copper (Cu) or silicon carbide particle reinforced aluminum composite (AlSiC), and forms part of the outer surface of the semiconductor module 1.

[0016] The insulating substrate 22 is disposed on the base 2 via a substrate joint 24. A plurality of insulating substrates 22 can be disposed on one base 2, and three insulating substrates 22 are disposed here. The insulating substrate 22 is a plate-shaped member made of ceramic such as silicon nitride. A circuit wiring pattern 20 is formed on the upper surface of the insulating substrate 22, and a conductor layer 21 is formed on the lower surface. The circuit wiring pattern 20 and the conductor layer 21 can be made of a metal such as gold, silver, or copper, and are made of copper (Cu) here.

[0017] The semiconductor chip 23 is disposed on the circuit wiring pattern 20 via a chip bonding portion 25. The semiconductor chip 23 is an element formed with a metal oxide semiconductor field effect transistor (MOSFET), an IGBT, a diode, etc. The wafer material of the semiconductor chip 23 can be silicon (Si) or silicon carbide (SiC).

[0018] The chip bonding portion 25 bonds the semiconductor chip 23 to the circuit wiring pattern 20. The substrate bonding portion 24 bonds the conductor layer 21 to the base 2. The insulating substrate 22 is bonded to the base 2 by bonding the conductor layer 21 to the base 2. Here, the chip bonding portion 25 and the substrate bonding portion 24 are solder layers, and Pb-based solder, Sn-based solder, or the like can be used. The insulating substrate 22 and the members formed on its upper and lower surfaces will be collectively described as the circuit board 10. That is, the circuit board 10 has the insulating substrate 22, the circuit wiring pattern 20 formed on the upper surface of the insulating substrate, the conductor layer 21 formed on the lower surface of the insulating substrate, the semiconductor chip 23 disposed on the circuit wiring pattern, and the chip bonding portion 25 that bonds the semiconductor chip to the circuit wiring pattern.

[0019] The semiconductor module 1 also has a case 7, an adhesive material 8, and a sealing resin 26. More specifically, the case 7 made of a resin such as PBT (Polybutylene Terephthalate) or PPS (Polyphenylene Sulfide) is fixed to the upper surface side of the base 2 with the adhesive material 8. The case 7 surrounds an insulating substrate 22 on which a semiconductor chip 23 is arranged, and the inside of the case 7 is filled with the sealing resin 26 up to a predetermined height. The sealing resin 26 is a member that comes into contact with and protects the components arranged on the base 2. The sealing resin 26 is provided on the upper surface of the base 2 and seals the insulating substrate 22 and the semiconductor chip 23. For example, epoxy resin, which is a hard resin suitable for high heat resistance, is used as the sealing resin 26. The semiconductor chip 23 is protected by the sealing resin 26. Although thermal stress on the insulating substrate 22 is rarely an issue, a material that is not a hard resin, such as silicone gel, can also be used as the sealing resin 26.

[0020] Although not shown, the semiconductor module 1 has external terminals for electrical connection to the outside, metal wires, a metal lead frame, and a lid that covers the upper surface of the case 7. The external terminals are terminals to which external devices and the like are connected, and are connected to the semiconductor chip 23 by metal wires and a metal lead frame.

[0021] In the semiconductor module 1, the shapes of the circuit wiring pattern 20 and the conductor layer 21 are set as shown in Figures 3A to 4B. First, as shown in Figures 3A and 3B, when the insulating substrate 22 is viewed from above, the circuit wiring pattern 20 has an uneven end face 33, which is an end face with a shape of repeated projections and depressions (hereinafter also referred to as an uneven shape). The conductor layer 21 has an uneven end face 34. In other words, both the circuit wiring pattern 20 and the conductor layer 21 have uneven end faces. This allows the semiconductor module 1 to distribute stress in the insulating substrate 22 that occurs at the positions of the end faces of the circuit wiring pattern 20 and the conductor layer 21. In plan view, the convex portions of the uneven end surface 33 of the circuit wiring pattern 20 and the convex portions of the uneven end surface 34 of the conductor layer 21 are arranged alternately and continuously, thereby enabling the stress of the insulating substrate 22 to be dispersed more efficiently.

[0022] Furthermore, the semiconductor module 1 has a longitudinal direction and a lateral direction perpendicular to the longitudinal direction, and both the circuit wiring pattern 20 and the conductor layer 21 have uneven end surfaces in the lateral direction. It is preferable to provide the uneven end surfaces at least in the lateral direction of the semiconductor module 1. Generally, the longitudinal direction experiences a greater amount of dimensional change due to differences in thermal expansion coefficient than the lateral direction, making deformation more likely to occur. Therefore, providing uneven end surfaces on the lateral sides perpendicular to the longitudinal direction can effectively reduce stress concentration. It is also possible to provide uneven shapes on the sides of the circuit wiring pattern 20 and the conductor layer 21 parallel to the longitudinal direction, thereby reducing stress concentration on the sides parallel to the longitudinal direction. The uneven shapes may be provided in both the lateral and longitudinal directions.

[0023] 4A and 4B, in a cross section including insulating substrate 22, end face 31 of circuit wiring pattern 20 is formed so as not to coincide with end face 32 of conductor layer 21 in the x direction. Here, the x direction is the protruding direction of the convex portions of the uneven shape. That is, circuit wiring pattern 20 and conductor layer 21 have end face positions that differ from each other in the protruding direction of the convex portions of the uneven end face. In plan view, in a cross section where circuit wiring pattern 20 has concave portions, conductor layer 21 has convex portions, and conversely, in a cross section where circuit wiring pattern has convex portions, conductor layer 21 has concave portions.

[0024] In the semiconductor module 1 having the above-described configuration, both the circuit wiring pattern and the conductor layer have uneven end faces, and the positions of the end faces in the protruding direction of the convex portions of the circuit wiring pattern and the conductor layer are different from each other, thereby dispersing stress in the insulating substrate and improving the reliability of the insulating substrate while using a hard resin that is compatible with high heat resistance. Furthermore, when viewed in a plane, the convex portions of the uneven end faces of the circuit wiring pattern and the convex portions of the uneven end faces of the conductor layer are arranged alternately and continuously, so that in each cross section, the end faces of the circuit wiring pattern and the end faces of the conductor layer can be positioned apart, thereby effectively dispersing stress in the insulating substrate.

[0025] Next, the effect of providing a concave-convex shape and not having the end faces coincide will be further explained. If thermal stress generated during a temperature cycle test causes peeling at the interfaces between the sealing resin 26 and the insulating substrate 22, between the sealing resin 26 and the conductor layer 21, between the sealing resin 26 and the base 2, or between the sealing resin 26 and the substrate joint 24, the shrinkage of the sealing resin 26 will cause bending deformation in the insulating substrate 22. As explained in the case of conventional semiconductor modules, if the end faces of the circuit wiring pattern and the end faces of the conductor layer coincide, stress concentration will occur at the base of the insulating substrate, increasing the generated stress. In other words, in Figure 11C, if interfacial peeling P10 occurs in the conventional semiconductor module 101, the positions of the end faces of the circuit wiring pattern 120 and the conductor layer 121 are aligned, which can lead to an increase in bending stress occurring in the root region R10 of the insulating substrate, resulting in a problem of cracks occurring in the insulating substrate. However, in the semiconductor module 1 according to the embodiment, as shown in FIG. 4A, the positions of the end faces are not aligned, so even if bending deformation occurs in the insulating substrate 22 due to shrinkage of the sealing resin 26, the stress concentration points are limited to two areas: the area where the end face 31 of the circuit wiring pattern 20 is located, and the area where the end face 32 of the conductor layer 21 is located, making it possible to distribute and reduce the stress generated in the insulating substrate 22.

[0026] 4A shows a case where recess end face 31B of circuit wiring pattern 20 is located to the right of protrusion end face 32A of conductor layer 21 in the figure (i.e., farther from end face 36 of insulating substrate 22), but a similar stress reduction effect can be achieved even when protrusion end face 31A of circuit wiring pattern 20 is located to the left of recess end face 32B of conductor layer 21 in the figure (i.e., closer from end face 36 of insulating substrate 22), as shown in FIG. 4B. Note that the protrusion end face is the end face of the top of the protrusion in the protruding direction of the protrusion, and the recess end face is similarly the end face of the bottom of the recess in the protruding direction of the protrusion. In addition, a thermal stress analysis simulating a temperature cycle test was conducted, and it was confirmed that the stress generated in the root region of the insulating substrate can be reduced by providing an uneven shape to the circuit wiring pattern and conductor layer, as in semiconductor module 1, and by not aligning the end faces.

[0027] Here, we consider the problems that arise when the edge surfaces of the circuit wiring pattern and the conductor layer are not provided with a concave-convex shape and the edge positions are not aligned. For example, Figure 1 of Patent Document 1 and Figure 5 of Patent Document 2 show that the edge positions of the components on the top and bottom surfaces of the insulating substrate are not aligned. Furthermore, Patent Documents 1 and 2 do not provide a concave-convex shape on the edge. With such a structure, when the ambient temperature changes, warpage occurs in the edge region of the insulating substrate due to differences in the linear expansion coefficients between the circuit wiring pattern, the insulating substrate, and the conductor layer. Furthermore, warpage of the insulating substrate can potentially lead to poor solder joints and uneven solder thickness during the process of soldering the insulating substrate to the base, reducing joint reliability. Specifically, we found that when the edge surfaces are not provided with a concave-convex shape and the edge positions of the circuit wiring pattern and the conductor layer are not aligned, warpage of the insulating substrate can reduce the reliability of the solder joint when soldering the insulating substrate to the base.

[0028] As illustrated in FIGS. 3A and 3B , in a plan view of the semiconductor module 1, the tops of the convex portions of the uneven end surface 33 of the circuit wiring pattern 20 and the uneven end surface 34 of the conductor layer 21 are located on the same straight line L1, L2. Therefore, the x-direction position of the convex end surface 31A of the circuit wiring pattern 20 coincides with the x-direction position of the convex end surface 32A of the conductor layer 21. That is, the distance between the end of the circuit wiring pattern 20 and the end of the insulating substrate 22 in FIG. 4B coincides with the distance between the end of the conductor layer 21 and the end of the insulating substrate 22 in FIG. 4A. Similarly, the x-direction position of the recessed end surface 31B of the circuit wiring pattern 20 coincides with the x-direction position of the recessed end surface 32B of the conductor layer 21. That is, the distance between the end of the circuit wiring pattern 20 and the end of the insulating substrate 22 in FIG. 4A coincides with the distance between the end of the conductor layer 21 and the end of the insulating substrate 22 in FIG. 4B.

[0029] This positional relationship allows the area of ​​the circuit wiring pattern on the upper surface of the insulating substrate 22 and the area of ​​the conductor layer on the lower surface of the insulating substrate 22 to be approximately the same in the edge region of the insulating substrate. Focusing on the x-direction, the end faces of the circuit wiring pattern 20 and the conductor layer 21 are located in the same area, and when the unevenness is smoothed, they are approximately the same distance from the edge face of the insulating substrate 22. Furthermore, if the circuit wiring pattern and the conductor layer are made of the same material and have the same thickness, their volumetric changes due to temperature can be approximately the same. This effectively suppresses warpage caused by differences in the linear expansion coefficients of these components during environmental temperature fluctuations. Therefore, for example, when soldering an insulating substrate to a base, the amount of warpage at the edge of the insulating substrate can be suppressed, reducing the load on the substrate joint during the joining process and improving the joint reliability of the substrate joint.

[0030] As explained above, a problem with semiconductor modules that use hard resins with high heat resistance is that, during temperature fluctuations such as temperature cycle tests, the influence of thermal stress can increase bending stress in the base region of the insulating substrate, potentially causing cracks in the insulating substrate. Furthermore, if the positions of the circuit wiring pattern and the edge faces of the conductor layer do not match, warping of the insulating substrate can reduce the reliability of the substrate joint when the insulating substrate is joined to the base. The semiconductor module 1 according to the embodiment can suppress the concentration of stress on the insulating substrate, reduce the occurrence of warping deformation, and improve the reliability of the insulating substrate and substrate joints while using a hard resin that achieves high heat resistance.

[0031] Even when the tops of the convex portions of the circuit wiring pattern and the conductor layer are not on the same straight line, warpage deformation at the edge of the insulating substrate can be suppressed by ensuring that the x-direction position of the end face of one of the convex portions is to the left of the x-direction position of the end face of the concave portion of the other member (i.e., closer to the edge face 36 of the insulating substrate). That is, it is sufficient to satisfy the following conditions: in plan view, the tops of the convex portions on the uneven edge face of the circuit wiring pattern are located closer to the edge face of the insulating substrate than the bottoms of the concave portions on the uneven edge face of the conductor layer, and the tops of the convex portions on the uneven edge face of the conductor layer are located closer to the edge face of the insulating substrate than the bottoms of the concave portions on the uneven edge face of the circuit wiring pattern. Figure 5A shows an example where the convex portion of circuit wiring pattern 20 is located closer to end face 36 of insulating substrate 22 than the convex portion of conductor layer 21, and Figure 5B shows an example where the convex portion of circuit wiring pattern 20 is located farther from end face 36 of insulating substrate 22 than the convex portion of conductor layer 21, and both satisfy this condition.

[0032] As an example, the width of the convex portions of the uneven end face, the length in the protruding direction, and the interval between the convex portions can be 0.1 mm or more and 1 mm or less, and preferably 0.2 mm or more and 0.5 mm or less. The circuit wiring pattern 20 and the conductor layer 21 are produced by, for example, press working or etching. When produced by press working, they can be formed on an end face perpendicular to the insulating substrate 22, as shown in FIGS. 4A and 4B. On the other hand, FIGS. 6A and 6B show an example of an end face produced by etching. Note that FIGS. 6A and 6B illustrate cross sections at positions corresponding to FIGS. 4A and 4B, respectively. In the case of etching, the end faces of both components are curved rather than perpendicular to the plane of insulating substrate 22. The x-direction position of end point 39 of circuit wiring pattern 20 in a cross section perpendicular to the insulating substrate does not coincide with the x-direction position of end point 40 of conductor layer 21. This makes it possible to reduce stress generated in the insulating substrate during a temperature cycle test even when the end faces are curved, just as in the case of end faces perpendicular to the insulating substrate.

[0033] In this way, when the end face of the circuit wiring pattern or conductor layer is not perpendicular to the insulating substrate, the position of the end face is defined as the position where the end face contacts the insulating substrate. In the examples of Figures 6A and 6B, the circuit wiring pattern and conductor layer widen as they approach the insulating substrate, and the end faces form obtuse angles with the insulating substrate at end points 39 and 40. On the other hand, depending on the processing conditions, the circuit wiring pattern and conductor layer may narrow as they approach the insulating substrate, and the end faces may form acute angles with the insulating substrate. In either case, the position where they contact the insulating substrate is defined as the position of the end face. Furthermore, the shapes of the circuit wiring pattern and conductor layer in plan view are defined as the shapes on the surfaces where they contact the insulating substrate.

[0034] Furthermore, by providing unevenness at the ends of the circuit wiring pattern 20 and the conductor layer 21 of the semiconductor module 1, the adhesive area between these components and the sealing resin 26 is increased, which is expected to improve the adhesive strength between these components and the sealing resin. At least one of the circuit wiring pattern 20 and the conductor layer 21 may have an uneven end face, which is an end face with a repeated uneven shape. By having at least one of the circuit wiring pattern 20 and the conductor layer 21 have an uneven end face and the positions of the end faces differ from each other in the protruding direction of the convex portions of the uneven end face, stress on the insulating substrate can be reduced.

[0035] [Variations] Next, a semiconductor module according to a modified example will be described with reference to Fig. 7 to Fig. 10B. The semiconductor module according to the modified example has a circuit board that is different from the semiconductor module 1 according to the embodiment, but the rest is the same. Therefore, only the circuit board of the modified example will be described, and a description of the other configurations will be omitted. Fig. 7 is a plan view illustrating an outline of a circuit board 10A according to a first modified example. Fig. 8A is a cross-sectional view taken along line VIIIA-VIIIA in Fig. 7. Fig. 8B is a cross-sectional view taken along line VIIIB-VIIIB in Fig. 7. Fig. 9 is a plan view illustrating an outline of a circuit board 10B according to a second modified example. Fig. 10A is a cross-sectional view taken along line XA-XA in Fig. 9. Fig. 10B is a cross-sectional view taken along line XB-XB in Fig. 9.

[0036] (First Modification) As illustrated in FIG. 7, the circuit board 10A of the first modified example has a different end shape of the circuit wiring pattern 20 compared to the circuit board 10 of the embodiment. In the embodiment, as shown in FIG. 1, the end of the circuit wiring pattern 20 in the x direction is uneven in plan view. However, in the circuit board 10A of the first modified example, as shown in FIG. 7, it has a linear, flat end face 37. Furthermore, as shown in FIGS. 7 to 8B, the x-direction position of end face 31 of the circuit wiring pattern is located between the x-direction positions of convex end face 32A and concave end face 32B of the conductor layer 21. In other words, one of the circuit wiring pattern and the conductor layer has an uneven end face, and the other end face is positioned so as to overlap the convex portion of one of the uneven end faces in plan view. This structure, like the embodiment, has the effect of reducing stress generated in the insulating substrate 22. Furthermore, warpage deformation in the edge region of the insulating substrate can be suppressed when the ambient temperature changes, improving the reliability of the substrate joint. Furthermore, a unique effect of the first modification is that the circuit wiring pattern on which the semiconductor chip 23 is arranged does not have an uneven shape, so the area in which the semiconductor chip can be arranged is not reduced, and the degree of freedom in chip layout design can be increased. Furthermore, the uneven edge surface of the conductor layer in the short direction effectively reduces stress concentration in the insulating substrate.

[0037] (Second Modification) As illustrated in FIG. 9 , the circuit board 10B of the second modified example has a different end shape of the conductor layer 21 compared to the circuit board 10 of the embodiment. In the embodiment, as shown in FIGS. 3A and 3B , when the circuit board is viewed from above or below, the end of the conductor layer 21 in the x direction has an uneven shape. However, in the circuit board 10B of the second modified example, as shown in FIG. 9 , the end face 32 of the conductor layer is linear and flat, as shown in FIG. 9 . Furthermore, as shown in FIGS. 9 to 10B , the x direction position of the end face 32 of the conductor layer is located between the x direction positions of the convex end faces 31A and the concave end faces 31B of the circuit wiring pattern 20. In other words, the circuit wiring pattern, which is one of the circuit wiring pattern and the conductor layer, has an uneven end face, and the other end face is positioned so as to overlap the convex portion of one of the uneven end faces in a plan view. This structure, like the embodiment, has the effect of reducing stress generated in the insulating substrate 22. Furthermore, warpage deformation in the edge region of the insulating substrate can be suppressed when the ambient temperature changes, improving the reliability of the substrate joint. A unique effect of the second modification is that the conductor layer in contact with the substrate joint does not have an uneven shape, which reduces the risk of voids occurring in the solder at the substrate joint.

[0038] In the first and second modified examples, one of the circuit wiring pattern and the conductor layer has an uneven end surface, and the positions of the end surface in the protruding direction of the convex portions of the uneven end surface are different from each other, so that it is possible to suppress the concentration of stress in the insulating substrate, as in the embodiment. Furthermore, by arranging the other end surface at a position that overlaps the convex portions of one of the uneven end surfaces in a plan view, it is possible to make the difference in distance from the end surface of the circuit wiring pattern and the conductor layer to the end surface of the insulating substrate equal to or less than the length in the protruding direction of the convex portions, and it is possible to reduce the occurrence of warpage deformation of the insulating substrate due to the difference in linear expansion coefficient. In the first modified example, it is preferable that the flat end surface 37 of the circuit wiring pattern is located in the center between the top of the convex portion and the bottom of the concave portion of the uneven end surface 34 of the conductor layer in a plan view. Also, in the second modified example, it is preferable that the flat end surface 38 of the conductor layer is located in the center between the top of the convex portion and the bottom of the concave portion of the uneven end surface 33 of the circuit wiring pattern in a plan view. This makes it possible to make the distance between the flat end surface and the end surface of the convex portion the same as the distance between the flat end surface and the end surface of the concave portion, thereby enhancing the effect of reducing stress and warpage deformation occurring in the insulating substrate.

[0039] Although the embodiments and modifications of the present invention have been described above, the present invention is not limited to the configurations described in these embodiments and modifications, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment and modification may be combined and applied.

[0040] The end faces of the circuit wiring pattern and the conductor layer that do not have a shape with repeated concave and convex portions can be arranged in positions that overlap in a plan view. Here, the end faces of the circuit wiring pattern and the conductor layer along the x-direction, i.e., the end faces along the longitudinal direction of the semiconductor module, are arranged in positions that overlap in a plan view. This can reduce warping of the insulating substrate in the short direction. The end faces of the circuit wiring pattern and the conductor layer along the x-direction can also be arranged in different positions from each other. This can reduce stress concentration in the insulating substrate. Furthermore, the uneven end surface may be provided on only a part of the side of the circuit wiring pattern or conductor layer, rather than the entire side. The convex portions of the uneven end surface do not have to be formed at a constant size or interval. [Explanation of symbols]

[0041] 1. Semiconductor module 2. Bass 7 Cases 8 Adhesive 10 Circuit Board 20 Circuit Wiring Pattern 21 Conductor layer 22 Insulating substrate 23 Semiconductor Chip 24 Substrate joint 25 Chip joint 26 Sealing resin 31 End face of circuit wiring pattern 32 End face of conductor layer 33 Uneven edge of circuit wiring pattern 34 Uneven edge of conductor layer 36 End face of insulating substrate 37 Flat end surface of circuit wiring pattern 38 Flat end surface of conductor layer 39 Circuit wiring pattern endpoints 40 End points of the conductor layer P10 Sealing resin interface peeling S10 Shrinkage of sealing resin

Claims

1. an insulating substrate disposed on the base via a substrate joint; a circuit wiring pattern formed on the upper surface of the insulating substrate; a conductor layer formed on the lower surface of the insulating substrate; a semiconductor chip disposed on the circuit wiring pattern via a chip bonding portion; a sealing resin provided on an upper surface side of the base and sealing the insulating substrate and the semiconductor chip, A semiconductor module characterized in that at least one of the circuit wiring pattern and the conductor layer has an uneven end face that is an end face with a shape that has repeated unevenness, and the positions of the end faces are different from each other in the protruding direction of the convex portions of the uneven end face.

2. Both the circuit wiring pattern and the conductor layer have the uneven end surface, 2. The semiconductor module according to claim 1, wherein, in a plan view, the convex portions of the uneven end surface of the circuit wiring pattern and the convex portions of the uneven end surface of the conductor layer are arranged alternately and continuously.

3. 3. The semiconductor module according to claim 2, wherein, in a plan view, the tops of the convex portions of the concave-convex end face of the circuit wiring pattern and the concave-convex end face of the conductor layer are aligned on the same straight line.

4. In a plan view, the tops of the convex portions of the uneven end surface of the circuit wiring pattern are located closer to the end surface of the insulating substrate than the bottoms of the concave portions of the uneven end surface of the conductor layer, 3. The semiconductor module according to claim 2, wherein the tops of the convex portions of the uneven end face of the conductor layer are located closer to the end face of the insulating substrate than the bottoms of the concave portions of the uneven end face of the circuit wiring pattern.

5. 2. The semiconductor module according to claim 1, wherein either the circuit wiring pattern or the conductor layer has the uneven end surface, and the other end surface is positioned so as to overlap the convex portion of one of the uneven end surfaces in a planar view.

6. 6. The semiconductor module according to claim 5, wherein the other end face is located at the center between the tops of the convex portions and the bottoms of the concave portions of one of the concave-convex end faces in plan view.

7. It has a longitudinal direction and a lateral direction perpendicular to the longitudinal direction, 2. The semiconductor module according to claim 1, wherein at least one of the circuit wiring pattern and the conductor layer has the uneven end surface in the short side direction.

8. It has a longitudinal direction and a lateral direction perpendicular to the longitudinal direction, 2. The semiconductor module according to claim 1, wherein at least one of the circuit wiring pattern and the conductor layer has the uneven end surface in the longitudinal direction.

9. It has a longitudinal direction and a lateral direction perpendicular to the longitudinal direction, 6. The semiconductor module according to claim 5, wherein the conductor layer has the uneven end surface in the short side direction.

10. 10. The semiconductor module according to claim 1, wherein the circuit wiring pattern and the end face of the conductor layer that does not have a shape with repeated projections and depressions are arranged in a position that overlaps in a plan view.

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