FET drive circuit, protection device and power storage device

Abstract

To suppress an FET component failure by shortening an FET switching time TS and expanding an ASO region.SOLUTION: A drive circuit for an FET Q20 includes a gate circuit 160 that applies a drive voltage to the gate G of the FET Q20, a gate-source resistor R20 connected between the gate and source of the FET Q20, and a discharge circuit 170 that is connected in parallel to the gate-source resistor R20 and has a resistance value at least smaller than that of the gate-source resistor R20. When the drive voltage is cut off, the discharge circuit 170 becomes conductive to discharge the charge between the gate and source of the FET Q20, and after discharging the charge, it switches to non-conductive.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a technique for improving the response of an FET. [Background technology]

[0002] One of the protection devices for an electricity storage device is a current interruption device. A relay or a FET can be used for the current interruption device. Patent Document 1 is an example of a document that uses a FET for a current interruption device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-166454 Summary of the Invention [Problem to be solved by the invention]

[0004] FIG. 1 shows an example of a gate circuit 160. The gate circuit 160 drives the gate G of the FET Q20, and in the example of FIG. 1, is composed of a switch Q3 and a diode D. When the switch Q3 is turned on, Vgs becomes a positive voltage equal to or greater than the threshold, and the FET Q20 turns on. R20 is a gate-source resistor. By setting R20 to a high resistance of around several megohms, it is possible to reduce the current consumption while the FET Q20 is on.

[0005] To switch FET Q20 from ON to OFF, Vg must be cut off and the charge on the parasitic capacitance C between the gate and source must be discharged to lower Vgs to a voltage below the threshold. However, if R20 is a high resistance, it takes time to discharge the charge, and switching takes time.

[0006] Figure 2 shows the relationship between the switching time TS of FETQ20 and heat loss W. If the switching time TS is long, the heat loss (switching loss) W increases. As a result, as shown in part A of Figure 3A, the ASO region (Area of ​​Safety Operation) may be deviated from, which could lead to FET failure. One way to avoid FETQ20 failure is to increase the number of FETQ20s connected in parallel, reducing the drain current per unit and preventing deviation from the ASO region.

[0007] The object of the present invention is to suppress component failures of FETQ20 without increasing the number of parallel connections by shortening the switching time TS of FETQ20 and expanding the ASO region. [Means for solving the problem]

[0008] The FET drive circuit includes a gate circuit that applies a drive voltage to the gate of the FET, a gate-source resistor connected between the gate and source of the FET, and a discharge circuit connected in parallel to the gate-source resistor. The discharge circuit becomes conductive when the drive voltage is cut off to discharge the charge between the gate and source of the FET, and then becomes non-conductive after the charge is discharged. [Effects of the Invention]

[0009] The present invention can suppress component failures of FETs without increasing the number of parallel connections by shortening the switching time of the FETs and expanding the ASO region. [Brief explanation of the drawings]

[0010] [Figure 1] FET gate circuit [Figure 2] Diagram showing the relationship between FET switching time and heat loss [Figure 3A] ASO characteristics [Figure 3B] ASO characteristics [Figure 4] FET drive circuit [Figure 5]Diagram showing the relationship between FET switching time and heat loss [Figure 6] Side view of a motorcycle [Figure 7] Block diagram of a motorcycle battery [Figure 8] Exploded perspective view of the battery [Figure 9] Battery Schematic [Figure 10] Battery Schematic [Figure 11] Battery Schematic [Figure 12] A diagram summarizing the monitoring IC, delay circuit output, and switch operation [Figure 13] Battery Schematic [Figure 14] Battery Schematic [Figure 15] A diagram summarizing the monitoring IC, delay circuit output, and switch operation [Figure 16] Battery Schematic DETAILED DESCRIPTION OF THE INVENTION

[0011] (Outline of this embodiment) (1) A driver circuit 150 for the FET Q 20 according to one embodiment of the present invention will be described. FIG. 4 shows a drive circuit 150 for the FET Q20. The FET Q20 is, for example, a power FET used for power applications. The FET Q20 is not limited to power applications and may be used for other applications. In the example of FIG. 4, the FET Q20 is an N-channel FET, but it may also be a P-channel FET. The FET is an example of a semiconductor switch.

[0012] The drive circuit 150 includes a gate circuit 160, a gate-source resistor R20, and a discharge circuit 170.

[0013] Gate circuit 160 applies drive voltage Vg to gate G of FET Q20. Gate-source resistor R20 is connected between the gate and source of FET Q20. Discharge circuit 170 is connected in parallel to gate-source resistor R20 and has a resistance value at least smaller than that of gate-source resistor R20.

[0014] The discharge circuit 170 becomes conductive when the drive voltage Vg is cut off, discharges the charge due to the parasitic capacitance C between the gate and source of the FET Q20, and after the charge is discharged, switches to a non-conductive state. In the drive circuit 150 described in (1), any configuration other than the above is optional and may be any configuration.

[0015] According to the drive circuit 150 of (1), the charge of the parasitic capacitance C is discharged using the discharge circuit 170 having a lower resistance than the gate-source resistor R20, so that the switching time TS of the FET Q20 can be shortened as shown in FIG.

[0016] By shortening the switching time TS, the ASO region can be expanded as shown in Figure 3B. Therefore, component failure of FET Q20 can be suppressed without increasing the number of parallel connections. Furthermore, since the discharge circuit 170 switches to non-conducting after discharging the charge, there is no power consumption in the discharge circuit 170 even if the FET Q20 is subsequently switched from OPEN to CLOSE. Therefore, the current consumption does not increase.

[0017] (2) The drive circuit described in (1) above may further include a delay circuit that switches the discharge circuit to non-conductive after a delay time has elapsed since the start of conduction (start of discharge). According to (2), the conduction time (discharge time) of the discharge circuit can be controlled by utilizing the delay operation of the delay circuit.

[0018] (3) In the drive circuit described in (2) above, the delay time may be longer than the time required for discharging the charge between the gate and source of the FET. According to (3), it is possible to prevent the discharge of the charge between the gate and source from being insufficient, thereby improving the reliability of the switching operation of the FET.

[0019] (4) The drive circuit according to any one of (1) to (3) may be applied to a protection device for a power storage device, which includes an FET that cuts off the current of the power storage device.

[0020] (5) The protection device described in (4) may be applied to a power storage device including a power storage element.

[0021] <Embodiment 1> An example in which the present invention is applied to a drive circuit of a current interruption device 70 for a battery will be described. 1. Battery structure explanation 6, the battery 20 (an example of a power storage device) according to the embodiment is a battery for a motorcycle mounted on a motorcycle 10. The battery 20 has a rated voltage of 12 volts (V) and can be used to replace (for example, as a retrofit) a conventional lead-acid battery.

[0022] As shown in Figure 7, a starter 10A, an alternator 10B, and accessories 10C (headlights, a car navigation system, etc.) mounted on a motorcycle 10 are connected to a battery 20. The battery 20 supplies 12V power to the starter 10A to start the engine. The battery 20 is charged by the alternator 10B while the engine is running.

[0023] 8, the battery 20 includes a management unit 53, a plurality of storage cells 3 (an example of a storage element), and a rectangular parallelepiped storage case 40 that houses them. The storage cells 3 may be battery cells such as lithium ion secondary batteries, or may be electrochemical cells such as capacitors.

[0024] Four storage cells 3 are connected in series to form the assembled battery 30. Alternatively, some of the storage cells 3 may be connected in parallel. For example, the assembled battery 30 may have eight storage cells 3 connected in two parallel connections and four in series, or twelve storage cells 3 connected in three parallel connections and four in series.

[0025] The storage case 40 is made of synthetic resin. The storage case 40 includes a case body 41, a lid 42 that closes the opening of the case body 41, a storage section 43 provided in the lid 42, a cover 44 that covers the storage section 43, an inner lid (bus bar frame) 45, and a partition plate 46. The inner lid 45 and the partition plate 46 do not necessarily have to be provided. The energy storage cells 3 are inserted between the partition plates 46 of the case body 41.

[0026] A plurality of metal bus bars 47 (conductive members) are placed on the inner lid 45. The inner lid 45 is placed near the terminal surface on which the cell terminals 32 of the storage cells 3 are provided, and the adjacent cell terminals 32 of adjacent storage cells 3 are connected by the bus bars 47, so that the storage cells 3 are connected in series.

[0027] The storage section 43 is box-shaped and has a protrusion 43a that protrudes outward from the center of one long side in a plan view. A positive terminal 51 and a negative terminal 52 made of metal such as a lead alloy are provided on both sides of the protrusion 43a on the lid section 42. A management unit 53 is stored in the storage section 43. The management unit 53 is connected to the energy storage cells 3 via wiring members and bus bars 47 (not shown). Instead of being stored in the storage section 43, the management unit 53 may be disposed adjacent to the battery pack 30, for example, above or to the side. The management unit 53 may have multiple circuit boards.

[0028] The energy storage cell 3 includes a hollow rectangular parallelepiped case 31 and a pair of cell terminals 32, 32 with opposite polarities provided on one side (terminal surface, top surface) of the case 31. The case 31 accommodates an electrode assembly 33 formed by stacking a positive electrode, a separator, and a negative electrode, and an electrolyte (electrolytic solution) not shown.

[0029] Although not shown in detail, the electrode assembly 33 is constructed by stacking a sheet-shaped positive electrode and a sheet-shaped negative electrode with two sheet-shaped separators in between and winding them (vertical or horizontal). The separators are formed from a porous resin film. Examples of the porous resin film that can be used include porous resin films made of resins such as polyethylene (PE) and polypropylene (PP).

[0030] The positive electrode is an electrode plate in which a positive electrode active material layer is formed on the surface of a long strip-shaped positive electrode substrate made of, for example, aluminum, an aluminum alloy, or the like. The positive electrode active material layer contains a positive electrode active material. The positive electrode active material used in the positive electrode active material layer can be a material capable of absorbing and releasing lithium ions. The positive electrode active material is, for example, LiFePO4, but is not limited thereto, and so-called ternary positive electrode active materials may also be used. The positive electrode active material layer may further contain a conductive additive, a binder, etc.

[0031] The negative electrode is an electrode plate in which a negative electrode active material layer is formed on the surface of a long strip-shaped negative electrode substrate made of, for example, copper or a copper alloy. The negative electrode active material layer contains a negative electrode active material. The negative electrode active material can be a material capable of absorbing and releasing lithium ions. Examples of the negative electrode active material include graphite, hard carbon, and soft carbon. The negative electrode active material layer may further contain a binder, a thickener, and the like.

[0032] The electrolyte housed in the housing case 40 together with the electrode assembly 33 can be the same as that used in conventional lithium-ion secondary batteries. For example, an electrolyte containing a supporting salt in an organic solvent can be used. As the organic solvent, for example, an aprotic solvent such as carbonates, esters, or ethers can be used. As the supporting salt, for example, a lithium salt such as LiPF6, LiBF4, or LiClO4 can be suitably used. The electrolyte may contain various additives such as a gas generating agent, a film-forming agent, a dispersant, or a thickener.

[0033] FIG. 8 shows a prismatic lithium ion battery including a wound electrode assembly 33 as an example of the storage cell 3. Alternatively, the storage cell 3 may be a cylindrical lithium ion battery or a laminated (pouch) lithium ion battery. The storage cell 3 may also be a lithium ion battery including a laminated electrode assembly. The storage cell 3 may also be an all-solid-state lithium ion battery using a solid electrolyte.

[0034] 2. Description of the Electrical Configuration of Battery 20 9 is a circuit diagram of the battery 20. The battery 20 includes a battery pack 30, a current interruption device 70, a monitoring IC 110, an output circuit 120, a reuse prohibition latch operation circuit 130, a recovery circuit 140, and a drive circuit 150. These circuits 110 to 150 are provided on the management unit 53, for example.

[0035] The battery pack 30 is composed of four storage cells 3 connected in series. The positive electrode of the battery pack 30 is connected to a positive terminal 51 via a power line 53a. The negative electrode of the battery pack 30 is connected to a negative terminal 52 via a power line 53b.

[0036] The current interruption device 70 is disposed on the power line 53b and is composed of a switch Q20 and a switch Q21.

[0037] The switches Q20 and Q21 are N-channel power FETs. FET stands for Field Effect Transistor. The source of the switch Q20 is connected to the negative electrode of the battery pack 30, and the drain is connected to the drain of the switch Q21. The source of the switch Q21 is connected to the negative terminal 52 of the battery 20.

[0038] The switch Q20 is a discharge cutoff switch that cuts off discharging, and the switch Q21 is a charge cutoff switch that cuts off charging.

[0039] The monitoring IC 110 monitors the state of the battery 20. Items monitored include the cell voltage of each storage cell 3, the total voltage, current, and temperature of the battery pack 30. When the battery 20 is normal, the monitoring IC 110 outputs a VDD voltage from the output terminal UV, and when an abnormality is detected, it outputs a GND voltage. VDD is the internal power supply voltage of the battery 20. GND is the reference potential.

[0040] The reuse prohibition latch operation circuit 130 is a circuit that, under predetermined conditions, shuts off the current interruption device 70 and prohibits the use of the battery 20. The reuse prohibition latch operation circuit 130 outputs VDD except when prohibiting the use of the battery 20. The recovery circuit 140 is a circuit that releases the cutoff of the current interruption device 70 and restores it.

[0041] The output circuit 120 is composed of switches Q1 and Q2 and a resistor R1. The switch Q1 is a P-channel FET, and the switch Q2 is an N-channel FET.

[0042] The source of switch Q1 is connected to VDD, and the drain is connected to the drain of switch Q2 via resistor R1, and the source of switch Q2 is connected to GND.

[0043] The gate of the switch Q1 and the gate of the switch Q2 are connected to the output terminal UV of the monitoring IC 110. The drain of the switch Q2 is connected to the gate of the switch Q3 via the output line L1.

[0044] The drive circuit 150 is a circuit that drives the gate G of the current interruption device 70. The drive circuit 150 is made up of a gate circuit 160, gate source resistors R20 and R21, a discharge circuit 170, and a delay circuit 180.

[0045] The gate circuit 160 is composed of a switch Q3 and diodes D1 to D4. The switch Q3 is a P-channel FET. The source of the switch Q3 is connected to the output terminal of the reuse-prohibit latch operation circuit 130, and the drain is connected to the anode of the diode D2.

[0046] The cathode of diode D2 is connected to the gate G of switch Q20. Diode D3 has its anode connected to the anode of diode D2 and its cathode connected to the gate G of switch Q21.

[0047] Diode D1 has an anode connected to the output terminal of recovery circuit 140 and a cathode connected to gate G of switch Q20. Diode D4 has an anode connected to the output terminal of recovery circuit 140 and a cathode connected to gate G of switch Q21.

[0048] A gate-source resistor R20 is connected between the gate and source of the switch Q20. A gate-source resistor R21 is connected between the gate and source of the switch Q21. The gate-source resistors R20 and R21 may each have a high resistance of about several MΩ.

[0049] The discharge circuit 170 is composed of a switch Q10, a switch Q11, and resistors R10 and R11. The switch Q10 is a P-channel FET. The switch Q10 has a gate connected to the output terminal UV of the monitoring IC 110. The switch Q10 has a source connected to the output terminal of the delay circuit 180 and a drain connected to GND via resistor R10.

[0050] Switch Q11 is an N-channel FET. Its gate is connected to the drain of switch Q10. Its source is connected to GND and its drain is connected to the gate of switch Q20 via resistor R11.

[0051] Resistor R11 is a discharge resistor that discharges the charge of parasitic capacitance C that exists between the gate and source of switch Q20, and has a resistance smaller than that of gate-source resistor R20. In this example, it is set to about 100 Ω.

[0052] The delay circuit 180 is connected to the output line L1 of the output circuit 120, and the output value of the output circuit 120 is taken in as an input voltage. The output terminal of the delay circuit 180 is connected to the source of the switch Q10. The delay circuit 180 operates as follows, triggered by a change in the output value of the output circuit 120 (the input voltage to the delay circuit).

[0053] When the input voltage switches from GND to VDD, the delay circuit 180 switches the output voltage from VDD to GND after a delay time has elapsed since the switching point. Also, when the input voltage switches from VDD to GND, the delay circuit 180 switches the output voltage from GND to VDD after a delay time has elapsed since the switching point. The delay circuit 180 functions to control the discharge time of the discharge circuit 170 through the delay operation described above. The delay circuit 180 can be, for example, a capacitor or a timer.

[0054] The battery 20 further includes a bypass line L2 and a switch Q30. The bypass line L2 bypasses the battery pack 30 and the current interruption device 70 and connects the two terminals 51 and 52. The switch Q30 is provided on the bypass line L2.

[0055] The switch Q30 is a P-channel FET, with its source connected to the positive terminal 51 and its drain connected via a resistor R3 to the negative terminal 52. The gate of the switch Q30 is connected to the gate G of the switch Q20.

[0056] 3. Description of the operation of the drive circuit 150 <Normal time> When the battery 20 is normal, the monitoring IC 110 controls the voltage of the output terminal UV to VDD, as shown in Fig. 9. The VDD output turns off both the switches Q10 and Q11, and the discharge circuit 170 becomes non-conductive.

[0057] Furthermore, the output voltage VDD of the monitoring IC 110 turns switch Q1 OFF and switch Q2 ON. As a result, the output line L1 becomes the GND potential, and the GND voltage is applied to the input terminal of the delay circuit 180. Furthermore, switch Q3 turns ON. While switch Q3 is ON, the drive voltage VDD is applied to gate G, and Vgs becomes a positive voltage equal to or greater than the threshold. As a result, switches Q20 and Q21 are CLOSE.

[0058] Furthermore, in the normal state, switch Q30 is turned off, so the input voltage to recovery circuit 140 is the voltage at terminal 52, that is, the GND level.

[0059] <Operation flow when overdischarge is detected> 10 and 11 are circuit diagrams showing the operation of the drive circuit 150 when over-discharge is detected, and FIG. 12 is a table summarizing the outputs of the monitoring IC 110 and delay circuit 180 and the operations of each switch Q for (1) to (8).

[0060] (1) When the monitoring IC 110 detects an over-discharge abnormality in the battery 20 (the voltage of the storage cell 3 becomes lower than the lower limit voltage), it switches the voltage of the output terminal UV from VDD to GND as shown in FIG. (2) The following operations are simultaneously performed by the GND output of the monitoring IC 110. (A) Switch Q10 turns ON. (B) Switch Q1 is ON and switch Q2 is OFF. With switch Q1 turned on and switch Q2 turned off, the output line L1 of the output circuit 120 becomes the VDD potential, and switch Q3 turns off. Also, the voltage of VDD is applied to the input terminal of the delay circuit 180 via the output line L1 of the output circuit 120.

[0061] (3) When the switch Q10 is turned on, the switch Q11 is turned on, which makes the discharge circuit 170 conductive. (4) When discharge circuit 170 becomes conductive, the charge of parasitic capacitance C between the gate and source of switch Q20 is discharged to GND via resistor R11. As a result, Vgs becomes lower than the threshold voltage, and switch Q20 turns OFF. Turning switch Q20 OFF cuts off the discharge of battery 20.

[0062] (5) When delay time T1 has elapsed since the input voltage was switched from GND to VDD (the start of discharge) due to the operation (B) above, delay circuit 180 switches the voltage of the output terminal from VDD to GND, as shown in Fig. 11. Delay time T1 is preferably longer than discharge time T2 of parasitic capacitance C (T1>T2).

[0063] (6) When the voltage at the output terminal of the delay circuit 180 switches to GND, the switch Q10 switches from ON to OFF, as shown in FIG. (7) When the switch Q10 is switched from ON to OFF, the switch Q11 is also switched from ON to OFF, and the discharge circuit 170 becomes non-conductive.

[0064] (8) After the switch Q20 is turned off, the gate G of the switch Q20 is maintained at the GND potential by the gate-source resistor R20, so the switch Q20 remains off.

[0065] Although it takes longer for switch Q21 to turn on than switch Q20, once the charge of parasitic capacitance C is discharged via gate-source resistor R21, switch Q21 switches from ON to OFF and remains OFF thereafter. As a result, discharging and charging of battery 20 are blocked.

[0066] <Operation flow when resuming charging> 13 and 14 are circuit diagrams showing the operation of the drive circuit 150 when charging resumes, and FIG. 15 is a table summarizing the outputs of the monitoring IC 110 and delay circuit 180 and the operations of each switch Q for (9) to (14).

[0067] (9) A user or the like connects the charger 200 between the positive and negative terminals 51 and 52 as shown in FIG.

[0068] (10) When the charger 200 is connected, the negative terminal 52 becomes a negative voltage. As a result, the voltage at the input terminal of the recovery circuit 140 switches from a positive voltage to a negative voltage. In response to the switch in the voltage at the input terminal, the recovery circuit 140 switches its output voltage from GND to VDD.

[0069] (11) When the output voltage of the recovery circuit 140 switches from GND to VDD, the drive voltage VDD is applied to the gates G of the switches Q20 and Q21 via the diodes D1 and D4, causing Vgs to become a positive voltage greater than or equal to the threshold. As a result, the switches Q20 and Q21 close. This cancels the current cutoff, and charging current I flows from the charger 200 to the battery 20.

[0070] (12) As charging continues, the voltage of the storage cell 3 increases and the over-discharge abnormality is resolved (the voltage of the storage cell 3 becomes higher than the lower limit voltage), and the monitoring IC 110 switches the voltage of the output terminal UV from GND to VDD, as shown in FIG. 14.

[0071] (13) When the output of the monitoring IC 110 switches from GND to VDD, the switch Q1 turns OFF and the switch Q2 turns ON. As a result, the output line L1 of the output circuit 120 becomes the GND potential, and the switch Q3 turns ON. Also, the voltage at the input terminal of the delay circuit 180 switches from VDD to GND.

[0072] (14) After detecting the change in input voltage, the delay circuit 180 switches the output voltage from GND to VDD when the delay time T1 has elapsed, thereby returning the drive circuit 150 to its original state.

[0073] During the operations (9) to (14), the two switches Q10 and Q11 are not turned on at the same time, so the switch Q20 does not turn off during charging.

[0074] The conditions for switches Q10 and Q11 to turn ON are as follows. Output voltage of the delay circuit - Output voltage of the monitoring IC < Gate voltage equal to or higher than the threshold for turning Q10 ON

[0075] That is, in this embodiment, switches Q10 and Q11 turn ON only when the output voltage of the monitoring IC100 changes from VDD to GND (when an abnormality of the battery 20 is detected), and when the output voltage of the monitoring IC100 is in the VDD state, switches Q10 and Q11 maintain OFF. Therefore, in the operation flows of (1) to (14), the following requirements can be satisfied.

[0076] A: When the output of the monitoring IC100 changes from VDD to GND due to the detection of an abnormality of the battery 20, quickly cut off (OPEN) the switch Q20. B: When the charger 200 is connected, the switch Q20 does not operate (does not OPEN).

[0077] In addition, when the charger 200 is connected, if the switch Q20 operates (OPENs), the charging current flows through the body diode of the switch Q20. Therefore, depending on the magnitude of the charging current, Q20 may generate heat and exceed the temperature rating, resulting in a failure. However, according to this configuration, the failure of the switch Q20 can be suppressed.

[0078] <Other Embodiments> The present invention is not limited to the embodiments described above and in the drawings. For example, the following embodiments are also included in the technical scope of the present invention.

[0079] (1) In the above embodiment, the battery 20 is for a motorcycle. The use of the battery 20 is not limited to motorcycles. It may be for a four - wheel vehicle, or for uses other than automobiles and vehicles.

[0080] (2) In the above embodiment, the present technology is applied to the drive circuit of the switch Q20 that cuts off the current of the battery 20. The present technology may also be applied to drive circuits of switches used for other power applications, such as load switches.

[0081] (3) In the above embodiment, the switches Q20 and Q21 are arranged at the negative terminal of the battery pack 30 and are N-channel FETs. The switches Q20 and Q21 may be arranged at the positive terminal of the battery pack 30 and a P-channel FET may be used.

[0082] (4) In the above embodiment, the discharge circuit 170 is provided on the gate G of the switch Q20 that cuts off discharging. As shown in FIG. 16, in addition to the switch Q20 that cuts off discharging, the discharge circuit 170 may also be provided on the gate of the switch Q21 that cuts off charging. By providing the discharge circuit 170 on the switch Q21 that cuts off charging, charging can be instantly cut off when an abnormality is detected. This is effective when the charging current becomes large. Furthermore, without being limited to the above, the discharge circuit 170 may be provided on either one of the two switches Q20 and Q21. [Explanation of symbols]

[0083] 20 Battery (electricity storage device) 30 battery packs 70 Current interrupter 150 Drive Circuit 160 Gate Circuit 170 Discharge circuit 180 Delay Circuit Q20, Q21 switches C parasitic capacitance R11 resistance R20 Gate-source resistor

Claims

1. A drive circuit for an FET, a gate circuit that applies a drive voltage to the gate of the FET; a gate-source resistor connected between the gate and source of the FET; a discharge circuit connected in parallel to the gate-source resistor and having a resistance smaller than at least the gate-source resistor; The discharge circuit becomes conductive when the drive voltage is cut off to discharge the charge between the gate and source of the FET, and after the charge is discharged, the discharge circuit becomes non-conductive.

2. 2. The drive circuit of claim 1, The drive circuit includes a delay circuit that switches the discharge circuit to a non-conductive state after a delay time has elapsed since the discharge circuit started to be conductive.

3. 3. The drive circuit according to claim 2, The delay time is longer than the discharge time of the charge between the gate and source of the FET.

4. A protection device for an electricity storage device, an FET that cuts off the current of the power storage device; A protection device comprising: a drive circuit according to any one of claims 1 to 3.

5. A power storage device comprising a power storage element and the protection device according to claim 4.

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