Design support apparatus, learning device, trained model, and learning system

Abstract

To facilitate the determination of target impedance.SOLUTION: A design support apparatus includes a data acquisition unit 305 and an inference unit 310. The data acquisition unit 305 acquires first information representing multiple functions of a chip included in an integrated circuit component that can be mounted on a first substrate, second information regarding operation timing of the multiple functions, and third information regarding current consumption of the multiple functions. Using a trained model 230, the inference unit infers target impedance of the first substrate as seen from the integrated circuit component mounted on the first substrate from model input data DIN including the first information, the second information, and the third information. The trained model 230 is a model in which a correspondence between input data and impedance data as output data for the input data is learned. The inference unit 310 infers the target impedance as power supply impedance for each of multiple frequencies.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present disclosure relates to a design support device, a learning device, a trained model, and a learning system, and is applied to, for example, power integrity design. [Background technology]

[0002] Power integrity refers to the quality of the power supply voltage on the power lines and / or power layers of a printed circuit board. For example, power integrity issues include noise generated inside IC (Integrated Circuit) components such as LSI (Large Scale Integration) that propagates through the power lines / power layers, and a drop in power supply voltage due to current consumption by IC components.

[0003] One of the power integrity design techniques is to design the circuit board so that the impedance between the power supply layer and the ground layer as seen from the terminal position of the IC component on the circuit board (called "source impedance") does not exceed the target impedance. The target impedance is generally used as the upper limit of the source impedance. It is not easy to determine the target impedance in the early stages of circuit board design.

[0004] Japanese Patent Laid-Open Publication No. 2011-22822 (Patent Document 1) discloses a method for easily determining a target impedance. The power integrity analyzer in this document assumes a current waveform that represents the change in the current consumption of an LSI on a time axis, specifically, a waveform in which identical triangular waves occur at regular intervals. The maximum value of this current waveform, the time required for it to change from a steady value to the maximum value, and the period of the triangular wave are input by the designer (user). The power integrity analyzer converts the current waveform on the time axis into a current spectrum on the frequency axis. Then, based on the rated value of the power supply voltage and the allowable fluctuation rate of the power supply voltage, the power integrity analyzer calculates a target impedance spectrum according to the formula: rated power supply voltage value × allowable fluctuation rate / current consumption spectrum. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-22822 Summary of the Invention [Problem to be solved by the invention]

[0006] Even with the method disclosed in Patent Document 1, it is still not easy to determine the target impedance because it is difficult for a printed circuit board designer to identify the maximum value of the current consumption waveform of an IC component and the time required for it to change from a steady value to the maximum value at the early stage of board design.

[0007] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to make it easier to determine the target impedance. [Means for solving the problem]

[0008] In one embodiment, a design support device for supporting power integrity design is provided. The design support device includes a data acquisition unit and an inference unit. The data acquisition unit acquires first information representing multiple functions of a chip included in an integrated circuit component mountable on a first substrate, second information regarding operation timings of the multiple functions, and third information regarding current consumption of the multiple functions. The inference unit uses a trained model to infer a target impedance of the first substrate as seen from the integrated circuit component mounted on the first substrate from input data including the first information, the second information, and the third information. The trained model is a model that has learned a correspondence relationship between the input data and impedance data as output data for the input data. The impedance data is data indicating the power supply impedance of the second substrate when the multiple functions are operating, as seen from the integrated circuit component mounted on a second substrate different from the first substrate, for each of a plurality of predetermined frequencies. The inference unit infers a target impedance as the power supply impedance for each of the plurality of frequencies. [Effects of the Invention]

[0009] According to the above embodiment, the power supply impedance of the second board when multiple functions are operating is output as the target impedance of the first board according to the input data using a trained model that has trained the correspondence between input data and the power supply impedance of the second board when an integrated circuit component is mounted on the second board. The input data (first information, second information, and third information) are information that can be easily identified by the designer of the first board at an early stage of board design. Therefore, the target impedance can be easily determined (inferred). [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating an IC component mounted on a printed circuit board according to an embodiment, and the configuration of the board. [Figure 2] FIG. 2 is a block diagram showing an example of a circuit model of an IC component and its external elements. [Figure 3]FIG. 10 is a circuit diagram showing a detailed configuration example of an IC component model. [Figure 4] FIG. 1 is a block diagram showing an example of a configuration of a design support apparatus according to an embodiment. [Figure 5] FIG. 10 is a block diagram showing a more detailed configuration example of a structural information input unit. [Figure 6] FIG. 2 is a block diagram showing a more detailed configuration example of an operation parameter input unit. [Figure 7] FIG. 10 is a diagram showing an example of an input screen for parameters of each function. [Figure 8] 1A and 1B are diagrams illustrating an example of a screen for inputting parameters of a general-purpose input / output (GPIO) and an example of a screen for inputting parameters of a communication circuit. [Figure 9] FIG. 1 is a timing diagram conceptually illustrating current waveforms for one function of the chip. [Figure 10] 10 is a flowchart showing the operation of the design support device. [Figure 11] FIG. 2 is a block diagram showing the functional configuration of the learning device. [Figure 12] FIG. 4 is a diagram illustrating an example of data acquired by a data acquisition unit. [Figure 13] FIG. 2 is a diagram showing the configuration of a neural network used in a model generation unit. [Figure 14] A figure for explaining an example of the frequency characteristics of the power supply impedance output from the trained model. [Figure 15] 10 is a flowchart illustrating an example of a learning process performed by a learning device. [Figure 16] FIG. 2 is a block diagram showing the functional configuration of an inference device and an information processing device. [Figure 17] FIG. 2 is a diagram illustrating an example of input data to an input unit. [Figure 18] FIG. 4 is a diagram illustrating an example of a screen displayed on a display unit. [Figure 19] 10 is a flowchart showing an example of processing related to inference processing by the inference device. [Figure 20]10 is a flowchart showing another example of processing related to inference processing by the inference device. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The same or corresponding parts in the drawings will be denoted by the same reference numerals, and the description thereof will not be repeated. The embodiments and their modifications may be combined with each other as appropriate.

[0012] 1 is a diagram showing an IC component mounted on a printed circuit board according to an embodiment, and the configuration of the board. Referring to FIG. 1, IC component 1 is an integrated circuit component that can be mounted on printed circuit board 2. IC component 1 includes a chip 3, an on-chip capacitor 4, bonding wires 5, and a package 6.

[0013] The chip 3 includes an IC such as a microcomputer, and specifically has multiple functions such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory). An on-chip capacitor 4 is provided on the chip 3 to absorb instantaneous current changes. Bonding wires 5 are provided between the chip 3 and the package 6.

[0014] The package 6 is provided on the printed circuit board 2 and includes a power terminal 7A and a ground terminal 7B. The power terminal 7A corresponds to the power terminal of the IC component 1. The ground terminal 7B corresponds to the ground terminal of the IC component 1. The current Ip is a power supply current that flows into the power terminal 7A and flows out of the ground terminal 7B when multiple functions of the chip 3 are operating. The current Ip corresponds to the total current consumption of the chip 3. The voltage Vp is a power supply voltage applied between the power terminal 7A and the ground terminal 7B. By dividing the voltage Vp by the current Ip, the power supply impedance Zp of the printed circuit board 2 as seen from the IC component 1 when multiple functions of the chip 3 are operating can be derived.

[0015] The printed circuit board 2 is a multilayer board and includes signal layers 9sa and 9sb, a power supply layer 9p, and a ground layer 9g. The signal layers 9sa and 9sb include various signal wirings. The ground layer 9g is a ground plane connected to the ground terminal 7B. The power supply layer 9p is a power supply plane connected to the power supply terminal 7A. The power supply layer 9p and the ground layer 9g are connected to an external power supply (not shown), and a power supply voltage VS from the external power supply is applied between these layers.

[0016] Fig. 2 is a block diagram showing an example of a circuit model of an IC component 1 and its external elements. Referring to Fig. 2, the circuit model 10 includes an IC component model 20 and external information 30. The IC component model 20 is a model of the IC component 1 as an electric circuit. The external information 30 is a model of the external elements of the IC component 1 as an electric circuit. The external elements include wiring from the power supply terminal 7A and the ground terminal 7B to an external power supply.

[0017] The IC component model 20 includes a current source model 21, an on-chip capacitor 4, an equivalent circuit 23 of the bonding wires, and an equivalent circuit 24 of the package.

[0018] The current source model 21 represents a model of the current source when the chip 3 is modeled as a current source. In the current source model 21, the total current consumption of the chip 3 is expressed as the sum of the current consumption Ii per cycle for each function used among the multiple functions of the chip 3 (i is the number for each function used). That is, the current source model 21 of the chip 3 is I = I1 + I2 + I3 + … + Ii + … (1) The method for determining the current consumption Ii for each of the above functions will be described later with reference to FIGS.

[0019] 3 is a circuit diagram showing a detailed example of the configuration of the IC component model 20. This example shows specific examples of the configuration of an equivalent circuit 23 of the bonding wires and an equivalent circuit 24 of the package.

[0020] 3, in IC component model 20, on-chip capacitor 4 is connected in parallel with current source model 21. The capacitance value of on-chip capacitor 4 is determined as, for example, an actual value of an on-chip capacitor of a similar IC component in the past.

[0021] The equivalent circuit 23 of the bonding wire is represented by a two-terminal pair circuit. This two-terminal pair circuit includes resistors 43 and 45, inductors 44 and 46, and a capacitor 47. The capacitor 47 is connected between output terminals 48 and 49 of the two-terminal pair circuit. The resistor 43 and the inductor 44 are connected in series between the high-potential input terminal 41 and the high-potential output terminal 48 of the two-terminal pair circuit. The resistor 45 and the inductor 46 are connected in series between the low-potential input terminal 42 and the low-potential output terminal 49 of the two-terminal pair circuit. An on-chip capacitor 4 and a current source model 21 are connected in parallel between the input terminals 41 and 42 of the two-terminal pair circuit. The resistance values ​​of the resistors 43 and 45, the inductance values ​​of the inductors 44 and 46, and the capacitance value of the capacitor 47 can be estimated based on the thickness of the bonding wire 5, the size of the IC component 1, and the like.

[0022] The package equivalent circuit 24 is also represented by a two-terminal circuit. This two-terminal circuit includes a resistor 53, an inductor 54, and a capacitor 55. The capacitor 55 is connected between output terminals 58 and 59 of the two-terminal circuit. The high-side output terminal 58 corresponds to the power supply terminal 7A. The low-side output terminal 59 corresponds to the ground terminal 7B. The resistor 53 and the inductor 54 are connected in series between the high-side input terminal 51 and the high-side output terminal 58 of the two-terminal circuit. The high-side input terminal 51 is connected to the high-side output terminal 48 of the two-terminal circuit representing the bonding wire equivalent circuit 23. The low-side input terminal 52 is directly connected to the low-side output terminal 59 and is also connected to the low-side output terminal 49 of the two-terminal circuit representing the bonding wire equivalent circuit 23. The package equivalent circuit 24 may be an equivalent circuit described in the IBIS (Input / Output Buffer Information Specification) model.

[0023] 2, external information 30 includes an equivalent circuit 31 of the printed circuit board wiring, an equivalent circuit 32 of the passive components, and a power supply 33 of the board wiring. The voltage of power supply 33 corresponds to the power supply voltage VS (FIG. 1). The ground wiring of printed circuit board 2 is connected to ground GND.

[0024] The circuit model 10 is an example assuming an equivalent circuit model of SPICE (Simulation Program with Integrated Circuit Emphasis), a commonly used electronic circuit simulator, but is not limited to this example. For example, S-parameters (Scattering Parameters), which are circuit network parameters used to represent the characteristics of high-frequency electronic circuits and high-frequency electronic components, may also be used. The simulation method is not limited to SPICE simulation. It is not limited to the equivalent circuit, and simulation using layout data, for example, may also be performed. Furthermore, when an equivalent circuit is used, it is not limited to the equivalent circuits shown in FIGS. 2 and 3.

[0025] By performing a simulation using a circuit model such as that shown in FIGS. 2 and 3, it is possible to calculate the voltage Vp that reflects the switching noise that occurs within the chip 3 when multiple functions of the chip 3 are operating.

[0026] 4 is a block diagram showing an example of the configuration of a design support device according to an embodiment. Referring to FIG. 4, design support device 70 is for supporting the design of power integrity of printed circuit board 2, and includes an IC component model generation device 80 and a power integrity analysis device 90.

[0027] The IC component model generating device 80 generates an IC component model 20 (FIGS. 2 and 3) based on input information from a designer. The input information is information described in a data sheet or the like provided by the manufacturer of the IC component 1, and can be easily identified (obtained) by the designer of the printed circuit board 2 at an early stage of board design. A more detailed configuration of the IC component model generating device 80 will be described later with reference to FIGS. 5 to 9.

[0028] The power integrity analysis device 90 calculates the voltage Vp by simulating the circuit model 10 (FIG. 2) based on the IC component model 20. The power integrity analysis device 90 includes a board wiring information input unit 91, a passive component information input unit 92, a power supply voltage input unit 93, a simulation execution unit 94, a result output unit (time axis) 95, and a result output unit (frequency axis) 96.

[0029] The board wiring information input unit 91 receives input of circuit parameters required to generate an equivalent circuit 31 (FIG. 2) of the printed board wiring. The passive component information input unit 92 receives input of circuit parameters required to generate an equivalent circuit 32 of the passive components. The power supply voltage input unit 93 receives input of the value of the power supply voltage VS of the board wiring.

[0030] The above configuration is modified as appropriate depending on the circuit model used in the simulation. For example, when a simulation using layout data is performed, the power integrity analysis apparatus 90 receives input of the layout data.

[0031] The simulation execution unit 94 includes a power supply voltage calculation unit 97, a voltage / current calculation unit 98, and a power supply impedance calculation unit 99. The power supply voltage calculation unit 97, the voltage / current calculation unit 98, and the power supply impedance calculation unit 99 calculate the time variations of the voltage Vp, the current Ip, and the power supply impedance Zp, respectively, through simulation based on the circuit model 10 of the printed circuit board. These time variation data reflect switching noise caused by the operation of multiple functions of the chip 3.

[0032] Furthermore, the power supply voltage calculation unit 97 performs a Fourier transform on the time-varying data of the calculated voltage Vp to calculate the spectrum of the switching noise contained in the voltage Vp. Similarly, the power supply impedance calculation unit 99 performs a Fourier transform on the time-varying data of the power supply impedance Zp to calculate the frequency characteristics of the power supply impedance Zp. Since the power supply impedance Zp generally has frequency dependency, it is shown as a continuous value on a graph with the horizontal axis representing frequency and the vertical axis representing power supply impedance. From the calculation results of the continuous frequency characteristics, the power supply impedance calculation unit 99 can extract only the power supply impedance Zp for each of a plurality of predetermined reference frequencies. These frequencies will be explained in detail later.

[0033] A result output unit (time axis) 95 displays the waveform of the voltage Vp on the time axis on a display or outputs it to an external printer (not shown).A result output unit (frequency axis) 96 displays the waveform of the voltage Vp on the frequency axis on a display or outputs it to an external printer.

[0034] The design support device 70 is realized by, for example, a computer including a CPU (Central Processing Unit), a storage device, an input / output device, etc., and a program running on the computer. Such a computer may be, for example, a server, an engineering workstation, or a personal computer.

[0035] The design support device 70 further includes a storage device 100, a learning device 200, an inference device 300, and an information processing device 400. The storage device 100 is an auxiliary storage device such as an HDD (Hard Disk Drive) or an SSD (Solid State Drive). The learning device 200, the inference device 300, and the information processing device 400 will be described in detail later.

[0036] The IC component model generation device 80 determines a power supply current waveform for each function selected by the designer as a function to be used, and determines the power supply current waveform of the current source model 21 (FIG. 1) of the chip 3 by superimposing the determined power supply current waveforms. Furthermore, the IC component model generation device 80 generates the final IC component model 20 based on the information about the inside of the package input by the designer.

[0037] Specifically, the IC component model generating device 80 includes a structural information input unit 81, an operation parameter input unit 82, a function-to-be-used selection unit 83, a current waveform calculation unit 84, and a model generating unit 85. Some or all of the functions of the function-to-be-used selection unit 83, the current waveform calculation unit 84, and the model generating unit 85 are performed by dedicated circuits such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The configuration of the IC component model generating device 80 will be described in detail below.

[0038] 5 is a block diagram showing a more detailed configuration example of the structural information input unit 81. Referring to FIG. 5, the structural information input unit 81 receives input of structural information relating to the power supply wiring structure of the IC component 1 from the chip 3 to the power supply terminal 7A and the ground terminal 7B of the package 6, i.e., information relating to the portion of the IC component model 20 other than the current source model 21. The structural information input unit 81 stores the input information in a storage device inside the design support device 70 or in a storage device such as a server outside the design support device 70. The structural information input unit 81 includes a capacitance input unit 101 for an on-chip capacitor, an equivalent circuit input unit 102 for a bonding wire, an equivalent circuit input unit 103 for a package, and a terminal information input unit 104.

[0039] The on-chip capacitor capacitance input unit 101 receives an input of the capacitance value of the on-chip capacitor 4 .

[0040] The bonding wire equivalent circuit input unit 102 receives input of circuit parameters of the bonding wire equivalent circuit 23 (FIGS. 2 and 3). In the case of the equivalent circuit of FIG. 3, the equivalent circuit input unit 102 receives input of the resistance values ​​of resistors 43 and 45, the inductance values ​​of inductors 44 and 46, and the capacitance value of capacitor 47.

[0041] The package equivalent circuit input unit 103 receives input of the circuit parameters of the package equivalent circuit 24 (FIGS. 2 and 3). In the case of the equivalent circuit of FIG. 3, the equivalent circuit input unit 103 receives input of the resistance value of the resistor 53, the inductance value of the inductor 54, and the capacitance value of the capacitor 55.

[0042] The terminal information input unit 104 receives input of information such as the types of the power supply terminals 7A and ground terminals 7B of the IC component 1. Based on this input information, the structural information input unit 81 generates an equivalent circuit of the portion of the IC component model 20 in FIG. 2 other than the current source model 21 of the chip 3.

[0043] 6 is a block diagram showing a more detailed example of the configuration of the operation parameter input unit 82 (FIG. 4). Referring to FIG. 6, the operation parameter input unit 82 receives input of operation parameters for each of the multiple functions of the chip 3. The operation parameters include information about the operation timing of the function (for example, the operation timing itself or the operating frequency) and information about the average current consumption of the function. This information is information described in data sheets provided by IC component manufacturers, and can be easily identified by designers in the early stages of board design.

[0044] The operation parameter input unit 82 includes an operation parameter input unit 110 for each function that operates on the internal clock, and a parameter input unit 120 for a GPIO / communication circuit that references the internal clock.

[0045] The operation parameter input unit 110 for each function includes an operating frequency calculation unit 111 for each function, a current consumption input unit 115 for each function, and a channel number input unit 116 for each function. Furthermore, the operation frequency calculation unit 111 for each function includes a main clock frequency input unit 112, a main clock division ratio input unit 113, and a frequency multiplication ratio input unit 114 for a PLL (Phase Locked Loop) circuit.

[0046] The GPIO / communication circuit parameter input unit 120 includes a GPIO operation timing input unit 121, a GPIO current consumption input unit 122, a communication circuit operating frequency input unit 123, and a communication circuit current consumption input unit 124. These functions in FIG. 6 will be described below.

[0047] The main clock frequency input unit 112 receives an input of the main clock frequency of the chip 3. The main clock division ratio input unit 113 receives an input of the division ratio for each function. The PLL circuit frequency multiplication ratio input unit 114 receives an input of the multiplication ratio for each function. The operating frequency calculation unit 111 calculates the operating frequency for each function by multiplying the main clock frequency by the division ratio or multiplication ratio for each function. The operating parameter input unit 110 for each function may directly receive an input of the operating frequency for each function instead of using the operating frequency calculation unit 111 for each function.

[0048] The current consumption input unit 115 for each function receives an input of the current consumption value for each channel of each function on the chip 3. The channel number input unit 116 for each function receives an input of the number of channels for each function on the chip 3 (i.e., how many channels the function has). The operation parameter input unit 110 for each function calculates the current consumption value for each function by multiplying the current consumption value for each channel of each function by the number of channels of the function. The operation parameter input unit 110 for each function may also receive an input of the current consumption value for all channels of each function. The operation parameter input unit 110 for each function may also receive an input of information on the total current consumption (current Ip in FIG. 1) of the chip 3 and calculate the current consumption of each function by dividing the input total current consumption by the functions used and the number of channels of each function.

[0049] If the chip 3 has a GPIO such as a microcomputer, the GPIO operation timing input unit 121 receives input of the operation timing for each function that is actually used (for example, in the case of an A / D converter, the sampling time, conversion period, etc.). The GPIO current consumption input unit 122 receives input of the current consumption value for each function that is actually used. These input values ​​can be easily identified by the designer at an early stage of board design from the data sheet for the IC component 1 provided by the manufacturer of the IC component 1.

[0050] If the chip 3 has a communication circuit, the communication circuit operating frequency input unit 123 receives an input of the operating frequency for each function of the communication circuit. The communication circuit current consumption input unit 124 receives an input of the current consumption value for each function of the communication circuit. If the performance of the communication circuit is specified by the operating timing itself rather than the operating frequency, the GPIO / communication circuit parameter input unit 120 may receive an input of the operating timing of the communication circuit as in the case of GPIO.

[0051] Fig. 7 is a diagram showing an example of an input screen for parameters of each function. Referring to Fig. 7, input screen 130 shows an example of an input screen when operation parameter input section 110 for each function of operation parameter input section 82 and use function selection section 83 receive input from a designer. In this example, chip 3 is assumed to be a microcomputer.

[0052] Referring to FIG. 7, input screen 130 includes an input section 131 for inputting whether each function is to be used, an input section 132 for inputting the function name of chip 3, an input section 133 for inputting the operating frequency of each function, an input section 134 for inputting the number of channels to be used for each function, and an input section 135 for inputting the current consumption value for each channel of each function.

[0053] The input section 131 for inputting whether each function is used corresponds to the function selection unit 83 (FIG. 4). Information input to this input section is also referred to as "used / unused information 131a." This information indicates, for each function, whether the function is used or not. In this example, all of the multiple functions are used functions. Information input to the function name input section 132 is information representing multiple functions of the chip 3 (more specifically, the attributes (types) of these functions). This information is also referred to as "function information 132a." The input section 133 for inputting the operating frequency of each function corresponds to the operating frequency calculation unit 111 (FIG. 6) of the operating parameter input unit 110 for each function. Information input to this input section is also referred to as "operating frequency information 133a." The operating frequency information 133a is information representing the operating frequency of each function and is shown as an example of information regarding the operating timing of multiple functions. The operating frequency information 182_1 may be replaced with information representing the operating timing of each function itself. In this example, the operating frequency of each function is directly input as the operating frequency information 133a, but the operating frequency calculation unit 111 may calculate the operating frequency of each function by receiving the frequency, division rate, and frequency multiplication rate of the main clock of the chip 3 as input.

[0054] An input section 134 for the number of channels used for each function corresponds to the number of channels input section 116 (FIG. 6) of the operation parameter input section 110 for each function. Information input into this input section is also referred to as "number of channels information 134a." An input section 135 for the current consumption value for each channel of each function corresponds to the current consumption input section 115 (FIG. 6) of the operation parameter input section 110 for each function. Information input into this input section is also referred to as "current consumption information for each channel 135a."

[0055] The use / non-use information 131a and the function information 132a are also collectively referred to as "function-related information 136." The channel number information 134a and the current consumption information per channel 135a are also collectively referred to as "current consumption information 137." The current consumption information 137 represents the average current consumption of each function and is shown as an example of information regarding the current consumption of multiple functions. The average current consumption of a function is determined by multiplying the number of channels for that function by the average current consumption per channel for that function. The operating frequency information 133a and the current consumption information 137 are also collectively referred to as "operating parameters 138." The operating parameters 138 are information described in a data sheet or the like provided by the manufacturer of the IC component 1, and can be easily identified by the designer of the printed circuit board 2 at an early stage of board design. The function-related information 136 and the operating parameters 138 are also collectively referred to as "input data 139."

[0056] Fig. 8 shows an example of an input screen for GPIO parameters and an example of an input screen for communication circuit parameters. The input screen in Fig. 8 shows an example of an input screen when the GPIO / communication circuit parameter input unit 120 (Fig. 6) of the operation parameter input unit 82 receives input from a designer. In this example, the chip 3 is a microcomputer.

[0057] Referring to FIG. 8(A), GPIO parameter input screen 140 includes a display section 141 for displaying the GPIO function name, an input section 142 for inputting the terminal name for each terminal of each GPIO function, an input section 143 for inputting the sampling time, conversion period, etc. as the operation timing for each terminal of each GPIO function, and an input section 144 for inputting the current consumption value for each terminal of each GPIO function.

[0058] The GPIO function name display section 141 corresponds to the function name input in the function name input section 132. The number of lines in the terminal name input screen 140 is equal to the input value of the number of channels (FIG. 7), and is provided for each function. The input section 143 for the operation timing for each terminal of each function corresponds to the GPIO operation timing input section 121 (FIG. 7) of the GPIO / communication circuit parameter input section 120 in the operation parameter input section 82 in FIG. 6. The input section 144 for the current consumption value for each terminal of each GPIO function corresponds to the GPIO current consumption input section 122 (FIG. 7) of the GPIO / communication circuit parameter input section 120. For each function for which "Use" has been input in the input section 131 for whether or not to use each function (FIG. 7), information indicating the operation timing and current consumption value must be input as operation parameters 146.

[0059] The input values ​​in the input section 143 for the operation timing of each terminal of each function are not limited to the sampling time and conversion period (FIG. 8), but may be any value required to determine the current waveform of the current source model 21 of the chip 3. If there is a GPIO function that is specified by the operating frequency rather than the operating timing, an input section for the operating frequency is provided on the input screen 140 of FIG. 8(A) instead of the input section 143 for the operation timing, as in FIG. 8(B).

[0060] Referring to FIG. 8(B), the input screen 150 for parameters of the communication circuit includes a display section 151 for the function name of the communication circuit, an input section 152 for inputting the terminal name for each terminal of each function of the communication circuit, an input section 153 for inputting the operating frequency for each terminal of each function of the communication circuit, and an input section 154 for inputting the current consumption value for each terminal of each function of the communication circuit.

[0061] The display section 151 for the function name of the communication circuit corresponds to the function name input in the function name input section 132 (FIG. 7). The number of lines in the terminal name input section 152 is equal to the input value of the number of channels for each function. The input section 153 for the operating frequency for each terminal of each function of the communication circuit corresponds to the communication circuit operating frequency input section 123 (FIG. 6) of the GPIO / communication circuit parameter input section 120 of the operation parameter input section 82. The input section 154 for the current consumption value for each terminal of each function of the communication circuit corresponds to the communication circuit current consumption input section 124 (FIG. 6) of the GPIO / communication circuit parameter input section 120. For each function for which "Use" has been input in the input section 131 for whether each function is to be used (FIG. 7), information indicating the operating frequency (operating timing) and the current consumption value must be input as operation parameters 156.

[0062] 9 is a timing diagram conceptually showing the current waveform of one function of chip 3. This current waveform is calculated by current waveform calculation unit 84 (FIG. 4) based on the input information (FIGS. 7 and 8) in operation parameter input unit 82 and use function selection unit 83.

[0063] 9, a triangular waveform pulse current flows between time t1 and time t2 when the clock of the operating frequency X [Hz] of the function rises and between time t3 and time t4 when the clock falls. The operating frequency X [Hz] corresponds to the operating frequency calculated by the operating frequency calculation unit 111 of the operating parameter input unit 110 of each function (FIG. 6), the operating frequency based on the operating timing input by the GPIO operating timing input unit 121 of the GPIO / communication circuit parameter input unit 120, or the frequency input by the operating frequency input unit 123 of the communication circuit.

[0064] In the case of Figure 9, the peak value of the pulse current at the rising edge of the clock is 5Z [A], and the peak value of the pulse current at the falling edge of the clock is Z [A]. Empirically, it is known that the peak current value at the rising edge is relatively large, and the peak current value at the falling edge is relatively small. In Figure 9, the ratio of the peak current value at the rising edge to the peak current value at the falling edge is 5:1, but it is not limited to 5:1.

[0065] The time for which each pulse current flows is empirically set to 1 / 20 of the operating cycle of the function in question (1 / X [seconds]), i.e., 1 / (20X) [seconds]. However, the time for which each pulse current flows is not limited to 1 / 20 of the operating cycle.

[0066] By integrating the current waveform of the pulse current over time at the rising and falling edges, the amount of charge [C] (also called the amount of electricity) that flows at the rising and falling edges can be calculated. Specifically, by calculating the area of ​​the triangle, (Amount of charge at rise) = 5 × Z / (20X) × 0.5 … (2) (Charge amount at the time of falling) = Z / (20X) × 0.5 … (3) Therefore, the amount of charge that flows per cycle is calculated by adding the above equations (2) and (3) as follows: (Amount of charge per cycle) = 3Z / (20X) ... (4) It is required that:

[0067] On the other hand, the average current consumption Y [A] corresponds to the values ​​input in the current consumption input section 115 of the operation parameter input section 110 for each function and the current consumption input sections 122 and 124 of the GPIO / communication circuit parameter input section 120 (all shown in FIG. 6). These values ​​can be easily identified in the early stages of board design from data sheets for IC components, etc.

[0068] Using the average current consumption Y [A], the amount of charge that flows per cycle: 1 / X [seconds] can be calculated by calculating the area of ​​the rectangle: (Amount of charge per cycle) = Y / X …(5) Since equation (4) and equation (5) are equal, Z=20Y / 3 …(6) The following relationship is obtained.

[0069] The rising peak current value 5Z [A] and the falling peak current value Z [A] can be calculated from the above equation (6). This allows the current waveforms of each function of the chip 3 output from the current source model 21 (Figures 2 and 3) to be determined.

[0070] While the above example shows the calculation of the current waveform based on the operating frequency of each function, the current waveform may also be calculated based on the operating timing itself, as shown in FIG. 8. For example, instead of the clock waveform, the on / off waveform of the digital input / output circuit and the on / off waveform of the communication circuit may be used. Therefore, more generally, the current waveform calculation unit 84 determines the timing at which a current pulse is periodically generated for each function of the chip 3 based on information about the operating timing of each function. The current waveform calculation unit 84 also determines the peak value of the current pulse based on the average current consumption of each function.

[0071] Fig. 10 is a flowchart showing the operation of the design support device 70 (Fig. 4). Hereinafter, steps are abbreviated as "S". Referring to Fig. 10, the structural information input unit 81 of the IC component model generation device 80 receives input of structural information of the IC component 1 (S100). Specifically, the structural information input unit 81 receives input of the capacitance value of the on-chip capacitor 4, each parameter value of the bonding wire equivalent circuit 23, and each parameter value of the package equivalent circuit 24.

[0072] The operation parameter input unit 82 receives input of operation parameters according to the use conditions of the chip 3 (S110). For example, the operation parameter input unit 82 receives input of operation parameters 138, 146, and 156 from the designer via input screens 130, 140, and 150 in FIGS.

[0073] The function selection unit 83 receives a selection input of a function to be used from among the multiple functions of the chip 3 (S120).

[0074] Based on the operating parameters and functions input in S110 and S120, the current waveform calculation unit 84 calculates the time during which the pulse current flows and the current waveform peak value for each function (S130). In this example, "1 / (20X)", "5Z", and "Z" (all shown in FIG. 9) are calculated for each function. This determines the current waveform for each function of the chip 3 in the IC component model 20. As a result, the output current waveform of the current source model 21 is determined by superposing these current waveforms.

[0075] The model generation unit 85 generates an IC component model 20 (FIG. 2) by combining the equivalent circuit determined based on the input of the structural information in S100 with the current source model 21 of the chip 3 determined in S130 (S140).

[0076] The board wiring information input unit 91 receives input of board wiring information, the passive component information input unit 92 receives input of passive component information, and the power supply voltage input unit 93 receives input of the value of the power supply voltage VS (S150). As a result, the external information 30 (FIG. 2) is determined.

[0077] 1 using the external information 30 determined in S150 and the IC component model 20 generated in S140 (S160). The simulation execution unit 94 executes a simulation using the circuit model 10 (S165). The simulation execution unit 94 calculates the voltage Vp and current Ip through the simulation, and thereby calculates the source impedance Zp (S170). Furthermore, the simulation execution unit 94 performs a Fourier transform on the voltage Vp and the source impedance Zp to calculate their frequency spectra.

[0078] The result output unit (time axis) 95 displays the time axis waveform of the voltage Vp on the display (S180).

[0079] The result output unit (frequency axis) 96 displays the frequency spectrum of the voltage Vp (S190). This completes the series of processes.

[0080] The order of the steps in the flowchart shown in Fig. 10 is merely an example and is not limited to this. For example, S100 may be executed at any time before S140. S150 may be executed at any time before S160.

[0081] The input of parameters and the like in S100, S110, and S150 does not necessarily have to be directly input by the designer into the design support device 70. For example, digital data pre-stored in an external server or disk array may be downloaded via a network to the design support device 70. Alternatively, data pre-stored in a storage device of the design support device 70 may be read by the CPU of the design support device 70.

[0082] According to the design support device 70, even if neither detailed information on the operating characteristics of the IC component 1 nor actual measured values ​​of the current consumption waveform of the chip 3 are available in the early stages of board design, it is possible to calculate the voltage Vp and current Ip through a circuit simulation using only easily available information such as data sheets provided by the manufacturer of the IC component 1. This makes it possible to automatically and easily calculate the source impedance Zp and its frequency characteristics.

[0083] In development efforts to expand product lineups, printed circuit boards for derivative products are sometimes developed based on the configuration of a core product whose operation has been confirmed (e.g., by slightly changing this configuration). Hereinafter, the printed circuit board for a derivative product under development will also be referred to as the "board under development." The printed circuit board for a core product whose operation has been confirmed will also be referred to as the "confirmed board." Like printed circuit board 2, the board under development and the confirmed board are each multilayer boards including signal layers 9sa and 9sb, a ground layer 9g, and a power supply layer 9p. The confirmed board is a multilayer board used as a reference for the design of the board under development, and these boards have similar configurations. In this example, the ground layer 9g and power supply layer 9p of the confirmed board have a similar (e.g., identical) configuration to the ground layer 9g and power supply layer 9p of the board under development, while the signal layer 9sa (or signal layer 9sb) of the confirmed board is different from the signal layer 9sa (or signal layer 9sb) of the board under development. The IC component 1 can be mounted on either the board under development or the confirmed board.

[0084] In the above-described product development, a board under development may be developed by mounting an IC component 1 (for example, a main microcomputer) identical to the IC component 1 mounted on the confirmed board on the board under development.

[0085] The power impedance Zp of the board under development as seen from the IC component 1 when the IC component 1 is mounted on the board under development is generally determined to be less than the power impedance Zp of the confirmed board as seen from the IC component 1 when the IC component 1 is mounted on the confirmed board. In other words, the power impedance of the confirmed board is used as the target impedance of the board under development.

[0086] If it is difficult for the designer of a board under development to grasp the target impedance of the board under development in the early stages of board design, or if it takes a lot of time to calculate the target impedance, the designer may not be able to properly develop the board under development.

[0087] Therefore, design support device 70 according to an embodiment has a configuration for dealing with the above problem. Learning device 200, inference device 300, and information processing device 400 (all shown in FIG. 4) of design support device 70 will be described below.

[0088] 11 is a block diagram showing the functional configuration of learning device 200. Referring to FIG. 11, learning device 200 includes a data acquisition unit 205, a learning dataset generation unit 210, and a model generation unit 215. Some or all of these functions are performed, for example, by the CPU of learning device 200 executing a program stored in its memory. Some or all of these functions may be performed by a dedicated circuit such as an ASIC, or may be performed on the cloud.

[0089] The data acquiring unit 205 acquires information input via the input screens 130, 140, and 150 from the IC component model generating device 80 and the power integrity analyzing device 90. This information is, for example, input data 139 (FIG. 7). As described above, the input data 139 includes function information 132a, operating frequency information 133a, and current consumption information 137. Furthermore, the data acquiring unit 205 acquires, from the power source impedance calculating unit 99, power source impedance data indicating the power source impedance Zp (specifically, each frequency component thereof) calculated by the power source impedance calculating unit 99 for each of the aforementioned multiple reference frequencies.

[0090] 12 is a diagram illustrating an example of data acquired by data acquiring unit 205. Referring to FIG. 12, this data includes input data 139 and power supply impedance data 190_1. Function-related information 136, operating frequency information 133a, number-of-channel information 134a, current consumption information per channel 135a, current consumption information 137, and input data 139 are also referred to as function-related information 181_1, operating frequency information 182_1, current consumption information 183_1, number-of-channel information 184_1, current consumption information per channel 185_1, and input data 180_1, respectively.

[0091] The power supply impedance data 190_1 is generated by the power supply impedance calculation unit 99 based on the input data 180_1. The power supply impedance data 190_1 is data indicating the power supply impedance Zp of the confirmed board when a plurality of functions of the chip 3 are operating, as seen from the IC component 1 mounted on the confirmed board. The power supply impedance data 190_1 indicates the power supply impedance Zp for each of the above-mentioned plurality of reference frequencies (in this example, fa to fe). Each reference frequency is not particularly limited, but in this example, it is the frequency of the main clock of the chip 3 or a frequency obtained by multiplying or dividing this frequency. The power supply impedances for these reference frequencies are Z1a to Z1e, respectively. The input data 180_1 and the power supply impedance data 190_1 are also referred to as learning data 500_1.

[0092] 11 again, the data acquisition unit 205 further collects a large number of learning data, each of which is data similar to the learning data 500_1. Each learning data indicates (a) the operating frequency (operating timing) of a combination of functions different from the example of FIG. 12, the number of channels, and the current consumption value for each channel, and (b) the power supply impedance Zp of the confirmed board corresponding to that combination. The data collected as described above is also referred to as "learning data 500_2, 500_3, ...."

[0093] The information related to (a) above, included in the training data 500_k (k=1, 2, 3, ...), is also referred to as "input data 180_k." The function-related information, operating frequency information, and current consumption information included in the input data 180_k are also referred to as function-related information 181_k, operating frequency information 182_k, and current consumption information 183_k, respectively. These pieces of information are examples of "first information," "second information," and "third information" in the present disclosure, respectively. The data related to (b) above, included in the training data 500_k, is also referred to as "power supply impedance data 190_k." In the training data 500_k, the power supply impedance data 190_k corresponds to output data for the input data 180_k.

[0094] The training dataset generation unit 210 combines the training data 500_1, 500_2, 500_3, ... according to a predetermined format to generate a training dataset 550 including these data. The training dataset generation unit 210 stores the training dataset 550 in the storage device 100.

[0095] The model generation unit 215 generates a trained model 230 using a training dataset 550 and stores the trained model 230 in the storage device 100. The trained model 230 is a model in which the correspondence between the input data 180_k and the power supply impedance data 190_k for each value of k has been learned. The model generation unit 215 generates the trained model 230 by so-called supervised learning in accordance with a neural network model. Supervised learning refers to a technique in which a set of input and result (label) data is provided to the learning device 200 to learn the characteristics of each training data and infer a result from the input. The training data 500_k corresponds to the supervised data in supervised learning.

[0096] In the embodiment, the power supply impedance data 190_k (power supply impedance Zp of the confirmed board) used to generate the training data set 550 is automatically generated by circuit simulation based on the function-related information 181_k, operating frequency information 182_k, current consumption information 183_k, structural information of the IC component 1, and information on the board under development (specifically, board wiring information, passive component information, and power supply voltage information). As a result, the time and effort required to generate (prepare) the training data set 550 can be reduced compared to when the power supply impedance Zp of the confirmed board is determined by experiment.

[0097] 13 is a diagram showing the configuration of a neural network used in model generation unit 215. The neural network includes an input layer, an intermediate layer (hidden layer), and an output layer. Each of these layers consists of multiple neurons.

[0098] Referring to FIG. 13, when input data containing n values ​​is input to the input layer (X1-Xn), the input value is multiplied by a weight W1 (w11, w12, ...) and the resulting value is input to the hidden layer (Y1-Yk). The input value to the hidden layer is further multiplied by a weight W2 (w21, w22, ...) and the resulting value is output from the output layer (Z1-Zm) as output data containing m values. The output result of the neural network varies depending on the values ​​of the weights W1 and W2. The neural network performs supervised learning by inputting input data 180_k to the input layer and adjusting the weights W1 and W2 so that the result output from the output layer approaches power source impedance data 190_k (correct data). The neural network may have two or more hidden layers.

[0099] The reason why information defining the operating state of each function of the chip 3, such as the function-related information 181_k, the operating frequency information 182_k, and the current consumption information 183_k, affects the power supply impedance Zp will be explained below.

[0100] First, the relationship between the function-related information 181_k and the power supply impedance Zp will be described. When a function of the chip 3 operates, a current Ip corresponding to the function flows through the IC component 1 at the function's operation timing. This causes the current Ip to fluctuate, generating switching noise. As a result, the voltage Vp of the IC component 1 fluctuates, and the power supply impedance Zp calculated based on the voltage Vp and the current Ip fluctuates. The extent to which the current Ip fluctuates varies depending on the function of the chip 3. Generally, functions with larger circuit scales and more frequent signal changes tend to have larger fluctuations in the current Ip. In this way, the degree of fluctuation in the current Ip is determined depending on the type of function operating. Therefore, the function-related information 181_k is data that affects the power supply impedance Zp and is suitable as an element of the learning data 500_k for outputting the power supply impedance Zp.

[0101] Next, the relationship between operating frequency information 182_k and power supply impedance Zp will be described. When a function operates, current Ip fluctuates at the operating frequency (operating timing) of the function. Therefore, power supply impedance Zp also fluctuates with the operating frequency of the function. Therefore, operating frequency information 182_k is data that affects power supply impedance Zp, and is suitable as an element of learning data 500_k.

[0102] Next, the relationship between current consumption information 183_k and power supply impedance Zp will be described. Generally, the greater the number of channels for a function, the greater the current Ip tends to be. Therefore, the greater the number of channels, the greater the fluctuation in current Ip tends to be. Therefore, channel number information 184_1 of current consumption information 183_k is a parameter that affects power supply impedance Zp, and is therefore suitable as an element of learning data 500_k. Furthermore, the peak current at the rise and fall of the current of each channel is related to the average current consumption and can cause fluctuations in current Ip (see FIG. 9). Therefore, current consumption information 185_1 for each channel is a parameter that affects power supply impedance Zp, and is therefore suitable as an element of learning data 500_k. From the above, current consumption information 183_k is suitable as an element of learning data 500_k.

[0103] 14 is a diagram illustrating an example of the frequency characteristics of the power supply impedance Zp output from the trained model 230. Referring to FIG. 14, a line 600 represents the continuous frequency characteristics of the power supply impedance Zp calculated by the power supply impedance calculation unit 99 when certain input data (for example, input data 180_1) is provided. Points p1a to p1e represent the frequency components of the power supply impedance Zp calculated as described above for a plurality of reference frequencies (fa to fe). In this example, a group of points representing the power supply impedance Zp output from the trained model 230 when other input data is provided is also shown for each input data.

[0104] Fig. 15 is a flowchart illustrating an example of a process related to the learning process by the learning device 200. Referring to Fig. 15, the data acquiring unit 205 acquires input data 180_k and power impedance data 190_k for each value of k from the IC component model generating device 80 and the power integrity analysis device 90, thereby acquiring learning data 500_k (S205).

[0105] The training data set generation unit 210 generates a training data set 550 by combining a large number of training data 500_k (S210).

[0106] The model generation unit 215 executes a learning process to generate the trained model 230 by supervised learning in accordance with the training data set 550 (S215).

[0107] The model generation unit 215 stores the trained model 130 in the storage device 100 (S220).

[0108] 16 is a block diagram showing the functional configuration of inference device 300 and information processing device 400. Referring to FIG.

[0109] The input unit 405 is a device such as a keyboard or a mouse that can input operations by the designer of the board under development. The input unit 405 receives input data consisting of function-related information, operating frequency information, and current consumption information for the chip 3 of the IC component 1 to be mounted on the board under development. The input unit 405 also receives input of wiring information, passive component information, and the value of the power supply voltage VS for the board under development. The display unit 410 is a display device that displays various screens.

[0110] The control unit 415 includes a CPU and a memory (neither of which are shown). The control unit 415 receives information input to the input unit 405 and controls the display unit 410. The information processing device 400 can also control an external printer. The functions of the control unit 415 are performed by the CPU executing a program stored in the memory, but may also be performed by a dedicated circuit such as an ASIC.

[0111] Fig. 17 is a diagram illustrating an example of input data to input unit 405. In this example, the same data as input data 180_1 is input to input unit 405, but input data different from this data (for example, data with different operating frequencies or average current consumption values ​​for each function) may be input.

[0112] 16 again, the inference device 300 includes, as its functional configuration, a data acquisition unit 305 and an inference unit 310. Some or all of these functions are performed by the CPU of the inference device 300 executing a program stored in its memory. Some or all of these functions may be performed by a dedicated circuit such as an ASIC, or may be realized by CPU processing of a computer shared with the design support device 70, or by CPU processing of another computer that can communicate with the computer that constitutes the design support device 70. The functions of the inference unit 310 may be performed on the cloud.

[0113] The data acquisition unit 305 acquires input data including function-related information, operating frequency information, and current consumption information from the control unit 415 as input for the trained model 230. This information is, for example, the same as the function-related information 181_k, operating frequency information 182_k, and current consumption information 183_k, respectively (k=1, as an example). The data acquisition unit 305 generates model input data DIN based on the acquired data. The model input data DIN is the same as the acquired data (e.g., input data 180_k), does not include power supply impedance data 190_k, and has the same format as the training data 500_k.

[0114] The inference unit 310 acquires the model input data DIN and reads the trained model 230 from the storage device 100. The inference unit 310 then infers the target impedance of the board under development from the model input data DIN using the trained model 230. Specifically, the inference unit 310 infers the power supply impedance Zp of the confirmed board output from the trained model 230 in accordance with the model input data DIN as the target impedance of the board under development. The inference unit 310 infers the target impedance for each of a plurality of reference frequencies (fa to fe). For example, it infers that the target impedances for these frequencies are Z1a to Z1e (FIG. 12), respectively. The inference unit 310 generates data indicating the inference results of the target impedance as model output data DY.

[0115] The model output data DY indicates a target impedance estimated based on a combination of function-related information, operating frequency information, and current consumption information included in the model input data DIN. The model output data DY indicates the estimation results of the target impedance for multiple reference frequencies (fa to fe) determined by the training data set 550, and is provided to the control unit 415.

[0116] According to the above-described configuration of the inference device 300, the power supply impedance Zp of the confirmed board when multiple functions of the chip 3 are operating is output as the target impedance of the board under development using the trained model 230 in accordance with the input data to the input unit 405. The trained model 230 is a model that has learned the correspondence between the input data 180_k and the power supply impedance Zp of the confirmed board for each value of k when the IC component 1 is mounted on the confirmed board. The input data to the input unit 405 (including function-related information, operating frequency information, and current consumption information) is information that can be easily identified by the designer of the board under development at an early stage of board design. Therefore, simply by inputting the above-described input data to the input unit 405, the designer can easily determine (infer) the target impedance of the board under development. This allows the designer to easily grasp the target impedance of the board under development. Therefore, the design support device 70 can appropriately support the power integrity design of the board under development.

[0117] The power supply impedance calculation unit 99 receives input data (function-related information, operating frequency information, and current consumption information) to the input unit 405 and information about the board under development (wiring information, passive component information, and the value of the power supply voltage VS) from the control unit 415. The power supply impedance calculation unit 99 automatically calculates the power supply impedance Zp of the board under development when multiple functions are operating for each reference frequency based on the current waveform of the current source model 21, structural information about the IC component 1, and information about the board under development. The current waveforms are calculated by the current waveform calculation unit 84 ( FIG. 4 ) based on the function-related information, operating frequency information, and current consumption information. The structural information is input to the structural information input unit 81 ( FIG. 4 ), for example. The calculation result of the power supply impedance Zp of the board under development is provided to the control unit 415. The structural information input unit 81, the current waveform calculation unit 84, the power supply impedance calculation unit 99, and the learning device 200 form an example of a “learning system” of the present disclosure.

[0118] The control unit 415 controls the display unit 410 to display a screen showing the contents of the model output data DY.

[0119] Fig. 18 is a diagram showing an example of a screen displayed on display unit 410. Referring to Fig. 18, points p2a to p2e represent the target impedance of the board under development for fa to fe, respectively. The control unit may control display unit 410 to display, side by side for the designer, the input data (function-related information, operating frequency information, and current consumption information) to input unit 405 and the estimated value of the target impedance indicated by model output data DY.

[0120] 16 again, the control unit 415 compares the power supply impedance Zp of the board under development with the target impedance for each reference frequency. Then, the control unit 415 determines whether the power supply impedance Zp of the board under development is greater than the target impedance for each reference frequency. If the power supply impedance Zp of the board under development is greater than the target impedance, the control unit 415 functions as a notification unit that executes notification processing to notify a user of the design support device 70 (e.g., the designer of the board under development) of specific measures for reducing the power supply impedance Zp of the board under development. The notification processing is, for example, controlling the display unit 410 to display the specific measures, or controlling an external printer to output the specific measures.

[0121] In one example, if the calculated value of the power supply impedance Zp of the board under development is smaller than the inferred value of the target impedance for all reference frequencies, the control unit 415 controls the display unit 410 to display a message indicating "no countermeasures required." If the calculated value of the power supply impedance Zp of the board under development is equal to or greater than the inferred value of the target impedance for at least one reference frequency, the control unit 415 controls the display unit 410 to display the message "countermeasures required" and text or an image indicating a specific proposed countermeasure.

[0122] One example of a proposed solution is to add a decoupling capacitor with appropriate impedance characteristics to the board under development. The impedance characteristics are designed to lower the power supply impedance Zp at frequencies or frequency bands where the calculated value of the power supply impedance Zp of the board under development is greater than the estimated value of the target impedance. Another example of a proposed solution is to modify the wiring pattern of the signal layers 9sa and 9sb of the board under development so that the power supply impedance Zp in the high-frequency range is lowered. For example, by shortening the distance from the power supply terminal of the IC component 1 to the decoupling capacitor or the output terminal of the power supply circuit as much as possible, the effects of the resistance and inductance of the wiring pattern can be reduced.

[0123] According to the above notification process, even if the power supply impedance Zp of the board under development is larger than its target impedance, it is possible to appropriately support the power integrity design so that the power supply impedance Zp of the board under development becomes less than the target impedance.

[0124] 19 is a flowchart showing an example of processing related to inference processing by inference device 300. Referring to Fig. 19, data acquisition unit 305 acquires input data to input unit 405 from control unit 415 (S305). Data acquisition unit 305 generates model input data DIN based on the acquired data (S310).

[0125] The inference unit 310 inputs the model input data DIN to the trained model 230 (S315). This generates the model output data DY. The control unit 415 acquires the model output data DY from the inference unit 310 (S320).

[0126] Fig. 20 is a flowchart showing another example of the processing related to the inference processing by inference device 300. With reference to Fig. 20, S405 to S420 are the same as S305 to S320, respectively, in Fig. 19. Therefore, detailed description will not be repeated.

[0127] The control unit 415 determines whether the power supply impedance Zp of the board under development is smaller than the target impedance for each of the multiple reference frequencies (S425). If the power supply impedance Zp is larger than the target impedance for at least one reference frequency (NO in S425), the control unit 415 controls the display unit 410 to display a message saying "measures required" (S430). The control unit 415 may further execute the notification process described above to display a proposed measure on the display unit 410. If the power supply impedance Zp is smaller than the target impedance for all reference frequencies (YES in S425), the control unit 415 controls the display unit 410 to display a message saying "measures not required" (S435). After S430 and S435, the process ends.

[0128] As described above, according to the embodiment, the power supply impedance Zp of the confirmed board when multiple functions of the chip 3 are operating is output as the target impedance of the board under development in accordance with the input data to the input unit 405 using the trained model 230. The input data consists of information contained in the data sheet of the IC component 1, and is therefore information that can be easily identified by the designer of the board under development at an early stage of board design. Therefore, the design support device 70 can easily determine (infer) the target impedance of this board.

[0129] According to the embodiment, it is possible to easily determine whether the power supply impedance Zp of a board under development is higher than the target impedance. In addition, if the power supply impedance Zp of the board under development is higher than the target impedance, the designer is notified of specific measures to reduce the power supply impedance Zp. This makes it possible to easily support power integrity design so that the power supply impedance Zp of the board under development is less than the target impedance.

[0130] In the embodiment, each of the multiple reference frequencies (fa to fe) is the frequency of the main clock of the chip 3, or a frequency that is a multiple or division of this frequency. The frequency of the main clock may be a frequency specific to an application provided by the chip 3. Therefore, the reference frequency may be important in the development of a board under development as an application-specific frequency or a frequency related to this frequency. Therefore, according to the embodiment, it is possible to easily determine the target impedance of the board under development for each of the application-specific frequency and the frequency related to this frequency. Therefore, the design support device 70 can more appropriately support the design of the power integrity of the board under development.

[0131] In the embodiment, the target impedance of a board under development is easily calculated without complex processing by inputting model input data DIN into the trained model 230 based on input data consisting of information (such as function information, operating frequency information, and current consumption information) that the designer can easily identify in the early stages of board design. To derive the target impedance of a board under development, it is possible to calculate the power supply impedance Zp of a confirmed board each time using circuit simulation, but such simulations require time and effort. In contrast, in the embodiment, the designer simply inputs the above input data into the input unit 405. Therefore, the target impedance can be derived without much time and effort.

[0132] Variant. The information regarding the operation timings of the multiple functions is not limited to information indicating the operation timing or operating frequency of each function. As long as there is information regarding such operation timings that is described in the data sheet of the IC component 1, that information may be used as the "second information" in the present disclosure.

[0133] The information about the current consumption of multiple functions is not limited to information indicating the average current consumption of each function. As long as there is information about such current consumption described in the data sheet of the IC component 1, that information may be used as the "third information" in the present disclosure.

[0134] The power supply impedance Zp of the confirmed board used to create the power supply impedance data 190_k is assumed to be automatically calculated by the power supply impedance calculation unit 99, but may also be determined by experiment.

[0135] The plurality of reference frequencies may be determined for each group, in which case the source impedance Zp and the target impedance are determined for each of the plurality of predetermined frequency bands. [Industrial Applicability]

[0136] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0137] 1 IC component, 2 printed circuit board, 3 chip, 4 on-chip capacitor, 5 bonding wire, 6 package, 7A power terminal, 7B ground terminal, 10 circuit model, 20 IC component model, 30 external information, 70 design support device, 90 power integrity analysis device, 99 power supply impedance calculation unit, 100 storage device, 200 learning device, 205, 305 data acquisition unit, 210 learning dataset generation unit, 215 model generation unit, 230 trained model, 300 inference device, 310 inference unit, 400 information processing device, 405 input unit, 410 display unit, 415 control unit, 500 learning data, 550 learning dataset.

Claims

1. A design support device for supporting power integrity design, comprising: a data acquisition unit that acquires first information representing a plurality of functions of a chip included in an integrated circuit component that can be mounted on a first substrate, second information relating to operation timings of the plurality of functions, and third information relating to current consumption of the plurality of functions; an inference unit that infers a target impedance of the first board as seen from the integrated circuit component mounted on the first board from input data including the first information, the second information, and the third information using a trained model; The trained model is a model in which a correspondence relationship between the input data and impedance data as output data for the input data is trained, the impedance data is data indicating a power supply impedance of a second substrate, different from the first substrate, when the plurality of functions are operating, as viewed from the integrated circuit component mounted on the second substrate, for each of a plurality of predetermined frequencies; The design support device, wherein the inference unit infers the target impedance as the power supply impedance for each of the plurality of frequencies.

2. a current waveform calculation unit that calculates a current waveform of the current source when the chip is modeled as a current source based on the first information, the second information, and the third information; a structural information input unit for receiving input of structural information relating to a power supply wiring structure of the integrated circuit component from the chip to a power supply terminal and a ground terminal of the package of the integrated circuit component; an impedance calculation unit that calculates a power supply impedance of the first substrate when the plurality of functions are operating, as viewed from the integrated circuit component mounted on the first substrate, based on the current waveform, the structural information, and information about the first substrate; 2. The design support device according to claim 1, further comprising: a notification unit that, when the power supply impedance of the first board is larger than the target impedance, notifies of a proposed measure for reducing the power supply impedance of the first board.

3. 2. The design support device according to claim 1, wherein the second information indicates, for each of the plurality of functions, an operation timing or an operation frequency of the function.

4. The design support device according to claim 1 , wherein the third information indicates, for each of the plurality of functions, an average current consumption of the function.

5. 5. The computer aided design device according to claim 4, wherein the average current consumption is determined by multiplying the number of channels of the function by the average current consumption per channel of the function.

6. 2. The design support device according to claim 1, wherein each of the plurality of frequencies is a frequency of a main clock of the chip, or a frequency obtained by multiplying or dividing the frequency of the main clock.

7. each of the first substrate and the second substrate is a multi-layer substrate including a power supply layer and a ground layer; 7. The design support device according to claim 1, wherein the second substrate is a multi-layer substrate used as a reference when designing the first substrate.

8. a dataset generation unit that generates a training dataset including input data including first information, second information, and third information, and impedance data as output data for the input data; a model generation unit that generates a trained model in which a correspondence relationship between the input data and the impedance data is trained using the training data set; the first information is information representing a plurality of functions of a chip of an integrated circuit component that can be mounted on a substrate, the second information is information relating to operation timings of the plurality of functions, the third information is information regarding current consumption of the plurality of functions, A learning device, wherein the impedance data is data that indicates the power supply impedance of the board when the multiple functions are operating, as seen from the integrated circuit components mounted on the board, for each of multiple predetermined frequencies.

9. The learning device according to claim 8 , wherein the second information indicates, for each of the plurality of functions, an operating frequency or an operating timing of the function.

10. The learning device according to claim 8 , wherein the third information indicates, for each of the plurality of functions, an average current consumption of the function.

11. The learning device according to claim 10 , wherein the average current consumption is determined by multiplying the number of channels of the function by the average current consumption per channel of the function.

12. 9. The learning device according to claim 8, wherein each of the plurality of frequencies is a multiple or division of the frequency of a main clock of the chip.

13. A trained model generated by the training device according to any one of claims 8 to 12.

14. A learning device according to any one of claims 8 to 12; a current waveform calculation unit that calculates a current waveform of the current source when the chip is modeled as a current source based on the first information, the second information, and the third information; a structural information input unit for receiving input of structural information relating to a power supply wiring structure of the integrated circuit component from the chip to a power supply terminal and a ground terminal of the package of the integrated circuit component; an impedance calculation unit that calculates the power supply impedance based on the current waveform, the structural information, and information about the substrate.

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