Method of manufacturing trench gate type field effect transistor

Abstract

To suppress residual unnecessary silicon oxide layer in an outer peripheral region when forming an interlayer insulating film.SOLUTION: A method of manufacturing a field effect transistor comprises: a step of preparing a substrate having an upper region, in which no material is filled, above a gate electrode in each gate trench; a step of forming a silicon oxide layer having a first silicon oxide layer positioned on a gate trench region and a second silicon oxide layer positioned on an outer peripheral region and being thicker than the first silicon oxide layer; a step of forming a mask layer having a first mask layer positioned on the gate trench region, a second mask layer positioned on the outer peripheral region and being thicker than the first mask layer, and an opening positioned on the outer peripheral region; and a step of etching the silicon oxide layer through the mask layer.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a trench gate field effect transistor.

[0002] Patent Document 1 discloses a method for manufacturing a trench-gate field-effect transistor. In this manufacturing method, first, a plurality of gate trenches are formed in the main surface of a semiconductor substrate. Next, a gate electrode is formed in each gate trench. At this stage, the region above the gate electrode in each gate trench (hereinafter referred to as the upper region) is not filled with a substance. Next, a silicon oxide layer is formed on the surface of the substrate. At this time, the silicon oxide layer is filled in each upper region. Thereafter, the silicon oxide layer is etched back so that the silicon oxide layer remains in the upper region and the main surface of the semiconductor substrate is exposed. The silicon oxide layer remaining in the gate trench becomes an interlayer insulating film covering the top of the gate electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-111347 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, when a silicon oxide layer is formed, the silicon oxide layer is filled in the gate trench (i.e., the upper region). Therefore, in the gate trench region where multiple gate trenches are provided, the thickness of the silicon oxide layer on the main surface of the semiconductor substrate is thinner than in the peripheral region surrounding the gate trench. Therefore, if the subsequent etch-back process is performed so that the silicon oxide layer remains in the gate trench, an unnecessary silicon oxide layer remains in the region in the peripheral region where the silicon oxide layer should be removed. Therefore, a process for removing the remaining unnecessary silicon oxide layer is required. This specification proposes a technology for preventing the unnecessary silicon oxide layer from remaining in the peripheral region when forming an interlayer insulating film. [Means for solving the problem]

[0005] This specification proposes a method for manufacturing a trench-gate field-effect transistor. The manufacturing method includes a first step, a second step, a third step, and a fourth step. The first step involves preparing a substrate (100) having a semiconductor substrate (12) and a gate electrode (18), the semiconductor substrate having a main surface (12a) including a gate trench region (90) with a plurality of gate trenches (14) formed therein and an outer peripheral region (92) surrounding the gate trench region, the gate electrode being disposed in each of the gate trenches, and an upper region (19) within each of the gate trenches that is not filled with a material above the gate electrode. The second step involves forming a silicon oxide layer (24) on the surface of the substrate. In the second step, the silicon oxide layer (24) is filled in each of the upper regions, and the silicon oxide layer is formed so that it has a first silicon oxide layer (24a) located on the gate trench region and a second silicon oxide layer (24b) located on the peripheral region and thicker than the first silicon oxide layer. In the third step, a mask layer (40) is formed to cover the surface of the silicon oxide layer. In the third step, the mask layer is formed so that it has a first mask layer (41a) located on the gate trench region, a second mask layer (41b) located on the peripheral region and thicker than the first mask layer, and an opening (41c) located on the peripheral region. In the fourth step, the silicon oxide layer is etched through the mask layer. In the fourth step, in the peripheral region, the second mask layer remains and the silicon oxide layer below the opening is removed, and in the gate trench region, the first mask layer is removed, the silicon oxide layer above the main surface is removed, and the silicon oxide layer remains in the upper region.

[0006] In this manufacturing method, in the third step, a thin first mask layer is formed on the gate trench region, and a thick second mask layer and an opening are formed on the peripheral region. Therefore, in the fourth step, the first mask layer is removed in the gate trench region, and then the silicon oxide layer is etched. Furthermore, in the opening, the silicon oxide layer is directly etched. Therefore, in the gate trench region, the silicon oxide layer in the opening can be removed while leaving the silicon oxide layer (i.e., the interlayer insulating film) in the upper region. Thus, according to this manufacturing method, it is possible to prevent unnecessary silicon oxide layer from remaining in the peripheral region when forming the interlayer insulating film. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a field effect transistor 10. FIG. [Figure 2] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 3] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 4] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 5] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 6] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 7] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 8] FIG. 2 is an explanatory diagram of an exposure process according to the first embodiment. [Figure 9] FIG. 2 is a plan view of a photomask used in the first embodiment. [Figure 10] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 11] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 12] FIG. 10 is an explanatory diagram of an exposure process according to the second embodiment. [Figure 13] FIG. 10 is an explanatory diagram of an exposure process according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0008] A field-effect transistor 10 of Example 1 shown in FIG. 1 has a semiconductor substrate 12. In this embodiment, the semiconductor substrate 12 is made of SiC (i.e., silicon carbide). A plurality of gate trenches 14 are provided in an upper surface 12a of the semiconductor substrate 12. Hereinafter, a region of the upper surface 12a of the semiconductor substrate 12 where the plurality of gate trenches 14 are provided will be referred to as a gate trench region 90, and a region around the gate trench region 90 will be referred to as a peripheral region 92. The inner surface of each gate trench 14 is covered with a gate insulating film 16. A gate electrode 18 is provided in each gate trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is covered with an interlayer insulating film 20.

[0009] A source electrode 22 and a silicon oxide layer 24 are provided on the upper surface 12a of the semiconductor substrate 12. The source electrode 22 covers the gate trench region 90. The source electrode 22 is in contact with the upper surface 12a. The source electrode 22 is insulated from the gate electrode 18 by an interlayer insulating film 20. The silicon oxide layer 24 covers the peripheral region 92. A contact hole 25 is provided in the silicon oxide layer 24. An electrode 26 in contact with the semiconductor substrate 12 is provided in the contact hole 25. A drain electrode 28 is provided on the lower surface 12b of the semiconductor substrate 12.

[0010] The semiconductor substrate 12 has a source region 30, a body region 32, a drift region 34, and a drain region 36. The source region 30 is an n-type region and is located in a region sandwiched between the gate trenches 14. The source region 30 is in ohmic contact with the source electrode 22. The source region 30 is in contact with the gate insulating film 16. The body region 32 is a p-type region and is in contact with the source region 30 from below. The body region 32 is in contact with the gate insulating film 16 below the source region 30. The drift region 34 is an n-type region and is in contact with the body region 32 from below. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is in contact with the gate insulating film 16 below the body region 32. The drain region 36 is a highly doped n-type region and is in contact with the drift region 34 from below. The drain region 36 is in ohmic contact with the drain electrode 28.

[0011] The field effect transistor 10 is a trench-gate metal-oxide-semiconductor field effect transistor (MOSFET). When a potential equal to or greater than a threshold is applied to the gate electrode 18, a channel is formed in the body region 32. The channel connects the source region 30 to the drift region 34, allowing current to flow from the drain electrode 28 to the source electrode 22. When the potential of the gate electrode 18 is reduced to a potential below the threshold, the channel disappears and the current stops.

[0012] Next, a description will be given of a method for manufacturing the field effect transistor 10. The field effect transistor 10 is manufactured from a semiconductor substrate 12 shown in Fig. 2. The semiconductor substrate 12 shown in Fig. 2 has a source region 30, a body region 32, a drift region 34, and a drain region 36.

[0013] 3, a plurality of gate trenches 14 are formed by etching in the upper surface 12a of the semiconductor substrate 12. Here, each gate trench 14 is formed so that it penetrates the source region 30 and the body region 32 and reaches the drift region 34.

[0014] 4, a silicon oxide film 16a is formed to cover the upper surface 12a of the semiconductor substrate 12 and the inner surfaces of the gate trenches 14. The silicon oxide film 16a in the gate trenches 14 is the gate insulating film 16.

[0015] Next, as shown in FIG. 5, a gate electrode 18 is formed in each gate trench 14. For example, the gate electrode 18 can be formed by forming a polysilicon layer on the silicon oxide film 16a and then etching back the polysilicon layer to leave the polysilicon layer in each gate trench 14. Herein, the gate electrode 18 is formed so that the upper surface of the gate electrode 18 is located below the upper surface 12a of the semiconductor substrate 12. Hereinafter, the region in the gate trench 14 above the gate electrode 18 will be referred to as an upper region 19. At the stage of FIG. 5, the upper region 19 is not filled with a material. Hereinafter, the semiconductor substrate 12 and the structures (e.g., gate electrodes 18, etc.) provided on its surface will be referred to as a substrate 100.

[0016] Next, as shown in FIG. 6 , a silicon oxide layer 23 is formed on the upper surface of the substrate 100 by CVD (chemical vapor deposition). Here, the silicon oxide layer 23 is formed using silicon oxide with high fluidity, such as BPSG (Boro-phosphosilicate glass) or PSG (Phosphorous Silicate Glass). Therefore, the silicon oxide layer 23 is filled in the upper region 19. That is, the upper region 19 is buried with the silicon oxide layer 23. Above the upper surface 12a of the semiconductor substrate 12 and in the upper region 19, the silicon oxide film 16a and the silicon oxide layer 23 are integrated to form a silicon oxide layer 24. Because the silicon oxide layer 23 is filled in the upper region 19, the thickness of the silicon oxide layer 24 (i.e., the distance between the upper surface of the silicon oxide layer 24 and the upper surface 12a of the semiconductor substrate 12) is thinner above the gate trench region 90 than above the peripheral region 92. Hereinafter, the thin silicon oxide layer 24 on the gate trench region 90 will be referred to as a first silicon oxide layer 24a, and the thick silicon oxide layer 24 on the peripheral region 92 will be referred to as a second silicon oxide layer 24b.

[0017] Next, as shown in FIG. 7, a resist layer 40 is formed on the upper surface of the silicon oxide layer 24.

[0018] Next, as shown in FIG. 8 , light is irradiated onto the upper surface of the resist layer 40 through a photomask 110 and a lens system 120. The photomask 110 is a so-called reticle, and has a pattern including light-transmitting portions 112 and light-shielding portions 114. The light-transmitting portions 112 transmit light, while the light-shielding portions 114 do not transmit light. Light irradiated onto the photomask 110 from above passes through the photomask at the light-transmitting portions 112. The light that has transmitted through the photomask 110 is irradiated onto the surface of the resist layer 40 via the lens system 120. The lens system 120 reduces the pattern of the photomask 110 and projects it onto the upper surface of the resist layer 40.

[0019] As shown in FIGS. 8 and 9 , the photomask 110 has a central portion 110a and an outer peripheral portion 110b. The central portion 110a is a portion that is projected onto the gate trench region 90, and the outer peripheral portion 110b is a portion that is projected onto the outer peripheral region 92. Light-transmitting portions 112a and 112b are provided in the outer peripheral portion 110b. The light-transmitting portion 112a extends in an annular shape along the periphery of the central portion 110a. The light-transmitting portion 112b is provided further outward than the light-transmitting portion 112a. As shown in FIG. 8 , light that has passed through the light-transmitting portions 112a and 112b is irradiated onto the resist layer 40 on the outer peripheral region 92. In the area irradiated with the light that has passed through the light-transmitting portions 112a and 112b, the light is irradiated onto the resist layer 40 with a high irradiation energy density. As a result, the resist layer 40 is altered in this area, forming an exposed portion 40c. An exposed portion 40c-1 is formed in the area corresponding to the light transmitting portion 112a, and an exposed portion 40c-2 is formed in the area corresponding to the light transmitting portion 112b. Furthermore, in the area of ​​the resist layer 40 on the outer circumferential region 92 that is not irradiated with light (i.e., the area where the light blocking portion 114 is imaged), the resist layer 40 is not altered. Hereinafter, the unaltered portion of the resist layer 40 is referred to as the non-exposed portion 40b.

[0020] The central portion 110a of the photomask 110 is provided with slit-shaped light-transmitting portions 112c. The light-transmitting portions 112c extend in a lattice pattern. The width of the slit-shaped light-transmitting portions 112c is smaller than the wavelength of the irradiated light. Therefore, the light transmitted through the light-transmitting portions 112c is not focused by the lens system 120, but is dispersed and irradiated onto the entire resist layer 40 on the gate trench region 90. As a result, the entire resist layer 40 on the gate trench region 90 is irradiated with light at a low irradiation energy density. As a result, the resist layer 40 on the gate trench region 90 is altered to a low level, forming intermediately exposed portions 40a. In other words, the intermediately exposed portions 40a are portions irradiated with light at a lower irradiation energy density than the exposed portions 40c.

[0021] Next, a developer is applied to the resist layer 40, thereby patterning the resist layer 40 as shown in FIG. 10. The exposed portion 40c is removed by the developer, forming an opening 41c in the resist layer 40. An opening 41c-1 is formed in the area corresponding to the exposed portion 40c-1, and an opening 41c-2 is formed in the area corresponding to the exposed portion 40c-2. The intermediately exposed portion 40a reacts with the developer and reduces in thickness, becoming a thin first mask layer 41a. The unexposed portion 40b is barely removed by the developer. Therefore, the unexposed portion 40b becomes a second mask layer 41b that is thicker than the first mask layer 41a. As shown in FIG. 10, the first mask layer 41a covers the first silicon oxide layer 24a in the gate trench region 90. The second mask layer 41b covers the second silicon oxide layer 24b in the peripheral region 92. The openings 41c-1 and 41c-2 are located on the outer peripheral region 92.

[0022] Next, the silicon oxide layer 24 is etched from above through the resist layer 40. For example, the silicon oxide layer 24 is etched by reactive ion etching. The mask layer is also etched during the etching process. The mask layer is etched at a slower rate than the silicon oxide layer 24. In the gate trench region 90, the first mask layer 41a is etched from above, and once the first mask layer 41a is removed, the underlying first silicon oxide layer 24a is etched. Here, as shown in FIG. 11 , the silicon oxide layer 24 is etched until the top surface 12a of the semiconductor substrate 12 is exposed in the gate trench region 90. The etching process is terminated with the silicon oxide layer 24 remaining in the upper region 19. The silicon oxide layer 24 remaining in the upper region 19 becomes the interlayer insulating film 20.

[0023] Furthermore, during the etching process, the second silicon oxide layer 24b exposed in the openings 41c-1 and 41c-2 is etched. Because the second silicon oxide layer 24b is exposed in the openings 41c-1 and 41c-2, the second silicon oxide layer 24b is etched at a fast rate from the start of etching. During the etching process, the second silicon oxide layer 24b below the openings 41c-1 and 41c-2 is removed. As a result, the upper surface 12a of the semiconductor substrate 12 is exposed in the openings 41c-1 and 41c-2.

[0024] In the etching process, only the surface layer of the thick second mask layer 41b provided in the outer peripheral region 92 is etched. When the etching is completed, the second mask layer 41b remains. Therefore, the second silicon oxide layer 24b remains below the second mask layer 41b.

[0025] Next, the remaining resist layer 40 is removed. Next, as shown in FIG.

[0026] As described above, according to this embodiment, even if the silicon oxide layer 24 below the openings 41c-1 and 41c-2 is thicker than the silicon oxide layer 24 in the gate trench region 90 before the etching step, the silicon oxide layer 24 below the openings 41c-1 and 41c-2 can be removed in the etching step. Therefore, the silicon oxide layer 24 below the openings 41c-1 and 41c-2 can be removed while leaving the silicon oxide layer 24 in the gate trench 14 (i.e., in the upper region 19). This manufacturing method prevents the silicon oxide layer 24 from remaining below the openings 41c-1 and 41c-2. Therefore, an etching step for removing the remaining unnecessary silicon oxide layer is not required, and the field-effect transistor 10 can be manufactured efficiently. [Example]

[0027] In the manufacturing method of Example 2, the exposure step is different from that of Example 1, but the other steps are the same as those of Example 1. FIG. 12 shows the exposure step of Example 2. In Example 2, a halftone portion 118 is provided in the center of a photomask 110. The light transmittance of the halftone portion 118 is lower than that of the light-transmitting portion 112 and higher than that of the light-shielding portion 114. The halftone portion 118 is provided over the entire central portion 110a of the photomask 110. In Example 2, light passes through the halftone portion 118 in the central portion 110a. The intensity of the light decreases when passing through the halftone portion 118. Therefore, the resist layer 40 on the gate trench region 90 is irradiated with light at a low irradiation energy density. As a result, an intermediate exposure portion 40a is formed in the resist layer 40 on the gate trench region 90. Therefore, in Example 2, as in Example 1, a field-effect transistor 10 can be efficiently manufactured while preventing unnecessary silicon oxide layers from remaining. [Example]

[0028] In the manufacturing method of Example 3, the arrangement of the half-tone portions 118 differs from that of Example 2, but the other configurations are the same as those of Example 2. FIG. 13 shows an exposure process of Example 3. In Example 3, half-tone portions 118 and light-transmitting portions 112d are alternately provided in a central portion 110a of a photomask 110. Light transmitted through the half-tone portions 118 is irradiated onto the resist layer 40 above each gate trench 14. As a result, intermediately exposed portions 40a are formed above each gate trench 14. Light transmitted through the light-transmitting portions 112d is irradiated onto the resist layer 40 above the region between each gate trench 14 (hereinafter referred to as the inter-trench region). As a result, exposed portions 40c are formed above the inter-trench region in Example 3. In this way, since the exposed portions 40c are formed above the inter-trench region, openings are formed above the inter-trench region in the subsequent development process. As a result, in the etching process, the silicon oxide layer 24 above the inter-trench region is directly etched. Therefore, the silicon oxide layer 24 on the inter-trench region can be removed more reliably.

[0029] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A method for manufacturing a trench gate field effect transistor, comprising: preparing a substrate having a semiconductor substrate and a gate electrode, the substrate having a main surface including a gate trench region in which a plurality of gate trenches are provided and an outer peripheral region arranged around the gate trench region, the gate electrode being arranged in each of the gate trenches, and an upper region in each of the gate trenches that is not filled with a material being provided above the gate electrode; forming a silicon oxide layer on the surface of the substrate, the silicon oxide layer filling each of the upper regions, the silicon oxide layer having a first silicon oxide layer located on the gate trench region and a second silicon oxide layer located on the periphery region and thicker than the first silicon oxide layer; forming a mask layer covering a surface of the silicon oxide layer, the mask layer having a first mask layer located on the gate trench region, a second mask layer located on the outer periphery region and thicker than the first mask layer, and an opening located on the outer periphery region; a step of etching the silicon oxide layer through the mask layer, wherein in the outer periphery region, the second mask layer remains and the silicon oxide layer under the opening is removed, and in the gate trench region, the first mask layer is removed, the silicon oxide layer above the main surface is removed, and the silicon oxide layer remains in the upper region; A manufacturing method comprising the steps of: (Configuration 2) the step of forming the mask layer comprises: forming a resist layer on the surface of the silicon oxide layer; irradiating the resist layer with light so as to form an exposed portion, a non-exposed portion, and an intermediate exposed portion irradiated with light at an irradiation energy density lower than that of the exposed portion; developing the resist layer, wherein the exposed portions become the openings, the intermediate exposed portions become the first mask layer, and the unexposed portions become the second mask layer; having The manufacturing method according to configuration 1. (Configuration 3) In the step of irradiating light, a photomask pattern having a light-transmitting portion and a light-shielding portion is projected onto the resist layer; a portion of the pattern that is projected onto the gate trench region has the light transmitting portion that has a width narrower than the wavelength of light irradiated onto the resist layer; The manufacturing method according to configuration 2. (Configuration 4) In the step of irradiating light, a photomask pattern having a light-transmitting portion, a light-shielding portion, and a halftone portion having a light transmittance between the light-transmitting portion and the light-shielding portion is projected onto the resist layer; a portion of the pattern that is projected onto the gate trench region has the half-tone portion; The manufacturing method according to configuration 2. (Configuration 5) 5. The manufacturing method according to configuration 4, wherein the pattern has the light-transmitting portion at a position corresponding to a region between the gate trenches.

[0030] According to the above-mentioned configuration 2, the non-exposed portions become the second mask layer (i.e., the thick portions of the mask layer), the exposed portions (i.e., the portions exposed by light with a high irradiation energy density) become the openings, and the intermediately exposed portions (i.e., the portions exposed by light with a relatively low irradiation energy density) become the first mask layer (i.e., the thin portions of the mask layer). According to this configuration, the first mask layer and the second mask layer can be formed simultaneously. Note that the irradiation energy (J / cm 2 ) is the light irradiation intensity (W / cm 2 ) and the irradiation time (sec).

[0031] According to the above-mentioned configuration 3, since the light transmitted through the light-transmitting portion having a width narrower than the wavelength is not imaged on the resist layer, the light transmitted through this light-transmitting portion is dispersed and irradiated onto the gate trench region, which allows the resist layer on the gate trench region to be irradiated with light at a relatively low irradiation energy density, thereby enabling the first mask layer to be suitably formed.

[0032] According to the above configuration 4, the gate trench region is irradiated with light that has passed through the halftone portion (that is, light with a relatively low irradiation energy density), so that the first mask layer can be suitably formed.

[0033] According to the fifth aspect, openings can be formed in the mask layer above the regions between the gate trenches, so that the silicon oxide layer can be more reliably removed from the regions between the gate trenches during etching.

[0034] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0035] 12: semiconductor substrate, 14: gate trench, 18: gate electrode, 19: upper region, 24: silicon oxide layer, 40: resist layer, 40a: intermediate exposed portion, 40b: non-exposed portion, 40c: exposed portion, 41a: first mask layer, 41b: second mask layer, 41c: opening, 90: gate trench region, 92: outer peripheral region, 110: photomask

Claims

1. A method for manufacturing a trench gate field effect transistor, comprising: a substrate (100) having a semiconductor substrate (12) and a gate electrode (18), the substrate having a main surface (12a) having a gate trench region (90) in which a plurality of gate trenches (14) are provided and an outer periphery region (92) arranged around the gate trench region, the gate electrode being arranged in each of the gate trenches, and an upper region (19) being provided in each of the gate trenches above the gate electrode and not filled with a material; forming a silicon oxide layer (24) on the surface of the substrate, the silicon oxide layer (24) filling each of the upper regions, the silicon oxide layer having a first silicon oxide layer (24a) located on the gate trench region and a second silicon oxide layer (24b) located on the outer periphery region and thicker than the first silicon oxide layer; a step of forming a mask layer (40) covering a surface of the silicon oxide layer, the mask layer being formed so as to have a first mask layer (41a) located on the gate trench region, a second mask layer (41b) located on the outer periphery region and thicker than the first mask layer, and an opening (41c) located on the outer periphery region; a step of etching the silicon oxide layer through the mask layer, wherein in the outer periphery region, the second mask layer remains and the silicon oxide layer under the opening is removed, and in the gate trench region, the first mask layer is removed, the silicon oxide layer above the main surface is removed, and the silicon oxide layer remains in the upper region; A manufacturing method comprising the steps of:

2. the step of forming the mask layer comprises: forming a resist layer (40) on the surface of the silicon oxide layer; a step of irradiating the resist layer with light so as to form an exposed portion (40c), a non-exposed portion (40b), and an intermediate exposed portion (40a) irradiated with light at an irradiation energy density lower than that of the exposed portion; developing the resist layer, wherein the exposed portions become the openings, the intermediate exposed portions become the first mask layer, and the unexposed portions become the second mask layer; having The method of claim 1.

3. In the step of irradiating light, a pattern of a photomask (110) having a light-transmitting portion (112) and a light-shielding portion (114) is projected onto the resist layer; a portion of the pattern projected onto the gate trench region has the light transmitting portion (112c) having a width narrower than the wavelength of light irradiated onto the resist layer; The method of claim 2.

4. In the step of irradiating light, a pattern of a photomask (110) having a light-transmitting portion (112), a light-shielding portion (114), and a halftone portion (118) having a light transmittance between the light-transmitting portion and the light-shielding portion is projected onto the resist layer; a portion of the pattern that is projected onto the gate trench region has the half-tone portion; The method of claim 2.

5. The manufacturing method according to claim 4, wherein the pattern has the light transmitting portion (112d) at a position corresponding to a region between the gate trenches.

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