Method of manufacturing wiring board

Abstract

To provide a high-quality wiring board in which variance in diameters in a plurality of via conductors, which should have the same diameter, is relatively small.SOLUTION: A method of manufacturing a wiring board includes: forming a resin insulation layer 11; forming a plurality of through holes by irradiating the resin insulation layer 11 with a laser beam; etching a surface of the resin insulation layer 11 and inner wall surfaces of the plurality of through holes; and forming via conductors 13 by filling the inner sides of the plurality of through holes 13b with conductors. The formation of the plurality of through holes includes setting a ratio of a diameter of a through hole having the smallest diameter in the plurality of through holes with respect to a diameter of a through hole having the largest diameter to 60% or more to 85% or less. The etching of the inner wall surface includes making the ratio of the diameter of a through hole 13a having the smallest diameter in the plurality of through holes with respect to the diameter of a through hole 13b having the largest diameter larger than a ratio before dry etching by 5% or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a wiring board. In the method for manufacturing a wiring board disclosed in Patent Document 1, a plurality of via formation holes penetrating an insulating layer are formed by irradiating an insulating layer with laser light. Via conductors are formed in the via formation holes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-58472 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method of manufacturing a wiring board disclosed in Patent Document 1, it is thought that there may be cases where the dimensional variations of the formed via conductors are relatively large. [Means for solving the problem]

[0005] A method for manufacturing a wiring board of the present invention includes forming a resin insulating layer, irradiating the resin insulating layer with laser light to form a plurality of through holes, etching the surface of the resin insulating layer and the inner wall surfaces of the plurality of through holes, and filling the plurality of through holes with a conductor to form via conductors. Forming the plurality of through holes includes setting a ratio of the diameter of the smallest through hole among the plurality of through holes to the diameter of the largest through hole among the plurality of through holes to be 60% or more and 85% or less, and etching the inner wall surfaces includes using dry etching to increase the ratio of the diameter of the smallest through hole among the plurality of through holes to the diameter of the largest through hole among the plurality of through holes by 5% or more compared to the ratio before the dry etching.

[0006] According to the embodiment of the present invention, a high-quality wiring board can be provided in which the variation in diameter among a plurality of via conductors that should have the same diameter is relatively small. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing an example of a wiring board manufactured by a method according to an embodiment of the present invention. [Figure 2A] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2B] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2C] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2D] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2E] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2F] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2G] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2H] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Next, a method for manufacturing a wiring board according to one embodiment of the present invention will be described with reference to the drawings. The drawings are not intended to accurately represent the proportions of the components, but are instead drawn to facilitate understanding of the features of the present invention. FIG. 1 partially illustrates a cross section of a wiring board 1, an example of a wiring board manufactured by the manufacturing method according to an embodiment. The wiring board 1 is formed of alternating insulating layers and conductor layers, and FIG. 1 illustrates a portion of the wiring board 1, including a resin insulating layer 11 and a conductor layer 12. One side of the illustrated wiring board 1 is formed as a component mounting surface F on which external electronic components, such as semiconductor devices, are mounted. In the following description, the side of each element constituting the wiring board 1 on which the component mounting surface F of the wiring board 1 is formed will be referred to as the "top," "upper side," "outside," or simply "outside." The component mounting surface F of the wiring board 1 shown in FIG. 1 is composed of a coating insulating layer 10 and the surface of bumps 14 that fill openings 10a in the coating insulating layer 10 and protrude from the coating insulating layer 10.

[0009] 1 shows three layers on the component mounting surface F side of the multiple resin insulating layers 11 and conductor layers 12 that the wiring board 1 has. The wiring board 1 has one or more resin insulating layers 11 and one or more conductor layers 12, and the number of resin insulating layers 11 and conductor layers 12 that the wiring board 1 has is not particularly limited and can be increased or decreased as appropriate.

[0010] The resin insulation layer 11 includes a plurality of via conductors 13 that have the same diameter by design. In the illustrated example, the two via conductors 13 formed in the uppermost resin insulation layer 11 of the three resin insulation layers 11 are the plurality of via conductors 13 that have the same diameter by design. The resin insulation layer 11 is not limited to the configuration illustrated in FIG. 1 . For example, the resin insulation layer 11 may include three or more via conductors 13. Furthermore, the resin insulation layer 11 that includes a plurality of via conductors 13 that have the same diameter by design may be any resin insulation layer 11. The resin insulation layer 11 may include via conductors 13 that have different diameters by design.

[0011] The conductor layer 12 has an arbitrary conductor pattern and is in contact with the resin insulating layer 11. The conductor layer 12 is electrically connected to the conductor layer 12 on the opposite side of the resin insulating layer 11 through the via conductors 13 formed in the resin insulating layer 11. In the illustrated example, each conductor layer 12 is formed integrally with the via conductors 13 below the conductor layer 12.

[0012] The uppermost conductor layer 12 may include component mounting pads 12a. The component mounting pads 12a are electrically connected to electrodes of external electronic components such as semiconductor elements via bumps 14 formed thereon.

[0013] The conductor layer 12 is formed using any material having suitable conductivity, such as copper or nickel. The configuration of the conductor layer 12 is not limited to the two-layer structure illustrated in FIG. 1. For example, the conductor layer 12 may be formed of a three-layer structure including a metal foil, an electroless plated film layer, and an electrolytic plated film layer, or a multi-layer structure of four or more layers. The conductor layer 12 may also have a single-layer structure consisting of an electroless plated film layer or an electrolytic plated film layer.

[0014] The via conductor 13 is formed in the through hole 13b of the resin insulating layer 11. In the illustrated example, the via conductor 13 has a tapered shape that decreases in diameter from the component mounting surface F toward the opposite side. The configuration of the via conductor 13 is not limited to the shape exemplified in FIG. 1. For example, the via conductor 13 may have a shape that decreases in diameter toward the component mounting surface F, or may be formed in a cylindrical shape that has the same diameter in the thickness direction of the resin insulating layer 11 and is approximately perpendicular to the conductor layer 12. Although the term "decreasing diameter" is used for convenience, the opening shape of the via conductor 13 is not necessarily limited to a circle. "Decreasing diameter" simply means that the distance between the longest two points on the periphery of the via conductor 13 in a horizontal cross section becomes smaller.

[0015] Among multiple via conductors 13 that are designed to have the same diameter, the ratio of the diameter of the via conductor 13 with the smallest diameter to the diameter of the via conductor 13 with the largest diameter is 65% or more. The "diameter" of a via conductor 13 refers to the distance between the longest two points on the circumference of the via conductor 13 in a horizontal cross section. In the illustrated example, the diameter of the via conductor 13 is longest at the connection portion between the via conductor 13 and the upper conductor layer 12. The diameter of the via conductor 13 is equal to the diameter of the through hole 13b.

[0016] When the diameters of two via conductors 13 are compared, the diameters of the two via conductors 13 at the same position in the thickness direction (Z direction) of the wiring board 1 are compared. That is, the diameter of one via conductor 13 is compared with the diameter of the other via conductor 13 at a specific distance (height) in the Z direction from the surface of the conductor layer 12. The height from the surface of the conductor layer 12 at which the diameters to be compared are located is selected arbitrarily. For example, the diameters to be compared may be the diameters of the via conductors 13 at the connection surface between the via conductor 13 and the upper conductor layer 12 (the upper surface of the via conductor 13). Alternatively, the diameters to be compared may be the diameters of the via conductors 13 at the connection surface between the via conductor 13 and the lower conductor layer 12 (the lower surface of the via conductor 13).

[0017] The bumps 14 are formed so as to cover the surfaces of the component mounting pads 12a, and the bumps 14 fill the openings 10a in the insulating covering layer 10 and protrude outward from the insulating covering layer 10. The bumps 14 are formed using any material having suitable electrical conductivity.

[0018] The covering insulating layer 10 covers the edges of the component mounting pads 12a, the sidewall surfaces of the bumps 14 formed on the component mounting pads 12a, and the resin insulating layer 11 exposed between the component mounting pads 12a. The covering insulating layer 10 is formed using any insulating resin material such as epoxy resin or polyimide resin.

[0019] 2A to 2H, a method for manufacturing a wiring board according to an embodiment will be described below using the wiring board 1 shown in Fig. 1 as an example. Similar to Fig. 1, Figs. 2A to 2H do not show the entire wiring board 1, but only show a partial cross section of the component mounting surface F side of the wiring board 1.

[0020] First, resin insulating layers 11 and conductor layers 12 are formed by a general wiring board manufacturing method, for example, using a build-up method. As shown in Fig. 2A, a wiring board 1p is prepared in which lamination of the uppermost resin insulating layer 11 has been completed. Fig. 2A shows a wiring board 1p in which three resin insulating layers 11 and two conductor layers 12 are laminated using a build-up method.

[0021] The resin insulating layer 11 is formed using any insulating resin material. Examples of resin insulating layer 11 that can be used include epoxy resin, polyimide resin, BT resin (bismaleimide-triazine resin), polyphenylene ether resin, and phenolic resin. The resin insulating layer 11 may contain an inorganic filler. Examples of inorganic fillers that can be used include silica and alumina. In the wiring board 1p illustrated in FIG. 2A, the resin insulating layer 11 does not contain a core material, but may contain a core material such as glass fiber or aramid fiber as necessary. The inclusion of a core material improves the strength of the wiring board 1. The multiple resin insulating layers 11 may be made of different materials, or all may be made of the same material.

[0022] Next, as shown in FIG. 2B, a protective film 15 is preferably formed on the uppermost resin insulating layer 11. The protective film 15 completely covers the surface of the uppermost resin insulating layer 11. For example, a polyethylene terephthalate (PET) film may be used as the protective film 15. A release agent may be formed between the protective film 15 and the resin insulating layer 11.

[0023] Next, as shown in FIG. 2C , a plurality of through holes 13 a are formed from the surface of the protective film 15 at positions corresponding to the formation locations of the via conductors 13 (see FIG. 2G ) in the uppermost resin insulating layer 11. For example, by irradiation with ultraviolet laser light, the through holes 13 a are formed in the protective film 15 and the resin insulating layer 11. By forming the through holes 13 a, the underlying conductor layer 12 is exposed in the through holes 13 a. The through holes 13 a are used to form the through holes 13 b (see FIG. 2E ) filled with the via conductors 13. For example, YAG laser light is used as the ultraviolet laser light. The through holes 13 a are formed to be smaller than the diameter of the via conductors 13 in the design. Irradiation with ultraviolet laser light having a short wavelength makes it easy to form small-diameter through holes 13 a. In the through holes 13 a illustrated in FIG. 2C , the through holes 13 a are formed so that their diameters decrease from the protective film 15 side toward the conductor layer 12 side, but the shape of the through holes 13 a is not limited thereto. The resin insulating layer 11 may be formed in a cylindrical shape with the same diameter in the thickness direction thereof.

[0024] It is believed that a portion of the inorganic filler (not shown) contained in the resin insulating layer 11 is exposed on the inner wall surface of the through hole 13a. In the resin insulating layer 11 in which a plurality of through holes 13a are formed, if the dispersion state of the inorganic filler becomes uneven, the diameters of the through holes 13a may vary. In the illustrated example, the through holes 13a having the smallest diameter dimension A0 and the through holes 13a having the largest diameter dimension B0 are formed.

[0025] In the manufacturing method of the embodiment, through holes 13a are formed so that the ratio (A0 / B0) of the diameter A0 of the smallest through hole 13a among the plurality of through holes 13a to the diameter B0 of the largest through hole 13a among the plurality of through holes 13a is 60% or more and 85% or less. If the ratio (A0 / B0) is 60% or more and 85% or less, by etching through holes 13a, through holes 13b (see FIG. 2E) filled with via conductors 13 can be formed to have a diameter substantially the same as the designed diameter with relatively small variation.

[0026] When the diameters of two through holes 13a (or through holes 13b) are compared, the diameters of the two through holes 13a (or through holes 13b) at the same position in the thickness direction (Z direction) of the resin insulating layer 11 are compared. That is, the diameter of one through hole 13a (or through holes 13b) and the diameter of the other through hole 13a (or through holes 13b) at a specific distance (height) in the Z direction from the surface of the conductor layer 12 are compared. The height from the surface of the conductor layer 12 at which the diameters to be compared are located is selected arbitrarily. For example, the diameters to be compared may be the opening diameter of the through hole 13a (or through holes 13b) on the upper surface of the resin insulating layer 11. Alternatively, the diameters to be compared may be the opening diameter of the through hole 13a (or through holes 13b) on the surface of the conductor layer 12.

[0027] 2D, protective film 15 is removed, and the surface of uppermost resin insulating layer 11 and the inner wall surfaces of through holes 13a are etched. The surface of uppermost resin insulating layer 11 and the inner wall surfaces of through holes 13a are dry-etched by, for example, plasma etching.

[0028] Plasma etching selectively removes silica or alumina contained as an inorganic filler in resin insulating layer 11. Selective removal of the inorganic filler involves an etching rate for the inorganic filler that is higher than an etching rate for the insulating resin that constitutes resin insulating layer 11.

[0029] 2E, through holes 13b having a diameter larger than that of through holes 13a are formed by etching. In the illustrated example, through holes 13b having a smallest diameter A1 and a largest diameter B1 are formed. Through holes 13b are filled with via conductors. The difference between the smallest diameter A1 of the plurality of through holes 13b obtained by etching and the smallest diameter A0 of the plurality of through holes (through holes 13a) before etching may be larger than the difference between the largest diameter B1 of the plurality of through holes 13b obtained by etching and the largest diameter B0 of the plurality of through holes 13a before etching. In other words, the diameters of the plurality of through holes (through holes 13a) before etching may be enlarged by etching to satisfy the relationship (A1-A0)>(B1-B0), thereby forming the plurality of through holes (through holes 13b) after etching. In other words, etching may be performed so that the expansion amount (length) of the diameter of the through hole having the smallest diameter A0 among the plurality of through holes 13a before etching is greater (longer) than the expansion amount (length) of the diameter of the through hole having the largest diameter B0 among the plurality of through holes 13a after etching. Therefore, the difference between the diameter of the through holes 13a having a predetermined diameter before and after etching may be greater than the difference between the diameter of the through holes 13a having a diameter larger than the predetermined diameter before and after etching. By such etching, the difference between the largest diameter B1 and the smallest diameter A1 of the plurality of through holes 13b after etching can be made smaller than the difference between the largest diameter B0 and the smallest diameter A0 among the plurality of through holes 13a before etching.

[0030] In the manufacturing method of the embodiment, for example, by performing etching as described above, through holes 13b are formed so that the ratio (A1 / B1) of the diameter A1 of the smallest through hole 13b to the diameter B1 of the largest through hole 13b among the plurality of through holes 13b is 5% or more larger than the ratio (A0 / B0) before etching. If the ratio (A1 / B1) is 5% or more larger than the ratio (A0 / B0) before etching, the variation in the diameter of via conductors 13 may be reduced to within the required tolerance. As a result, it may be possible to form a plurality of via conductors 13 each having approximately the same diameter as the design diameter.

[0031] The diameter of the largest through hole 13b among the plurality of through holes 13b is preferably 12.5 μm or less. When through holes 13b with a diameter of 12.5 μm or less are formed, there is a significant effect of reducing the variation in the diameters of through holes 13b.

[0032] In order to form through-holes 13b having substantially the same diameter as the designed diameter, the etching conditions are controlled, such as the type and concentration of etching gas, temperature, time, pressure, and applied voltage.

[0033] Next, as shown in FIG. 2F, a metal film layer 121 is formed on the uppermost resin insulating layer 11 and the surface of the inner wall of the through hole 13b. The metal film layer 121 is formed by electroless plating, sputtering, or the like. The metal film layer 121 is, for example, an electroless copper plating film layer. A plating resist 16 having an opening 16a at a position corresponding to the formation location of the component mounting pad 12a (see FIG. 2G) is formed on the metal film layer 121. The plating resist 16 is formed by forming a resin layer containing, for example, a photosensitive polyhydroxyether resin, epoxy resin, phenolic resin, or polyimide resin, and then exposing and developing the resin layer using a mask with an appropriate opening pattern. An electrolytic plating film layer 122 is formed by electrolytic plating using the metal film layer 121 as a seed layer. The electrolytic plating film layer 122 fills the inside of the through hole 13b of the resin insulating layer 11 and the inside of the opening 16a of the plating resist 16.

[0034] 2G, after plating resist 16 is removed, exposed metal film layer 121 is removed by etching to expose resin insulating film 11. As shown in the figure, the inside of through hole 13b is completely filled with a conductor composed of metal film layer 121 and electroplated film layer 122, and via conductor 13 is formed.

[0035] In the manufacturing method of this embodiment, the diameter of the via conductors 13 is equal to the diameter of the through holes 13b. The via conductors 13 are formed so that the ratio of the diameter of the via conductor 13 having the smallest diameter among the plurality of via conductors 13 to the diameter of the via conductor 13 having the largest diameter among the plurality of via conductors 13 is 65% or more. As a result, the plurality of via conductors 13, which are intended to have the same diameter in terms of design, can be formed with small variation in diameter.

[0036] The via conductors 13 and the component mounting pads 12a may be formed using any material with suitable conductivity, such as copper or nickel. The via conductors 13 and the component mounting pads 12a are not limited to the two-layer structure shown in the figure. For example, they may be configured with a three-layer structure of copper foil, an electroless copper plating film layer, and an electrolytic copper plating film layer. Alternatively, they may be configured with a single layer structure of an electroless copper plating film layer or an electrolytic copper plating film layer.

[0037] 2H, a coated insulating film 10 is formed on the uppermost resin insulating film 11. For example, by irradiation with UV laser light, openings 10a are formed through the coated insulating layer 10 to expose the surfaces of the component mounting pads 12a. The coated insulating film 10 is made of an insulating resin containing, for example, a photosensitive epoxy resin or a polyimide resin.

[0038] Bumps 14 are formed in the openings 10a. The bumps 14 are formed, for example, by mounting solder balls or by electroless plating. The bumps 14 may be shaped to be electrically connected to connection pads on external electronic components. By going through the above steps, the formation of the wiring substrate 1 is completed.

[0039] In the manufacturing method of this embodiment, the variation in dimensions of a plurality of via conductors, which are intended to have the same diameter in design, is relatively small, and a high-quality wiring board is formed.

[0040] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to the drawings, and the conditions, order, etc. may be changed as appropriate. Depending on the structure of the wiring board to be manufactured, some steps may be omitted, and other steps may be added. [Explanation of symbols]

[0041] 1. Wiring board 11 Resin insulation layer 12 Conductor layer 12a Component mounting pad 121 Metal film layer 122 Electroplated film layer 13 Via conductor 13a, 13b through hole 15 Protective film 16 Plating resist 16a aperture

Claims

1. forming a resin insulating layer; forming a plurality of through holes by irradiating the resin insulating layer with laser light; etching a surface of the resin insulating layer and inner wall surfaces of the plurality of through holes; filling the through holes with a conductor to form via conductors; A method for manufacturing a wiring substrate, comprising: forming the plurality of through holes includes making a ratio of a diameter of a through hole having a smallest diameter among the plurality of through holes to a diameter of a through hole having a largest diameter among the plurality of through holes to be 60% or more and 85% or less; Etching the inner wall surface includes dry etching such that the ratio of the diameter of the smallest through hole among the plurality of through holes to the diameter of the largest through hole among the plurality of through holes is 5% or more larger than the ratio before the dry etching.

2. 2. The method for manufacturing a wiring board according to claim 1, wherein the diameter of the largest through hole among the plurality of through holes after the etching is 12.5 [mu]m or less.

3. 2. The method for manufacturing a wiring board according to claim 1, wherein the resin insulating layer contains a filler.

4. 2. The method for manufacturing a wiring board according to claim 1, wherein the laser light is an ultraviolet laser light.

5. 2. The method for manufacturing a wiring board according to claim 1, wherein the dry etching includes a plasma treatment.

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