Method for manufacturing wiring board

Abstract

To improve a yield in manufacture of a wiring board.SOLUTION: A method for manufacturing a wiring board includes forming a first build-up part 10 including a first conductor layer 12 on a support substrate SP including one or a plurality of product areas. Each product area has a rectangular shape with a dimension of each side of 80 mm or more and 240 mm or less in plan view, the lamination of the first conductor layer 12 includes forming a first resist layer RL1 having a first resist pattern and forming a conductor pattern following the first resist pattern, the lamination of the first conductor layer 12 includes forming the conductor pattern so that a minimum value of a width of wiring included in the conductor pattern is 2 μm or less, and a minimum value of an interval of the wiring is 2 μm or less, and the formation of the first resist layer RL1 having the first resist pattern includes exposing the first resist layer RL1 by direct imaging exposure.SELECTED DRAWING: Figure 3E

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a wiring board including a second wiring board and a first wiring board. The first wiring board is formed by laminating an insulating resin and a wiring layer on a support substrate. The second wiring board is manufactured separately from the first wiring board, and the first wiring board and the second wiring board are joined together. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-4926 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, a first wiring board and a second wiring board, in which a relatively fine wiring layer is formed in a wiring pattern conforming to a resist pattern, must be joined via bumps, and an insulating resin must be filled between the first wiring board and the second wiring board. Furthermore, the formation of the first wiring board includes forming the wiring layer on the insulating resin layer by filling openings in the resist pattern with a conductor. This may result in a low yield in the manufacturing of wiring boards. [Means for solving the problem]

[0005] A method for manufacturing a wiring board of the present invention includes forming a first buildup portion by alternately laminating first conductor layers and first insulating layers across one or more product areas on a support substrate having the one or more product areas, wherein each of the product areas has a rectangular shape with each side measuring 80 mm or more and 240 mm or less in a plan view, laminating the first conductor layers includes forming a first resist layer having a first resist pattern and forming a conductor pattern according to the first resist pattern, laminating the first conductor layers includes forming the conductor pattern so that the minimum width of wiring included in the conductor pattern is 2 μm or less and the minimum spacing between wiring is 2 μm or less, and forming the first resist layer having the first resist pattern includes exposing the first resist layer by direct imaging exposure.

[0006] According to the embodiment of the present invention, wiring substrates including a plurality of conductor layers with different wiring densities can be provided with a high yield. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing an example of a wiring substrate manufactured by a manufacturing method according to an embodiment of the present invention. [Figure 2] 10 is a cross-sectional view showing another example of a wiring board manufactured by the manufacturing method according to the embodiment of the present invention. [Figure 3A] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3B] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3C] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3D] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3E] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3F] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3G]1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3H] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3I] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3J] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3K] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3L] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3M] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3N] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3O] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3P] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3Q] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3R] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0008] A wiring board manufactured by a wiring board manufacturing method according to an embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing wiring board 1, which is an example of a wiring board manufactured by a manufacturing method according to an embodiment. Note that wiring board 1 is merely one example of a manufactured wiring board. The layered structure of the manufactured wiring board and the number of conductor layers and insulating layers are not limited to the layered structure of wiring board 1 shown in FIG. 1 and the number of conductor layers and insulating layers included in wiring board 1. Furthermore, the referenced drawings are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention.

[0009] The wiring board 1 has a layered structure including a first buildup section 10 composed of multiple conductor layers and insulating layers stacked alternately. In the example shown in FIG. 1, the wiring board 1 is located on a second buildup section 20. The wiring board 1 may further include a third buildup section 30 composed of an insulating layer and a conductor layer stacked thereon, on the side of the second buildup section 20 opposite the first buildup section 10. The wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite the first surface 1F) that are perpendicular to its thickness direction. As shown in FIG. 1, the surface of the first buildup section 10 (first surface 10F) constitutes the first surface 1F. If the wiring board 1 has a third buildup section 30, the second surface 1B may be constituted by the surface of the third buildup section 30 (second surface 30B). When the third buildup section 30 is not formed and the wiring board is composed of the first buildup section 10 and the second buildup section 20, the second surface 1B can be formed by the surface (second surface 20B) of the second buildup section 20. As will be described later with reference to FIG. 2, when the third buildup section 30 and the second buildup section 20 are not formed and the wiring board is composed of the first buildup section 10, the second surface 1B can be formed by the surface (second surface 10B) of the first buildup section 10. The wiring board 1 is formed as a coreless wiring board that does not include a core layer.

[0010] The first buildup section 10 includes relatively fine wiring and may have a relatively high density of circuit wiring. In the example of FIG. 1, the first buildup section 10 has insulating layers (first insulating layers) 11 and conductor layers (first conductor layers) 12 that are alternately stacked. The conductor layers 12 that face each other across the first insulating layer 11 are connected by via conductors (first via conductors) 13. The first conductor layers 12 are patterned to have a predetermined conductor pattern. The first surface 10F of the first buildup section 10 is composed of the surface (top surface) of the first conductor layer 12 and the surface (top surface) of the first insulating layer 11 that is exposed from the pattern of the conductor layer 12. In the example shown, the conductor layer 12 that constitutes the first surface 10F is formed into a pattern having a plurality of conductor pads 12p.

[0011] 1, first surface 10F of first buildup section 10, i.e., the first surface 1F side of wiring board 1, will be referred to as the "top" or "upper side," and second surface 1B side of wiring board 1 will be referred to as the "bottom" or "lower side." Furthermore, in each component, the surface facing first surface 1F of wiring board 1 will also be referred to as the "top surface," and the surface facing second surface 1B of wiring board 1 will also be referred to as the "bottom surface."

[0012] The conductor pad 12p is the uppermost surface of the first buildup section 10, i.e., the outermost surface of the wiring board 1, and constitutes a component mounting surface to which external electronic components can be connected on the wiring board 1. The component mounting surface of the wiring board 1 may have multiple component mounting areas. For example, as shown in the example of FIG. 1, two component mounting areas (EA1, EA2) may be formed corresponding to areas where electronic components E1, E2 are to be mounted.

[0013] When mounting an external electronic component on the illustrated wiring board 1, the exposed upper surface of the conductor pad 12p can be electrically and mechanically connected to the external electronic component by, for example, interposing a conductive bonding material (not shown) such as solder between the upper surface of the conductor pad 12p and the connection pad of the external electronic component. In this case, a plating layer (not shown) including, for example, a nickel layer and a tin layer may be formed in advance on the upper surface of the conductor pad 12p.

[0014] When multiple component mounting areas are formed, a conductor pattern may be formed in the conductor layer 12 in the first buildup section 10 such that conductor pads 12p located in adjacent component mounting areas can be electrically connected to each other. When the wiring board 1 is used, the multiple electronic components mounted thereon are electrically connected to each other via a short path via the first buildup section 10. Examples of electronic components E1 and E2 that can be mounted on the wiring board 1 include active components such as semiconductor integrated circuit devices and transistors.

[0015] 1, the second surface 10B opposite to the first surface 10F of the first buildup section 10 is composed of the surface (bottom surface) of the insulating layer 11 and the surfaces (bottom surface and side surfaces) of the conductor layer 12. The first buildup section 10 is laminated such that the second surface 10B faces the first surface 20F of the second buildup section 20 opposite to the second surface 20B.

[0016] The insulating layer 11 of the first buildup section 10 may be formed using an insulating resin such as an epoxy resin or a phenolic resin. The insulating layer 11 may include any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). Examples of conductors constituting the conductor layer 12 and the via conductors 13 include copper and nickel, and copper is preferably used. For ease of viewing, the conductor layer 12 and the via conductors 13 are shown as single layers in FIG. 1, but the conductor layer 12 and the via conductors 13 may have a multi-layer structure. For example, the conductor layer 12 and the via conductors 13 may have a two-layer structure including a metal film layer (preferably a sputtered film layer or an electroless plated film layer) and a plated film layer (preferably an electrolytic plated film layer).

[0017] The via conductors 13, which penetrate the insulating layer 11 in the thickness direction, are formed by filling through holes 11a penetrating the insulating layer 11 with a conductor. In the example of FIG. 1, the via conductors 13 are integrally formed with the conductor layer 12 provided below them. Therefore, the via conductors 13 and the conductor layer 12 may be formed using the same metal film layer and plating film layer. The conductor layer 12 is formed on the lower surface of the insulating layer 11. The through holes 11a are formed so that the aspect ratio of the via conductors 13 (height from the upper surface of the lower conductor layer 12 to which the via conductors 13 are connected to the lower surface of the upper conductor layer 12 / diameter of the via conductors 13 on the upper surface of the lower conductor layer 12) is, for example, approximately 0.5 or more and approximately 1.0 or less. The via diameter of the via conductors 13 (diameter of the via conductors 13 on the upper surface of the lower conductor layer 12 to which the via conductors 13 are connected) is approximately 10 μm. Although the term "diameter" is used, the planar shape of the via conductor 13 is not necessarily limited to a circle. The "diameter" refers to the distance between the longest two points on the periphery of the via conductor 13 in a horizontal cross section.

[0018] The conductor layer 12 of the wiring board 1 may have fine wiring FW, which is a high-density wiring having a relatively small wiring width and distance between wirings (wiring spacing). The fine wiring FW may have the smallest wiring width and distance between wirings among the wirings that make up the wiring board 1.

[0019] In the illustrated example, of the multiple conductor layers 12 included in the first buildup section 10, four conductor layers 12 have fine wiring FW, which is high-density wiring. Any number of conductor layers 12 in the first buildup section 10 may have fine wiring FW. There is no limit to the number of conductor layers 12 with fine wiring FW that the first buildup section 10 has.

[0020] The fine wiring FW included in the first buildup section 10 may have a wiring width and wiring spacing (distance between wirings) smaller than the wiring width and wiring spacing (distance between wirings) of wiring included in the conductor layer (second conductor layer) 22 in the second buildup section 20 (described later). Specifically, the minimum wiring width of the fine wiring FW is 2 μm or less, and the minimum wiring spacing is 2 μm or less. Having the fine wiring FW in the first buildup section 10 may provide wiring with more appropriate characteristics corresponding to the electrical signals that can be carried by the wiring in the first buildup section 10. From a similar perspective, the aspect ratio of the fine wiring FW that can be included in the first conductor layer 12 is, for example, 2.0 or more and 4.0 or less.

[0021] When the conductor layer 12 is formed to include the fine wiring FW as described above, it may be preferable that the via conductors 13 connecting the opposing conductor layers 12 with the insulating layer 11 interposed therebetween are also formed at a fine pitch. Small diameter through holes 11a for the via conductors 13 may be formed in the insulating layer 11. Therefore, although the insulating layer 11 may contain an inorganic filler such as fine particles made of silica (SiO2), alumina, or mullite, it may be preferable that the insulating layer 11 does not contain an inorganic filler so that small diameter through holes 11a can be easily formed.

[0022] In the first buildup section 10 including the conductor layer 12 including the fine wiring FW, the thickness of the insulating layer 11 is, for example, about 7.5 μm to 10 μm. In this case, the insulating layer 11 preferably does not include a core material (reinforcing material) made of glass fiber, aramid fiber, or the like. The thickness of the conductor layer 12 is 7 μm or less.

[0023] In the example shown in FIG. 1, the first buildup section 10 is stacked on the second buildup section 20. That is, the second surface 10B of the first buildup section 10 faces the first surface 20F of the second buildup section 20. Like the first buildup section 10, the second buildup section 20 has insulating layers (second insulating layers) 21 and conductor layers (second conductor layers) 22 that are alternately stacked. In the insulating layers 21, via conductors 23 are formed that penetrate each insulating layer 21 and connect opposing conductor layers via each insulating layer 21. Each conductor layer 22 is patterned to have a predetermined conductor pattern. As shown in FIG. 1, like the first buildup section 10, the second buildup section 20 does not include a core layer.

[0024] 1 , the second surface 20B of the second buildup section 20, which is composed of the lower surface of the insulating layer 21, the lowest layer of the second buildup section 20, and the lower and side surfaces of the conductor layer 22, faces the first surface 30F of the third buildup section 30. The third buildup section 30 includes an insulating layer 211 and a conductor layer 212 formed on its lower surface. The insulating layer 211 covers the lowermost conductor layer 22 of the second buildup section 20 and the lower surface of the lowermost insulating layer 21 of the second buildup section 20 that is not covered by the conductor layer 22. Via conductors 33 are formed in the insulating layer 211, penetrating the insulating layer 211 and connecting the conductor layer 212 to the conductor layer 22 of the second buildup section 20.

[0025] The insulating layer 21 constituting the second buildup section 20 may be formed using the same insulating resin as the insulating layer 11. The insulating layer 21 may include a core material (reinforcing material) made of glass fiber or aramid fiber. The insulating layer 211 of the third buildup section 30 includes a core material 21b made of glass fiber. The insulating layers 21 and 211 may further include an inorganic filler (not shown) made of fine particles such as silica (SiO2), alumina, or mullite. The conductor layer 22 of the second buildup section 20 and the conductor layer 212 of the third buildup section 30, as well as the via conductors 23 and 33, may be formed using any metal such as copper or nickel, similar to the conductor layer 12 and via conductor 13.

[0026] As described above, the wiring width and spacing of the wiring included in the conductor layer 22 of the second buildup section 20 and the conductor layer 212 of the third buildup section 30 are larger than the wiring width and spacing of the wiring included in the conductor layer 12 of the first buildup section 10. The thickness of the conductor layer 22 is formed to be thicker than the thickness of the conductor layer 12, for example, 10 μm or more. The conductor layer 22 of the second buildup section 20 does not include a wiring pattern in which wiring can be arranged at a pitch as fine as that of the fine wiring FW of the first buildup section 10. For example, the minimum wiring width of the wiring included in the conductor layer 22 is approximately 4 μm, and the minimum wiring spacing is approximately 6 μm. The via diameter of the via conductor 23 (the diameter of the via conductor 23 on the top surface of the lower conductor layer 22 to which the via conductor 23 is connected) is approximately 50 μm.

[0027] The insulating layer 211 and the conductor layer 212 of the third buildup section 30 are both formed thicker than the insulating layer 21 and the conductor layer 22 in the second buildup section 20. For example, the thickness of the insulating layer 211 is not less than 100 μm and not more than 200 μm. The thickness of the conductor layer 212 is approximately 20 μm. The via diameter of the via conductor 33 formed in the insulating layer 211 (the diameter of the via conductor 33 on the upper surface of the conductor layer 212) is approximately 100 μm.

[0028] Like the conductor layer 12 and the via conductor 13, the conductor layers 22, 212 and the via conductors 23, 33 may have a multilayer structure, for example, a two-layer structure including a metal film layer and a plating film layer. The second buildup section 20 and the third buildup section 30 do not include a fine wiring pattern like the fine wiring FW of the first buildup section 10. In such a case, the metal film layer of the two-layer structure forming the conductor layer 22 and the via conductor 23 and the conductor layer 212 and the via conductor 33 may be an electroless plating film layer formed by an electroless plating film, particularly an electroless copper plating film layer, and the plating film layer may be an electrolytic plating film layer formed by an electrolytic plating film, particularly an electrolytic copper plating film layer.

[0029] 1, the wiring board 1 further includes a solder resist layer 31 formed on the surfaces of the insulating layer 211 and the conductor layer 212. The solder resist layer 31 is formed using, for example, a photosensitive polyimide resin or an epoxy resin. An opening 31a is formed in the solder resist layer 31, and a conductor pad 32p of the conductor layer 212 of the third buildup section 30 is exposed through the opening 31a.

[0030] The second surface 1B of the wiring board 1, which is opposite to the component mounting surface of the wiring board 1, can be a connection surface to be connected to an external element when the wiring board 1 itself is mounted on an external element such as an external wiring board (e.g., the motherboard of an electrical device). The conductor pad 32p can be connected to an external board, electrical component, or mechanical component. In a plan view, the wiring board 1 has a rectangular shape with each side measuring 80 mm or more and 240 mm or less. Note that "plan view" means viewing an object with a line of sight parallel to the thickness direction of the wiring board 1.

[0031] 2 shows a wiring board 1a as another example of a wiring board manufactured by the manufacturing method of the embodiment. The wiring board 1a includes a first buildup portion 10 having a first surface 10F and a second surface 10B, and a solder resist layer SR covering the second surface 10B. A conductor layer 12 is exposed through an opening SRa formed in the solder resist layer SR. That is, the first surface 1F of the wiring board 1a is formed by the first surface 10F of the first buildup portion 10, and the second surface 1B of the wiring board 1a is formed by the second surface 10B of the first buildup portion 10. If a wiring board manufactured by the manufacturing method of the wiring board of the embodiment does not include a buildup portion other than the first buildup portion 10, it may have the configuration of the wiring board 1a shown in the figure.

[0032] Next, with reference to FIGS. 3A to 3R, a method for manufacturing a wiring board according to an embodiment will be described, taking the case of manufacturing the wiring board 1 shown in FIG. 1 as an example. Each component formed in the manufacturing method described below can be formed using the material exemplified as the material of the corresponding component in the description of the wiring board 1 in FIG. 1, unless otherwise specified. In the following description of the method for manufacturing the wiring board 1, the side closer to the core material GS constituting the support substrate SP will be referred to as the "bottom" or "lower side," and the side farther from the support substrate SP will be referred to as the "top" or "upper side." Therefore, the surface of each element constituting the wiring board 1 that faces the support substrate SP will be referred to as the "lower surface," and the surface facing the opposite side from the support substrate SP will also be referred to as the "upper surface."

[0033] The method for manufacturing a wiring board according to the embodiment includes manufacturing a first buildup section 10 on a support substrate SP. The method for manufacturing a wiring board 1 to be described includes stacking a second buildup section 20 on the first buildup section 10. A third buildup section 30 is further stacked on the second buildup section 20 (see FIG. 1).

[0034] First, as shown in FIG. 3A, a support substrate SP is prepared. In the wiring board manufacturing method of this embodiment, the support substrate SP used has excellent flatness on two surfaces perpendicular to its thickness direction. The two surfaces perpendicular to the thickness direction of the support substrate SP have a flatness of, for example, ±2.5 μm or less. Note that "flatness" here is an index that numerically expresses the smoothness (uniformity) of a plane, and is based on or conforms to JIS B 0621-1984. Therefore, a flatness of ±2.5 μm or less indicates that the concavity or convexity in the thickness direction of the support substrate SP relative to a virtual plane is 2.5 μm or less on each side. The support substrate SP includes, for example, a core material GS, which is a glass substrate, a first metal film layer ML1 laminated on both surfaces of the core material GS, and a second metal film layer ML2 laminated on the metal film layer ML1 via an adhesive layer AL. The first and second metal film layers ML1 and ML2 are metal film layers formed, for example, by electroless plating or sputtering. While the first and second metal film layers ML1 and ML2 are depicted as single layers in the illustration, they may include multiple layers. For example, the first and second metal film layers ML1 and ML2 may each have a two-layer structure composed of a titanium layer and a copper layer. The adhesive layer AL may include, for example, an azobenzene-based polymer adhesive that can be attached and detached by light irradiation. The support substrate SP may include, as the core material GS, a glass substrate, or any of a silicon substrate, a metal substrate, and a ceramic substrate.

[0035] 3A and 3B to 2R illustrate an example in which one wiring substrate is formed on a support substrate SP, and a method for manufacturing a wiring substrate is described below, but multiple wiring substrates can be formed on the support substrate SP. Specifically, the surface of the support substrate SP has one or more continuous product areas, and a laminate (build-up portion) including one wiring substrate in each product area is formed on the surface of the support substrate SP. When the support substrate SP has multiple product areas, the formed laminate is divided into each product area to manufacture the wiring substrates.

[0036] Next, as shown in FIG. 3B, a conductor layer 12 having a plurality of conductor pads 12p is formed on the support substrate SP. In forming the conductor layer 12 in contact with the support substrate SP, for example, a plating resist is formed on the metal film layer ML2, and openings corresponding to the formation areas of the pattern of the conductor pads 12p are formed in the plating resist by, for example, photolithography. Next, a plating film layer is formed in the openings by electrolytic plating using the metal film layer ML2 as a seed layer. After the plating film layer is formed, the plating resist is removed, resulting in the state shown in FIG. 3B.

[0037] Next, as shown in FIG. 3C, an insulating layer 11 is laminated to cover the upper and side surfaces of the conductor layer 12 and the surface of the support substrate SP exposed from the conductor pattern of the conductor layer 12. For example, an insulating resin such as epoxy resin or phenol resin can be used as the insulating layer 11. Fluorine resin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI) may also be used. The insulating layer 11 is formed by thermocompression bonding these resins formed into a film shape. Next, through holes 11a are formed in the insulating layer 11 at the positions where the via conductors 13 (see FIG. 1) will be formed by irradiating the insulating layer 11 with, for example, carbon dioxide laser light or excimer laser light.

[0038] Although not shown, the formation of the through holes 11a by irradiation with a laser such as a carbon dioxide laser beam can be performed by irradiating the laser while the upper surface of the insulating layer 11 is protected by covering it with a protective film such as a polyethylene terephthalate (PET) film. The through holes 11a are formed by penetrating the protective film and the insulating layer 11. After the formation of the through holes 11a, a desmearing process may be performed to prevent a decrease in adhesion or an increase in resistance components during the formation of the conductor layer 12 due to processing-induced deformation products generated at the bottom of the through holes 11. The desmearing process may preferably be a dry desmearing process using plasma gas. The desmearing process may also be performed while protecting the surface of the insulating layer 11 with a protective film such as a polyethylene terephthalate (PET) film formed on the surface of the insulating layer 11.

[0039] 3C and 3D to 3R, which will be referred to below, show stacks formed on one surface of the support substrate SP, and do not show stacks that may be formed on the opposite surface. However, the opposite surface of the support substrate SP may also have stacks in the same manner and number, or may have conductor layers and insulating layers in a manner and number different from those on one surface, or may not have such conductor layers and insulating layers.

[0040] 3D, a metal film layer 121 is formed on the inner wall of the through hole 11a and on the surface of the insulating layer 11 by electroless plating, sputtering, or the like. Preferably, the metal film layer 121 may be a sputtering film formed by sputtering. Note that, if a protective film is provided on the surface of the insulating layer 11 during the formation of the through hole 11a and / or the desmear treatment, the protective film may be peeled off and removed before the formation of the metal film layer 121.

[0041] Next, as shown in FIG. 3E, a dry film resist containing, for example, a photosensitive epoxy resin is adhered to the metal film layer 121, and a resist layer RL1 is formed in contact with the upper surface of the metal film layer 121. Subsequently, exposure of the resist layer RL1 is performed. In the wiring board manufacturing method of the embodiment, direct imaging exposure is performed in the step of exposing the resist layer RL1. In direct imaging exposure, a photomask is not used, and the resist layer RL1 is directly irradiated with irradiation light L. As a light source for the irradiation light L, for example, a semiconductor laser with a wavelength of 350 nm to 410 nm or an ultra-high pressure mercury lamp can be used. The irradiation light L is scanned according to a drawing pattern corresponding to the conductor pattern of the first conductor layer 12 to be formed on the insulating layer 11 (see FIG. 3H). The exposure amount can be determined by the illuminance of the exposure light source and the scanning speed of the irradiation light L.

[0042] Next, as shown in FIG. 3F, a resist pattern corresponding to the conductor pattern of the first conductor layer 12 (see FIG. 3H) to be formed on the insulating layer 11 is formed on the first resist layer RL1. Specifically, after the above-mentioned process of exposing the resist layer RL1 is completed, the resist layer RL1 is developed using a developer made of an aqueous sodium carbonate solution, which may contain, for example, a surfactant, an antifoaming agent, and a small amount of an organic solvent to promote development, to form openings RL1o. If the conductor pattern of the first conductor layer 12 to be formed on the insulating layer 11 includes wiring FW (see FIG. 3H), the openings RL1o corresponding to the wiring FW are formed so that the minimum opening width is 2 μm or less and the minimum spacing between the openings is 2 μm or less. Note that in the description of the method for manufacturing a wiring board, the resist layer exposed by direct imaging exposure in forming the conductor layer 12 of the first buildup section 10 is also referred to as the first resist layer RL1, and the resist pattern formed on the first resist layer RL1 is also referred to as the first resist pattern.

[0043] 3G, a plating film layer 122 is formed in the opening RL1o of the first resist layer RL1 by electrolytic plating using the metal film layer 121 as a power supply layer. The inside of the through hole 11a is completely filled with the electrolytic plating film 122, and the via conductor 13 is formed.

[0044] Next, the first resist layer RL1 is removed using an alkaline stripping solution, and then the portion of the metal film layer 121 that is not covered by the plating film layer 122 is removed by etching. As a result, as shown in Fig. 3H, a conductor layer 12 having a two-layer structure consisting of the metal film layer 121 and the plating film layer 122 and having fine wiring FW is formed. The conductor layer 12 can be formed to a thickness of, for example, 7 µm or less, and the wiring FW can be formed so that the minimum wiring width is 2 µm or less, the minimum wiring spacing is 2 µm or less, and the aspect ratio is, for example, 2.0 or more and 4.0 or less.

[0045] As described above, in the wiring board manufacturing method of the embodiment, direct imaging exposure is used to form the resist pattern of the first resist layer RL1. This is believed to improve the yield in the manufacturing of wiring boards. Specifically, in exposure methods using a photomask, exposure is performed on a photomask-by-photomask basis, and therefore the depth of focus can only be adjusted on a photomask-by-photomask basis. On the other hand, direct imaging exposure does not require the use of a photomask, and therefore the depth of focus can be adjusted on an exposure beam-by-exposure beam basis. Therefore, by performing direct imaging exposure in the formation of the conductor layer 12, which may include relatively fine wiring FW, it is believed that the resolution of the resist pattern is superior to that obtained when exposure is performed using a photomask.

[0046] In the method for manufacturing a wiring board, each product area on the surface of the support substrate SP has a rectangular shape with each side measuring 80 mm or more and 240 mm or less in plan view. Therefore, the stack (build-up portion) formed across one or more product areas of the support substrate SP has a rectangular shape with each side measuring at least 80 mm or more in plan view. When manufacturing a relatively large stack like this, exposure using a photomask that limits the area that can be exposed in a single exposure requires repeated exposure of different areas, which can increase the number of steps in the exposure process. In contrast, direct imaging exposure scans the entire area of ​​the wiring board with irradiation light in a single exposure, thereby suppressing the increase in steps in the exposure process and potentially improving the yield of wiring board manufacturing.

[0047] Next, as shown in Figure 3I, a desired number of insulating layers 11 and conductor layers 12, as well as via conductors 13 penetrating each insulating layer, are formed on the conductor layer 12 and insulating layer 11 in a manner similar to the method for forming the insulating layer 11, conductor layer 12, and via conductors 13 described above.

[0048] 3J, the uppermost insulating layer 11 and conductor layer 12 of the insulating layers 11 and conductor layers 12 of the first buildup section 10 are formed on the upper side of the conductor layer 12. As shown in the figure, the uppermost conductor layer 12 does not include wiring FW. In such a case, the conductor layer 12 may be formed by a method including forming a resist pattern by exposing a resist layer using a photomask. Furthermore, the uppermost conductor layer 12 not including wiring FW may be formed by a method similar to the formation of the insulating layer 11 and the conductor layer 12 on the insulating layer 11 described above (a method including direct imaging exposure of a resist layer).

[0049] In the method for manufacturing a wiring board according to the embodiment, any one of the conductor layers 12 constituting the first buildup section 10 may be formed by a method including direct imaging exposure to a resist layer. Therefore, for example, in the illustrated example, the lowermost conductor layer 12 in the first buildup section 10 that does not include wiring FW (the conductor layer 12 in contact with the support substrate SP) may also be formed by a method including formation of a resist pattern by exposure using a photomask to a resist layer, or may also be formed by a method including direct imaging exposure.

[0050] 3K, the lowermost insulating layer 21 of the second buildup section 20 (see FIG. 3P) is laminated on the uppermost insulating layer 11 and conductor layer 12 of the first buildup section 10. Next, through holes 21a are formed in a manner similar to the formation of through holes 11a and metal film layer 121 described with reference to FIGS. 3C and 3D, and metal film layer 221 is formed on the upper surface of insulating layer 21 and on the inner surface of through hole 21a.

[0051] Next, as shown in FIG. 3L, a resist layer RL2 is formed on the metal film layer 221. Subsequently, exposure is performed on the resist layer RL2. In the step of exposing the resist layer RL2, exposure using a photomask M may be performed. Alternatively, direct imaging exposure may be performed in the step of exposing the resist layer RL2. In this case, direct imaging exposure may be performed with a larger beam spot diameter and a lower resolution of the formed resist pattern than the direct imaging exposure performed in the step of exposing the resist layer RL1.

[0052] Next, as shown in FIG. 3M, similar to the development of the first resist layer RL1 described above with reference to FIG. 3F, the resist layer RL2 is developed using a developer to form a resist pattern corresponding to the conductor pattern of the second conductor layer 22 (see FIG. 3P). Specifically, openings RL2o corresponding to the conductor pattern of the second conductor layer 22 to be formed are formed. If the conductor pattern of the second conductor layer 22 to be formed on the insulating layer 21 includes wiring, the openings RL2o corresponding to the wiring can be formed so that the minimum opening width is approximately 4 μm and the minimum opening spacing is approximately 6 μm. The resist layer used in forming the conductor layer 22 is also referred to as the second resist layer RL2, and the resist pattern formed on the second resist layer RL2 is also referred to as the second resist pattern.

[0053] 3N, a plating film layer 222 is formed in the opening RL2o of the second resist layer RL2 by electrolytic plating using the metal film layer 221 as a power supply layer. The inside of the through hole 21a is completely filled with the electrolytic plating film 222, and the via conductor 23 is formed.

[0054] Next, the second resist layer RL2 is removed using a stripping solution, and then the portion of the metal film layer 221 that is not covered by the plating film layer 222 is removed by etching. As a result, as shown in FIG. 3O, a second conductor layer 22 having a two-layer structure consisting of the metal film layer 221 and the plating film layer 222 is formed. The second conductor layer 22 may be formed to have a thickness of, for example, 10 μm or more. The second conductor layer 22 may be formed to have wiring with a minimum wiring width of approximately 4 μm and a minimum wiring spacing of approximately 6 μm.

[0055] Next, as shown in FIG. 3P , the above-described steps of forming insulating layers 21, conductor layers 22, and via conductors 23 are repeated to form a desired number of insulating layers 21 and conductor layers 22, as well as via conductors 23 that penetrate each insulating layer 21. Formation of second buildup section 20 on first buildup section 10 is then completed. In forming first buildup section 10 and second buildup section 20, the minimum wiring width of the wiring FW in first conductor layer 12 may be smaller than the minimum wiring width of the wiring in second conductor layer 22, and the minimum wiring spacing between wiring FW in first conductor layer 12 may be smaller than the minimum wiring spacing between wiring in second conductor layer 22. Note that in FIG. 3P and subsequent FIGS. 3Q and 2R, metal film layers 121 and 221 and plating film layers 122 and 222 are not depicted, and conductor layers 12 and 22 are depicted as single layers, as in FIG. 1 .

[0056] As described above, the second buildup section 20, which has a conductor layer 22 with a relatively gentler wiring rule than the first buildup section 10, can be laminated continuously with the first buildup section 10 on the support substrate SP after laminating the first buildup section 10 on the support substrate SP. Therefore, compared to a manufacturing method in which the first buildup section 10 and the second buildup section 20, which are formed separately, are joined via a connecting member, a wiring substrate with better flatness can be manufactured in fewer steps. Furthermore, the influence of a photomask is relatively small when forming the conductor layer 22 with a relatively gentler wiring rule compared to when forming a conductor layer with a finer wiring rule. Exposure methods using a photomask, such as projection exposure, proximity exposure, and contact exposure, do not require scanning of irradiation light and require a relatively short time to form a resist pattern. Therefore, forming a resist pattern (second resist pattern) by exposure using a photomask in forming the conductor layer 22 can shorten the time required for the exposure process, potentially improving the manufacturing efficiency of wiring substrates.

[0057] Next, as shown in FIG. 3Q, insulating layer 211, conductor layer 212, and via conductors 33 penetrating insulating layer 211 of third buildup section 30 are formed on insulating layer 21 and conductor layer 22, the uppermost layers of second buildup section 20, using a method similar to that used to form insulating layer 21, conductor layer 22, and via conductor 23. Prepreg containing an insulating resin such as epoxy resin or BT resin impregnated into reinforcing material (core material) 21b made of glass fiber is used as the insulating resin for forming insulating layer 211. Next, solder resist layer 31 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of insulating layer 211 and conductor layer 212. Then, openings 31a defining conductor pads 32p are formed by photolithography.

[0058] Next, as shown in FIG. 3R, the support substrate SP is removed from the laminate including the first buildup section 10. The lower surface of the second metal film layer ML2 below the conductor pads 12p is exposed. To remove the support substrate SP, the adhesive layer AL is softened by, for example, irradiating it with laser light, and then the second metal film layer ML2 of the support substrate SP is peeled off. Next, the second metal film layer ML2 is removed by etching, exposing the lower surfaces of the conductor pads 12p and the insulating layer 11. Note that the laminate, which may include multiple wiring substrates, is divided into product areas and formed as individual, independent wiring substrates. The wiring substrate 1 shown in FIG. 1 is completed.

[0059] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to FIGS. 3A to 3R, and the conditions and order of steps may be arbitrarily changed. Furthermore, certain steps may be omitted, or other steps may be added. The method for manufacturing a wiring board according to the embodiment may include at least forming a first buildup portion including a first conductor layer and a first insulating layer on a support substrate having a rectangular product area with each side dimension of 80 mm or more and 240 mm or less in a planar view, forming the first conductor layer with a minimum wiring width of 2 μm or less and a minimum wiring spacing of 2 μm or less, and forming the first conductor layer by a method including forming a first resist pattern by direct imaging exposure. For example, a solder resist layer having openings exposing the conductor pads 12 p may be formed on the conductor pads 12 p and the insulating layer 11 exposed after the second metal film layer ML2 is removed by etching. Furthermore, a conductor bump connected to the conductor pad 12 p may be formed in the opening of the solder resist layer. A plating layer including a nickel layer and a tin layer may be formed on the surface of the conductor bump. [Explanation of symbols]

[0060] 1. Wiring board 10 First build-up section 20 Second build-up section 30 Third Build-up Section 11 Insulating layer (first insulating layer) 12 Conductor layer (first conductor layer) 21 Insulating layer (second insulating layer) 22 Conductor layer (second conductor layer) 13, 23, 33 via conductors 121, 221 metal film layer 122, 222 plating film layer 12p, 32p contact pads FW wiring (fine wiring) SP support board RL1 Resist layer (first resist layer) RL2 Resist layer (second resist layer)

Claims

1. 1. A method for manufacturing a wiring board, comprising: forming a first buildup portion by alternately stacking first conductor layers and first insulating layers across one or more product areas on a support substrate having the one or more product areas; The shape of each of the product areas is a rectangle with each side measuring 80 mm or more and 240 mm or less in plan view, laminating the first conductor layer includes forming a first resist layer having a first resist pattern and forming a conductor pattern according to the first resist pattern; laminating the first conductor layer includes forming the conductor pattern so that the minimum width of the wiring included in the conductor pattern is 2 μm or less and the minimum spacing between the wiring is 2 μm or less; Forming the first resist layer having the first resist pattern includes exposing the first resist layer by direct imaging exposure.

2. 2. The method for manufacturing a wiring board according to claim 1, forming a second buildup section by alternately stacking second conductor layers and second insulating layers on a side of the first buildup section opposite to the support substrate; The first conductor layer and the second conductor layer are formed so that the minimum wiring width of the wiring in the first conductor layer is smaller than the minimum wiring width of the wiring in the second conductor layer, and the minimum wiring spacing of the wiring in the first conductor layer is smaller than the minimum wiring spacing of the wiring in the second conductor layer.

3. 3. The method for manufacturing a wiring board according to claim 2, Stacking the second conductor layer includes forming a second resist layer having a second resist pattern and forming a conductor pattern according to the second resist pattern, and forming the second resist layer having the second resist pattern includes exposing the second resist layer using a photomask.

4. 2. A method for manufacturing a wiring board according to claim 1, wherein the flatness of the surface of the support substrate is ±2.5 μm or less.

5. 5. The method for manufacturing a wiring board according to claim 4, wherein the support substrate is selected from the group consisting of a glass substrate, a silicon substrate, a metal substrate, and a ceramic substrate.

6. 2. The method for manufacturing a wiring board according to claim 1, wherein the first conductor layer is formed to a thickness of 7 [mu]m or less, and the second conductor layer is formed to a thickness of 10 [mu]m or more.

7. 2. The method for manufacturing a wiring board according to claim 1, wherein the first conductor layer is formed to include wiring having an aspect ratio of 2.0 or more and 4.0 or less.

8. 2. The method for manufacturing a wiring board according to claim 1, further comprising forming a third buildup section by alternately stacking a third insulating layer and a third conductor layer on the opposite side of the second buildup section from the first buildup section.

Images