Method for manufacturing wiring board

Abstract

To improve a yield in manufacture of a wiring board.SOLUTION: A method for manufacturing a wiring board includes forming a first build-up part 10 and a second build-up part 20. The formation of the first build-up part 10 includes laminating a first insulation layer 11 on a support substrate SP, and forming a first via conductor 13 and a first conductor layer 12, the formation of the second build-up part 20 includes laminating a second insulation layer 21 on the first build-up part 10, and forming a second via conductor 23 and a second conductor layer 22, the first conductor layer 12 and the second conductor layer 22 are formed so that minimum values of a wiring width and a wiring interval of the first conductor layer 12 are smaller than minimum values of a wiring width and a wiring interval of the second conductor layer 22, and the formation of the first via conductor 13 includes forming a first through hole 11a on the first insulation layer 11 containing a photosensitive insulation resin by photolithography processing.SELECTED DRAWING: Figure 2O

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a wiring board including a second wiring board and a first wiring board, in which the second wiring board is manufactured separately from the first wiring board, and the first wiring board and the second wiring board are joined together. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-4926 Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board manufacturing method disclosed in Patent Document 1, the first wiring board and the second wiring board need to be joined via bumps, and an insulating resin needs to be filled between the first wiring board and the second wiring board, which may result in a low yield in the manufacturing of wiring boards. [Means for solving the problem]

[0005] The method for manufacturing a wiring board of the present invention includes forming a first buildup portion on a support substrate having one or more product areas, and forming a second buildup portion on the opposite side of the first buildup portion from the support substrate. Forming the first build-up portion includes stacking a first insulating layer over the one or more product areas on the support substrate, and forming a first via conductor that penetrates the first insulating layer and a first conductor layer on the first insulating layer; forming the second build-up portion includes stacking a second insulating layer on the first build-up portion, and forming a second via conductor that penetrates the second insulating layer and a second conductor layer on the second insulating layer; the first conductor layer and the second conductor layer are formed so that the minimum wiring width of the wiring included in the first conductor layer is smaller than the minimum wiring width of the wiring included in the second conductor layer and the minimum wiring spacing of the wiring included in the first conductor layer is smaller than the minimum wiring spacing of the wiring included in the second conductor layer; the first insulating layer includes a photosensitive insulating resin; and forming the first via conductor includes forming a first through hole in the first insulating layer by photolithography processing.

[0006] According to the embodiment of the present invention, wiring substrates having good flatness and including a plurality of conductor layers with different wiring densities can be provided with a high yield. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing an example of a wiring substrate manufactured by a manufacturing method according to an embodiment of the present invention. [Figure 2A] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2B] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2C] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2D] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2E]1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2F] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2G] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2H] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2I] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2J] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2K] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2L] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2M] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2N] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2O] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2P] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2Q] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 2R] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0008] A wiring board manufactured by a wiring board manufacturing method according to an embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing wiring board 1, which is an example of a wiring board manufactured by a manufacturing method according to an embodiment. Note that wiring board 1 is merely one example of a wiring board to be manufactured. The layered structure of the manufactured wiring board and the number of conductor layers and insulating layers are not limited to the layered structure of wiring board 1 shown in FIG. 1 and the number of conductor layers and insulating layers included in wiring board 1. Furthermore, the drawings referred to are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention.

[0009] The wiring board 1 has a layered structure including a first buildup section 10 and a second buildup section 20, each of which is composed of a plurality of alternating conductor layers and insulating layers. As shown in FIG. 1, the wiring board 1 may further include a third buildup section 30, located on the side of the second buildup section 20 opposite the first buildup section 10, which is composed of an insulating layer and a conductor layer stacked thereon. The wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite the first surface 1F) that are perpendicular to its thickness direction. As shown in FIG. 1, the surface (first surface 10F) of the first buildup section 10 constitutes the first surface 1F. If the wiring board 1 has the third buildup section 30, the second surface 1B may be composed of the surface (second surface 30B) of the third buildup section 30. When the third buildup section 30 is not formed and the wiring board is composed of the first buildup section 10 and the second buildup section 20, the second surface 1B may be composed of the surface (second surface 20B) of the second buildup section 20. The wiring board 1 is formed as a coreless wiring board that does not include a core layer.

[0010] The first buildup section 10 includes relatively fine wiring and may have a relatively high density of circuit wiring. In the example of FIG. 1, the first buildup section 10 has insulating layers (first insulating layers) 11 and conductor layers (first conductor layers) 12 that are alternately stacked. The conductor layers 12 that face each other across the first insulating layer 11 are connected by via conductors (first via conductors) 13. The first conductor layers 12 are patterned to have a predetermined conductor pattern. The first surface 10F of the first buildup section 10 is composed of the surface (top surface) of the first conductor layer 12 and the surface (top surface) of the first insulating layer 11 that is exposed from the pattern of the conductor layer 12. In the example shown, the conductor layer 12 that constitutes the first surface 10F is formed into a pattern having a plurality of conductor pads 12p.

[0011] 1, first surface 10F of first buildup section 10, i.e., the first surface 1F side of wiring board 1, will be referred to as the "top" or "upper side," and second surface 1B side of wiring board 1 will be referred to as the "bottom" or "lower side." Furthermore, in each component, the surface facing first surface 1F of wiring board 1 will also be referred to as the "top surface," and the surface facing second surface 1B of wiring board 1 will also be referred to as the "bottom surface."

[0012] The conductor pad 12p is the uppermost surface of the first buildup section 10, i.e., the outermost surface of the wiring board 1, and constitutes a component mounting surface to which external electronic components can be connected on the wiring board 1. The component mounting surface of the wiring board 1 may have multiple component mounting areas. For example, as shown in the example of FIG. 1, two component mounting areas (EA1, EA2) may be formed corresponding to areas where electronic components E1, E2 are to be mounted.

[0013] When mounting an external electronic component on the illustrated wiring board 1, the exposed upper surface of the conductor pad 12p can be electrically and mechanically connected to the external electronic component by, for example, interposing a conductive bonding material (not shown) such as solder between the upper surface of the conductor pad 12p and the connection pad of the external electronic component. In this case, a plating layer (not shown) including, for example, a nickel layer and a tin layer may be formed in advance on the upper surface of the conductor pad 12p.

[0014] When multiple component mounting areas are formed, a conductor pattern may be formed in the conductor layer 12 in the first buildup section 10 such that conductor pads 12p located in adjacent component mounting areas can be electrically connected to each other. When the wiring board 1 is used, the multiple electronic components mounted thereon are electrically connected to each other via a short path via the first buildup section 10. Examples of electronic components E1 and E2 that can be mounted on the wiring board 1 include active components such as semiconductor integrated circuit devices and transistors.

[0015] 1, the second surface 10B opposite to the first surface 10F of the first buildup section 10 is composed of the surface (bottom surface) of the insulating layer 11 and the surfaces (bottom surface and side surfaces) of the conductor layer 12. The first buildup section 10 is laminated such that the second surface 10B faces the first surface 20F of the second buildup section 20 opposite to the second surface 20B.

[0016] In a wiring board manufactured by the wiring board manufacturing method of the embodiment, the insulating layer 11 of the first buildup section 10 contains a photosensitive insulating resin. The first insulating layer 11 may contain, for example, a photosensitive polyimide resin (PI), a photosensitive epoxy resin, a photosensitive polyhydroxystyrene resin (PHS), a photosensitive polybenzoxazole resin (PBO), a photosensitive benzocyclobutene resin (BCB), a photosensitive polysiloxane resin, or a novolac resin. Specifically, as will be described later in the description of the wiring board manufacturing method, the inclusion of a photosensitive insulating resin in the first insulating layer 11 allows the formation of relatively small first via conductors 13 that penetrate the first insulating layer 11 in the thickness direction by exposure and development. The first insulating layer 11 preferably does not contain a core material (reinforcement material) made of glass fiber, aramid fiber, or the like.

[0017] Examples of conductors constituting the first conductor layer 12 and the first via conductors 13 include copper and nickel, and copper is preferably used. For ease of viewing, the first conductor layer 12 and the first via conductors 13 are shown as single layers in Fig. 1, but the conductor layer 12 and the via conductors 13 may have a multi-layer structure. For example, the conductor layer 12 and the via conductors 13 may have a two-layer structure including a metal film layer (preferably a sputtering film layer or an electroless plating film layer) and a plating film layer (preferably an electrolytic plating film layer).

[0018] The first via conductors 13 that penetrate the first insulating layer 11 in the thickness direction are formed by filling through holes (first through holes) 11a that penetrate the first insulating layer 11 with a conductor. The first through holes 11a, which are formed by exposing and developing the first insulating layer 11 that contains a photosensitive insulating resin, are formed as relatively fine, small-diameter via holes. Therefore, the first via conductors 13, which are made of a conductor filling the first through holes 11a, are formed as so-called photovias with a relatively small diameter.

[0019] The first through hole 11a may be formed to have a diameter of 12.5 μm or less on the lower surface of the first insulating layer 11. That is, the via diameter of the first via conductor 13 (the diameter of the via conductor 13 on the upper surface of the lower conductor layer 12 to which the via conductor 13 is connected) may be 12.5 μm or less. The thickness of the first insulating layer 11 is, for example, about 7.5 μm to 10 μm. The through hole 11a may be formed to have, for example, an aspect ratio of the via conductor 13 (height from the upper surface of the lower conductor layer 12 to which the via conductor 13 is connected to the lower surface of the upper conductor layer 12 / diameter of the via conductor 13 on the upper surface of the lower conductor layer 12). Although the term "diameter" is used, the planar shapes of the through hole 11a and the via conductor 13 are not necessarily limited to circular. The "diameter" refers to the distance between the longest two points on the periphery of the through hole 11a and the via conductor 13 in a horizontal cross section. 1, the via conductor 13 is integrally formed with the underlying conductor layer 12. Therefore, the via conductor 13 and the conductor layer 12 can be formed from the same metal film layer and plating film layer.

[0020] The conductor layer 12 of the wiring board 1 may have fine wiring FW, which is a high-density wiring having a relatively small wiring width and distance between wirings (wiring spacing). The fine wiring FW may have the smallest wiring width and distance between wirings among the wirings that make up the wiring board 1.

[0021] In the illustrated example, of the multiple conductor layers 12 included in the first buildup section 10, four conductor layers 12 have fine wiring FW, which is high-density wiring. Any number of conductor layers 12 in the first buildup section 10 may have fine wiring FW. There is no limit to the number of conductor layers 12 with fine wiring FW that the first buildup section 10 has.

[0022] The fine wiring FW included in the first buildup section 10 has a wiring width and wiring spacing (distance between wirings) smaller than the wiring width and wiring spacing (distance between wirings) of wiring included in the conductor layer (second conductor layer) 22 in the second buildup section 20 (described later). Specifically, for example, the minimum wiring width of the fine wiring FW is 2 μm or less, and the minimum wiring spacing is 2 μm or less. The inclusion of fine wiring FW in the first buildup section 10 may provide wiring with more appropriate characteristics corresponding to the electrical signals that may be carried by the wiring in the first buildup section 10. From a similar perspective, the aspect ratio of the fine wiring FW that may be included in the first conductor layer 12 is, for example, 2.0 or more and 4.0 or less. The thickness of the conductor layer 12 is 7 μm or less.

[0023] When the conductor layer 12 is formed to include the fine wiring FW as described above, it may be preferable that the via conductors 13 connecting the opposing conductor layers 12 with the insulating layer 11 interposed therebetween are also formed at a fine pitch. Therefore, although the first insulating layer 11 may contain an inorganic filler such as fine particles made of silica (SiO2), alumina, or mullite, it may be preferable that the first insulating layer 11 does not contain an inorganic filler so that small-diameter through holes 11a can be easily formed.

[0024] As shown in FIG. 1, the first buildup section 10 is laminated on the second buildup section 20. That is, the second surface 10B of the first buildup section 10 faces the first surface 20F of the second buildup section 20. The wiring densities of the wiring included in the first buildup section 10 and the wiring included in the second buildup section 20 are different. As will be described later, these laminated sections with different wiring densities are laminated while being fixed on a support substrate. Therefore, the wiring board 1 is provided as a wiring board with relatively good flatness.

[0025] Similar to the first buildup section 10, the second buildup section 20 has insulating layers (second insulating layers) 21 and conductor layers (second conductor layers) 22 that are alternately stacked. Via conductors (second via conductors) 23 that penetrate each insulating layer 21 and connect opposing conductor layers via each insulating layer 21 are formed in the insulating layers 21. Each conductor layer 22 is patterned to have a predetermined conductor pattern. As shown in FIG. 1, similar to the first buildup section 10, the second buildup section 20 does not include a core layer.

[0026] 1 , a second surface 20B of the second buildup section 20, which is composed of the lower surface of the insulating layer 21, the lowest layer of the second buildup section 20, and the lower and side surfaces of the conductor layer 22, faces a first surface 30F of the third buildup section 30. The third buildup section 30 includes an insulating layer (third insulating layer) 211 and a conductor layer (third conductor layer) 212 formed on the surface below the insulating layer 211. The insulating layer 211 covers the lowermost conductor layer 22 of the second buildup section 20 and the lower surface of the lowermost insulating layer 21 of the second buildup section 20 that is not covered by the conductor layer 22. A via conductor (third via conductor) 33 is formed in the insulating layer 211, penetrating the insulating layer 211 and connecting the conductor layer 212 to the conductor layer 22 of the second buildup section 20.

[0027] The second insulating layer 21 constituting the second buildup section 20 and the third insulating layer 211 constituting the third buildup section 30 may be formed using an insulating resin such as epoxy resin or phenol resin. The second insulating layer 21 and the third insulating layer 211 may contain any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). The insulating layers 21 and 211 may contain a core material (reinforcing material) made of glass fiber or aramid fiber. In the illustrated example, the second insulating layer 21 of the second buildup section 20 does not contain a core material, while the third insulating layer 211 of the third buildup section 30 contains a core material 21b made of, for example, glass fiber. The insulating layers 21 and 211 may further contain an inorganic filler (not shown) made of fine particles such as silica (SiO2), alumina, or mullite. Like the first conductor layer 12 and the first via conductor 13, the second conductor layer 22, the second via conductor 23, the third conductor layer 212, and the third via conductor 33 can be formed using any metal such as copper or nickel.

[0028] As described above, the wiring width and spacing of the wiring included in the conductor layer 22 of the second buildup section 20 and the conductor layer 212 of the third buildup section 30 are larger than the wiring width and spacing of the wiring included in the conductor layer 12 of the first buildup section 10. The thickness of the conductor layer 22 is formed to be thicker than the thickness of the conductor layer 12, for example, 10 μm or more. The conductor layer 22 of the second buildup section 20 does not include a wiring pattern in which wiring can be arranged at a pitch as fine as that of the microwiring FW of the first buildup section 10. For example, the minimum wiring width of the wiring included in the conductor layer 22 is approximately 4 μm, and the minimum wiring spacing is approximately 6 μm. As will be described in detail later, the second via conductors 23, unlike the first via conductors 13, can be formed by filling second through holes 21a formed in the second insulating layer 21 by laser processing or drilling with a conductor. The second via conductors 23 can be formed to have a diameter larger than that of the first via conductors 13. The via diameter of the second via conductor 23 (the diameter of the via conductor 23 on the upper surface of the lower conductive layer 22 to which the via conductor 23 is connected) is about 50 μm.

[0029] The insulating layer 211 and the conductor layer 212 of the third buildup section 30 are both formed thicker than the insulating layer 21 and the conductor layer 22 in the second buildup section 20. For example, the thickness of the insulating layer 211 is not less than 100 μm and not more than 200 μm. The thickness of the conductor layer 212 is approximately 20 μm. The via diameter of the via conductor 33 formed in the insulating layer 211 (the diameter of the via conductor 33 on the upper surface of the conductor layer 212) is approximately 100 μm.

[0030] Like the conductor layer 12 and the via conductor 13, the conductor layers 22, 212 and the via conductors 23, 33 may have a multilayer structure, for example, a two-layer structure including a metal film layer and a plating film layer. The second buildup section 20 and the third buildup section 30 do not include a fine wiring pattern like the fine wiring FW of the first buildup section 10. In such a case, the metal film layer of the two-layer structure forming the conductor layer 22 and the via conductor 23 and the conductor layer 212 and the via conductor 33 may be an electroless plating film layer formed by an electroless plating film, particularly an electroless copper plating film layer, and the plating film layer may be an electrolytic plating film layer formed by an electrolytic plating film, particularly an electrolytic copper plating film layer.

[0031] 1, the wiring board 1 further includes a solder resist layer 31 formed on the surfaces of the insulating layer 211 and the conductor layer 212. The solder resist layer 31 is formed using, for example, a photosensitive polyimide resin or an epoxy resin. An opening 31a is formed in the solder resist layer 31, and a conductor pad 32p of the conductor layer 212 of the third buildup section 30 is exposed through the opening 31a.

[0032] The second surface 1B of the wiring board 1, which is the surface opposite to the component mounting surface of the wiring board 1, can be a connection surface to be connected to an external element when the wiring board 1 itself is mounted on an external element such as an external wiring board (e.g., the motherboard of an electrical device). The conductor pad 32p can be connected to an external board, electrical component, or mechanical component. In a plan view, the wiring board 1 can have a rectangular shape with each side measuring 80 mm or more and 240 mm or less. Note that "plan view" means viewing an object with a line of sight parallel to the thickness direction of the wiring board 1.

[0033] Next, with reference to FIGS. 2A to 2R, a method for manufacturing a wiring board according to an embodiment will be described, taking the case of manufacturing the wiring board 1 shown in FIG. 1 as an example. Each component formed in the manufacturing method described below can be formed using the material exemplified as the material of the corresponding component in the description of the wiring board 1 in FIG. 1, unless otherwise specified. In the following description of the method for manufacturing the wiring board 1, the side closer to the core material GS constituting the support substrate SP will be referred to as the "bottom" or "lower side," and the side farther from the support substrate SP will be referred to as the "top" or "upper side." Therefore, the surface of each element constituting the wiring board 1 that faces the support substrate SP will be referred to as the "lower surface," and the surface facing the opposite side from the support substrate SP will also be referred to as the "upper surface."

[0034] The manufacturing method of the wiring board of the embodiment includes manufacturing a first buildup section 10 on a support substrate SP and stacking a second buildup section 20 on the first buildup section 10, and in the manufacturing method of the wiring board 1 described, a third buildup section 30 is further stacked on the second buildup section 20 (see Figure 1).

[0035] First, as shown in FIG. 2A, a support substrate SP is prepared. In the wiring board manufacturing method of this embodiment, the support substrate SP used has excellent flatness on two surfaces perpendicular to its thickness direction. The two surfaces perpendicular to the thickness direction of the support substrate SP have a flatness of, for example, ±2.5 μm or less. Note that "flatness" here is an index that numerically expresses the smoothness (uniformity) of a plane and conforms to JIS B 0621-1984. Therefore, a flatness of ±2.5 μm or less indicates that the concavity or convexity in the thickness direction of the support substrate SP relative to a virtual reference plane is 2.5 μm or less on each side. The support substrate SP includes, for example, a core material GS, which is a glass substrate, a first metal film layer ML1 laminated on both surfaces of the core material GS, and a second metal film layer ML2 laminated on the metal film layer ML1 via an adhesive layer AL. The first and second metal film layers ML1 and ML2 are metal film layers formed, for example, by electroless plating or sputtering. Although the first and second metal film layers ML1 and ML2 are depicted as single layers in the drawings, they may each include multiple layers. For example, the first and second metal film layers ML1 and ML2 may each have a two-layer structure consisting of a titanium layer and a copper layer. The adhesive layer AL may include, for example, an azobenzene-based polymer adhesive that can be attached and detached by light irradiation. The support substrate SP may include a glass substrate as the core material GS, or any of a silicon substrate, a metal substrate, and a ceramic substrate.

[0036] 2A and 2B to 2R illustrate an example in which one wiring substrate is formed on a support substrate SP, and a method for manufacturing a wiring substrate is described below, but multiple wiring substrates can be formed on the support substrate SP. Specifically, the surface of the support substrate SP has one or more continuous product areas, and a laminate (build-up portion) including one wiring substrate in each product area is formed on the surface of the support substrate SP. When the support substrate SP has multiple product areas, the formed laminate is divided into each product area to manufacture the wiring substrates.

[0037] Next, as shown in FIG. 2B, a conductor layer 12 having a plurality of conductor pads 12p is formed on the support substrate SP. In forming the conductor layer 12 in contact with the support substrate SP, for example, a plating resist is formed on the metal film layer ML2, and openings corresponding to the formation areas of the pattern of the conductor pads 12p are formed in the plating resist by, for example, photolithography. Next, a plating film layer is formed in the openings by electrolytic plating using the metal film layer ML2 as a seed layer. After the plating film layer is formed, the plating resist is removed, resulting in the state shown in FIG. 2B.

[0038] 2C, a first insulating layer 11 is laminated to cover the upper and side surfaces of the conductor layer 12 and the surface of the support substrate SP exposed by the conductor pattern of the conductor layer 12. In the wiring board manufacturing method of the embodiment, a photosensitive insulating resin is used for the first insulating layer 11. Specifically, for example, photosensitive polyimide resin (PI), photosensitive epoxy resin, photosensitive polyhydroxystyrene resin (PHS), photosensitive polybenzoxazole resin (PBO), photosensitive benzocyclobutene resin (BCB), photosensitive polysiloxane resin, or novolac resin can be used for the first insulating layer 11. These photosensitive insulating resins formed into a film are used to cover the upper and side surfaces of the conductor layer 12 and the surface of the support substrate SP exposed by the conductor pattern of the conductor layer 12 using a laminator equipped with heating and pressure means, thereby forming the first insulating layer 11. Next, as shown in the figure, a photomask FM having openings corresponding to the first via conductors 13 (see Figure 2H) to be formed in the first insulating layer 11 is prepared on the upper side of the first insulating layer 11, and the first insulating layer 11 is exposed to irradiation light L passing through the openings in the photomask FM.

[0039] 2D, the insulating layer 11 is developed using a developer, and first through holes 11a are formed at the positions where the first via conductors 13 (see FIG. 2H) will be formed in the insulating layer 11. The first through holes 11a can be formed in the upper surface of the first insulating layer 11 so as to have a diameter of 12.5 μm or less.

[0040] 2C and 2D, and 2E to 2R referred to below, show a laminate formed on one surface of the support substrate SP, and do not show a laminate that may be formed on the opposite surface. However, the opposite surface of the support substrate SP may also have a laminate in the same manner and number, or a different manner and number of conductor layers and insulating layers from those on one surface, or such conductor layers and insulating layers may not be formed.

[0041] 2E, a metal film layer 121 is formed by electroless plating, sputtering, or the like on the inner wall of the through hole 11a and the surface of the insulating layer 11. Preferably, the metal film layer 121 may be a sputtering film formed by sputtering.

[0042] Next, as shown in FIG. 2F, a dry film resist containing, for example, a photosensitive epoxy resin is adhered to the metal film layer 121, and a resist layer (first resist layer) RL1 is formed in contact with the upper surface of the metal film layer 121. A resist pattern (first resist pattern) including openings RL1o corresponding to the conductor pattern of the first conductor layer 12 to be formed on the insulating layer 11 (see FIG. 2H) is formed in the first resist layer RL1. The first resist pattern can be formed by direct imaging exposure and development of the first resist layer RL1. In direct imaging exposure, a photomask is not used, and irradiation light LL is directly irradiated onto the resist layer RL1. When wiring FW (see FIG. 2H) is included as the conductor pattern of the first conductor layer 12 to be formed on the insulating layer 11, the openings RL1o corresponding to the wiring FW can be formed so that the minimum width of the openings RL1o is 2 μm or less and the minimum spacing between the openings is 2 μm or less.

[0043] 2G, a plating film layer 122 is formed in the opening RL1o of the first resist layer RL1 by electrolytic plating using the metal film layer 121 as a power supply layer. The inside of the through hole 11a is completely filled with the electrolytic plating film 122, thereby forming the first via conductor 13. The thickness of the first insulating layer 11 is, for example, approximately 7.5 μm to 10 μm, and the aspect ratio of the first via conductor 13 (height from the lower surface of the upper metal film layer 121 to which the via conductor 13 is connected to the upper surface of the lower conductor layer 12 / diameter of the via conductor 13 on the upper surface of the first insulating layer 11) can be approximately 0.5 or more and approximately 1.0 or less.

[0044] Next, the first resist layer RL1 is removed using an alkaline stripping solution, and then the portion of the metal film layer 121 that is not covered by the plating film layer 122 is removed by etching. As a result, as shown in Fig. 2H, a conductor layer 12 having a two-layer structure consisting of the metal film layer 121 and the plating film layer 122 and having fine wiring FW is formed. The conductor layer 12 can be formed to a thickness of, for example, 7 µm or less, and the wiring FW can be formed so that the minimum wiring width is 2 µm or less, the minimum wiring spacing is 2 µm or less, and the aspect ratio is, for example, 2.0 or more and 4.0 or less.

[0045] As described above, in the wiring board manufacturing method of the embodiment, the formation of the first via conductors 13 in the first buildup section 10 includes forming the first through holes 11a in the first insulating layer 11 containing a photosensitive insulating resin by photolithography. That is, the first via conductors 13 are formed as so-called photovias. The first conductor layer 12 in the first buildup section 10 is formed to include relatively fine wiring FW, and the first via conductors 13 are also formed with relatively small diameters and narrow pitches. As a result, the number of first via conductors 13 to be formed per unit area may be relatively large. In such cases, forming the through holes using laser light or drilling may be costly. When forming the through holes using photolithography, the through holes are formed by exposing a predetermined area all at once, so there is little risk of cost increase even when a large number of first via conductors 13 are to be formed.

[0046] In the method for manufacturing a wiring board, each product area on the surface of the support substrate SP may have a rectangular shape with each side measuring 80 mm or more and 240 mm or less in plan view. Therefore, the laminate (build-up portion) formed across one or more product areas of the support substrate SP has at least a rectangular shape with each side measuring 80 mm or more in plan view. In this way, when the wiring substrate 1 has a relatively large planar area, costs may be more effectively reduced.

[0047] As described above with reference to FIG. 2G, direct imaging exposure can be used to form the resist pattern of the first resist layer RL1. In exposure methods using a photomask, exposure is performed on a photomask-by-photomask basis, and therefore the depth of focus can only be adjusted on a photomask-by-photomask basis. On the other hand, direct imaging exposure does not require the use of a photomask, and therefore the depth of focus can be adjusted on an exposure beam-by-exposure beam basis. For this reason, it is believed that performing direct imaging exposure in the formation of the conductor layer 12, which may include relatively fine wiring FW, will result in a resist pattern with superior resolution compared to when exposure using a photomask is performed.

[0048] Next, as shown in Figure 2I, a desired number of insulating layers 11 and conductor layers 12, as well as via conductors 13 penetrating each insulating layer, are formed on the conductor layer 12 and insulating layer 11 in a manner similar to the method for forming the insulating layer 11, conductor layer 12, and via conductors 13 described above.

[0049] Next, as shown in FIG. 2J, the uppermost insulating layer 11 and conductor layer 12 among the insulating layers 11 and conductor layers 12 of the first buildup section 10 are formed on the upper side of the conductor layer 12.

[0050] 2K, a second insulating layer 21, which is the bottommost layer of the second buildup section 20 (see FIG. 2P), is laminated on the surfaces of the uppermost insulating layer 11 and conductor layer 12 of the first buildup section 10. For example, an insulating resin such as an epoxy resin or a phenol resin is used as the second insulating layer 21, and a film of this resin is laminated on the first buildup section 10. For example, a fluororesin, a liquid crystal polymer (LCP), a fluoroethylene resin (PTFE), a polyester resin (PE), or a modified polyimide resin (MPI) may be used as the second insulating layer 21.

[0051] Next, as shown in Fig. 2L, through holes (second through holes) 21a are formed in the second insulating layer 21 at the positions where the second via conductors 23 (see Fig. 2O) are to be formed, for example, by irradiation with carbon dioxide laser light, excimer laser light, or the like, or by drilling. Subsequently, a metal film layer 221 is formed on the upper surface of the second insulating layer 21 and on the inner surfaces of the through holes 21a. The second insulating layer 21 may include a core material. Therefore, when the second through holes 21a are formed by laser light or drilling in forming the second via conductors 23 in the second insulating layer 21, the through holes 21a can be more reliably formed with the desired dimensions.

[0052] Next, as shown in FIG. 2M, a resist layer RL2 is formed on the metal film layer 221. Subsequently, the resist layer RL2 is exposed to light. In the process of exposing the resist layer RL2, exposure using a photomask MM may be performed. Alternatively, direct imaging exposure may be performed in the process of exposing the resist layer RL2. In this case, direct imaging exposure may be performed with a larger beam spot diameter and a lower resolution of the formed resist pattern than the direct imaging exposure performed in the process of exposing the resist layer RL1. Subsequently, the resist layer RL2 is exposed and developed to form a resist pattern (second resist pattern) having openings RL2o corresponding to the conductor pattern of the second conductor layer 22 to be formed (see FIG. 2O). When the conductor pattern of the second conductor layer 22 to be formed on the insulating layer 21 includes wiring, the openings RL2o corresponding to the wiring may be formed so that the minimum opening width is approximately 4 μm and the minimum opening interval is approximately 6 μm.

[0053] Next, as shown in FIG. 2N, a plating film layer 222 is formed in the opening RL2o of the second resist layer RL2 by electrolytic plating using the metal film layer 221 as a power supply layer. The inside of the through hole 21a is completely filled with the electrolytic plating film 222, forming the via conductor 23. Note that the effect of the photomask is relatively small when forming the second conductor layer 22 with a relatively loose wiring rule compared to when forming a conductor layer with a fine wiring rule. The exposure method using a photomask does not require scanning of the irradiation light, and the time required to form the resist pattern is relatively short. Therefore, by forming the second resist pattern by exposure using a photomask in the formation of the conductor layer 22, the time required for the exposure process can be shortened, which may improve the manufacturing efficiency of the wiring board.

[0054] Next, the second resist layer RL2 is removed using a stripping solution, and then the portion of the metal film layer 221 that is not covered by the plating film layer 222 is removed by etching. As a result, as shown in FIG. 2O, a second conductor layer 22 having a two-layer structure consisting of the metal film layer 221 and the plating film layer 222 is formed. The second conductor layer 22 can be formed to have a thickness of, for example, 10 μm or more. The second conductor layer 22 can be formed to have a minimum wiring width of approximately 4 μm and a minimum wiring spacing of approximately 6 μm.

[0055] Next, as shown in FIG. 2P , the process of forming the second insulating layer 21, the second conductor layer 22, and the second via conductors 23 described above is repeated to form a desired number of insulating layers 21 and conductor layers 22, as well as via conductors 23 that penetrate each insulating layer 21. Formation of the second buildup section 20 on the first buildup section 10 is completed. The first buildup section 10 and the second buildup section 20 are formed such that the minimum wiring width of the wiring FW in the first conductor layer 12 is smaller than the minimum wiring width of the wiring in the second conductor layer 22, and the minimum wiring spacing between the wiring FW in the first conductor layer 12 is smaller than the minimum wiring spacing between the wiring in the second conductor layer 22. Note that in FIG. 2P and subsequent FIGS. 2Q and 2R, the metal film layers 121 and 221 and the plating film layers 122 and 222 are not depicted, and the conductor layers 12 and 22 are depicted as single layers, as in FIG. 1 .

[0056] As described above, in the wiring board manufacturing method of the embodiment, the second buildup section 20 is laminated continuously with the first buildup section 10 in contact with the upper surface of the first buildup section 10. The continuous lamination of the first buildup section 10 and the second buildup section 20 is performed on a support substrate SP. It is believed that a wiring board with better flatness can be provided compared to a manufacturing method in which the first buildup section 10 and the second buildup section 20 are laminated separately and then joined via a connecting member. Furthermore, because a step of joining the first buildup section 10 and the second buildup section 20 using a bonding material is not required, defects in the joining step are avoided, and it is believed that the yield in the manufacturing of wiring boards is improved.

[0057] Next, as shown in FIG. 2Q, the insulating layer (third insulating layer) 211, the conductor layer (third conductor layer) 212, and the via conductors (third via conductors) 33 penetrating the insulating layer 211 of the third buildup section 30 are formed on the insulating layer 21 and the conductor layer 22, which are the uppermost layers of the second buildup section 20, using a method similar to that used to form the insulating layer 21, the conductor layer 22, and the via conductors 23. The insulating resin that forms the insulating layer 211 is a prepreg containing an insulating resin such as epoxy resin or BT resin impregnated into a reinforcing material (core material) 21b made of glass fiber. Next, the solder resist layer 31 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 211 and the conductor layer 212. Then, openings 31a that define the conductor pads 32p are formed by photolithography.

[0058] Next, as shown in FIG. 2R, the support substrate SP is removed from the laminate including the first buildup section 10. The lower surface of the second metal film layer ML2 below the conductor pads 12p is exposed. To remove the support substrate SP, the adhesive layer AL is softened by, for example, irradiating it with laser light, and then the second metal film layer ML2 of the support substrate SP is peeled off. Next, the second metal film layer ML2 is removed by etching, exposing the lower surfaces of the conductor pads 12p and the insulating layer 11. Note that the laminate, which may include multiple wiring substrates, is divided into product areas and formed as individual, independent wiring substrates. The wiring substrate 1 shown in FIG. 1 is completed.

[0059] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to FIGS. 2A to 2R, and the conditions and order of the steps may be arbitrarily changed. Furthermore, certain steps may be omitted, or other steps may be added. The method for manufacturing a wiring board according to the embodiment may include at least forming a first buildup section including a first conductor layer and a first insulating layer and a second buildup section including a second conductor layer and a second insulating layer such that the minimum wiring width in the first conductor layer is smaller than the minimum wiring width in the second conductor layer and the minimum wiring spacing in the first conductor layer is smaller than the minimum wiring spacing in the second conductor layer, and forming first through holes by photolithography in the first insulating layer containing a photosensitive resin. For example, a solder resist layer having openings exposing the conductor pads 12p may be formed on the conductor pads 12p and the insulating layer 11 exposed after the second metal film layer ML2 is removed by etching. Furthermore, a conductor bump connected to the conductor pads 12p may be formed in the openings in the solder resist layer. A plating layer containing a nickel layer and a tin layer may be formed on the surface of the conductive bump. [Explanation of symbols]

[0060] 1. Wiring board 10 First build-up section 20 Second build-up section 30 Third Build-up Section 11 Insulating layer (first insulating layer) 12 Conductor layer (first conductor layer) 21 Insulating layer (second insulating layer) 22 Conductor layer (second conductor layer) 13 Via conductor (first via conductor) 23 Via conductor (second via conductor) 33 Via conductor (third via conductor) 121, 221 metal film layer 122, 222 plating film layer 12p, 32p contact pads 11a Through hole (1st through hole) 21a Through hole (2nd through hole) FM Photomask FW wiring SP support board RL1 Resist layer (first resist layer) RL2 Resist layer (second resist layer)

Claims

1. forming a first build-up portion on a support substrate having one or more product areas; forming a second buildup portion on an opposite side of the first buildup portion from the support substrate; A method for manufacturing a wiring substrate, comprising: forming the first build-up portion includes stacking a first insulating layer over the one or more product areas on the support substrate, and forming a first via conductor penetrating the first insulating layer and a first conductor layer on the first insulating layer; forming the second buildup portion includes stacking a second insulating layer on the first buildup portion, and forming second via conductors penetrating the second insulating layer and a second conductor layer on the second insulating layer; the first conductor layer and the second conductor layer are formed such that a minimum value of the wiring width of the wiring included in the first conductor layer is smaller than a minimum value of the wiring width of the wiring included in the second conductor layer, and a minimum value of the wiring spacing of the wiring included in the first conductor layer is smaller than a minimum value of the wiring spacing of the wiring included in the second conductor layer; the first insulating layer includes a photosensitive insulating resin; Forming the first via conductor includes forming a first through hole in the first insulating layer by photolithography.

2. 2. A method for manufacturing a wiring board according to claim 1, wherein forming the second build-up portion includes directly covering the surface of the first build-up portion opposite the support substrate with the second insulating layer.

3. A method for manufacturing a wiring board as described in claim 1, wherein the second insulating layer contains a thermosetting insulating resin material, and forming the second via conductor includes forming a second through hole in the second insulating layer by laser processing or drilling.

4. 2. The method for manufacturing a wiring board according to claim 1, wherein the first via conductor and the second via conductor are formed such that the diameter of the first via conductor is smaller than the diameter of the second via conductor.

5. 5. A method for manufacturing a wiring board according to claim 4, wherein the first through hole is formed to have a diameter of 12.5 [mu]m or less.

6. 2. A method for manufacturing a wiring board according to claim 1, wherein forming the first conductor layer includes forming a first resist layer having a first resist pattern by direct imaging exposure, and forming a conductor pattern according to the first resist pattern.

7. 7. A method for manufacturing a wiring board according to claim 6, wherein forming the second conductor layer includes forming a second resist layer having a second resist pattern by exposure using a photomask, and forming a conductor pattern according to the second resist pattern.

8. 2. The method for manufacturing a wiring board according to claim 1, wherein the shape of each of the product areas is a rectangle with each side measuring 80 mm or more and 240 mm or less in plan view.

9. 2. A method for manufacturing a wiring board according to claim 1, wherein the flatness of the surface of the support substrate is ±2.5 μm or less.

10. 2. The method for manufacturing a wiring board according to claim 1, wherein the support substrate is selected from the group consisting of a glass substrate, a silicon substrate, a metal substrate, and a ceramic substrate.

11. 2. A method for manufacturing a wiring board according to claim 1, wherein forming the first conductor layer includes forming the wiring included in the first conductor layer so that the minimum wiring width is 2 μm or less and the minimum wiring spacing is 2 μm or less.

12. 2. The method for manufacturing a wiring board according to claim 1, further comprising the step of forming a third buildup section by alternately stacking third insulating layers and third conductor layers on the opposite side of the second buildup section from the first buildup section.

Images