Capacitor and manufacturing method of the capacitor

Abstract

To provide a capacitor capable of reducing damage to a substrate and a manufacturing method of the same.SOLUTION: According to a manufacturing method of a capacitor of an embodiment, in a processing substrate 1 including a semiconductor substrate 2 including a main surface 2a having one or more concave portions 5, a conductive layer provided in the main surface 2a of the semiconductor substrate 2 and the one or more concave portions 5, and a dielectric layer 3, the method includes steps of: providing an opening part 6 by opening the dielectric layer 3 and the conductive layer located on the main surface 2a of the semiconductor substrate 2; providing a first conductive material part 8 on the main surface 2a located in the opening part 6; processing the conductive layer into a pattern shape including a connection part 10 extending from the conductive layer and connected to the opening part 6; providing a second conductive material part 13 electrically connecting the first contact electrode 11 and the second contact electrode 12; removing the first conductive material part 8 by dry etching; and removing the second conductive material part 13 by wet etching.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to capacitors and methods for manufacturing capacitors. [Background technology]

[0002] In the process of manufacturing a Si capacitor, after forming a trench in a Si substrate, a dielectric film and a poly-Si film are deposited, and then the poly-Si film is patterned. The poly-Si film is patterned using, for example, chemical dry etching (CDE). CDE is performed while the Si substrate being processed is clamped by an electrostatic chuck. When the poly-Si film is patterned, the contact between the poly-Si film and the Si substrate is lost. As a result, charges remain on the poly-Si film, and the Si substrate does not separate from the stage even after dechucking. This causes damage such as cracks to occur in the Si substrate when it is lifted from the stage by conductive lift pins. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-258452 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-296462 [Patent Document 3] Japanese Patent Application Publication No. 2023-102918 [Patent Document 4] Japanese Patent Application Laid-Open No. 2004-200640 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the invention is to provide a capacitor capable of reducing damage to a substrate, and a method for manufacturing the same. [Means for solving the problem]

[0005] According to the embodiment of the method for manufacturing a capacitor, in a processing substrate including a semiconductor substrate having a main surface with one or more recesses, a conductive layer provided on the main surface of the semiconductor substrate and in the one or more recesses, and a dielectric layer disposed between the conductive layer and the semiconductor substrate, openings are formed in the dielectric layer and the conductive layer located on the main surface of the semiconductor substrate; providing a first conductive material portion on the major surface located within the opening; processing the conductive layer by dry etching to form a pattern shape including a connection portion extending from the conductive layer and connected to the opening; providing a first contact electrode electrically connected to the conductive layer, a second contact electrode electrically connected to the semiconductor substrate, and a second conductive material portion electrically connecting the first contact electrode and the second contact electrode; removing the first conductive material portion by dry etching to cut off the electrical connection between the connection portion and the semiconductor substrate; The second conductive material portion is removed by wet etching to cut off the electrical connection between the first contact electrode and the second contact electrode. Includes.

[0006] According to the embodiment, the capacitor includes a semiconductor substrate having a main surface with one or more recesses; a conductive layer disposed within one or more recesses and on a major surface of a semiconductor substrate; a dielectric layer disposed between the conductive layer and the semiconductor substrate; a connecting portion formed by extending a conductive layer located on a main surface of a semiconductor substrate; an opening connected to the connection portion and having a bottom wall that is the main surface of the semiconductor substrate; a first contact electrode electrically connected to the conductive layer; a second contact electrode electrically connected to the semiconductor substrate; a hole located between the first contact electrode and the second contact electrode, the hole having a bottom wall on the main surface of the semiconductor substrate; an insulating layer provided in the opening and the hole; Equipped with. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a top view of a substrate to be processed, which is subjected to a first step of a method according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view of the processed substrate shown in FIG. 1 taken along line II-II. [Figure 3] FIG. 2 is a schematic circuit diagram showing the connection state of a portion that will become a first fuse portion (poly-Si fuse portion). [Figure 4] 4 is a top view of a substrate to be processed, which is subjected to a second step of the method of the embodiment. FIG. [Figure 5] 5 is a cross-sectional view of the processing substrate shown in FIG. 4 taken along line VV. [Figure 6] FIG. 10 is a top view of a substrate to be processed, which is subjected to a third step of the method of the embodiment. [Figure 7] 7 is a cross-sectional view of the processed substrate shown in FIG. 6 taken along line VII-VII. [Figure 8] FIG. 3 is a schematic circuit diagram showing a connection state of a first fuse portion (poly-Si fuse portion). [Figure 9] FIG. 10 is a top view of a processing substrate to be subjected to a fourth step of the method of the embodiment. [Figure 10] 10 is a cross-sectional view of the processed substrate shown in FIG. 9 taken along line XX. [Figure 11] FIG. 10 is a top view of a processing substrate subjected to a fifth step of the method of the embodiment. [Figure 12] 12 is a cross-sectional view of the processed substrate shown in FIG. 11 taken along line XII-XII. [Figure 13] FIG. 10 is a top view of a processing substrate subjected to a sixth step of the method of the embodiment. [Figure 14] 14 is a cross-sectional view of the processed substrate shown in FIG. 13 taken along line XIV-XIV. [Figure 15] FIG. 3 is a schematic circuit diagram showing a connection state between a first fuse portion (poly-Si fuse portion) and a second fuse portion (Al fuse portion). [Figure 16] FIG. 10 is a top view of a substrate to be processed, which is subjected to a seventh step of the method according to the embodiment. [Figure 17] 17 is a cross-sectional view of the processed substrate shown in FIG. 16 taken along line XVII-XVII. [Figure 18]FIG. 10 is a top view of a processing substrate subjected to the eighth step of the method of the embodiment. [Figure 19] 19 is a cross-sectional view of the processed substrate shown in FIG. 18 taken along line XIX-XIX. [Figure 20] FIG. 3 is a schematic circuit diagram showing a connection state between a first fuse portion (poly-Si fuse portion) and a second fuse portion (Al fuse portion). [Figure 21] FIG. 10 is a top view of a processing substrate subjected to the ninth step of the method of the embodiment. [Figure 22] 22 is a cross-sectional view of the processed substrate shown in FIG. 21 taken along line XXII-XXII. [Figure 23] FIG. 4 is a schematic circuit diagram showing a connection state of a second fuse portion (Al fuse portion) and a third fuse portion (Al fuse portion). [Figure 24] FIG. 10 is a top view of a processing substrate subjected to the tenth step of the method of the embodiment. [Figure 25] 25 is a cross-sectional view of the processed substrate shown in FIG. 24 taken along line XIII-XXIII. [Figure 26] FIG. 4 is a schematic circuit diagram showing a connection state of a second fuse portion (Al fuse portion) and a third fuse portion (Al fuse portion). [Figure 27] FIG. 11 is a cross-sectional view of the processing substrate, cut along the x-axis direction, on which the eleventh step of the method of the embodiment is performed. [Figure 28] FIG. 2 is a top view showing a capacitor manufactured by a method according to an embodiment. [Figure 29] 29 is a cross-sectional view of the capacitor shown in FIG. 28 taken along line XXVIIII-XXVIIII. [Figure 30] 10A and 10B are schematic diagrams illustrating a process of attaching a substrate to be dry-etched to a stage of an electrostatic chuck. [Figure 31] FIG. 2 is a schematic diagram showing a state of a processing substrate attached to a stage of an electrostatic chuck. [Figure 32] FIG. 2 is a schematic diagram showing a state in which a processing substrate is clamped on a stage of an electrostatic chuck. [Figure 33] FIG. 10 is a schematic diagram showing the state of the processing substrate attached to the stage of the electrostatic chuck after dry etching. [Figure 34]34 is a schematic diagram showing the state of the processing substrate shown in FIG. 33 when the processing substrate is dechucked from the stage of the electrostatic chuck. FIG. [Figure 35] FIG. 10 is a schematic diagram showing a state in which damage occurs to a processing substrate when the processing substrate is dechucked from the stage of an electrostatic chuck. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that components that perform the same or similar functions are designated by the same reference numerals throughout the drawings, and redundant description will be omitted.

[0009] Dry etching is performed in a reaction chamber with the substrate being clamped to a stage of an electrostatic chuck (ESC). The electrostatic chuck used in the dry etching process will be described with reference to FIGS. 30 to 35.

[0010] 30 is a schematic diagram showing the process of attaching a substrate to be dry-etched to the stage of an electrostatic chuck. First, the substrate 100 to be dry-etched is pressed against the stage 200 of the electrostatic chuck by conductive lift pins 201.

[0011] As shown in FIG. 31 , the processing substrate 100 includes a semiconductor substrate 101, a dielectric layer 102, and a conductive layer 103. The semiconductor substrate 101 is a Si wafer having a doped layer 101b doped with impurities on one main surface 101a. A plurality of recesses (trenches) 104 are provided on one main surface 101a of the semiconductor substrate 101. The depth direction of each recess (trenches) 104 is along the z-axis direction. The plurality of recesses (trenches) 104 are arranged along the x-axis direction at intervals from one another. Each recess (trenches) 104 extends along the y-axis direction.

[0012] The dielectric layer 102 is provided on the main surface 101a of the semiconductor substrate 101 and on the inner surfaces of each of the recesses 104. The conductive layer 103 is embedded in each recess 104. The conductive layer 103 covers the dielectric layer 102 in the recess 104 and the dielectric layer 102 located on the main surface 101a of the semiconductor substrate 101. The conductive layer 103 also covers the opposite main surface 101c and an end surface 101d connecting the two main surfaces 101a and 101c. The conductive layer 103 is formed, for example, from polysilicon doped with impurities. Therefore, as shown in FIG. 30, when the conductive lift pins 201 of the electrostatic chuck are brought into contact with the substrate 100 to be processed, charges 202 from the electrostatic chuck can be accumulated in the conductive layer 103. As a result, as shown in FIG. 32, the semiconductor substrate 101 of the substrate 100 is electrostatically attracted to the stage 200 of the electrostatic chuck. This establishes electrical continuity between the conductive layer 103 and the stage 200 of the electrostatic chuck. In this state, when the processing substrate 100 is removed from the electrostatic chuck by pushing up the conductive lift pins 201, the residual charge 202 in the conductive layer 103 can be discharged from the conductive layer 103 to the stage.

[0013] However, when the conductive layer 103 is patterned by dry etching, the electrical connection between the conductive layer 103 and the stage 200 of the electrostatic chuck is broken, as shown in FIG. 33 . As a result, residual charges 202 remain on the conductive layer 103, as shown in FIG. 34 . The region 203 where the residual charges 202 remain is indicated by a dotted line frame. Therefore, as shown in FIG. 35 , even if the process substrate 100 is pushed up by the conductive lift pins 201, the residual charges cannot be discharged. As a result, the process substrate 100 remains electrostatically adsorbed to the stage 200, resulting in damage 204, such as cracks, in the semiconductor substrate 101 of the process substrate 100. Note that if the process substrate 100 does not include the dielectric layer 102, the charges 202 accumulated in the conductive layer 103 will leak to the stage 200 through the semiconductor substrate 101, even after the conductive layer 103 is processed into a pattern shape by dry etching. Therefore, the problem of dechucking failure does not occur.

[0014] A method for manufacturing a capacitor according to an embodiment will be described with reference to Figures 1 to 29. In each figure, the z-axis direction is parallel to the thickness direction of the semiconductor substrate, the x-axis direction is parallel to the main surface of the semiconductor substrate, and the y-axis direction is parallel to the main surface of the semiconductor substrate and perpendicular to the x-axis direction.

[0015] (1st step) The first step includes providing a dielectric layer and a first conductive layer on a semiconductor substrate having one or more recesses on one main surface. The first step will be described with reference to FIGS. 1 to 3. FIG. 1 is a top view of the substrate to be processed. FIG. 2 is a cross-sectional view of the substrate to be processed shown in FIG. 1 taken along line II-II. FIG. 3 is a schematic circuit diagram showing the connection state of the portion that will become the first fuse portion (poly-Si fuse portion).

[0016] The handle substrate 1 includes a semiconductor substrate 2, a dielectric layer 3, and a first conductive layer 4.

[0017] The semiconductor may be selected from the group consisting of silicon (Si), germanium (Ge), semiconductors made of compounds of group III and group V elements, such as gallium arsenide (GaAs) and gallium nitride (GaN), and silicon carbide (SiC). Note that the term "group" as used herein refers to the "group" of the short periodic table.

[0018] The semiconductor substrate is, for example, a semiconductor wafer. The semiconductor wafer may be doped with impurities, and may have semiconductor elements such as transistors and diodes formed thereon. The main surface of the semiconductor wafer may be parallel to any crystal plane of the semiconductor. For example, the semiconductor wafer may be a Si wafer (silicon wafer) whose main surface is a (100) plane or a Si wafer (silicon wafer) whose main surface is a (110) plane.

[0019] The semiconductor substrate 2 illustrated in FIG. 2 is a Si wafer having a doped layer 2b doped with P-type or N-type impurities on one main surface 2a of the semiconductor substrate 2. A plurality of recesses (trenches) 5 are provided on one main surface 2a of the semiconductor substrate 2. The recesses (trenches) 5 can be processed, for example, by MacEtch (Metal-Assisted Chemical Etching). The depth direction of each recess (trenches) 5 is along the z-axis direction. Some recesses 5 are arranged along the x-axis direction at intervals from each other, and other recesses 5 are arranged along the y-axis direction at intervals from each other. A pattern in which the recesses 5 are arranged along the x-axis direction and a pattern in which the recesses 5 are arranged along the y-axis direction are alternately arranged along the x-axis direction and the y-axis direction. FIG. 2 shows a pattern in which the recesses 5 are arranged along the x-axis direction, and omits a pattern in which the recesses 5 are arranged along the y-axis direction.

[0020] The dielectric layer 3 is provided on the main surface 2a of the semiconductor substrate 2 and on the inner surface of each recess 5. The dielectric layer is made of, for example, an organic dielectric or an inorganic dielectric. Examples of organic dielectrics include polyimide. Ferroelectrics can also be used as inorganic dielectrics, but examples of inorganic dielectric layers include oxide films and nitride films. Paraelectrics such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, and tantalum oxide are preferred. These paraelectrics exhibit small changes in dielectric constant with temperature. Therefore, using a paraelectric for the dielectric layer can improve the heat resistance of the capacitor.

[0021] The first conductive layer 4 is embedded in each recess 5. The first conductive layer 4 is in contact with the dielectric layer 3 in the recess 5. The first conductive layer 4 covers the dielectric layer 3 located on the main surface 2a of the semiconductor substrate 2. The first conductive layer 4 embedded in each recess 5 is connected to the first conductive layer 4 located on the main surface 2a of the semiconductor substrate 2 via the dielectric layer 3. Therefore, the first conductive layers 4 embedded in each recess 5 are electrically connected to each other. The first conductive layer 4 is, for example, polysilicon (poly-Si) doped with impurities. Poly-Si doped with impurities has low resistance. Examples of impurities include P-type and N-type impurities. The first conductive layer 4 is not limited to polysilicon and can be formed of a metal or alloy such as molybdenum, aluminum, gold, tungsten, platinum, nickel, and copper. The first conductive layer 4 may have a single-layer structure or a multi-layer structure.

[0022] The dielectric layer 3 and the first conductive layer 4 may be formed not only on the main surface 2a of the semiconductor substrate 2 but also on the other main surface 2c and an end surface connecting these main surfaces 2a and 2c.

[0023] A fuse portion has not yet been provided on the process substrate 1. Therefore, the portion that will become the fuse portion is in a state E1 in which the first conductive layer 4, the dielectric layer 3, and the semiconductor substrate 2 form a capacitor with an MIM (Metal-Insulator-Metal) structure, as shown in FIG.

[0024] (2nd process) The second step includes providing one or more openings in the dielectric layer and the first conductive layer located on the main surface of the semiconductor substrate. The second step will be described with reference to Figures 4 and 5. Figure 4 is a top view of the substrate to be processed. Figure 5 is a cross-sectional view of the substrate to be processed shown in Figure 4 taken along line VV.

[0025] One or more openings 6 are formed through the dielectric layer 3 and the first conductive layer 4 located on the principal surface 2a of the semiconductor substrate 2. The openings 6 are preferably formed away from the area where the recess 5 pattern is formed. In the example shown in FIG. 4, the openings 6 are formed near the center of a side of the principal surface 2a of the semiconductor substrate 2 that is parallel to the y-axis direction. The openings 6 are cylindrical cavities whose inner walls are the dielectric layer 3 and the first conductive layer 4 and whose bottom wall is the principal surface 2a of the semiconductor substrate 2. Although the openings 6 will form the first fuse section, the first fuse section is not yet completed at the end of the second process. Therefore, the area that will become the first fuse section is in a state E1 where a capacitor with an MIM structure similar to that of the first process is being formed.

[0026] In FIGS. 4 and 5, the number of openings 6 is one, but the present invention is not limited to this and it is also possible to have a plurality of openings.

[0027] The opening 6 can be formed by dry etching such as chemical dry etching (CDE). An example of CDE is reactive ion etching (RIE).

[0028] Dry etching is performed while the substrate 1 is held by an electrostatic chuck (ESC chuck). The first conductive layer 4 is formed, for example, from impurity-doped polysilicon, and is therefore capable of storing charge from the electrostatic chuck. Therefore, the semiconductor substrate 2 of the substrate 1 is electrostatically attracted to the stage of the electrostatic chuck. Although not shown, the first conductive layer 4 is provided not only on the main surface 2a of the semiconductor substrate 2 but also on the other main surface 2c and the edge surface connecting these main surfaces 2a and 2c. Therefore, the first conductive layer 4 is electrically connected to the stage of the electrostatic chuck. After the dry etching process, when the substrate 1 is removed from the electrostatic chuck by pushing up the conductive lift pins, residual charge in the first conductive layer 4 can be released from the first conductive layer 4 to the stage, allowing the substrate 1 to be removed from the electrostatic chuck without being damaged.

[0029] (3rd step) The third step includes providing a first conductive material portion in the opening. The first conductive material portion constitutes a first fuse portion (e.g., a polysilicon fuse portion). The third step will be described with reference to FIGS. 6 to 8. FIG. 6 is a top view of a processed substrate. FIG. 7 is a cross-sectional view of the processed substrate shown in FIG. 6 taken along line VII-VII. FIG. 8 is a schematic circuit diagram showing the connection state of the first fuse portion (polysilicon fuse portion).

[0030] A second conductive layer 7 is provided on the first conductive layer 4 located over the entire main surface 2a of the semiconductor substrate 2 of the process substrate 1. At this time, a first conductive material portion 8 made of the same material as the second conductive layer 7 is embedded in the opening 6. The first conductive material portion 8 is in direct contact with the main surface 2a of the semiconductor substrate 2 located in the opening 6. The first conductive material portion 8 is also in contact with the first conductive layer 4. Therefore, the first conductive layer 4 is electrically connected to the semiconductor substrate 2 via the first conductive material portion 8. The first conductive material portion 8 is also called a first fuse portion (poly-Si fuse portion). As shown in FIG. 8 , the electrical connection state of the first fuse portion (poly-Si fuse portion) is a state E2 in which the first conductive layer 4 is directly electrically connected to the semiconductor substrate 2.

[0031] The second conductive layer 7 may be formed of, for example, the same material as the first conductive layer 4. Note that, for ease of understanding, the boundary between the first conductive layer 4 and the second conductive layer 7 is illustrated in Fig. 7, but the boundary (interface) between the first conductive layer 4 and the second conductive layer 7 may not be clear.

[0032] (4th step) The fourth step includes patterning the first conductive layer and the second conductive layer by dry etching. The fourth step will be described with reference to Figs. 9 and 10. Fig. 9 is a top view of the processed substrate. Fig. 10 is a cross-sectional view of the processed substrate shown in Fig. 9 taken along line XX.

[0033] The first conductive layer 4 and the second conductive layer 7 of the substrate 1 are patterned using dry etching. Alternatively, dry etching may be performed after forming a mask using photolithography. The purpose of patterning is to separate the first conductive layer 4 and the second conductive layer 7 into individual chips (to achieve the desired area for each chip). However, processing the first conductive layer 4 and the second conductive layer 7 into the desired area would disrupt the electrical continuity between the first conductive layer 4 and the first fuse portion 8. Therefore, the first conductive layer 4 and the second conductive layer 7 are patterned to provide a connection portion (wiring portion) 10 that connects the first conductive layer 4 and the first fuse portion 8. Specifically, the first conductive layer 4 and the second conductive layer 7 located outside the area where the pattern of the recess 5 is formed—in other words, the edge portion of the principal surface 2a of the semiconductor substrate 2—are removed by dry etching, except for the portion that will become the connection portion 10. The connection portion 10, which is formed by directly extending from the first conductive layer 4 and the second conductive layer 7, is connected to the opening 6. Therefore, the connection portion 10 is located on the inner wall of the opening 6. The first fuse portion 8 embedded in the opening 6 contacts the connecting portion 10 located on the inner wall of the opening 6. The first fuse portion 8 also contacts the main surface 2a of the semiconductor substrate 2 located on the bottom wall of the opening 6. As a result, the first conductive layer 4 and the second conductive layer 7 are electrically connected to the semiconductor substrate 2 by the connecting portion 10 and the first fuse portion 8. The electrical connection state of the first fuse portion (poly-Si fuse portion) 8 becomes the same state E2 as in the third step.

[0034] Examples of dry etching include the same types as those described in the third step.

[0035] Dry etching is performed while the substrate 1 is held by an electrostatic chuck (ESC chuck). After the dry etching process, when the substrate 1 is removed from the electrostatic chuck by pushing up the conductive lift pins, the residual charges in the first conductive layer 4 and the second conductive layer 7 flow from the first fuse portion 8 to the semiconductor substrate 2 and can be released from the semiconductor substrate 2 to the stage, allowing the substrate 1 to be removed from the electrostatic chuck without being damaged.

[0036] (5th step) The fifth step includes patterning the dielectric layer 3 by dry etching. The fifth step will be described with reference to Figs. 11 and 12. Fig. 11 is a top view of the processed substrate. Fig. 12 is a cross-sectional view of the processed substrate shown in Fig. 11 taken along line XII-XII.

[0037] The dielectric layer 3 of the processing substrate 1 is processed into a pattern shape by dry etching. Dry etching may be performed after forming a mask by photolithography. The purpose of patterning is to separate the dielectric layer 3 formed over the entire main surface 2a of the semiconductor substrate 2 into individual chips (to achieve the desired area per chip). The electrical connection state of the first fuse portion 8 (poly-Si fuse portion) is the same state E2 as in the third step.

[0038] Examples of dry etching include the same types as those described in the third step.

[0039] Dry etching is performed while the substrate 1 is held by an electrostatic chuck (ESC chuck). After the dry etching process, when the substrate 1 is removed from the electrostatic chuck by pushing up the conductive lift pins, the residual charges in the first conductive layer 4 and the second conductive layer 7 flow from the first fuse portion 8 to the semiconductor substrate 2 and can be released from the semiconductor substrate 2 to the stage, allowing the substrate 1 to be removed from the electrostatic chuck without being damaged.

[0040] (6th step) The sixth step includes providing a first contact electrode on the conductive layer, providing a second contact electrode on the semiconductor substrate, and providing a second conductive material portion that electrically connects the first contact electrode and the second contact electrode. The first contact electrode, the second contact electrode, and the second conductive material portion may be formed in this order, or the second conductive material portion may be formed after the first contact electrode and the second contact electrode, or all of these steps may be performed at once. The sixth step will be described with reference to FIGS. 13 to 15. FIG. 13 is a top view of the processed substrate. FIG. 14 is a cross-sectional view of the processed substrate shown in FIG. 13 taken along line XIV-XIV. FIG. 15 is a schematic circuit diagram showing the connection state of the first fuse portion (poly-Si fuse portion).

[0041] The conductive layer includes a first conductive layer 4 and a second conductive layer 7. The first contact electrode 11 is provided on the xy plane of the second conductive layer 7. Meanwhile, the second contact electrode 12 is provided on the main surface 2a of the semiconductor substrate 2. The second conductive material portion 13 is disposed, for example, between the first contact electrode 11 and the second contact electrode 12, at a position facing the first fuse portion 8 with the first contact electrode 11 sandwiched therebetween. The second conductive material portion 13 is in contact with both the first contact electrode 11 and the second contact electrode 12. The second conductive material portion 13 electrically connects the first contact electrode 11 and the second contact electrode 12. As a result, the first contact electrode 11 and the second contact electrode 12 are short-circuited by the second conductive material portion 13. Therefore, the second conductive material portion 13 acts as a second fuse portion (Al fuse portion) that electrically connects the conductive layer to the semiconductor substrate 2. Therefore, as shown in FIG. 15, there is a state E3 in which the conductive layer is electrically connected to the semiconductor substrate 2 by each of the first fuse portion 8 and the second fuse portion 13.

[0042] The first contact electrode 11, the second contact electrode 12, and the second conductive material portion 13 are each formed from a metal such as aluminum. The first contact electrode 11, the second contact electrode 12, and the second conductive material portion 13 are each obtained by forming a film by, for example, sputtering. Sputtering allows the first contact electrode 11, the second contact electrode 12, and the second conductive material portion 13 to be provided all at once, thereby reducing the number of steps required for manufacturing.

[0043] Before Al sputtering, a barrier layer may be provided on the second conductive layer 7 and the semiconductor substrate 2. The barrier layer may be made of, for example, Ti or TiN. The barrier layer may also be formed by, for example, sputtering.

[0044] (7th step) The seventh step includes forming an insulating layer (first insulating layer). The seventh step will be described with reference to Fig. 16 and Fig. 17. Fig. 16 is a top view of the processed substrate. Fig. 17 is a cross-sectional view of the processed substrate shown in Fig. 16 taken along line XVII-XVII.

[0045] A first insulating layer 14 is provided at a target position on the processing substrate 1 to insulate the first contact electrode 11, the second contact electrode 12, the first fuse portion 8, and the second fuse portion 13. The first insulating layer 14 is also called an interlayer insulating film. The first insulating layer 14 is formed from an insulating material such as tetraethoxysilane (TEOS) or polyethyleneimine (PI).

[0046] The state of the first fuse portion 8 and the second fuse portion 13 is the same state E3 as in the sixth step.

[0047] (8th step) The eighth step includes removing the first fuse portion 8 by dry etching. The eighth step will be described with reference to Figs. 18 to 20. Fig. 18 is a top view of the processed substrate. Fig. 19 is a cross-sectional view of the processed substrate shown in Fig. 18 taken along line XIX-XIX. Fig. 20 is a schematic circuit diagram showing the connection state of the first fuse portion (poly-Si fuse portion) and the second fuse portion (Al fuse portion).

[0048] The first fuse portion 8 embedded in the opening 6 is removed by dry etching. Dry etching may be performed after forming a mask by photolithography. This cuts off the electrical continuity (state E2) between the conductive layer (in this case, consisting of the first conductive layer 4 and the second conductive layer 7) and the semiconductor substrate 2. The cut state is indicated by symbol E4 in FIG. 20.

[0049] Examples of dry etching include the same types as those described in the third step.

[0050] Dry etching is performed while the process substrate 1 is held by an electrostatic chuck (ESC chuck). Although dry etching cuts off the electrical continuity via the first fuse portion 8, electrical continuity (state E3) between the conductive layer and the semiconductor substrate 2 is maintained by the second fuse portion 13. When the process substrate 1 is removed from the electrostatic chuck by pushing up the conductive lift pins, the residual charge in the conductive layer flows from the second fuse portion 13 to the semiconductor substrate 2 and can be released from the semiconductor substrate 2 to the stage, allowing the process substrate 1 to be removed from the electrostatic chuck without being damaged.

[0051] (9th step) The ninth step includes providing a first pad electrode on the first contact electrode and providing a second pad electrode on the second contact electrode. The first pad electrode and the second pad electrode may be formed in this order, or the order may be reversed, or they may be formed together. The ninth step will be described with reference to FIGS. 21 to 23. FIG. 21 is a top view of a processed substrate. FIG. 22 is a cross-sectional view of the processed substrate shown in FIG. 21 taken along line XXII-XXII. FIG. 23 is a schematic circuit diagram showing the connection state of the second fuse portion (Al fuse portion) and the third fuse portion (Al fuse portion).

[0052] The electrode layer 17, which will become the first pad electrode 15 and the second pad electrode 16, is provided on the xy plane including the first contact electrode 11 and the second contact electrode 12. A third conductive material portion 18 may also be embedded in the opening 6. The third conductive material portion 18 contacts the main surface 2a of the semiconductor substrate 2 located within the opening 6, and also contacts the connection portion 10 located on the inner wall of the opening 6. Therefore, the third conductive material portion 18 electrically connects the conductive layer constituting the connection portion 10 to the semiconductor substrate 2, and therefore functions as the third fuse portion 18. Therefore, the process substrate 1 has a conduction state E5 due to the second fuse portion 13 and the third fuse portion 18.

[0053] The electrode layer 17 (including the first pad electrode 15 and the second pad electrode 16) and the third fuse portion 18 are each formed from a metal such as aluminum. The electrode layer 17 and the third fuse portion 18 are each obtained by forming a film by, for example, sputtering.

[0054] (10th step) The tenth step includes patterning the electrode layer into a target shape by wet etching. The tenth step will be described with reference to Figs. 24 to 26. Fig. 24 is a top view of the processed substrate. Fig. 25 is a cross-sectional view of the processed substrate shown in Fig. 24 taken along line XIIIIII-XXIIII. Fig. 26 is a schematic circuit diagram showing the connection state of the second fuse portion (Al fuse portion) and the third fuse portion (Al fuse portion).

[0055] The electrode layer 17 is patterned into a desired shape by wet etching. The wet etching may be performed after forming a mask by photolithography. This separates the first pad electrode 15 and the second pad electrode 16 from each other. The first pad electrode 15 is in contact with the xy plane of the first contact electrode 11 and is electrically connected to the first contact electrode 11. The second pad electrode 16 is in contact with the xy plane of the second contact electrode 12 and is electrically connected to the second contact electrode 12. The second fuse portion 13 and the third fuse 18 embedded in the opening 6 are removed by wet etching. Removing the second fuse portion 13 forms a hole 19 between the first contact electrode 11 and the second contact electrode 12, with the main surface 2a of the semiconductor substrate 2 as its bottom wall. As a result, electrical continuity between the first contact electrode 11 and the second contact electrode 12 and electrical continuity between the semiconductor substrate 2 located within the first opening 6 and the connection portion 10 are cut off. Therefore, as shown in FIG. 26, the process substrate 1 is in a state E6 in which the electrical continuity through the second fuse portion 13 and the electrical continuity through the third fuse portion 18 are cut off.

[0056] Examples of wet etching agents include an aqueous solution containing HF and an aqueous solution containing mixed acid (e.g., containing acetic acid, phosphoric acid, and nitric acid). When the first pad electrode 15, the second pad electrode 16, and the third conductive material portion 18 are made of aluminum, an aqueous solution containing mixed acid can be used as the wet etching agent. When a barrier layer is provided, an aqueous solution containing HF can be used as the wet etching agent.

[0057] In Figure 25, for ease of understanding, it is shown as if there is a boundary between the first contact electrode 11 and the first pad electrode 15, and between the second contact electrode 12 and the second pad electrode 16, but there is not necessarily a boundary (interface).

[0058] (Step 11) The eleventh step includes providing an insulating layer (second insulating layer) and providing a mask layer. The eleventh step will be described with reference to Fig. 27. Fig. 27 shows a cross-sectional view of the processing substrate taken along the x-axis direction.

[0059] The entire upper surface of the process substrate 1 along the xy plane is covered with the second insulating layer 20. Therefore, the second insulating layer 20 is embedded in the hole 19 formed after the second fuse portion 13 is removed and in the opening 6 formed after the third fuse 18 is removed. The connection portion 10 is also covered with the second insulating layer 20. The second insulating layer 20 is formed from an insulating material such as tetraethoxysilane (TEOS) or polyethyleneimine (PI).

[0060] The mask layer 21 is provided on the second insulating layer 20. The mask layer 21 has a pattern shape with openings 22. The pattern shape is not particularly limited as long as it has the desired shape, and for example, it can be provided so that the first pad electrode 15 and the second pad electrode 16 are located on the upper surface along the xy plane of the capacitor. The mask layer 21 can be formed from organic materials such as polyimide, fluororesin, phenolic resin, acrylic resin, and novolac resin, or inorganic materials such as silicon oxide and silicon nitride. The mask layer 21 can be formed, for example, by an existing semiconductor process.

[0061] In FIG. 27, for ease of understanding, it is depicted as if there is a boundary between the first insulating layer 14 and the second insulating layer 20, but there is not necessarily a boundary (interface).

[0062] (12th step) The twelfth step includes patterning the second insulating layer into a target shape. The twelfth step will be described with reference to Figures 28 and 29. Figure 28 is a top view of a capacitor. Figure 29 is a cross-sectional view of the capacitor shown in Figure 28 taken along line XXVIIII-XXVIIII.

[0063] The second insulating layer 20 is patterned into a desired shape. Patterning can be performed by, for example, wet etching, patterning by exposure and development, or the like. As a result of patterning, as shown in FIG. 29 , the first pad electrode 15 and the second pad electrode 16 are positioned in the openings 23 in the second insulating layer 20 on the upper surface of the capacitor 31 along the xy plane. The first pad electrode 15 and the second pad electrode 16 are electrically insulated by the second insulating layer 20 interposed between them. The second insulating layer 20 also surrounds the outer wall of the second pad electrode 16. For ease of understanding, FIG. 29 shows a boundary between the first insulating layer 14 and the second insulating layer 20, but this does not necessarily mean that a boundary (interface) exists.

[0064] A capacitor 31 shown in FIGS. 28 and 29 is obtained by a method including the above-described first to twelfth steps. The capacitor 31 shown in FIGS. 28 and 29 includes a semiconductor substrate 2 having a main surface 2a with one or more recesses 5, conductive layers 4 and 7 provided in each recess 5 of the semiconductor substrate and on the main surface 2a, a dielectric layer 3 disposed between the conductive layers 4 and 7 and the semiconductor substrate 2, connection portions 10 extending directly from one or more of the conductive layers 4 and 7, and an opening 6 connected to the connection portion 10 and having a bottom wall defined by the main surface 2a of the semiconductor substrate 2. The capacitor 31 has a hole 19 formed by removing the second fuse portion 13. An insulating layer 20 (an insulating material) may be embedded in the opening 6 and the hole 19.

[0065] When the process substrate 1 on which the first fuse portion 8 was formed was clamped to the electrostatic chuck, a pattern shape was processed in the conductive layer by reactive ion etching, and then the process substrate 1 was removed from the electrostatic chuck 10 times. In every case, the process substrate 1 was removed from the electrostatic chuck without causing any damage, such as cracks, to the process substrate 1. Furthermore, when the process substrate 1 was removed from the electrostatic chuck 10 times after the first fuse portion 8 was removed by reactive ion etching, the process substrate 1 was removed from the electrostatic chuck 10 times. In every case, the process substrate 1 was removed from the electrostatic chuck without causing any damage, such as cracks, to the process substrate 1.

[0066] Note that an embodiment may include all of steps 1 to 12, or some steps may be omitted. Also, other steps such as forming a mask layer, forming a barrier layer, or cleaning may be performed between any of steps 1 to 12.

[0067] The method and capacitor of the embodiment can be applied to, for example, a capacitor having a semiconductor substrate made of a Si wafer having a diameter of 8 inches or more (for example, a capacitor used in a memory such as a DRAM).

[0068] According to at least one of the etching methods described above, after a pattern shape is formed on the conductive layer by dry etching, the semiconductor substrate is electrically connected to the conductive layer via the first conductive material portion and the connection portion. Therefore, after dry etching, the substrate can be removed from the electrostatic chuck without causing damage, such as cracks, to the substrate. Furthermore, when the first conductive material portion is removed by dry etching, the electrical connection between the conductive layer and the semiconductor substrate by the first conductive material portion is severed. After that, the electrical connection between the conductive layer and the semiconductor substrate is ensured by the second conductive material portion. Therefore, after the first conductive material portion is removed by dry etching, the substrate can be removed from the electrostatic chuck without causing damage, such as cracks. Therefore, the method and capacitor of the embodiment can reduce damage, such as cracks, to the substrate.

[0069] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0070] 1,100...processing substrate, 2, 101...semiconductor substrate, 2a, 101a...one main surface, 2b, 101b...doped layer, 2c, 101c...other main surface, 101d...end surface, 3, 102...dielectric layer, 4...first conductive layer, 5, 104...recess (trench), 6...opening, 7...second conductive layer, 8...first fuse portion, 10...connection portion, 11...first contact electrode, 12...second contact electrode, 13...second fuse portion, 14...first insulating layer, 15...first pad electrode, 16...second pad electrode, 17...electrode layer, 18...third fuse portion, 19...hole, 20...second insulating layer, 21...mask layer, 31...capacitor, 200...stage, 201...conductive lift pin, 202...charge.

Claims

1. In a processing substrate including a semiconductor substrate having a main surface with one or more recesses, a conductive layer provided on the main surface of the semiconductor substrate and in the one or more recesses, and a dielectric layer disposed between the conductive layer and the semiconductor substrate, an opening is formed by opening the dielectric layer and the conductive layer located on the main surface of the semiconductor substrate; providing a first conductive material portion on the major surface located within the opening; processing the conductive layer by dry etching to form a pattern shape including a connection portion extending from the conductive layer and connected to the opening; providing a first contact electrode electrically connected to the conductive layer, a second contact electrode electrically connected to the semiconductor substrate, and a second conductive material portion electrically connecting the first contact electrode and the second contact electrode; removing the first conductive material portion by dry etching to cut off the electrical connection between the connection portion and the semiconductor substrate; removing the second conductive material portion by wet etching to cut off the electrical connection between the first contact electrode and the second contact electrode; A method for manufacturing a capacitor, comprising:

2. 2. The method for manufacturing a capacitor according to claim 1, wherein the semiconductor substrate is a substrate containing Si, and the conductive layer and the first conductive material portion each contain poly-Si.

3. The method for manufacturing a capacitor according to claim 1 , wherein the first contact electrode, the second contact electrode, and the second conductive material portion each contain Al.

4. 2. The method for manufacturing a capacitor according to claim 1, wherein the dry etching is performed while the processing substrate is held by an electrostatic chuck.

5. 2. The method for manufacturing a capacitor according to claim 1, further comprising, after removing the first conductive material portion by dry etching, providing a first pad electrode electrically connected to the first contact electrode, a second pad electrode electrically connected to the second contact electrode, and a third conductive material portion for electrically connecting the main surface of the semiconductor substrate located within the opening to the connection portion.

6. a semiconductor substrate having a major surface with one or more recesses; a conductive layer disposed within the one or more recesses and on the main surface of the semiconductor substrate; a dielectric layer disposed between the conductive layer and the semiconductor substrate; a connection portion formed by extending the conductive layer located on the main surface of the semiconductor substrate; an opening connected to the connection portion and having the main surface of the semiconductor substrate as a bottom wall; a first contact electrode electrically connected to the conductive layer; a second contact electrode electrically connected to the semiconductor substrate; a hole located between the first contact electrode and the second contact electrode, the hole having a bottom wall on the main surface of the semiconductor substrate; an insulating layer provided in the opening and the hole; A capacitor comprising:

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