Printed circuit board and electronic control device

Abstract

To ensure the degree of freedom of a wiring pattern arrangement while improving a thermal efficiency of a printed circuit board.SOLUTION: A printed circuit board 2 includes: dielectric layers 21 to 29; conductor pattern layers 11 to 20; a positive electrode terminal through hole 31; a positive electrode through via 35; and a first positive electrode inner layer via 37. The positive terminal through hole 31 penetrates the dielectric layers 21 to 29, and a positive terminal 101 of a capacitor 100 is inserted therein. The positive electrode through via 35 penetrates the dielectric layers 21 to 29 and is connected to the positive electrode terminal through hole 31 by a conductor pattern layer. The first positive electrode inner layer via 37 penetrates dielectric layers 27 to 29. The positive electrode through via 35 and the first positive electrode inner layer via 37 are connected to each other by the conductor pattern layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a printed circuit board and an electronic control device. [Background technology]

[0002] When connecting a printed circuit board and the terminals of electronic components to be connected to the printed circuit board by soldering, the heat generated during soldering is not easily transmitted to the back side, resulting in poor solderability. When solder connectivity is poor, cracks will form inside the solder when thermal stress is applied, and as the cracks gradually increase, the electrical connection will be lost, leading to failure.

[0003] Patent document 1 describes a technology that efficiently transfers heat during soldering to the back surface by arranging multiple through vias that are thermally connected to the through holes and pass through the printed circuit board around the through holes into which the terminals of electronic components are inserted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-17560 Summary of the Invention [Problem to be solved by the invention]

[0005] After detailed investigation by the inventors, it was found that increasing the number of through vias to improve thermal efficiency increases the number of situations in which wiring patterns must be placed around the through vias, which may reduce the freedom to place wiring patterns on a printed circuit board (i.e., the freedom to design artwork).

[0006] The present disclosure aims to improve the thermal efficiency of a printed circuit board while ensuring the degree of freedom in wiring pattern layout. [Means for solving the problem]

[0007] One aspect of the present disclosure is a printed circuit board (2) comprising dielectric layers (21 to 29) from layer 1 to layer (N-1), where N is an integer of 3 or greater, a plurality of conductor pattern layers (11 to 20) from layer 1 to layer N, a through hole (31), a through via (35), and an inner layer via (37).

[0008] A plurality of conductive pattern layers from the first layer to the Nth layer are alternately stacked with a plurality of dielectric layers. The through-hole penetrates the dielectric layers from the first layer to the (N-1)th layer, has a through-hole conductor (31a) formed on the inner circumferential surface, and receives a terminal (101) of a mounting component (100) inserted therein.

[0009] The through via penetrates multiple dielectric layers from the first layer to the (N-1)th layer, has a through via conductor (35a) formed on its inner surface, and is connected to the through hole by at least one of the conductive pattern layers from the first layer to the (N-1)th layer.

[0010] The inner layer via penetrates each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-1)th layer to the (N-1)th layer, and an inner layer via conductor (37a) is formed on the inner surface.

[0011] The through vias and inner layer vias are connected to each other by at least one conductor pattern layer from the second conductor pattern layer to the (N-1)th conductor pattern layer. The printed circuit board of the present disclosure configured in this manner has inner layer vias connected to through vias, thereby increasing the number of paths for heat conduction between the first layer of conductive pattern layer and the Nth layer of conductive pattern layer, thereby improving the thermal efficiency of the printed circuit board.

[0012] Furthermore, in the printed circuit board of the present disclosure, the inner layer vias are formed to penetrate each of the dielectric layers from any one of the second layer to the (N-1)th layer to the (N-1)th layer. Therefore, the printed circuit board of the present disclosure can change the number of dielectric layers through which the inner layer vias penetrate and the arrangement of the inner layer vias depending on the wiring pattern within the printed circuit board. This allows the printed circuit board of the present disclosure to ensure flexibility in wiring pattern arrangement.

[0013] As described above, the printed circuit board of the present disclosure can improve the thermal efficiency of the printed circuit board while ensuring the degree of freedom in arranging wiring patterns. Another aspect of the present disclosure is an electronic control device (1) including a mounting component (100) and a printed circuit board (2) on which the mounting component is mounted.

[0014] The printed circuit board includes dielectric layers (21-29) from the first layer to the (N-1)th layer, where N is an integer equal to or greater than 3, a plurality of conductor pattern layers (11-20) from the first layer to the Nth layer, a through hole (31), a through via (35), and an inner layer via (37). The through vias and inner layer vias are connected to each other by at least one conductor pattern layer from the second layer to the (N-1)th layer.

[0015] The electronic control device of the present disclosure configured in this manner is a device that includes the printed circuit board of the present disclosure, and can obtain the same effects as the printed circuit board of the present disclosure. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 2 is a block diagram showing the configuration of an electronic control device. [Figure 2] 1 is a cross-sectional view showing the configuration of a printed circuit board according to a first embodiment. [Figure 3] 3A and 3B are diagrams illustrating the shape of a conductive pattern layer on a mounting surface. [Figure 4] 1A and 1B are diagrams showing the shape of a conductive pattern layer on a dielectric layer inside a substrate. [Figure 5] 10A and 10B are diagrams showing the shape of a conductive pattern layer on a soldering surface. [Figure 6] FIG. 10 is a cross-sectional view showing the configuration of a printed circuit board according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] [First embodiment] A first embodiment of the present disclosure will be described below with reference to the drawings. The electronic control device 1 of this embodiment is a device that controls a control target (not shown), and as shown in Fig. 1, includes a printed circuit board 2. The electronic control device 1 is configured by accommodating the printed circuit board 2 in a housing (not shown).

[0018] On the printed circuit board 2, a microcomputer 3, a drive circuit 4, and a power supply circuit 5 are mounted. The microcomputer 3 executes various control processes for controlling the controlled object, and outputs a control signal indicating a control amount for controlling the controlled object to the drive circuit 4.

[0019] Based on a control signal from the microcomputer 3, the drive circuit 4 outputs a drive signal for driving the controlled object to the controlled object. The power supply circuit 5 is a circuit that generates a predetermined power supply voltage for operating the microcomputer 3 and the drive circuit 4.

[0020] 2, the printed circuit board 2 includes ten conductor pattern layers 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20, and nine dielectric layers 21, 22, 23, 24, 25, 26, 27, 28, and 29. The printed circuit board 2 is formed by alternately stacking the ten conductor pattern layers 11 to 20 and the nine dielectric layers 21 to 29 along a stacking direction D1.

[0021] Therefore, the conductor pattern layer 11 is arranged on the dielectric layer 21. The conductor pattern layer 12 is arranged between the dielectric layer 21 and the dielectric layer 22. The conductor pattern layer 13 is arranged between the dielectric layer 22 and the dielectric layer 23. The conductor pattern layer 14 is arranged between the dielectric layer 23 and the dielectric layer 24. The conductor pattern layer 15 is arranged between the dielectric layer 24 and the dielectric layer 25. The conductor pattern layer 16 is arranged between the dielectric layer 25 and the dielectric layer 26. The conductor pattern layer 17 is arranged between the dielectric layer 26 and the dielectric layer 27. The conductor pattern layer 18 is arranged between the dielectric layer 27 and the dielectric layer 28. The conductor pattern layer 19 is arranged between the dielectric layer 28 and the dielectric layer 29. The dielectric layer 29 is arranged on the conductor pattern layer 20.

[0022] The printed circuit board 2 is formed with a positive terminal through-hole 31 into which a positive terminal 101 of the capacitor 100 is inserted, and a negative terminal through-hole 32 into which a negative terminal 102 of the capacitor 100 is inserted. The capacitor 100 is, for example, a component of the power supply circuit 5. In this embodiment, the capacitor 100 is an aluminum electrolytic capacitor.

[0023] The positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32 are formed to penetrate the dielectric layers 21 to 29. A conductor 31a is formed over the entire inner circumferential surface of the positive electrode terminal through-hole 31. A conductor 32a is formed over the entire inner circumferential surface of the negative electrode terminal through-hole 32. Hereinafter, the conductor 31a and the conductor 32a will be referred to as the positive electrode terminal through-hole conductor 31a and the negative electrode terminal through-hole conductor 32a, respectively.

[0024] The printed circuit board 2 includes a solder resist 33. The solder resist 33 is disposed on the conductive pattern layer 11 and on the area of ​​the dielectric layer 21 where the conductive pattern layer 11 is not disposed. However, the solder resist 33 is disposed so as not to cover the openings of the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32. This forms resist openings 33a so that the openings of the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32 are exposed.

[0025] The positive electrode terminal 101 and the negative electrode terminal 102 of the capacitor 100 are linear conductors. The positive electrode terminal 101 and the negative electrode terminal 102 are inserted into the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32, respectively, through the resist opening 33a. The ends of the positive electrode terminal 101 and the negative electrode terminal 102 protrude from the openings of the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32 on the surface of the plate-shaped printed circuit board 2 opposite to the surface on which the resist opening 33a is formed.

[0026] Hereinafter, of the two surfaces of the printed circuit board 2 formed in a plate shape, the surface on which the main body 103 of the capacitor 100 is arranged will be referred to as the mounting surface 2a. Also, of the two surfaces of the printed circuit board 2, the surface on which the ends of the positive terminal 101 and the negative terminal 102 of the capacitor 100 protrude will be referred to as the soldering surface 2b.

[0027] With the positive terminal 101 and negative terminal 102 of the capacitor 100 inserted into the positive terminal through-hole 31 and the negative terminal through-hole 32, respectively, the capacitor 100 is fixed to the printed circuit board 2 by filling solder 34 between the positive terminal 101 and the positive terminal through-hole 31 and between the negative terminal 102 and the negative terminal through-hole 32.

[0028] As shown in FIGS. 2, 3, 4 and 5, a plurality of positive electrode through vias 35 are formed around the positive electrode terminal through hole 31, and a plurality of negative electrode through vias 36 are formed around the negative electrode terminal through hole 32.

[0029] The positive electrode through via 35 and the negative electrode through via 36 are formed to penetrate the dielectric layers 21 to 29. A conductor 35a is formed over the entire inner circumferential surface of the positive electrode through via 35. A conductor 36a is formed over the entire inner circumferential surface of the negative electrode through via 36. Hereinafter, the conductor 35a and the conductor 36a will be referred to as the positive electrode through via conductor 35a and the negative electrode through via conductor 36a, respectively.

[0030] As shown in Figures 2 and 3, the conductor pattern layer 11 includes a first positive electrode connection pattern 111 that connects the positive electrode terminal through-hole conductor 31a and the positive electrode through-hole via conductor 35a, and a first negative electrode connection pattern 112 that connects the negative electrode terminal through-hole conductor 32a and the negative electrode through-hole via conductor 36a.

[0031] As shown in Figure 2, the conductive pattern layer 12 includes a first positive electrode connection pattern 121 that connects the positive electrode terminal through-hole conductor 31a and the positive electrode through-via conductor 35a, and a first negative electrode connection pattern 122 that connects the negative electrode terminal through-hole conductor 32a and the negative electrode through-via conductor 36a.

[0032] The conductor pattern layers 13, 14, 15, 16, 17, 18, 19, 20 each include a first positive electrode connection pattern 131, 141, 151, 161, 171, 181, 191, 201 that connects the positive electrode terminal through-hole conductor 31a and the positive electrode through-hole via conductor 35a, and a first negative electrode connection pattern 132, 142, 152, 162, 172, 182, 192, 202 that connects the negative electrode terminal through-hole conductor 32a and the negative electrode through-hole via conductor 36a.

[0033] 2 and 4, a plurality of first positive electrode inner layer vias 37 are formed around a plurality of positive electrode through vias 35, and a plurality of first negative electrode inner layer vias 38 are formed around a plurality of negative electrode through vias 36. Furthermore, a plurality of second positive electrode inner layer vias 39 are formed around a plurality of first positive electrode inner layer vias 37, and a plurality of second negative electrode inner layer vias 40 are formed around a plurality of first negative electrode inner layer vias 38.

[0034] The plurality of first positive electrode inner layer vias 37 are arranged in a semicircle so as to cover the plurality of positive electrode through vias 35 arranged in a semicircle. The plurality of first negative electrode inner layer vias 38 are arranged in a semicircle so as to cover the plurality of negative electrode through vias 36 arranged in a semicircle.

[0035] The plurality of second positive electrode inner layer vias 39 are arranged in a semicircle so as to cover the plurality of first positive electrode inner layer vias 37 arranged in a semicircle. The plurality of second negative electrode inner layer vias 40 are arranged in a semicircle so as to cover the plurality of first negative electrode inner layer vias 38 arranged in a semicircle.

[0036] The first positive electrode inner layer via 37 and the first negative electrode inner layer via 38 are formed to penetrate the dielectric layers 27, 28, and 29. A conductor 37a is formed over the entire inner circumferential surface of the first positive electrode inner layer via 37. A conductor 38a is formed over the entire inner circumferential surface of the first negative electrode inner layer via 38. Hereinafter, the conductor 37a and the conductor 38a will be referred to as the first positive electrode inner layer via conductor 37a and the first negative electrode inner layer via conductor 38a, respectively.

[0037] The second positive electrode inner layer via 39 and the second negative electrode inner layer via 40 are formed to penetrate the dielectric layers 27, 28, and 29. A conductor 39a is formed over the entire inner circumferential surface of the second positive electrode inner layer via 39. Similarly, a conductor 40a is formed over the entire inner circumferential surface of the second negative electrode inner layer via 40. Hereinafter, the conductor 39a and the conductor 40a will be referred to as the second positive electrode inner layer via conductor 39a and the second negative electrode inner layer via conductor 40a, respectively.

[0038] The conductor pattern layers 17, 18, 19, 20 each include a second positive electrode connection pattern 173, 183, 193, 203 that connects the positive electrode through via conductor 35a, the first positive electrode inner layer via conductor 37a, and the second positive electrode inner layer via conductor 39a, and a second negative electrode connection pattern 174, 184, 194, 204 that connects the negative electrode through via conductor 36a, the first negative electrode inner layer via conductor 38a, and the second negative electrode inner layer via conductor 40a.

[0039] The printed circuit board 2 configured in this manner includes first to ninth dielectric layers 21 to 29, first to tenth conductive pattern layers 11 to 20, a positive electrode terminal through hole 31, a positive electrode through via 35, and a first positive electrode inner layer via 37.

[0040] Positive terminal through-hole 31 passes through first to ninth dielectric layers 21 to 29, has positive terminal through-hole conductor 31a formed on its inner circumferential surface, and has positive terminal 101 of capacitor 100 inserted therein.

[0041] The positive electrode through via 35 penetrates the first to ninth dielectric layers 21 to 29, has a positive electrode through via conductor 35a formed on its inner surface, and is connected to the positive electrode terminal through hole 31 by at least one of the first to ninth conductive pattern layers 11 to 19.

[0042] The first positive electrode inner layer via 37 penetrates through each of the seventh dielectric layer 27 to the ninth dielectric layer 29, and has a first positive electrode inner layer via conductor 37a formed on the inner circumferential surface.

[0043] The positive electrode through via 35 and the first positive electrode inner layer via 37 are connected to each other by the conductive pattern layers 17, 18, and 19. Such a printed circuit board 2 has a first positive electrode inner layer via 37 connected to the positive electrode through via 35, thereby increasing the number of paths for conducting heat between the first conductive pattern layer 11 and the tenth conductive pattern layer 20, thereby improving the thermal efficiency of the printed circuit board 2.

[0044] Furthermore, in the printed circuit board 2, the first positive electrode inner layer vias 37 are formed so as to penetrate each of the dielectric layers from any one of the second to ninth dielectric layers 22 to 29 to the ninth dielectric layer 29. Therefore, in the printed circuit board 2, the number of dielectric layers through which the first positive electrode inner layer vias 37 penetrate and the arrangement of the first positive electrode inner layer vias 37 can be changed according to the wiring pattern within the printed circuit board 2. This allows the printed circuit board 2 to ensure a degree of freedom in the arrangement of the wiring pattern.

[0045] As a result, the printed circuit board 2 can improve the thermal efficiency of the printed circuit board 2 while ensuring the degree of freedom in arranging the wiring patterns. The printed circuit board 2 also has a second positive electrode inner layer via 39, which is arranged on the opposite side of the first positive electrode inner layer via 37 from the positive electrode through via 35, penetrates through each of the dielectric layers 27 to 29 from the seventh dielectric layer 27 to the ninth dielectric layer 29, and has a second positive electrode inner layer via conductor 39a formed on its inner surface.

[0046] Such a printed circuit board 2 can further increase the paths for heat conduction between the first conductive pattern layer 11 and the tenth conductive pattern layer 20, thereby further improving the thermal efficiency of the printed circuit board 2.

[0047] In the embodiment described above, the capacitor 100 corresponds to a mounted component, the positive terminal 101 corresponds to a terminal, the positive terminal through hole 31 corresponds to a through hole, the positive terminal through hole conductor 31a corresponds to a through hole conductor, the positive through via 35 corresponds to a through via, and the positive through via conductor 35a corresponds to a through via conductor.

[0048] In addition, the first positive electrode inner layer via 37 corresponds to an inner layer via, the first positive electrode inner layer via conductor 37a corresponds to an inner layer via conductor, the second positive electrode inner layer via 39 corresponds to an additional inner layer via, and the second positive electrode inner layer via conductor 39a corresponds to an additional inner layer via conductor.

[0049] [Second embodiment] A second embodiment of the present disclosure will be described below with reference to the drawings. In the second embodiment, only the parts that are different from the first embodiment will be described. The same reference numerals will be used to designate common components.

[0050] The electronic control device 1 of the second embodiment differs from the first embodiment in that the shapes of the first positive electrode inner layer via 37, the first negative electrode inner layer via 38, the second positive electrode inner layer via 39, and the second negative electrode inner layer via 40 are changed.

[0051] As shown in FIG. 6, the first positive electrode inner layer via 37 is composed of divided vias 41, 42, and 43 and third positive electrode connection patterns 145 and 175. Divided via 41 is formed to penetrate dielectric layers 22-23. A conductor 41a is formed over the entire inner circumferential surface of divided via 41. Divided via 42 is formed to penetrate dielectric layers 24-26. A conductor 42a is formed over the entire inner circumferential surface of divided via 42. Divided via 43 is formed to penetrate dielectric layers 27-29. A conductor 43a is formed over the entire inner circumferential surface of divided via 43. Hereinafter, conductors 41a, 42a, 43a will be referred to as divided via conductors 41a, 42a, 43a, respectively.

[0052] The divided via 41 is connected to the positive electrode through via 35 by the second positive electrode connection pattern 123. The divided via 42 is connected to the positive electrode through via 35 by the second positive electrode connection pattern 153. The divided via 43 is connected to the positive electrode through via 35 by the second positive electrode connection patterns 183, 193, and 203.

[0053] Split via 41 and split via 42 are arranged so that the distance between split via 41 and positive terminal through hole 31 is shorter than the distance between split via 42 and positive terminal through hole 31. Furthermore, split via 42 and split via 43 are arranged so that the distance between split via 42 and positive terminal through hole 31 is shorter than the distance between split via 43 and positive terminal through hole 31.

[0054] The conductive pattern layer 14 includes a third positive electrode connecting pattern 145 that connects the split via conductor 41a and the split via conductor 42a. The conductive pattern layer 17 includes a third positive electrode connecting pattern 175 that connects the split via conductor 42a and the split via conductor 43a.

[0055] The first negative electrode inner layer via 38 is composed of divided vias 51, 52, and 53 and third negative electrode connection patterns 146 and 176. Divided via 51 is formed to penetrate dielectric layers 22-23. A conductor 51a is formed over the entire inner circumferential surface of divided via 51. Divided via 52 is formed to penetrate dielectric layers 24-26. A conductor 52a is formed over the entire inner circumferential surface of divided via 52. Divided via 53 is formed to penetrate dielectric layers 27-29. A conductor 53a is formed over the entire inner circumferential surface of divided via 53. Hereinafter, conductors 51a, 52a, 53a will be referred to as divided via conductors 51a, 52a, 53a, respectively.

[0056] The divided via 51 is connected to the negative electrode through via 36 by the second negative electrode connection pattern 124. The divided via 52 is connected to the negative electrode through via 36 by the second negative electrode connection pattern 154. The divided via 53 is connected to the negative electrode through via 36 by the second negative electrode connection patterns 184, 194, and 204.

[0057] Split via 51 and split via 52 are arranged so that the distance between split via 51 and negative terminal through hole 32 is shorter than the distance between split via 52 and negative terminal through hole 32. Furthermore, split via 52 and split via 53 are arranged so that the distance between split via 52 and negative terminal through hole 32 is shorter than the distance between split via 53 and negative terminal through hole 32.

[0058] The conductive pattern layer 14 includes a third negative electrode connecting pattern 146 that connects the split via conductor 51a and the split via conductor 52a. The conductive pattern layer 17 includes a third negative electrode connecting pattern 176 that connects the split via conductor 52a and the split via conductor 53a.

[0059] The second positive electrode inner layer via 39 is composed of divided vias 61 and 62 and a third positive electrode connection pattern 185. Divided via 61 is formed to penetrate dielectric layer 27. A conductor 61a is formed over the entire inner circumferential surface of divided via 61. Divided via 62 is formed to penetrate dielectric layers 28-29. A conductor 62a is formed over the entire inner circumferential surface of divided via 62. Hereinafter, conductors 61a and 62a will be referred to as divided via conductors 61a and 62a, respectively.

[0060] The divided via 61 is connected to the divided via 43 by the fourth positive electrode connection pattern 177. The divided via 62 is connected to the divided via 43 by the fourth positive electrode connection patterns 197 and 207. The split via 61 and the split via 62 are arranged so that the distance between the split via 61 and the positive terminal through hole 31 is shorter than the distance between the split via 62 and the positive terminal through hole 31 .

[0061] The conductive pattern layer 18 includes a third positive electrode connecting pattern 185 that connects the divided via conductor 61a and the divided via conductor 62a. The second negative electrode inner layer via 40 is composed of divided vias 71 and 72 and a third negative electrode connection pattern 186.

[0062] Divided via 71 is formed to penetrate dielectric layer 27. A conductor 71a is formed over the entire inner circumferential surface of divided via 71. Divided via 72 is formed to penetrate dielectric layers 28-29. A conductor 72a is formed over the entire inner circumferential surface of divided via 72. Hereinafter, conductors 71a and 72a will be referred to as divided via conductors 71a and 72a, respectively.

[0063] The divided via 71 is connected to the divided via 53 by the fourth positive electrode connection pattern 178. The divided via 62 is connected to the divided via 53 by the fourth positive electrode connection patterns 198 and 208. The split via 71 and the split via 72 are arranged so that the distance between the split via 71 and the negative terminal through hole 32 is shorter than the distance between the split via 72 and the negative terminal through hole 32 .

[0064] The conductive pattern layer 18 includes a third negative electrode connecting pattern 186 that connects the divided via conductor 71a and the divided via conductor 72a. In the printed circuit board 2 configured in this manner, the first positive electrode inner layer via 37 and the second positive electrode inner layer via 39 are arranged so that the distance to the positive electrode terminal through hole 31 becomes shorter as they approach the tenth conductive pattern layer 20 and the first conductive pattern layer 11. This allows the printed circuit board 2 to further ensure freedom in wiring pattern arrangement on the mounting surface 2a side on which the capacitor 100 is mounted.

[0065] The first positive electrode inner layer via 37 is formed by a plurality of divided vias 41, 42, 43 that penetrate at least one dielectric layer and penetrate different dielectric layers. The divided via 41 penetrates the dielectric layers 22 to 23. The divided via 42 penetrates the dielectric layers 24 to 26. The divided via 43 penetrates the dielectric layers 27 to 29. Specifically, the first positive electrode inner layer via 37 is formed in a non-linear shape along the stacking direction D1 by connecting the divided vias 41, 42, 43 with the third positive electrode connection patterns 145, 175.

[0066] The second positive electrode inner layer via 39 is formed by a plurality of divided vias 61, 62 that penetrate at least one dielectric layer. The divided via 61 penetrates the dielectric layer 27. The divided via 62 penetrates the dielectric layers 28 to 29. Specifically, the second positive electrode inner layer via 39 is formed in a non-linear shape along the stacking direction D1 by connecting the divided vias 61, 62 with the third positive electrode connection pattern 185.

[0067] Such a printed circuit board 2 allows the arrangement of the divided vias 41, 42, 43 and the divided vias 61, 62 to be changed to change the shapes of the first positive electrode inner layer via 37 and the second positive electrode inner layer via 39 according to the wiring pattern within the printed circuit board 2, thereby further ensuring freedom in circuit design.

[0068] Although one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment and can be implemented in various modifications. [Variation 1] In the above embodiment, the first to tenth conductive pattern layers 11 to 20 are provided, but the number of conductive pattern layers may be three or more.

[0069] [Variation 2] In the above embodiment, a form in which a capacitor 100 is mounted on a printed circuit board 2 is shown, but the mounted component mounted on the printed circuit board 2 is not limited to the capacitor 100, and may be any electronic component having a terminal that is inserted into a through hole.

[0070] [Variation 3] In the first embodiment, the first positive electrode inner layer via 37, the first negative electrode inner layer via 38, the second positive electrode inner layer via 39, and the second negative electrode inner layer via 40 penetrate the dielectric layers 27 to 29. However, the first positive electrode inner layer via 37, the first negative electrode inner layer via 38, the second positive electrode inner layer via 39, and the second negative electrode inner layer via 40 may penetrate the dielectric layers from any one of the dielectric layers 22 to 29 to the dielectric layer 29. For example, the first positive electrode inner layer via 37, the first negative electrode inner layer via 38, the second positive electrode inner layer via 39, and the second negative electrode inner layer via 40 may penetrate the dielectric layers 27 to 29 or the dielectric layers 22 to 29.

[0071] In the above embodiments, multiple functions of one component may be realized by multiple components, or one function of one component may be realized by multiple components. Furthermore, multiple functions of multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Furthermore, part of the configuration of the above embodiments may be omitted. Furthermore, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments. [Explanation of symbols]

[0072] 1...Electronic control device, 2...Printed circuit board, 11 to 20...Conductive pattern layers, 21 to 29...Dielectric layers, 31...Positive electrode terminal through hole, 31a...Positive electrode terminal through hole conductor, 35...Positive electrode through via, 35a...Positive electrode through via conductor, 37...First positive electrode inner layer via, 37a...First positive electrode inner layer via conductor, 100...Capacitor, 101...Positive electrode terminal, 102...Negative electrode terminal

Claims

1. Dielectric layers (21 to 29) from the first layer to the (N-1)th layer, where N is an integer of 3 or more; a plurality of conductor pattern layers (11 to 20) from a first layer to an Nth layer alternately stacked with the plurality of dielectric layers; a through-hole (31) that penetrates through the dielectric layers from the first layer to the (N-1)th layer, has a through-hole conductor (31a) formed on the inner circumferential surface, and into which a terminal (101) of a mounting component (100) is inserted; a through via (35) that penetrates the plurality of dielectric layers from the first layer to the (N-1)th layer, has a through via conductor (35a) formed on its inner circumferential surface, and is connected to the through hole by at least one of the conductor pattern layers from the first layer to the (N-1)th layer; an inner layer via (37) that penetrates each of the dielectric layers from any one of the second layer to the (N-1)th layer to the (N-1)th layer, and has an inner layer via conductor (37a) formed on its inner circumferential surface; Equipped with The printed circuit board (2) includes a through via and an inner layer via, which are connected to each other by at least one of the conductor pattern layers from the second layer to the (N-1)th layer.

2. 2. The printed circuit board according to claim 1, further comprising: The printed circuit board is provided with an additional inner layer via (39) that is positioned on the opposite side of the through via across the inner layer via, penetrates each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-1)th layer to the dielectric layer of the (N-1)th layer, and has an additional inner layer via conductor (39a) formed on its inner surface.

3. 3. The printed circuit board according to claim 2, A printed circuit board in which at least one of the inner layer vias and the additional inner layer vias is arranged so that the distance to the through hole becomes shorter as it approaches the conductive pattern layer of the first layer from the conductive pattern layer of the Nth layer.

4. 4. The printed circuit board according to claim 2 or 3, At least one of the inner layer via and the additional inner layer via is formed by a plurality of divided vias (41, 42, 43, 61, 62) that penetrate at least one of the dielectric layers.

5. 5. The printed circuit board according to claim 4, At least one of the inner layer via and the additional inner layer via is formed non-linearly along the stacking direction in which the multiple dielectric layers are stacked by connecting multiple divided vias with at least one of the conductor pattern layers.

6. The device includes a mounting component (100) and a printed circuit board (2) on which the mounting component is mounted, The printed circuit board is Dielectric layers (21 to 29) from the first layer to the (N-1)th layer, where N is an integer of 3 or more; a plurality of conductor pattern layers (11 to 20) from a first layer to an Nth layer alternately stacked with the plurality of dielectric layers; a through-hole (31) that penetrates the dielectric layers from the first layer to the (N-1)th layer, has a through-hole conductor (31a) formed on the inner circumferential surface, and into which a terminal (101) of the mounting component is inserted; a through via (35) that penetrates the plurality of dielectric layers from the first layer to the (N-1)th layer, has a through via conductor (35a) formed on its inner circumferential surface, and is connected to the through hole by at least one of the conductor pattern layers from the first layer to the (N-1)th layer; an inner layer via (37) that penetrates each of the dielectric layers from any one of the second layer to the (N-1)th layer to the (N-1)th layer, and has an inner layer via conductor (37a) formed on its inner circumferential surface; Equipped with The through vias and the inner layer vias are connected to each other by at least one of the conductor pattern layers from the second layer to the (N-1)th layer.

7. 7. The electronic control device according to claim 6, further comprising: An electronic control device comprising an additional inner layer via (39) positioned on the opposite side of the through via across the inner layer via, penetrating each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-1)th layer to the (N-1)th layer, and having an additional inner layer via conductor (39a) formed on its inner surface.

8. 8. The electronic control device according to claim 7, An electronic control device in which at least one of the inner layer vias and the additional inner layer vias is arranged so that the distance to the through hole becomes shorter as it approaches the conductive pattern layer of the Nth layer toward the conductive pattern layer of the first layer.

9. The electronic control device according to claim 7 or 8, At least one of the inner layer via and the additional inner layer via is formed by a plurality of divided vias (41, 42, 43, 61, 62) that penetrate at least one of the dielectric layers.

10. 10. The electronic control device according to claim 9, An electronic control device in which at least one of the inner layer vias and the additional inner layer vias is formed non-linearly along the stacking direction in which the multiple dielectric layers are stacked by connecting multiple divided vias with at least one of the conductor pattern layers.

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