Substrate with built-in electronic component and manufacturing method thereof

Abstract

To provide a substrate with a built-in electronic component that does not increase in size in a width direction even when an electronic component become thicker, and a manufacturing method thereof .SOLUTION: An electronic component-embedded substrate 1 includes: a first substrate 10; a second substrate 30 on which an electronic component 50 is mounted; a substrate connecting member 70 that electrically connects a first pad 14p of the first substrate to a second pad 34p of the second substrate; and a sealing resin 90. The first substrate is disposed on the opposite side to the second substrate across the electronic component. The substrate connecting member includes: a first core 21 in contact with the first pad; a second core 41 in contact with the first core and the second pad; and a conductive member 71 that covers the first core and the second core and is in contact with the first pad and the second pad. The first core and the second core are spherical, and the diameter of the second core is smaller than the diameter of the first core.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a substrate with built-in electronic components and a method for manufacturing the same. [Background technology]

[0002] A substrate with built-in electronic components has been proposed, which comprises a first substrate, a second substrate opposite the first substrate, a substrate connecting member interposed between the first and second substrates to transmit signals between the first and second substrates, and a sealing resin that seals the space between the first and second substrates where the substrate connecting member is interposed, and in which electronic components such as semiconductor chips are mounted on the second substrate (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO2007 / 069606 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-described electronic component built-in substrate, if the electronic component becomes thicker, the width of the substrate connecting member must be increased, which results in the electronic component built-in substrate becoming larger in the width direction.

[0005] An object of the present invention is to provide a substrate with built-in electronic components that is less likely to become large in width even if the electronic components become thicker. [Means for solving the problem]

[0006] This electronic component-embedded substrate has a first substrate, a second substrate on which an electronic component is mounted, and a substrate connecting member that electrically connects a first pad of the first substrate to a second pad of the second substrate, wherein the first substrate is positioned on the opposite side of the second substrate with the electronic component sandwiched therebetween, and the substrate connecting member includes a first core that contacts the first pad, a second core that contacts the first core and the second pad, and a conductive member that covers the first core and the second core and contacts the first pad and the second pad, wherein the first core and the second core are spherical, and the diameter of the second core is smaller than the diameter of the first core. [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to provide a substrate with built-in electronic components that is less likely to become larger in width even if the electronic components become thicker. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view illustrating an example of an electronic component built-in substrate according to a first embodiment. [Figure 2] 4A to 4C are diagrams (part 1) illustrating a manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 3] 5A to 5C are diagrams (part 2) illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view illustrating an electronic component built-in substrate according to a modified example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] First Embodiment [Structure of electronic component embedded board] FIG. 1 is a cross-sectional view illustrating an electronic component built-in substrate according to the first embodiment.

[0011] 1, the electronic component built-in substrate 1 has a first substrate 10, a second substrate 30, a semiconductor chip 50, a substrate connecting member 70, and a sealing resin 90. In the electronic component built-in substrate 1, the semiconductor chip 50 is mounted on the second substrate 30, and the first substrate 10 is disposed on the opposite side of the second substrate 30 with the semiconductor chip 50 sandwiched between them. The sealing resin 90 is filled between the first substrate 10 and the second substrate 30 and covers the semiconductor chip 50.

[0012] In this embodiment, for convenience, the solder resist layer 13 side of the electronic component built-in substrate 1 in FIG. 1 is referred to as the upper side or one side, and the solder resist layer 37 side is referred to as the lower side or the other side. The surface of each part facing the solder resist layer 13 is referred to as one side or upper side, and the surface facing the solder resist layer 37 is referred to as the other side or lower side. However, the electronic component built-in substrate 1 can be used upside down or positioned at any angle. Furthermore, a planar view refers to viewing an object from the normal direction of one side of the solder resist layer 13, and a planar shape refers to the shape of the object viewed from the normal direction of one side of the solder resist layer 13. When the electronic component built-in substrate 1 is shown upside down compared to FIG. 1, the definitions of the upper and lower sides are reversed to match the illustration in the drawing.

[0013] The first substrate 10 has an insulating layer 11, a wiring layer 12, a solder resist layer 13, a wiring layer 14, and a solder resist layer 15.

[0014] In the first substrate 10, the insulating layer 11 may be, for example, a so-called glass epoxy substrate in which glass cloth is impregnated with an insulating resin such as an epoxy resin. Alternatively, the insulating layer 11 may be a substrate in which a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber is impregnated with an insulating resin such as an epoxy resin. The thickness of the insulating layer 11 may be, for example, approximately 60 to 200 μm. Note that the glass cloth and other components are not shown in the drawings.

[0015] The wiring layer 12 is formed on one side of the insulating layer 11. The wiring layer 12 is electrically connected to the wiring layer 14 via the insulating layer 11. The wiring layer 12 is configured to include via wiring filled in a via hole 11x that penetrates the insulating layer 11 and exposes one surface of the wiring layer 14, and a wiring pattern formed on one surface of the insulating layer 11.

[0016] The via holes 11x are recesses in the shape of an inverted truncated cone, with the diameter of the opening on the solder resist layer 13 side being larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14. The diameter of the opening of the via holes 11x may be, for example, about 50 μm. The wiring layer 12 may be made of a material such as copper (Cu). The thickness of the wiring pattern constituting the wiring layer 12 may be, for example, about 10 to 20 μm.

[0017] The solder resist layer 13 is formed on one surface of the insulating layer 11 so as to cover the wiring layer 12. The solder resist layer 13 can be formed from, for example, a photosensitive resin. The thickness of the solder resist layer 13 can be, for example, about 15 to 35 μm. The solder resist layer 13 has openings 13x, and a portion of the wiring layer 12 is exposed in the openings 13x. The wiring layer 12 exposed in the openings 13x constitutes pads 12p. The pads 12p function as pads that are electrically connected to electronic components (not shown), such as semiconductor chips and semiconductor packages.

[0018] The solder resist layer 13 may be provided so as to completely expose the pads 12p. In this case, the solder resist layer 13 may be provided so that the side surfaces of the pads 12p contact the inner wall surfaces of the openings 13x, or so as to leave a gap between the side surfaces of the pads 12p and the inner wall surfaces of the openings 13x.

[0019] If necessary, a metal layer may be formed on one surface of the pad 12p, or an anti-oxidation treatment such as an OSP (organic solderability preservative) treatment may be performed. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and a Au layer in this order), and a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and a Au layer in this order). Furthermore, an external connection terminal such as a solder ball may be formed on one surface of the pad 12p.

[0020] The wiring layer 14 is formed on the other surface of the insulating layer 11. The wiring layer 14 includes, for example, pads and a wiring pattern provided on the same surface as the pads. One surface of the wiring layer 14 is in contact with and electrically connected to the lower ends of the via wirings filled in the via holes 11x of the wiring layer 12. The material and thickness of the wiring layer 14 can be, for example, the same as those of the wiring pattern constituting the wiring layer 12.

[0021] The solder resist layer 15 is formed on the other surface of the insulating layer 11 so as to cover the wiring layer 14. The material and thickness of the solder resist layer 15 can be, for example, the same as those of the solder resist layer 13. The solder resist layer 15 has openings 15x, and a portion of the wiring layer 14 is exposed in the openings 15x. The planar shape of the openings 15x can be, for example, circular. The wiring layer 14 exposed in the openings 15x constitutes pads 14p. The pads 14p function as pads electrically connected to the substrate connecting member 70. If necessary, the other surface of the pads 14p may be formed with the aforementioned metal layer or subjected to an anti-oxidation treatment such as OSP treatment.

[0022] The second substrate 30 has an insulating layer 31 , a wiring layer 32 , an insulating layer 33 , a wiring layer 34 , a solder resist layer 35 , a wiring layer 36 , and a solder resist layer 37 .

[0023] In the second substrate 30, the material and thickness of the insulating layer 31 can be, for example, the same as those of the insulating layer 11. The wiring layer 32 is formed on one surface of the insulating layer 31. The material and thickness of the wiring layer 32 can be, for example, the same as those of the wiring pattern that constitutes the wiring layer 12.

[0024] The insulating layer 33 is formed on one surface of the insulating layer 31 so as to cover the wiring layer 32. The insulating layer 33 may be made of an insulating resin such as a thermosetting epoxy resin. The insulating layer 33 may contain a filler such as silica (SiO2). The thickness of the insulating layer 33 may be, for example, about 15 to 35 μm.

[0025] The wiring layer 34 is formed on one side of the insulating layer 33. The wiring layer 34 is configured to include via wirings filled in via holes 33x that penetrate the insulating layer 33 and expose one surface of the wiring layer 32, and a wiring pattern formed on one surface of the insulating layer 33. The wiring pattern of the second substrate 30 on which the semiconductor chip 50 is mounted has a higher density than the wiring pattern of the first substrate 10.

[0026] The via hole 33x is an inverted truncated cone-shaped recess that opens on the solder resist layer 35 side and has a bottom surface formed by one surface of the wiring layer 32. The material of the wiring layer 34 and the thickness of the wiring pattern that constitutes the wiring layer 34 can be the same as those of the wiring layer 12, for example.

[0027] The solder resist layer 35 is a protective insulating layer formed on one surface of the insulating layer 33 so as to cover the wiring layer 34. The material and thickness of the solder resist layer 35 may be the same as those of the solder resist layer 13, for example. The solder resist layer 35 has openings 35x, and a portion of the wiring layer 34 is exposed in the openings 35x. The planar shape of the openings 35x may be, for example, circular. The wiring layer 34 exposed in the openings 35x forms pads 34p and 34q.

[0028] The pad 34p functions as a pad to be bonded to the substrate connecting member 70. The pad 34q functions as a pad to be bonded to the electrode 52 of the semiconductor chip 50. A plurality of pads 34p and 34q are formed on the semiconductor chip 50 side of the second substrate 30. The pad 34q and the electrode 52 can be bonded via, for example, a conductive bonding material. Examples of the conductive bonding material that can be used include a solder material such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu.

[0029] The opening diameters of the pads 34p electrically connected to the substrate connecting member 70 and the pads 34q electrically connected to the semiconductor chip 50 can be set independently. If necessary, the aforementioned metal layer may be formed on one surface of the pads 34p and 34q, or an anti-oxidation treatment such as OSP treatment may be performed.

[0030] The wiring layer 36 is formed on the other side of the insulating layer 31. The wiring layer 36 is configured to include via wiring filled in via holes 31x that penetrate the insulating layer 31 and expose the other surface of the wiring layer 32, and a wiring pattern formed on the other surface of the insulating layer 31.

[0031] The via hole 31x is a truncated cone-shaped recess that opens on the solder resist layer 37 side and has a bottom formed by the other surface of the wiring layer 32, with the area of ​​the opening being larger than the area of ​​the bottom. The upper end of the via wiring filled in the via hole 31x of the wiring layer 36 contacts and is conductive with the other surface of the wiring layer 32. The material of the wiring layer 36 and the thickness of the wiring pattern that constitutes the wiring layer 36 can be the same as, for example, the wiring layer 12.

[0032] The solder resist layer 37 is formed on the other surface of the insulating layer 11 so as to cover the wiring layer 36. The material and thickness of the solder resist layer 37 can be, for example, the same as those of the solder resist layer 13. The solder resist layer 37 has openings 37x, and a portion of the wiring layer 36 is exposed in the openings 37x. The wiring layer 36 exposed in the openings 37x constitutes pads 36p. The pads 36p function as pads electrically connected to a mounting substrate such as a motherboard. An external connection terminal such as a solder ball may be formed on the other surface of the pad 36p. If necessary, the aforementioned metal layer may be formed on the other surface of the pad 36p, or an anti-oxidation treatment such as OSP treatment may be performed.

[0033] A semiconductor chip 50 is flip-chip mounted face-down (with the circuit-forming surface facing one surface of the second substrate 30) on one surface of the second substrate 30. More specifically, the semiconductor chip 50 has a chip body 51 equipped with a semiconductor integrated circuit and electrodes 52 serving as connection terminals, and the electrodes 52 of the semiconductor chip 50 are electrically connected to pads 34q of the second substrate 30. The electrodes 52 may be, for example, gold bumps, solder bumps, or copper posts with solder on their tips.

[0034] The electronic components built into the electronic component built-in substrate 1 are not limited to semiconductor chips, and instead of semiconductor chips, passive elements such as capacitors, inductors, resistors, etc. may be built in. Also, a so-called CSP (chip size package) in which rewiring is formed on a semiconductor chip may be built in. Alternatively, these may be mixed.

[0035] To improve reliability, it is preferable to fill the gap between the semiconductor chip 50 and the second substrate 30 with underfill resin 60. The underfill resin 60 may cover part or all of the side surfaces of the semiconductor chip 50. The underfill resin 60 does not cover the top surface of the semiconductor chip 50.

[0036] The substrate connecting member 70 is disposed between the pad 14p of the first substrate 10 and the pad 34p of the second substrate 30, electrically connecting the pad 14p and the pad 34p. The substrate connecting member 70 also serves to ensure a predetermined distance between the first substrate 10 and the second substrate 30. The area of ​​the portion of the surface of the pad 34p that contacts the substrate connecting member 70 is smaller than the area of ​​the portion of the surface of the pad 14p that contacts the substrate connecting member 70. Here, the area of ​​the portion of the surface of the pad 34p that contacts the substrate connecting member 70 refers to the area of ​​the surface of the pad 34p that is exposed in the opening 35x. The area of ​​the portion of the surface of the pad 14p that contacts the substrate connecting member 70 refers to the area of ​​the surface of the pad 14p that is exposed in the opening 15x. In a cross-sectional view, the width of the portion of the surface of the pad 14p that contacts the substrate connecting member 70 can be, for example, approximately 140 to 180 μm. In addition, the width of the portion of the surface of the pad 34p that contacts the board connecting member 70 in a cross-sectional view can be, for example, about 110 to 150 μm.

[0037] The substrate connecting member 70 includes a first core 21, a second core 41, and a conductive member 71 that covers the first core 21 and the second core 41. The first core 21 is in contact with the pad 14p. The second core 41 is located on the second substrate 30 side of the first core 21 and is in contact with the pad 34p. The first core 21 and the second core 41 are in contact with each other. The sum of the heights of the first core 21 and the second core 41 is greater than the height from the surface of the second substrate 30 to the surface of the semiconductor chip 50 facing the first substrate 10.

[0038] The first core 21 and the second core 41 are spherical, and the diameter of the second core 41 is smaller than the diameter of the first core 21. In order to reduce the width of the conductive member 71, it is preferable that the diameter of the second core 41 be approximately 1 / 2 to 1 / 4 of the diameter of the first core 21. The diameter of the first core 21 can be, for example, approximately 180 μm, and the diameter of the second core 41 can be, for example, approximately 50 μm.

[0039] For example, a metal core made of a metal such as copper or a resin core made of a resin can be used as the first core 21 and the second core 41. For example, a solder material such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu can be used as the conductive member 71.

[0040] For example, in a plan view, the substrate connection members 70 can be arranged peripherally around the semiconductor chip 50. For example, when the maximum width of the substrate connection members 70 is approximately 150 μm in a cross-sectional view, the pitch of the substrate connection members 70 can be approximately 200 μm. When viewed in a cross-sectional view, the width of the substrate connection members 70 on the side closer to the pads 34p is narrower than the width on the side closer to the pads 14p.

[0041] The board connecting member 70 has an elongated shape with its longitudinal direction parallel to the thickness direction of the electronic component-embedded substrate 1. This allows the pitch between adjacent board connecting members 70 to be narrowed, enabling the electronic component-embedded substrate 1 to be made smaller in the width direction. For example, if the distance between the first board 10 and the second board 30 is the same as that shown in FIG. 1, using a board connecting member that is nearly circular in cross section would prevent the pitch between adjacent board connecting members from being narrowed, resulting in the electronic component-embedded substrate becoming larger in the width direction. Using the board connecting member 70 with the illustrated shape can avoid this problem. This effect is particularly effective when the thickness of the semiconductor chip 50 increases and the distance between the first board 10 and the second board 30 increases.

[0042] Furthermore, the wiring pattern of the second substrate 30 on which the semiconductor chip 50 is mounted is denser than the wiring pattern of the first substrate 10. Furthermore, the area of ​​the portion of the surface of the pad 34p that contacts the substrate connecting member 70 is smaller than the area of ​​the portion of the surface of the pad 14p that contacts the substrate connecting member 70. This improves the degree of freedom in designing a high-density wiring pattern on the second substrate 30.

[0043] The sealing resin 90 is filled between the opposing surfaces of the first substrate 10 and the second substrate 30, and covers the substrate connecting member 70 and the semiconductor chip 50. The sealing resin 90 is also filled in the gap between the opposing surfaces of the semiconductor chip 50 and the first substrate 10. As the sealing resin 90, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used.

[0044] [Manufacturing method for electronic component embedded substrates] 2 and 3 are diagrams illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment.

[0045] 2(a), a first substrate 10 is fabricated, and a substrate connecting member 20 is mounted on the first substrate 10. The substrate connecting member 20 includes a first core 21 that contacts the pad 14p and a first conductive member 22 that covers the first core 21. Specifically, an insulating layer 11 made of a so-called glass epoxy substrate or the like is prepared, and a wiring layer 14 is formed on the other surface of the insulating layer 11. Next, a via hole 11x is formed in the insulating layer 11 to expose one surface of the wiring layer 14, and a wiring layer 12 is further formed on one surface of the insulating layer 11. The wiring layer 12 and the wiring layer 14 are electrically connected via the insulating layer 11.

[0046] After the via holes 11x are formed, it is preferable to perform a desmear process to remove resin residue adhering to the surface of the wiring layer 14 exposed at the bottom of the via holes 11x. The via holes 11x can be formed, for example, by a laser processing method using a CO2 laser or the like. The wiring layers 12 and 14 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method. For example, the wiring layers 12 and 14 can be formed by copper plating or the like.

[0047] Next, a solder resist layer 13 that covers the wiring layer 12 is formed on one surface of the insulating layer 11, and a solder resist layer 15 that covers the wiring layer 14 is formed on the other surface of the insulating layer 11. The solder resist layer 13 can be formed by applying an insulating resin such as a liquid or paste-like photosensitive epoxy resin to one surface of the insulating layer 11 so as to cover the wiring layer 12 by screen printing, roll coating, spin coating, or the like.

[0048] Similarly, the solder resist layer 15 can be formed by applying an insulating resin such as a liquid or paste-like photosensitive epoxy resin in a similar manner to the other surface of the insulating layer 11 so as to cover the wiring layer 14. Alternatively, instead of applying a liquid or paste-like resin, an insulating resin such as a film-like photosensitive epoxy resin may be laminated.

[0049] Then, the applied or laminated insulating resin is exposed and developed to form openings 13x and 15x in the solder resist layers 13 and 15, and the pads 12p and 14p are formed. This completes the first substrate 10. The openings 13x and 15x may also be formed by laser processing or blasting. The planar shape of each of the openings 13x and 15x may be, for example, circular. The diameter of each of the openings 13x and 15x can be designed as desired to suit the connection target.

[0050] Next, the substrate connection member 20 is placed on the surface of the pad 14p exposed in the opening 15x of the solder resist layer 15 of the first substrate 10. The substrate connection member 20 may be a cored solder ball having a spherical first core 21 and a first conductive member 22 covering the outer peripheral surface of the first core 21. The substrate connection member 20 is then heated to a predetermined temperature to melt the surface of the first conductive member 22 of the substrate connection member 20, which is then hardened and bonded to the pad 14p. The substrate connection member 20 may be arranged, for example, in a peripheral configuration.

[0051] 2(b), a second substrate 30 is fabricated, and a substrate connecting member 40 is mounted on the second substrate 30. The substrate connecting member 40 has a second core 41 that contacts the pad 34p and a second conductive member 42 that covers the second core 41. A semiconductor chip 50 is also mounted on the pad 34q of the second substrate 30. The second substrate 30 can be fabricated, for example, by appropriately repeating the steps used to fabricate the first substrate 10. The substrate connecting member 40 can be mounted in the same manner as the substrate connecting member 20.

[0052] The semiconductor chip 50 is mounted on the second substrate 30 so that the electrodes 52 on the underside of the chip body 51 are bonded to the pads 34q. Specifically, first, a conductive bonding material such as a paste-like solder material is applied to the pads 34q of the second substrate 30. Then, the semiconductor chip 50 is prepared, and, for example, the back surface of the semiconductor chip 50 is attached to the underside of a pickup jig. Then, the pickup jig with the semiconductor chip 50 attached to its underside is moved above the second substrate 30, and the electrodes 52 of the semiconductor chip 50 are aligned with the conductive bonding material, and the semiconductor chip 50 is placed on the second substrate 30. After the pickup jig is removed from the semiconductor chip 50, the conductive bonding material is heated and melted by reflow or the like, and then solidified. As a result, the electrodes 52 of the semiconductor chip 50 are electrically connected to the pads 34q of the second substrate 30 via the conductive bonding material. It is then preferable to fill the gap between the semiconductor chip 50 and the second substrate 30 with underfill resin 60 to improve reliability.

[0053] Next, in the step shown in Fig. 2(c), a first substrate 10 on which the substrate connecting member 20 has been mounted in the step shown in Fig. 2(a) and a second substrate 30 on which the substrate connecting member 40 and the semiconductor chip 50 have been mounted in the step shown in Fig. 2(b) are prepared. Then, the first substrate 10 is stacked on the second substrate 30, and the substrate connecting member 20 and the substrate connecting member 40 are brought into contact with each other.

[0054] Specifically, first, a first mold and a second mold positioned above the first mold with a predetermined distance therebetween are prepared. Then, the second substrate 30 is held above the first mold, and the first substrate 10 is held below the second mold. Next, the second mold is lowered toward the first mold until the substrate connecting member 20 mounted on the first substrate 10 contacts the substrate connecting member 40 mounted on the second substrate 30, and the first substrate 10 is stacked on the second substrate 30. Note that, as shown in the figure, the total height of the substrate connecting member 20 and the substrate connecting member 40 is greater than the height from the surface of the second substrate 30 to the surface of the semiconductor chip 50 facing the first substrate 10.

[0055] 3(a), while the first substrate 10 and the second substrate 30 are heated, the first substrate 10 is moved toward the second substrate 30 until the first core 21 and the second core 41 come into contact with each other, and the first conductive member 22 and the second conductive member 42 melt to form an integrated conductive member 71. As shown in the figure, the total height of the first core 21 and the second core 41 is greater than the height from the surface of the second substrate 30 to the surface of the semiconductor chip 50 on the first substrate 10 side.

[0056] Specifically, for example, the first and second molds are heated with a heater to melt the first conductive member 22 and the second conductive member 42, while the second mold is lowered toward the first mold until the first core 21 and the second core 41 come into contact, and the first substrate 10 is pressed against the second substrate 30. As a result, heat from the second mold is transferred to the substrate connecting member 20 via the first substrate 10, and heat from the first mold is transferred to the substrate connecting member 40 via the second substrate 30, causing the first conductive member 22 and the second conductive member 42 to melt and become one, thereby forming the conductive member 71. The conductive member 71 covers the first core 21 and the second core 41 and contacts the pads 14p and 34p. The heating temperature of the heater may be equal to or higher than the temperature at which the first conductive member 22 and the second conductive member 42 melt, and may be, for example, approximately 250°C.

[0057] Thereafter, the heating of the first and second molds is stopped, and the conductive member 71 is solidified. As a result, the upper side of the conductive member 71 is joined to the pad 14p of the first substrate 10, and the lower side is joined to the pad 34p of the second substrate 30. That is, a substrate connecting member 70 that is approximately elliptical in cross section is formed, and the first substrate 10 and the second substrate 30 are electrically connected via the substrate connecting member 70. Also, a gap is formed between the opposing surfaces of the semiconductor chip 50 and the first substrate 10. In cross section, the width of the substrate connecting member 70 on the side closer to the pad 34p is narrower than the width on the side closer to the pad 14p.

[0058] 3(b), a sealing resin 90 is formed to fill the gap between the first substrate 10 and the second substrate 30 and cover the semiconductor chip 50. For example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used as the sealing resin 90. The sealing resin 90 can be formed by, for example, a transfer molding method using a sealing mold.

[0059] The above steps complete the electronic component built-in substrate 1. If necessary, external connection terminals such as solder balls may be formed on the pads 36p.

[0060] <Modification of the first embodiment> In the modified example of the first embodiment, an example is shown in which the pads on the second substrate 30 side are larger than the pads on the first substrate 10 side. Note that in the modified example of the first embodiment, the description of the same components as those in the embodiment already described may be omitted.

[0061] FIG. 4 is a cross-sectional view illustrating an electronic component built-in substrate according to a modified example of the first embodiment. Referring to FIG. 4, in the electronic component built-in substrate 1A, the area of ​​the portion of the surface of the pad 34p that contacts the substrate connecting member 70 is larger than the area of ​​the portion of the surface of the pad 14p that contacts the substrate connecting member 70. In a cross-sectional view, the width of the portion of the surface of the pad 14p that contacts the substrate connecting member 70 can be, for example, approximately 110 to 150 μm. Also, in a cross-sectional view, the width of the portion of the surface of the pad 34p that contacts the substrate connecting member 70 can be, for example, approximately 140 to 180 μm. Also, in a cross-sectional view, the width of the substrate connecting member 70 on the first substrate 10 side is narrower than the width on the second substrate 30 side. The manufacturing method of the electronic component built-in substrate 1A is the same as the manufacturing method of the electronic component built-in substrate 1.

[0062] In the electronic component built-in substrate 1A, similar to the electronic component built-in substrate 1, the substrate connecting members 70 are elongated with the longitudinal direction being the thickness direction of the electronic component built-in substrate 1A. This allows the pitch between adjacent substrate connecting members 70 to be narrowed, making it possible to reduce the width of the electronic component built-in substrate 1A. This effect is particularly effective when the thickness of the semiconductor chip 50 increases and the gap between the first substrate 10 and the second substrate 30 increases.

[0063] Furthermore, in the electronic component built-in substrate 1A, the width of the substrate connecting member 70 on the first substrate 10 side is narrower than the width on the second substrate 30 side. Therefore, when forming the sealing resin 90 in the manufacturing process of the electronic component built-in substrate 1A, the fluidity of the sealing resin 90 is improved on the side of the substrate connecting member 70 closer to the pads 14p. As a result, the sealing resin 90 can be easily filled into the gap between the opposing surfaces of the semiconductor chip 50 and the first substrate 10. Furthermore, the risk of voids occurring between the opposing surfaces of the semiconductor chip 50 and the first substrate 10 can be reduced.

[0064] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0065] For example, the first and second substrates may be build-up substrates with multiple wiring layers and insulating layers. In this case, a coreless build-up substrate or a build-up substrate with a core may be used. Also, a lead frame may be used as the first substrate.

[0066] Furthermore, one of the first core 21 and the second core 41 may be a resin core and the other a metal core. For example, by using a resin core for the first core 21, which has a larger diameter than the second core 41, it is possible to provide a larger margin for elastic deformation than when the second core 41, which has a smaller diameter than the first core 21, is a resin core. As a result, even if there is variation in the thickness of the first substrate 10 and / or the second substrate 30, the first core 21 will elastically deform when the first substrate 10 and the second substrate 30 are brought closer to each other, thereby reducing poor contact between the substrate connecting member 20 and the substrate connecting member 40. [Explanation of symbols]

[0067] 1,1A Electronic component embedded board 10 First board 11, 31, 33 Insulating layer 11x, 31x, 33x via holes 12, 14, 32, 34, 36 wiring layers 12p, 14p, 34p, 34q, 36p pads 13, 15, 35, 37 Solder resist layer 13x, 15x, 15y, 35x, 37x opening 20, 40, 70 PCB connection material 21 First Core 22 First conductive member 30 Second board 41 Second Core 42 second conductive member 50 semiconductor chips 51 Chip body 52 electrodes 60 Underfill resin 71 Conductive materials 90 Sealing resin

Claims

1. a first substrate; a second substrate on which electronic components are mounted; a substrate connecting member that electrically connects the first pad of the first substrate and the second pad of the second substrate; the first substrate is disposed on the opposite side of the second substrate with the electronic component interposed therebetween, the board connecting member includes a first core in contact with the first pad, a second core in contact with the first core and the second pad, and a conductive member covering the first core and the second core and in contact with the first pad and the second pad, The electronic component-embedded substrate, wherein the first core and the second core are spherical, and the diameter of the second core is smaller than the diameter of the first core.

2. the first substrate has a first wiring pattern on the same surface as the first pad; the second substrate has a second wiring pattern on the same surface as the second pad; The electronic component built-in substrate according to claim 1 , wherein the second wiring pattern has a higher density than the first wiring pattern.

3. 3. The electronic component built-in substrate according to claim 1, wherein an area of ​​a portion of the surface of the second pad that contacts the board connecting member is smaller than an area of ​​a portion of the surface of the first pad that contacts the board connecting member.

4. 3. The electronic component built-in substrate according to claim 1, wherein the first core of the first and second cores is a resin core.

5. 3. The electronic component built-in substrate according to claim 1, wherein an area of ​​a portion of the surface of the second pad that contacts the board connecting member is larger than an area of ​​a portion of the surface of the first pad that contacts the board connecting member.

6. 3. The electronic component-embedded substrate according to claim 1, wherein a sum of the height of the first core and the height of the second core is greater than a height from a surface of the second substrate to a surface of the electronic component facing the first substrate.

7. a step of mounting a first substrate connecting member on a first substrate, the first substrate connecting member having a first core contacting a first pad and a first conductive member covering the first core; a step of mounting an electronic component and a second substrate connecting member on a second substrate, the second substrate connecting member having a second core in contact with a second pad and a second conductive member covering the second core; stacking the first substrate on the second substrate and bringing the first substrate connecting member into contact with the second substrate connecting member; a step of moving the first substrate toward the second substrate while heating the first substrate and the second substrate until the first core and the second core come into contact with each other, and melting the first conductive member and the second conductive member to form an integrated conductive member, the first core and the second core are spherical, and the diameter of the second core is smaller than the diameter of the first core; The conductive member covers the first core and the second core and contacts the first pad and the second pad.

8. 8. The method for manufacturing a substrate with built-in electronic components according to claim 7, wherein a sum of the height of the first core and the height of the second core is greater than a height from a surface of the second substrate to a surface of the electronic component facing the first substrate.

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