Semiconductor assembly, conversion device, semiconductor device, and method for inspecting output level of amplifier

Abstract

To provide a semiconductor assembly capable of analyzing a failure related to an incorporated amplifier by a non-destructive inspection.SOLUTION: A semiconductor assembly 11 comprises: a mounting member 15 including a first connection terminal 17b which is connectable to an external device; and a semiconductor device 13 including a first electrode 21b, a monitor electrode 21c, a class-D amplifier 24, and a comparison circuit 25 and arranged on the mounting member 15. The first electrode 21b is connected to the first connection terminal 17b via a first connection member 31b. The monitor electrode 21c is connected to the first connection terminal 17b via a monitor connection member 31c. The class-D amplifier 24 is connected to the first electrode 21b. The comparison circuit 25 receives a first input 25b connected to the monitor electrode 21c and one or a plurality of reference voltages and has a second input 25c.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor assemblies, conversion devices, semiconductor devices, and methods for testing the output level of amplifiers. [Background technology]

[0002] Patent Document 1 discloses a class D amplifier. The class D amplifier turns an output transistor for driving a load on and off to intermittently energize the load. Patent Document 1 also discloses a problem of reducing ringing in the output signal of a semiconductor integrated circuit in a class D amplifier without sacrificing operating speed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-22176 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor integrated circuit is provided as an assembly, and this assembly is fabricated, for example, by mounting the semiconductor integrated circuit on a lead frame and then encapsulating the semiconductor integrated circuit and the lead frame with a molding resin. Therefore, if a characteristic variation occurs in an assembly of a semiconductor integrated circuit, it is difficult to identify the cause of the variation by external visual observation and measurement. The characteristic variation is due to, for example, a possible characteristic variation of the circuit or a possible defect in the connection of the assembly.

[0005] Defects in integrated circuits can be analyzed by destructive testing, which involves removing the molding compound from the assembly to expose the integrated circuit and then observing the exposed integrated circuit (e.g., optically), specifically by examining the bonding pads and wires using an optical microscope or scanning electron microscope. However, some integrated circuit assemblies do not use molding compound. Furthermore, chemical processes are used to remove the molding compound from the assembly. Chemical processes can obscure the cause of the defect.

[0006] In a semiconductor integrated circuit including an amplifier, the amplifier drives a load by changing the drive current of an output transistor. Specifically, in a semiconductor integrated circuit including a class-D amplifier, the class-D amplifier drives a load by turning the output transistor on or off. The output transistor passes a large current to drive the load. The large current is provided to the load from one of the output transistors of the class-D amplifier, and the current that flows through the load flows into the other output transistor of the class-D amplifier. Therefore, this large current flows not only in the output line of the class-D amplifier, but also in the high-potential power supply line and low-potential power supply line of the semiconductor integrated circuit including the output transistor. Therefore, the amplitude of the drive waveform of the output of the class-D amplifier is affected by changes in the characteristics of the output line, high-potential power supply line, and low-potential power supply line.

[0007] What is required is a non-destructive test method for analyzing failures in semiconductor assemblies. Specifically, the output characteristics of a designed amplifier are known. Accordingly, when a specific signal is applied to the amplifier's input, the amplifier can be made to generate a designed signal value. This signal is provided as an output value at the amplifier's output, specifically, at a lead terminal of the assembly. When a load is connected to this lead terminal, a current can be passed through the amplifier via the lead terminal.

[0008] The present disclosure aims to provide a method for inspecting the output level of a semiconductor assembly, a converter, a semiconductor device, or an amplifier, which enables non-destructive testing to analyze defects associated with the amplifier of the semiconductor assembly. [Means for solving the problem]

[0009] A semiconductor assembly according to a first aspect of the present disclosure comprises: a mounting member including a first connection terminal configured to be connectable to an external device of the semiconductor assembly; and a semiconductor device having a first electrode, a monitor electrode, an amplifier, and a comparison circuit and arranged on the mounting member, wherein the first electrode is connected to the first connection terminal via a first connection member, the monitor electrode is connected to the first connection terminal via a monitor connection member, the amplifier includes an amplifier circuit having an output connected to the first electrode, the amplifier circuit receives a mode signal specifying a test mode, the comparison circuit has a first input connected to the monitor electrode and a second input configured to receive one or more reference voltages, and the comparison circuit is enabled to operate in the test mode.

[0010] A conversion device according to a second aspect of the present disclosure comprises the semiconductor assembly described in the first aspect and a load having a first input and a second input, the first input and the second input of the load being connected to the first connection terminal and the second connection terminal of the semiconductor assembly, respectively.

[0011] A semiconductor device according to a third aspect of the present disclosure comprises a first electrode and a second electrode configured to be connectable to a first external conductor and a second external conductor, a monitor electrode configured to be connectable to a third external conductor, a class D amplifier including a first driver circuit configured to drive the first electrode and a second driver circuit configured to drive the second electrode, and a comparison circuit having a first input connected to the monitor electrode and a second input configured to receive a reference voltage, wherein the monitor electrode, the first electrode, and the second electrode are arranged so that one of the first electrode and the second electrode can be connected to the monitor electrode via the third external conductor.

[0012] A method for inspecting the output level of an amplifier according to a fourth aspect of the present disclosure comprises preparing a semiconductor assembly as described in the first aspect, connecting a load to the first electrode and the second electrode of the semiconductor assembly, supplying power to the semiconductor assembly, and monitoring the output of the comparison circuit of the semiconductor assembly after supplying the power. [Effects of the Invention]

[0013] According to the above aspects, methods for inspecting the output levels of semiconductor assemblies, converters, semiconductor devices, and amplifiers are provided, which enable analysis of amplifier-related defects in semiconductor assemblies by non-destructive testing. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram schematically showing a semiconductor assembly according to the present embodiment. [Figure 2] FIG. 2 is a diagram schematically showing a semiconductor assembly according to this embodiment. [Figure 3] FIG. 3 is a diagram showing a schematic equivalent circuit of the semiconductor assembly according to this embodiment. [Figure 4] FIG. 4 is a diagram showing a typical waveform in the semiconductor assembly according to this embodiment. [Figure 5] FIG. 5 is a diagram illustrating an example failure analysis in an example semiconductor assembly according to an embodiment of the present invention. [Figure 6] FIG. 6 is a diagram illustrating an example failure analysis in an example semiconductor assembly according to an embodiment of the present invention. [Figure 7] FIG. 7 is a diagram illustrating an example failure analysis in an example semiconductor assembly according to an embodiment of the present invention. [Figure 8] FIG. 8 is a diagram illustrating an example failure analysis in an example semiconductor assembly according to an embodiment of the present invention. [Figure 9] FIG. 9 is a diagram showing the operation of the comparison circuit according to this embodiment. [Figure 10] FIG. 10 is a flow chart including exemplary steps in a method for checking the output level of an amplifier according to the present invention. [Figure 11] FIG. 11 is a diagram schematically illustrating an exemplary amplifier circuit of a semiconductor assembly according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Identical parts are designated by the same reference numerals and redundant description will be omitted.

[0016] FIG. 1 is a diagram schematically showing a semiconductor assembly according to the present embodiment.

[0017] The semiconductor assembly 11 includes a semiconductor device 13 and a mounting member 15. The mounting member 15 includes a first connection terminal 17b, which is configured to be connectable to, for example, an external device (e.g., a load 29) of the semiconductor assembly 11. The mounting member 15 may include, for example, a lead frame, a sealing resin body, or a package. The first connection terminal 17b may include, for example, a lead terminal.

[0018] The semiconductor device 13 is disposed on a mounting member 15. The semiconductor device 13 includes a first electrode 21b, a monitor electrode 21c, an amplifier 23, and a comparison circuit 25. The amplifier 23 includes an amplifier circuit 22 connected to the first electrode 21b. An exemplary amplifier 23 may include, for example, a class-D amplifier or a class-AB amplifier. The first electrode 21b is connected to a first connection terminal 17b via a first connection member 31b. The monitor electrode 21c is connected to the first connection terminal 17b via a monitor connection member 31c. The first electrode 21b and the monitor electrode 21c may be, for example, pad electrodes of the semiconductor device 13. Furthermore, the first connection member 31b and the monitor connection member 31c may include external conductors such as bonding wires or bump electrodes.

[0019] The comparison circuit 25 has a first input 25b, a second input 25c, and an output 25g. The comparison circuit 25 may include a first comparator 26b. In the comparison circuit 25 (first comparator 26b), the first input 25b is connected to the monitor electrode 21c and receives a monitor signal (SMON). The second input 25c receives one or more reference voltages (VREF). The comparison circuit 25 also has a mode input 25h that receives a mode signal specifying a test mode or a normal mode. In response to the mode signal STST, the comparison circuit 25 receives a signal (e.g., EN) that enables the first comparator 26b, for example. The comparison circuit 25 can generate an output enable signal from the mode signal STST, which enables the comparison circuit 25 to output the comparison result.

[0020] The output characteristics of the amplifier 23 are designed. Therefore, the output characteristics of the amplifier 23 are known. Accordingly, when a specific signal (e.g., a test mode signal in test mode) is applied to the input of the amplifier 23, the amplifier 23 can be caused to generate a designed signal value. This signal is provided as an output value to the output of the amplifier 23, specifically, to a lead terminal of the semiconductor assembly 11. When a load is connected to this lead terminal, a current can be caused to flow through the amplifier 23 via the lead terminal. Fluctuations in the internal characteristics of the semiconductor assembly 11 appear as changes in the current flowing through the amplifier 23. The change in current is generated as a change in voltage at the monitor electrode 21c, which is connected to the first connection terminal 17b via the monitor connection member 31c.

[0021] The comparator circuit 25 has a first input 25b connected to the monitor electrode 21c and is capable of detecting a change in the voltage of the monitor electrode 21c.

[0022] 2 is a diagram schematically illustrating a semiconductor assembly according to this embodiment. The semiconductor assembly 11 will be further described with continued reference to FIGS. 1 and 2. An exemplary amplifier 23 may include a class D amplifier 24.

[0023] The mounting member 15 further includes a second connection terminal 17d, and the second connection terminal 17d is configured to be connectable to an external device of the semiconductor assembly 11.

[0024] The semiconductor device 13 further includes a second electrode 21d, which is connected to a second connection terminal 17d via a second connection member 31d.

[0025] The first electrode 21b, the monitor electrode 21c, and the second electrode 21d are arranged so as to satisfy the following two conditions. Condition 1: The first electrode 21b and the second electrode 21d are connectable to the first connection terminal 17b and the second connection terminal 17d, respectively. Condition 2: The monitor electrode 21c is connectable to one of the first connection terminal 17b and the second connection terminal 17d. The first electrode 21b, the second electrode 21d, and the monitor electrode 21c are arranged in accordance with the arrangement of the first connection terminals 17b and the second connection terminals 17d.

[0026] The class-D amplifier 24 includes a first driver circuit 27b as an amplifier circuit 22, and the first driver circuit 27b is configured to be able to drive the first electrode 21b. The class-D amplifier 24 includes a second driver circuit 27c, and the second driver circuit 27c is configured to be able to drive the second electrode 21d.

[0027] The output characteristics of the class-D amplifier 24 are designed. Therefore, the output characteristics of the class-D amplifier 24 are known. Accordingly, when a specific signal (e.g., a test mode signal in a test mode) is applied to the input of the class-D amplifier 24, the class-D amplifier 24 can be caused to generate a designed signal value. This signal is provided as an output value to the output of the class-D amplifier 24, specifically, to a lead terminal of the semiconductor assembly 11. When a load is connected to this lead terminal, a current can be caused to flow through the class-D amplifier 24 via the lead terminal. Fluctuations in the internal characteristics of the semiconductor assembly 11 appear as changes in the current flowing through the class-D amplifier 24. The change in current is generated as a change in voltage at the monitor electrode 21c, which is connected to the first connection terminal 17b via the monitor connection member 31c.

[0028] The comparator circuit 25 has a first input 25b connected to the monitor electrode 21c and is capable of detecting a change in the voltage of the monitor electrode 21c.

[0029] As shown in FIGS. 1 and 2, the semiconductor assembly 11 is connected to a load 29 .

[0030] The exemplary load 29 can have a first input 29b and a second input 29c. The first input 29b of the load 29 is connected to the first electrode 21b via the first connection terminal 17b and the first connection member 31b, and the first electrode 21b is connected to a first driver circuit 27b serving as the amplifier circuit 22. The second input 29c of the load 29 is connected to the second electrode 21d via the second connection terminal 17d and the monitor connection member 31d, and the second electrode 21d is connected to the second driver circuit 27c. The exemplary load 29 can be driven by the first driver circuit 27b and the second driver circuit 27c.

[0031] Specifically, the load 29 may include a transducer 30 configured to generate longitudinal waves that propagate through a medium in response to electrical signals received at the first input 29 b and the second input 29 c. An exemplary transducer 30 may include an acoustic speaker. The medium may include, for example, the atmosphere.

[0032] The mounting member 15 further includes a first power supply terminal 17f and a second power supply terminal 17g, and the first power supply terminal 17f and the second power supply terminal 17g are configured to be connectable to the outside of the semiconductor assembly 11.

[0033] The first power supply terminal 17f and the second power supply terminal 17g can be connected to the first power supply electrode 21f and the second power supply electrode 21g via the third connection member 31f and the fourth connection member 31g, respectively. The first power supply terminal 17f and the second power supply terminal 17g are connected to the first driver circuit 27b and the second driver circuit 27c of the class-D amplifier 24. The exemplary first power supply terminal 17f can be connected to a high-potential power supply, and the exemplary second power supply terminal 17g can be connected to a low-potential power supply.

[0034] The class-D amplifier 24 is connected to a pre-driver circuit 33, and the pre-driver circuit 33 drives the class-D amplifier 24. Specifically, the pre-driver circuit 33 drives a first driver circuit 27b and a second driver circuit 27c. The first driver circuit 27b and the second driver circuit 27c operate in response to respective drive signals from the pre-driver circuit 33.

[0035] The pre-driver circuit 33 also includes a first pre-driver circuit 33b and a second pre-driver circuit 33c, which drive the first driver circuit 27b and the second driver circuit 27c, respectively. The first driver circuit 27b and the second driver circuit 27c pass large currents. Therefore, the pre-driver circuit 33, specifically the first pre-driver circuit 33b and the second pre-driver circuit 33c, can adjust the timing of these drive signals and operate to reduce the through current of the first driver circuit 27b and the second driver circuit 27c.

[0036] The class D amplifier 24 is supplied with power from a first power supply terminal 17f and a second power supply terminal 17g.

[0037] The first pre-driver circuit 33b and the second pre-driver circuit 33c are connected to the first power supply electrode 21f and the second power supply electrode 21g, and are supplied with power from a power supply common to the class D amplifier 24.

[0038] The semiconductor device 13 may further include a third power supply electrode 21h and a fourth power supply electrode 21j. The third power supply electrode 21h and the fourth power supply electrode 21j can be connected to a third power supply terminal 17h and a fourth power supply terminal 17j via a fifth connection member 31h and a sixth connection member 31j, respectively.

[0039] The semiconductor device 13 further includes a signal generating circuit 35, which has a first output 35d and a second output 35f. The first output 35d and the second output 35f are connected to an input 33d of the first pre-driver circuit 33b and an input 33f of the second pre-driver circuit 33c, respectively. The exemplary signal generating circuit 35 is connected to the first power supply electrode 21f and the second power supply electrode 21g and can be powered therefrom. However, the signal generating circuit 35 can also be connected to the third power supply electrode 21h and the fourth power supply electrode 21j and can be powered therefrom.

[0040] The signal generating circuit 35 receives a mode signal STST at a test input 35b, which specifies the test mode or the normal mode.

[0041] The signal generation circuit 35 is configured to generate a first signal S1 at a first output 35d and a second signal S2 at a second output 35f in test mode. When the first driver circuit 27b receives the first signal S1 via the first pre-driver circuit 33b, it outputs one of a first value and a second value to the first output 27d. When the second driver circuit 27c receives the second signal S2 via the second pre-driver circuit 33c, it outputs the other of the first value and the second value to the second output 27f.

[0042] The signal generation circuit 35 is configured to generate a third signal S3 at a first output 35d and a fourth signal S4 at a second output 35f in test mode. When the first driver circuit 27b receives the third signal S3 via the first pre-driver circuit 33b, it outputs the other of the first value and the second value at the first output 27d. When the second driver circuit 27c receives the fourth signal S4 via the second pre-driver circuit 33c, it outputs one of the first value and the second value at the second output 27f.

[0043] When the first signal S1 and the third signal S3 are output alternately, for example, periodically, to form a square wave, the output of the first driver circuit 27b also changes periodically in response to this input. Furthermore, when the second signal S2 and the fourth signal S4 are output alternately, for example, periodically, to form a square wave, the output of the second driver circuit 27c also changes periodically in response to this input. The comparator circuit 25 can perform comparison in response to this periodic operation.

[0044] The exemplary semiconductor device 13 includes a PWM signal generating circuit 37 configured to generate a PWM control signal for controlling an external device (e.g., a load 29). The exemplary PWM signal generating circuit 37 may include the signal generating circuit 35. Alternatively, the exemplary pre-driver circuit 33 may include the signal generating circuit 35. Alternatively, the signal generating circuit 35 may be configured as a circuit independent of the PWM signal generating circuit 37 and the pre-driver circuit 33.

[0045] 2, the exemplary first driver circuit 27b may include a p-type field effect transistor 40p (e.g., a pchMOS transistor, "P1" in FIG. 3) and an n-type field effect transistor 40n (e.g., an nchMOS transistor, "N1" in FIG. 3). The drains of the p-type field effect transistor 40p and the n-type field effect transistor 40n are connected at a shared node to provide a drive signal to the output 27d.

[0046] The exemplary second driver circuit 27c may include a p-type field effect transistor 42p (e.g., an n-channel MOS transistor, "P2" in FIG. 3) and an n-type field effect transistor 42n (e.g., an n-channel MOS transistor, "N2" in FIG. 3). The drains of the p-type field effect transistor 42p and the n-type field effect transistor 42n are connected at a shared node to provide a drive signal to the output 27f.

[0047] The first pre-driver circuit 33b includes a first p-side driver 32b, a first n-side driver 32c, and a first signal generator 32d.

[0048] In the normal mode, the first signal generator 32d receives the first drive signal SDRV1 from the signal generating circuit 35. The first signal generator 32d generates a pair of adjustment signals adjusted from the first drive signal SDRV1 so as to shorten the simultaneous conduction period of the p-type field effect transistor 40p and the n-type field effect transistor 40n. The pair of adjustment signals is provided to the first p-side driver 32b and the first n-side driver 32c.

[0049] In the test mode, the first pre-driver circuit 33b makes one of the p-type field effect transistor 40p and the n-type field effect transistor 40n, for example, the p-type field effect transistor 40p, conductive, and makes the other, for example, the n-type field effect transistor 40n, non-conductive.

[0050] The second pre-driver circuit 33c includes a second p-side driver 34b, a second n-side driver 34c, and a second signal generator 34d.

[0051] At the normal node, the second signal generator 34d receives the second drive signal SDRV2 from the signal generation circuit 35. The second signal generator 34d generates a pair of adjustment signals adjusted from the second drive signal SDRV2 so that the simultaneous conduction period of the second p-side driver 34b and the second n-side driver 34c is shortened. The pair of adjustment signals is provided to the second p-side driver 34b and the second n-side driver 34c.

[0052] In the test mode, the second pre-driver circuit 33c makes one of the p-type field effect transistor 42p and the n-type field effect transistor 42n, for example, the n-type field effect transistor 42n, conductive, and makes the other, for example, the p-type field effect transistor 42p, non-conductive.

[0053] The exemplary semiconductor device 13 includes a second monitor electrode 21k, which is connected to the second connection terminal 17d via a second monitor connection member 31k.

[0054] The comparison circuit 25 may include a second comparator 26c in addition to the first comparator 26b. In the comparison circuit 25 (second comparator 26c), a third input 25f is connected to the monitor electrode 21k. The second comparator 26c can receive a second monitor signal (SMON2) from the monitor electrode 21k. A fourth input 25d receives one or more reference voltages. The comparison circuit 25 may include an output circuit 26d that receives comparison result signals from the first comparator 26b and the second comparator 26c. The output circuit 26d provides a comparison result in accordance with a reference signal (VREF) provided to the first comparator 26b and the second comparator 26c, respectively.

[0055] Like the first comparator 26b of the comparison circuit 25, the second comparator 26c uses MOS transistors in its input circuit, and therefore, except for transient currents, no current flows through the monitor connecting member 31c or the second monitor connecting member 31k for voltage comparison. Accordingly, the comparison results of the comparison circuit 25 are substantially unaffected by defects in the monitor connecting member 31c or the second monitor connecting member 31k (e.g., bonding wires), except for disconnections.

[0056] 1 and 2, the semiconductor device 13 may further include a reference voltage circuit 39. The reference voltage circuit 39 is connected to the second input 25c of the comparison circuit 25. The reference voltage of the comparison circuit 25 is generated by the reference voltage circuit 39 in the test mode. The reference voltage circuit 39 may include a resistor voltage divider circuit (voltage divider circuit) configured to generate the reference voltage. An exemplary reference voltage circuit 39 may include a first circuit 39b connected to the first comparator 26b and a second circuit 39c connected to the second comparator 26c. In the exemplary reference voltage circuit 39, the reference voltage of the first circuit 39b may be different from the reference voltage of the second circuit 39c. The exemplary reference voltage circuit 39 may include a selection circuit configured to provide one of the reference voltages to the comparison circuit 25 in response to a selection signal, and the selection circuit may be connected between the third power electrode 21h and the fourth power electrode 21j.

[0057] As will be understood from the following explanation, the resistance change due to a defect in a connecting member such as a bonding wire is estimated to be several ohms. To facilitate the first comparator 26b and the second comparator 26c to detect such a small resistance change, the resistive voltage divider circuit of the exemplary reference voltage circuit 39 can be connected to the first power supply electrode 21f and the second power supply electrode 21g. The exemplary reference voltage circuit 39 can also be connected to the first power supply electrode 21f and the second power supply electrode 21g. Because the change in resistance due to the expected defect is very small, for example, on the order of 1 ohm to several ohms, the resistive voltage divider circuit can be connected to the first power supply electrode 21f and the second power supply electrode 21g to facilitate this detection.

[0058] The exemplary comparison circuit 25 may be connected to the first power supply electrode 21f and the second power supply electrode 21g, and the exemplary first comparator 26b and the exemplary second comparator 26c may be connected to the first power supply electrode 21f and the second power supply electrode 21g.

[0059] The exemplary semiconductor device 13 may include a test circuit 45. The test circuit 45 may receive a mode signal from a test electrode 21m. The test electrode 21m may be connected to a connection terminal 17m via a test connection member 31m.

[0060] In the exemplary connection members, each of the connection members (31b, 31c, 31d, 31f, 31g, 31h, 31j, 31k, and 31m) can include a bonding wire.

[0061] The exemplary semiconductor device 13 may include a processing circuit 47, which may perform signal processing on the input signal. The output of the processing circuit 47 may be connected to the signal generating circuit 35.

[0062] FIG. 3 is a diagram showing a schematic equivalent circuit of the semiconductor assembly according to this embodiment.

[0063] As can be understood from the above explanation, in test mode, the first power supply terminal 17f, the third connection member 31f (third bonding wire), the first power supply electrode 21f, the first driver circuit 27b, the first electrode 21b, and the first connection member 31b (first bonding wire) are connected to the second connection terminal 17d, the second connection member 31d (second bonding wire), the second electrode 21d, the second driver circuit 27c, the second power supply electrode 21g, the fourth connection member 31g (fourth bonding wire), and the second power supply terminal 17g via the load 29 (converter 30), forming a closed circuit with respect to the power supply.

[0064] This closed circuit ideally passes a current determined by the on-resistance of the transistor in the first driver circuit 27b, the on-resistance of the transistor in the second driver circuit 27c, and the internal resistance of the load 29 (converter 30).

[0065] The term "ideal" refers to a state in which, for example, the third, first, second, and fourth bonding wires themselves and their respective bonds with adjacent conductors are free of significant defects. Furthermore, the term "ideal" refers to a state in which the on-resistance of the conductive transistors of first driver circuit 27b and second driver circuit 27c is free of significant defects.

[0066] 3, the symbols "P1" and "P2" refer to p-type transistors in the first driver circuit 27b and the second driver circuit 27c, respectively. The symbols "N1" and "N2" refer to n-type transistors in the first driver circuit 27b and the second driver circuit 27c, respectively.

[0067] Additionally, the internal resistance of converter 30 is represented by "RL." The symbols "SPVDD_L," "SPVDD," "SPP," "SPP_L," "SPM_L," "SPM," "SPGND," and "SPGND_L" refer to voltages at the respective components.

[0068] FIG. 4 is a diagram showing a typical waveform in the semiconductor assembly according to this embodiment.

[0069] The estimated on-resistance of the transistor is 0.5 ohms. The bond wire has a resistance of 0.001 ohms as a normal value. The internal resistance RL of the converter 30 is 8 ohms. The bond wire has a resistance of 2 ohms as a result of the defect.

[0070] Parts (a) and (b) of Figure 4 show the waveforms at the input of the pre-driver circuits (33b, 33c) of a normal semiconductor assembly and the voltage waveform "SPP" of the first electrode 21b of Figure 3. Part (a) of Figure 4 shows the waveform of the input signal.

[0071] The normal amplitude of the voltage waveform "SPP" at the terminal in Figure 3 is estimated as follows: (0.5) / (0.5×2+8)=0.5 / 9, =0.055. (0.5+8) / (0.5×2+8)=8.5 / 9 =0.944. 0.944-0.055=0.889 (rounded to 0.89), Accordingly, the amplitude of the voltage waveform "SPP" at the terminal in Figure 3 is 0.89 times the power supply SPVDD.

[0072] The amplitude ratio (ratio to the power supply voltage) of the defect in the voltage waveform "SPP" of the terminal in Figure 3 (a defect in which all four bonding wires show a resistance of 2 ohms) is estimated as follows: (2×2+0.5) / (2×4+0.5×2+8)=4.5 / 17 =0.2647, (2×2+0.5+8) / (2×4+0.5×2+8)=12.5 / 17 =0.7353, 0.2647-0.7353=0.4705 (rounded to 0.47). Accordingly, as shown in part (d) of FIG. 4, the amplitude of the voltage waveform "SPP" at the terminal in FIG. 3 becomes 0.47 times the power supply SPVDD.

[0073] Next, an equivalent circuit incorporating a defect in a semiconductor assembly will be described.

[0074] 5, 6, 7, and 8 are diagrams illustrating an example failure analysis in an example semiconductor assembly according to this embodiment.

[0075] 5 to 8, each of the transistors in the first driver circuit 27b and the second driver circuit 27c is represented as an equivalent circuit with a series-connected equivalent resistor 41 and switch 43. The symbols "P1," "P2," "N1," and "N2" are used to associate the transistors in the first driver circuit 27b and the second driver circuit 27c. Furthermore, "ON" and "OFF" written near the switch 43 indicate that the switch 43 (transistor) is conductive and non-conductive, respectively. The transistors in the first driver circuit 27b and the second driver circuit 27c have an ON resistance "RON."

[0076] In the following description, as an example of deterioration over time, the first bonding wire 31b, the second bonding wire 31d, the third bonding wire 31f, the fourth bonding wire 31g, and the monitor bonding wire 31c are uniformly deteriorated. These bonding wires are represented using the electrical symbol for resistor to indicate deterioration. Furthermore, the reference symbols "R1," "R2," "R3," "R4," "RM1," and "RM2" represent the resistance values ​​of the first bonding wire 31b, the second bonding wire 31d, the third bonding wire 31f, the fourth bonding wire 31g, the monitor bonding wire 31c, and the monitor bonding wire 31k, respectively.

[0077] The power supply voltage and ground voltage are referred to as "SPVDD" and "SPGND," respectively. RALL = R1 + R2 + R3 + R4 + 2 × RON + RL I=SPVDD / RALL It is written as follows.

[0078] In the estimation, the on-resistance of the transistor is 0.5 ohms. The bond wire has a resistance of 0.001 ohms as a normal value. As a result of a defect, the bond wire has a resistance of, for example, 2 ohms. The internal resistance RL of the converter 30 is 8 ohms. "V17b" and "V17d" represent the voltages of the components indicated by the reference symbols "17b" and "17d", respectively.

[0079] Typical defects are shown below. Non-conducting due to a fault in the transistors (P1, P2): V17b=V17d=SPGND. The current is zero. Non-conducting due to a fault in transistors (N1, N2): V17b=V17d=SPVDD. The current is zero. Breakage due to peeling of the first bonding wire (31b): V17b=SPVDD. V17d=SPGND. Breakage due to peeling of the second bonding wire (31d): V17b=SPVDD. V17d=SPGND.

[0080] 5, in the test mode, the transistor P1 of the first driver circuit 27b is conductive and the transistor N1 is not conductive, and the transistor P2 of the second driver circuit 27c is not conductive and the transistor N2 is conductive.

[0081] When the circuit of Figure 5 is closed, the circuit causes a current I5 to flow through the third bonding wire (R3), the transistor (P1), the first electrode 21b, the first bonding wire (R1), the internal resistance RL of the converter 30, the second bonding wire (R2), the second electrode 21d, the transistor (N2), and the fourth bonding wire (R4).

[0082] The first comparator 26b is connected to the first connection terminal 17b via a monitor bonding wire 31c. The voltages (V17b, V17d) on the two connection members 17b, 17d are estimated as follows: V17b=I5×(RL+R2+RON+R4) / RALL V17d=I5×(R2+RON+R4) / RALL V17b>V17d

[0083] 6, in the test mode, the transistor N1 of the first driver circuit 27b is conductive and the transistor P1 is not conductive, and the transistor P2 of the second driver circuit 27c is conductive and the transistor N2 is not conductive.

[0084] When the circuit of Figure 6 is closed, the circuit causes a current I6 to flow through the third bonding wire (R3), the transistor (P2), the second electrode 21d, the second bonding wire (R2), the internal resistance RL of the converter 30, the first bonding wire (R1), the first electrode 21b, the transistor (N1), and the fourth bonding wire (R4).

[0085] The first comparator 26b is connected to the first connection terminal 17b via a monitor bonding wire 31c. The voltages (V17b, V17d) on the two connection members 17b, 17d are estimated as follows: V17b=I6×(R1+RON+R4) / RALL V17d=I6×(RL+R1+RON+R4) / RALL V17b <V17d

[0086] 7, in the test mode, the transistor P1 of the first driver circuit 27b is conductive and the transistor N1 is not conductive, and the transistor N2 of the second driver circuit 27c is conductive and the transistor P2 is not conductive.

[0087] When the circuit of Figure 7 is closed, the circuit causes a current I7 to flow through the third bonding wire (R3), the transistor (P1), the first electrode 21b, the first bonding wire (R1), the internal resistance RL of the converter 30, the second bonding wire (R2), the second electrode 21d, the transistor (N2), and the fourth bonding wire (R4).

[0088] The second comparator 26c is connected to the second connection terminal 17d via a monitor bonding wire 31k. The voltages V17b and V17d on the two connection members 17b and 17d are estimated as follows: V17b=I7×(R1+RON+R4) / RALL V17d=I7×(RL+R1+RON+R4) / RALL V17b>V17d

[0089] 8, in the test mode, the transistor N1 of the first driver circuit 27b is conductive and the transistor P1 is not conductive, and the transistor P2 of the second driver circuit 27c is conductive and the transistor N2 is not conductive.

[0090] When the circuit of Figure 8 is closed, the circuit causes a current I8 to flow through the third bonding wire (R3), the transistor (P2), the second electrode 21d, the second bonding wire (R2), the internal resistance RL of the converter 30, the first bonding wire (R1), the first electrode 21b, the transistor (N1), and the fourth bonding wire (R4).

[0091] The second comparator 26c is connected to the second connection terminal 17d via a monitor bonding wire 31k. The voltages V17b and V17d on the two connection members 17b and 17d are estimated as follows: V17b=I8×(R1+RON+R4) / RALL V17d=I8×(RL+R1+RON+R4) / RALL V17b <V17d

[0092] FIG. 9 is a diagram showing the operation of the comparison circuit according to this embodiment.

[0093] In the test mode, for example, the transistor P1 of the first driver circuit 27b is on and the transistor N1 is off, and the transistor P2 of the second driver circuit 27c is off and the transistor N2 is on.

[0094] In the connection shown in FIG. 5, in the semiconductor assembly 11 without any defects, V17b=4.72V (SPVDD×0.94 times) An exemplary comparison voltage of the comparison circuit 25 is 3.85V (SPVDD×0.77 times) can be set to.

[0095] This comparison voltage can be generated by a resistor divider of two resistors (eg, 300Ω and 1000Ω) connected in series.

[0096] When the input voltage is applied to the comparison circuit 25, which receives an exemplary comparison voltage (3.85V), the comparison circuit 25 generates a "no fault" determination signal (ERR=L).

[0097] For a semiconductor assembly 11 containing uniformly degraded bonding wires (resistance 2 Ω), V17b=3.68V (SPVDD×0.74 times) When this input voltage is applied to the comparison circuit 25, which receives an exemplary comparison voltage (3.85V), the comparison circuit 25 generates a "failure" determination signal (ERR=H).

[0098] In addition, in the semiconductor assembly 11 including a deteriorated single bonding wire (R1=resistance 3Ω), V17b=3.54V (SPVDD×0.71 times) When this input voltage is applied to the comparison circuit 25, which receives an exemplary comparison voltage (3.85V), the comparison circuit 25 generates a "failure" determination signal (ERR=H) in response to the signal (EN), as shown in FIG.

[0099] In this way, an abnormality in the resistance value due to corrosion of the bonding wire, for example, can be detected.

[0100] The reference voltages of the first comparator 26b and the second comparator 26c can be identified based on the following list:

[0101] For a semiconductor assembly 11 with all good bond wires (resistance 0 Ω) and transistor RON (resistance 0.5 Ω), the total resistance of the circuit is 9 Ω, where the internal resistance of the transducer is 8 Ω.

[0102] R3;R1;R2;R4;Ratio(17b);Ratio(17d). 0Ω;0Ω;0Ω;0Ω;0.9444, 0.0555.

[0103] For a semiconductor assembly 11 with a single bond wire failure (3 ohms resistance), a transistor RON (0.5 ohms resistance), and a good bond wire (0 ohms resistance), the total resistance of the circuit is 12 ohms.

[0104] R3;R1;R2;R4;Ratio(17b);Ratio(17d). 3Ω;0Ω;0Ω;0Ω;0.7083, 0.0416. 0Ω;3Ω;0Ω;0Ω;0.7083, 0.0416. 0Ω;0Ω;3Ω;0Ω;0.9583, 0.2916. 0Ω;0Ω;0Ω;3Ω;0.9583, 0.2916. The ratio (17b) and the ratio (17d) indicate the resistance ratio at the respective connection terminals (17b, 17d).

[0105] For a semiconductor assembly 11 with two bond wire failures (2 Ω resistance), a transistor RON (0.5 Ω resistance), and a good bond wire (0 Ω resistance), the total resistance of the circuit is 13 Ω.

[0106] R3;R1;R2;R4;Ratio(17b);Ratio(17d). 2Ω;2Ω;0Ω;0Ω;0.6538, 0.0416. 2Ω;0Ω;2Ω;0Ω;0.8076, 0.192. 0Ω;2Ω;0Ω;2Ω;0.8076, 0.192. 0Ω;2Ω;2Ω;0Ω;0.9625, 0.0384. 2Ω;0Ω;0Ω;2Ω;0.8076, 0.1923. 0Ω;0Ω;2Ω;2Ω;0.9615, 0.1923.

[0107] For a semiconductor assembly 11 with three bond wire failures (2 Ω resistance), a transistor RON (0.5 Ω resistance), and a good bond wire (0 Ω resistance), the total resistance of the circuit is 15 Ω.

[0108] R3;R1;R2;R4;Ratio(17b);Ratio(17d). 2Ω;2Ω;2Ω;0Ω;0.7, 0.0333. 2Ω;2Ω;0Ω;2Ω;0.7, 0.1666. 0Ω;2Ω;2Ω;2Ω;0.9666, 0.1666. 2Ω;0Ω;2Ω;2Ω;0.8333, 0.1666.

[0109] For a semiconductor assembly 11 with four bond wire failures (2 ohms resistance) and a transistor RON (0.5 ohms resistance), the total resistance of the circuit is 17 ohms.

[0110] R3;R1;R2;R4;Ratio(17b);Ratio(17d). 2Ω;2Ω;2Ω;2Ω;0.7352, 0.2647.

[0111] Two comparators (26b, 26c) can be provided in the comparison circuit 25. By specifying the respective reference voltages for the comparators (26b, 26c) based on the above list and switching the reference voltages in each of the comparators (26b, 26c), the characteristics of the semiconductor assembly 11 can be determined non-destructively.

[0112] 10 is a flowchart including exemplary steps in a method for checking the output level of an amplifier according to the present embodiment. The method 100 includes at least one of the following steps: In the following description, for ease of understanding, reference numerals already given will be used where possible, and redundant description will be omitted.

[0113] The method 100 includes step ST1, in which a semiconductor assembly 11 is prepared. The preparation includes, for example, fabricating the semiconductor assembly 11 or obtaining the semiconductor assembly 11.

[0114] The method 100 includes step ST2, in which a load is connected to the semiconductor assembly 11. Specifically, the load is connected to the class D amplifier of the semiconductor assembly 11.

[0115] The method 100 includes step ST3, in which power is supplied to the semiconductor assembly 11.

[0116] The method 100 includes step ST4, in which after supplying power to the semiconductor assembly 11, the output of the comparison circuit 25 of the semiconductor assembly 11 is monitored.

[0117] The method 100 includes step ST5, in which the output level of the class D amplifier of the semiconductor assembly 11 is checked after supplying power from the power supply.

[0118] The method 100 includes step ST6, in which, after supplying power, an output value of the comparison circuit 25 is obtained, and whether or not a malfunction occurs is determined based on this output value.

[0119] FIG. 11 is a diagram schematically illustrating an exemplary amplifier circuit of a semiconductor assembly according to this embodiment.

[0120] The semiconductor assembly 11 may include a class AB amplifier in the amplifier circuit 22. An exemplary class AB amplifier includes an output stage 51, a bias stage 53, and an input stage 55.

[0121] The output stage 51 includes a p-type field effect transistor 52p and an n-type field effect transistor 52n. The drains of the p-type field effect transistor 52p and the n-type field effect transistor 52n are connected to each other to form the output of the amplifier circuit 22. Specifically, the drains of the p-type field effect transistor 52p and the n-type field effect transistor 52n are connected to the first electrode 21b. The source and back gate of the p-type field effect transistor 52p are connected to the third power supply electrode 21f, and the source and back gate of the n-type field effect transistor 52n are connected to the fourth power supply electrode 21g.

[0122] The bias stage 53 is connected to the gates of the p-type field effect transistor 52 p and the n-type field effect transistor 52 n to determine the operating point of the transistors of the output stage 51 and to drive the output stage 51 .

[0123] The bias stage 53 also receives a mode signal STST. In the test mode, the bias stage 53 individually controls the gate of the p-type field effect transistor 52p and the gate of the n-type field effect transistor 52n. This control makes it possible to adjust the current that each of the p-type field effect transistor 52p and the n-type field effect transistor 52n passes through the load of the amplifier circuit 22. For example, the gate of the p-type field effect transistor 52p or one of the n-type field effect transistors 52n is made conductive to pass a current through the load.

[0124] The input stage 55 may include, for example, an operational amplifier 54. The operational amplifier generates, from an input signal provided to the input stage 55, a p-side signal and an n-side signal that respectively drive a p-type field effect transistor 52p and an n-type field effect transistor 52n of the output stage 51. These signals are provided to the bias stage 53.

[0125] In an exemplary control in the test mode, the bias stage 53 can make only one of the p-type field effect transistor 52p and the n-type field effect transistor 52n conductive to pass current. The state of characteristic variations can be investigated using a known external load resistor, the first bonding wire, the third bonding wire, the fourth bonding wire, the ON resistance of the p-type field effect transistor 52p and the n-type field effect transistor 52n, and the comparator circuit 25. The characteristic variations can be caused by, for example, variations in the circuit characteristics, changes in the interface between the pad electrodes of the semiconductor integrated circuit and the bonding wire, changes in the characteristics of the bonding wire, and changes in the interface between the lead electrodes of the lead frame and the bonding wire.

[0126] According to this embodiment, it is possible to provide a method for inspecting the output level of a semiconductor assembly, a converter, a semiconductor device, and an amplifier, which enables defects related to the built-in amplifier to be analyzed by non-destructive inspection.

[0127] This embodiment further has the following various aspects.

[0128] A semiconductor assembly according to a first aspect of this embodiment comprises: a mounting member including a first connection terminal configured to be connectable to an external device of the semiconductor assembly; and a semiconductor device having a first electrode, a monitor electrode, an amplifier, and a comparison circuit and arranged on the mounting member, wherein the first electrode is connected to the first connection terminal via a first connection member, the monitor electrode is connected to the first connection terminal via a monitor connection member, the amplifier includes an amplifier circuit having an output connected to the first electrode, the amplifier circuit receives a mode signal specifying a test mode, the comparison circuit has a first input connected to the monitor electrode and a second input configured to receive one or more reference voltages, and the comparison circuit is enabled to operate in the test mode.

[0129] In a semiconductor assembly relating to a second aspect according to the first aspect of this embodiment, the amplifier includes a class D amplifier, the mounting member further includes a second connection terminal configured to be connectable to an external device of the semiconductor assembly, the semiconductor device further has a second electrode, the second electrode being connected to the second connection terminal via a second connection member, the class D amplifier includes a first driver circuit configured to drive the first electrode as the amplification circuit, and the class D amplifier includes a second driver circuit configured to drive the second electrode.

[0130] In a semiconductor assembly according to a third aspect in accordance with the second aspect of this embodiment, the mounting member includes a first power supply terminal and a second power supply terminal configured to be connectable to the outside of the semiconductor assembly, the semiconductor device further includes a first power supply electrode and a second power supply electrode connected to the first driver circuit and the second driver circuit of the class D amplifier, and the first power supply terminal and the second power supply terminal can be connected to the first power supply electrode and the second power supply electrode via a third connecting member and a fourth connecting member, respectively.

[0131] In a semiconductor assembly according to a fourth aspect in accordance with the third aspect of this embodiment, the class D amplifier includes a pre-driver circuit configured to drive the first driver circuit and the second driver circuit, the pre-driver circuit including a first pre-driver circuit connected to an input of the first driver circuit and a second pre-driver circuit connected to an input of the second driver circuit, and the first pre-driver circuit and the second pre-driver circuit can be connected to the first power supply electrode and the second power supply electrode.

[0132] In a semiconductor assembly according to a second aspect in accordance with the first aspect of this embodiment, the semiconductor device further includes a signal generation circuit having a first output connected to an input of the first pre-driver circuit and a second output connected to an input of the second pre-driver circuit, the signal generation circuit having an input for receiving a mode signal that designates a test mode and a normal mode, and the signal generation circuit can be configured to generate, in the test mode, a first signal at the first output that causes the first driver circuit to output one of a first value and a second value different from the first value, and to generate, at the second output, a second signal that causes the second driver circuit to output the other of the first value and the second value.

[0133] In a semiconductor assembly relating to a sixth aspect in accordance with the fifth aspect of this embodiment, the signal generation circuit may be configured to generate, in the test mode, a third signal at the first output that causes the first driver circuit to output the other of the first value and the second value, and to generate a fourth signal at the second output that causes the second driver circuit to output one of the first value and the second value.

[0134] In a semiconductor assembly according to a seventh aspect in accordance with the fifth or sixth aspect of this embodiment, the semiconductor device includes a PWM signal generating circuit configured to generate a PWM control signal for controlling the external device, and the PWM signal generating circuit may include the signal generating circuit.

[0135] In a semiconductor assembly according to an eighth aspect of the present embodiment, which is in accordance with the third, fourth, fifth, sixth, or seventh aspect, the first connecting member, the second connecting member, the third connecting member, and the fourth connecting member may include a first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire, respectively.

[0136] In a semiconductor assembly according to a ninth aspect of the present embodiment, which is in accordance with the third, fourth, fifth, sixth, seventh, or eighth aspect of the present embodiment, the semiconductor assembly may further include a reference voltage circuit connected to the second input of the comparison circuit, and the reference voltage circuit may include at least one voltage divider circuit configured to generate the reference voltage.

[0137] In a semiconductor assembly according to a tenth aspect in accordance with the ninth aspect of this embodiment, a voltage divider circuit of the reference voltage circuit may be connected between the first power supply terminal and the second power supply terminal.

[0138] A conversion device according to an eleventh aspect of this embodiment comprises a semiconductor assembly described in any one of the second to tenth aspects, and a load having a first input and a second input, wherein the first input and the second input of the load can be connected to the first connection terminal and the second connection terminal of the semiconductor assembly, respectively.

[0139] In the transducer device according to the twelfth aspect according to the eleventh aspect of this embodiment, the load may include an acoustic speaker.

[0140] A semiconductor device according to a thirteenth aspect of this embodiment comprises a first electrode and a second electrode configured to be connectable to a first external conductor and a second external conductor, a monitor electrode configured to be connectable to a third external conductor, a class D amplifier including a first driver circuit configured to drive the first electrode and a second driver circuit configured to drive the second electrode, and a comparison circuit having a first input connected to the monitor electrode and a second input configured to receive a reference voltage, and the monitor electrode, the first electrode, and the second electrode are arranged so that one of the first electrode and the second electrode can be connected to the monitor electrode via the third external conductor.

[0141] According to a fourteenth aspect of this embodiment, a method for inspecting the output level of an amplifier includes preparing a semiconductor assembly described in any one of the second to tenth aspects, connecting a load to the first electrode and the second electrode of the semiconductor assembly, supplying power to the semiconductor assembly, and monitoring the output of the comparison circuit of the semiconductor assembly after supplying the power.

[0142] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0143] 11. Semiconductor assembly, 13. Semiconductor device, 15. Mounting member, 17b, 17d, 17f, 17g, 17h, 17j, 17m, ... connection terminal, 21b,...first electrode, 21c,...Monitor electrode, 21d,...second electrode, 21f, 21g, 21h, 21j...power electrode, 21k, 21m... test electrode, 22... Amplification circuit, 23...amplifier, 24... Class D amplifier, 25...comparison circuit, 26b...1st comparator 26c...Second comparator 26d... Output circuit, 27b...first driver circuit; 27c...Second driver circuit, 29... Load, 30... converter, 31b, 31d, 31f, 31g, 31h, 31j, ...connecting members, 31c, 31d, 31k, 31m... Test connection members, 32b···p-side driver, 32c···n-side driver, 32d...signal generator, 33 Pre-driver circuit, 33b, 33c: Pre-driver circuit, 34b···p-side driver, 34c···n-side driver, 34d...signal generator, 35...signal generation circuit, 35b Test input, 37...PWM signal generation circuit, 39... Reference voltage circuit, 40n n-type field effect transistor 40p···p-type field effect transistor 41 Equivalent resistance 42n n-type field effect transistor 42p···p-type field-effect transistor 43···switch, 45... Test circuit, 47···Processing circuit, SDRV1, SDRV2 drive signals, SPVDD power supply, STST... mode signal.

Claims

1. a mounting member including a first connection terminal configured to be connectable to an external device of the semiconductor assembly; a semiconductor device having a first electrode, a monitor electrode, an amplifier, and a comparison circuit and disposed on the mounting member; Equipped with the first electrode is connected to the first connection terminal via a first connection member; the monitor electrode is connected to the first connection terminal via a monitor connection member; the amplifier includes an amplifier circuit having an output connected to the first electrode; the amplifier circuit receives a mode signal that designates a test mode, the comparison circuit has a first input connected to the monitor electrode and a second input configured to receive one or more reference voltages; the comparison circuit is enabled in the test mode; Semiconductor assembly.

2. the amplifier includes a class D amplifier; the mounting member further includes a second connection terminal configured to be connectable to an external device of the semiconductor assembly; The semiconductor device further includes a second electrode, the second electrode is connected to the second connection terminal via a second connection member; the class D amplifier includes, as the amplifier circuit, a first driver circuit configured to drive the first electrode; the class D amplifier includes a second driver circuit configured to drive the second electrode.

10. The semiconductor assembly of claim 1.

3. the mounting member includes a first power supply terminal and a second power supply terminal configured to be connectable to an external device of the semiconductor assembly; the semiconductor device further includes a first power supply electrode and a second power supply electrode connected to the first driver circuit and the second driver circuit of the class D amplifier, the first power supply terminal and the second power supply terminal are connected to the first power supply electrode and the second power supply electrode via a third connection member and a fourth connection member, respectively; 3. The semiconductor assembly of claim 2.

4. the class D amplifier includes a pre-driver circuit configured to drive the first driver circuit and the second driver circuit, the pre-driver circuit including a first pre-driver circuit connected to an input of the first driver circuit and a second pre-driver circuit connected to an input of the second driver circuit; the first pre-driver circuit and the second pre-driver circuit are connected to the first power supply electrode and the second power supply electrode; 4. The semiconductor assembly of claim 3.

5. the semiconductor device further includes a signal generation circuit having a first output connected to an input of the first pre-driver circuit and a second output connected to an input of the second pre-driver circuit; the signal generating circuit has an input for receiving a mode signal that specifies a test mode or a normal mode; the signal generation circuit is configured to generate, in the test mode, a first signal at the first output that causes the first driver circuit to output one of a first value and a second value different from the first value, and to generate, at the second output, a second signal that causes the second driver circuit to output the other of the first value and the second value.

5. The semiconductor assembly of claim 4.

6. the signal generation circuit is configured to generate, in the test mode, a third signal at the first output that causes the first driver circuit to output the other of the first value and the second value, and a fourth signal at the second output that causes the second driver circuit to output the one of the first value and the second value.

6. The semiconductor assembly of claim 5.

7. the semiconductor device includes a PWM signal generation circuit configured to generate a PWM control signal for controlling the external device; the PWM signal generating circuit includes the signal generating circuit; 6. The semiconductor assembly of claim 5.

8. the first connection member, the second connection member, the third connection member, and the fourth connection member include a first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire, respectively; 4. The semiconductor assembly of claim 3.

9. a reference voltage circuit connected to the second input of the comparator circuit; the reference voltage circuit comprises at least one voltage divider circuit configured to generate the reference voltage; 4. The semiconductor assembly of claim 3.

10. the voltage divider circuit of the reference voltage circuit is connected between the first power supply terminal and the second power supply terminal; 10. The semiconductor assembly of claim 9.

11. A semiconductor assembly according to any one of claims 2 to 10; a load having a first input and a second input; Equipped with the first input and the second input of the load are connected to the first connection terminal and the second connection terminal of the semiconductor assembly, respectively; Conversion device.

12. The load includes an acoustic speaker.

12. The conversion device according to claim 11.

13. a first electrode and a second electrode configured to be connectable to a first outer conductor and a second outer conductor; a monitor electrode configured to be connectable to a third external conductor; a class D amplifier including a first driver circuit configured to be able to drive the first electrode and a second driver circuit configured to be able to drive the second electrode; a comparison circuit having a first input connected to the monitor electrode and a second input configured to receive a reference voltage; Equipped with the monitor electrode, the first electrode, and the second electrode are arranged such that one of the first electrode and the second electrode is connectable to the monitor electrode via the third external conductor; Semiconductor device.

14. Providing a semiconductor assembly according to any one of claims 2 to 10; connecting a load to the first electrode and the second electrode of the semiconductor assembly; providing a power source to the semiconductor assembly; monitoring an output of the comparison circuit of the semiconductor assembly after supplying the power supply; 1. A method for testing an amplifier output level, comprising:

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