Semiconductor manufacturing equipment member and regeneration method thereof

Abstract

To reduce the precision required for the thickness between a chucking electrode and a wafer mounting surface, and increase the bonding strength between ceramic plates.SOLUTION: A semiconductor manufacturing equipment member 10 includes a first ceramic plate 21 having a wafer mounting surface 26 on its upper surface and serving as a chucking electrode 27, a second ceramic plate 22 disposed on the lower surface of the first ceramic plate 21, and a first amorphous layer 24 present between the first ceramic plate 21 and the second ceramic plate 22. The first ceramic plate 21 has a volume resistivity that allows it to exert a Johnsen-Rahbek force.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor manufacturing equipment member and a method for recycling the same. [Background technology]

[0002] Conventionally, semiconductor manufacturing equipment components are known that utilize plasma to perform CVD, etching, and the like on wafers. As disclosed in Patent Document 1, one such semiconductor manufacturing equipment component is known to have a ceramic insulating layer formed on the upper surface of a ceramic dielectric layer in which an electrostatic electrode is embedded. The ceramic insulating layer is formed, for example, of a CVD film, a PVD film, an AD film, or a thermal spray film. The ceramic insulating layer has a wafer mounting surface on its upper surface. Alumina is also cited as an example of the material for the ceramic insulating layer. Therefore, the wafer is attracted to the wafer mounting surface by Coulomb force. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7214867 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the wafer is attracted by Coulomb force, the thickness of the ceramic insulating layer must be highly accurate, and the bonding strength between the ceramic insulating layer and the ceramic dielectric layer is often insufficient.

[0005] The present invention has been made to solve the above-mentioned problems, and a main object of the present invention is to reduce the precision required for the thickness between the chucking electrode and the wafer mounting surface and to increase the bonding strength between the ceramic plates. [Means for solving the problem]

[0006] [1] The semiconductor manufacturing equipment member of the present invention is a first ceramic plate having a wafer mounting surface on its upper surface and incorporating an adsorption electrode; a second ceramic plate disposed on the lower surface of the first ceramic plate; a first amorphous layer present between the first ceramic plate and the second ceramic plate; Equipped with the first ceramic plate has a volume resistivity capable of exerting a Johnsen-Rahbek force; It is something.

[0007] In this semiconductor manufacturing equipment component, the volume resistivity of the first ceramic plate, which has a wafer-mounting surface on its upper surface, is such that the Johnson-Rahbek force (JR force) can be exerted. Therefore, the required precision for the thickness between the chucking electrode and the wafer-mounting surface is lower than when using Coulomb force. Furthermore, the presence of the first amorphous layer between the first and second ceramic plates results in a relatively high bonding strength between the two plates.

[0008] In this specification, "upper" and "lower" do not represent absolute positional relationships, but rather relative positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0009] [2] In the semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member described in [1] above), the thickness of the first ceramic plate above the chucking electrode may be 0.5 mm or more. When the first ceramic plate loses its original characteristics due to aging or the like, the upper surface (including the wafer mounting surface) of the first ceramic plate may be ground down to the chucking electrode, and then the wafer mounting surface may be re-formed on the ground surface. This process is easily performed if the thickness of the upper surface of the chucking electrode is 0.5 mm or more.

[0010] [3] In the semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member according to the above [1] or [2]), the volume resistivity of the first ceramic plate is 1×10 9 More than 1×10 12 In this way, the semiconductor manufacturing equipment component can easily exert its JR force.

[0011] [4] In the semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member according to any one of [1] to [3] above), the first ceramic plate may be an aluminum nitride plate, and the second ceramic plate may be an alumina plate. In this way, the first ceramic plate is likely to exhibit JR force, and the second ceramic plate is likely to exhibit electrical insulation performance.

[0012] [5] The semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member according to any one of [1] to [4] above) may comprise a first deteriorated layer present on the side of the first ceramic plate that contacts the first amorphous layer, and a second deteriorated layer present on the side of the second ceramic plate that contacts the first amorphous layer.

[0013] [6] The semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member according to any one of [1] to [5] above) may include a third ceramic plate disposed on the lower surface of the second ceramic plate, and a second amorphous layer present between the second ceramic plate and the third ceramic plate. In this case, the third ceramic plate may be made of a material having a higher thermal conductivity than the second ceramic plate, or may be made of a material having a lower purity than the second ceramic plate.

[0014] [7] In the semiconductor manufacturing equipment component of the present invention (the semiconductor manufacturing equipment component described in [6] above), a refrigerant flow path through which a refrigerant circulates or a gas flow path for supplying gas to the wafer mounting surface may be provided at a position of the second ceramic plate facing the second amorphous layer or at a position of the third ceramic plate facing the second amorphous layer.

[0015] [8] The semiconductor manufacturing equipment member of the present invention (the semiconductor manufacturing equipment member described in [6] or [7] above) may comprise a third deteriorated layer present on the side of the second ceramic plate that contacts the second amorphous layer, and a fourth deteriorated layer present on the side of the third ceramic plate that contacts the second amorphous layer.

[0016] [9] The method for recycling semiconductor manufacturing equipment components of the present invention comprises: (a) processing an upper surface of the first ceramic plate of the semiconductor manufacturing equipment member according to any one of [1] to [8] above up to the chucking electrode to form a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; (b) further processing the processed surface to form a new wafer-mounting surface; may also include:

[0017]

[10] The method for recycling a semiconductor manufacturing equipment member of the present invention comprises: (a) processing an upper surface of the first ceramic plate of the semiconductor manufacturing equipment member according to any one of [1] to [8] above up to the chucking electrode to form a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; (b) directly bonding a ceramic plate for regeneration having a volume resistivity capable of exerting the Johnsen-Rahbek force to the processed surface; may also include:

[0018] In this case, the ceramic plate for recycling used in step (b) may not have a wafer mounting surface on its upper surface before direct bonding, and a wafer mounting surface may be formed on its upper surface after direct bonding, or a plate with a wafer mounting surface already formed on its upper surface before direct bonding may be directly bonded.

[0019]

[11] The method for recycling a semiconductor manufacturing equipment member of the present invention comprises: (a) processing the first ceramic plate of the semiconductor manufacturing equipment member according to any one of [1] to [8] above to remove the second ceramic plate so as to expose the second ceramic plate, and forming a processed surface on the second ceramic plate; (b) directly bonding a ceramic plate for regeneration, which has a volume resistivity capable of exerting the Johnsen-Rahbek force and has an adsorption electrode built in, to the processed surface; may also include:

[0020] In this case, the ceramic plate for recycling used in step (b) may not have a wafer mounting surface on its upper surface before direct bonding, and a wafer mounting surface may be formed on its upper surface after direct bonding, or a plate with a wafer mounting surface already formed on its upper surface before direct bonding may be directly bonded. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a plan view of a semiconductor manufacturing equipment member 10. [Figure 2] Cross section AA of Figure 1. [Figure 3] Enlarged view of a portion of Figure 2. [Figure 4] FIG. [Figure 5] 1 is a cross-sectional view of a semiconductor manufacturing equipment member 10 having a coolant flow path 70. FIG. [Figure 6] 1 is a cross-sectional view of a semiconductor manufacturing equipment member 10 having a coolant flow path 70. FIG. [Figure 7] 1 is a cross-sectional view of a semiconductor manufacturing equipment member 10 having a gas flow path 80. FIG. [Figure 8] 1 is a cross-sectional view of a semiconductor manufacturing equipment member 10 having a gas flow path 80. FIG. [Figure 9]1 is a process diagram for recycling a semiconductor manufacturing equipment component 10. FIG. [Figure 10] 1 is a process diagram for recycling a semiconductor manufacturing equipment component 10. FIG. [Figure 11] 1 is a process diagram for recycling a semiconductor manufacturing equipment component 10. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0022] A preferred embodiment of the present invention will be described below with reference to the drawings, in which: Fig. 1 is a plan view of a semiconductor manufacturing equipment member 10, Fig. 2 is a cross-sectional view taken along line AA in Fig. 1, and Fig. 3 is an enlarged view of a portion of Fig. 2.

[0023] As shown in FIG. 2, the semiconductor manufacturing equipment member 10 includes a ceramic plate stack 20, a cooling plate 30, and an adhesive sheet 40.

[0024] The ceramic plate stack 20 is a three-layer ceramic disk. The ceramic plate stack 20 includes a first ceramic plate 21 having a wafer mounting surface 26 on its upper surface, a second ceramic plate 22 disposed on the lower surface of the first ceramic plate 21, and a third ceramic plate 23 disposed on the lower surface of the second ceramic plate 22. A first amorphous layer 24 exists between the first ceramic plate 21 and the second ceramic plate 22, and a second amorphous layer 25 exists between the second ceramic plate 22 and the third ceramic plate 23. When measured by XRD, the first amorphous layer 24 exhibits a broader peak than the first ceramic plate 21 and the second ceramic plate 22, and the second amorphous layer 25 exhibits a broader peak than the second ceramic plate 22 and the third ceramic plate 23. In a cross-sectional magnification image of the ceramic plate stack 20 observed under a transmission electron microscope (TEM) at 4,000,000 magnification, the first and second amorphous layers 24, 25 are observed as thin bands. The first amorphous layer 24 may be formed as a single layer or as multiple layers (e.g., three layers). This also applies to the second amorphous layer 25. To increase the bonding strength between the first ceramic plate 21 and the second ceramic plate 22 and between the second ceramic plate 22 and the third ceramic plate 23, the average thicknesses t1, t2 of the first and second amorphous layers 24, 25 are preferably 0.1 nm or greater, more preferably 1 nm or greater. Furthermore, to prevent the inclusion of different materials, the average thicknesses t1, t2 of the first and second amorphous layers 24, 25 are preferably 30 nm or less, more preferably 20 nm or less. Therefore, the average thicknesses t1 and t2 of the first and second amorphous layers 24 and 25 are preferably, for example, 0.1 nm to 30 nm, and more preferably 1 nm to 20 nm. When the first amorphous layer 24 is composed of multiple layers, the thickness of the first amorphous layer 24 refers to the total thickness of the multiple layers. This also applies to the second amorphous layer 25.

[0025] The average thicknesses t1 and t2 of the first and second amorphous layers 24 and 25 are measured by TEM observation using the following procedure. On a TEM photograph (magnification: 4,000,000 times) of one field of view, the thicknesses of the first and second amorphous layers 24 and 25 are measured at five locations at 10-nm intervals along the bonding interface, and the average thicknesses of the first and second amorphous layers 24 and 25 in one field of view are calculated. Similar thickness measurements by TEM observation are performed on five fields of view, including the center, periphery, and radial center of the semiconductor manufacturing equipment member 10 when viewed from above. The average thickness t1 of the first amorphous layer 24 is calculated by dividing the sum of the average thicknesses of the first amorphous layer 24 in the five fields of view by the number of fields, which is five. The average thickness t2 of the second amorphous layer 25 is calculated by dividing the sum of the average thicknesses of the second amorphous layer 25 in the five fields of view by the number of fields, which is five.

[0026] The fact that the thin strip observed by TEM is an amorphous layer can be confirmed by observing a wider halo pattern inside the thin strip compared to the outer sides of the thin strip when X-ray diffraction (XRD) patterns are obtained for the inside of the thin strip and both outer sides of the thin strip (ceramic plates). Usually, when XRD diffraction patterns are measured for both outer sides of the thin strip (ceramic plates), diffraction patterns corresponding to the crystals of the material that makes up each ceramic plate are observed.

[0027] The upper surface of the first ceramic plate 21 serves as a wafer mounting surface 26 on which a wafer W is mounted. An annular seal band 26a is formed along the outer edge of the wafer mounting surface 26, and a plurality of small circular protrusions 26b are formed on the entire inner surface of the seal band 26a. The seal band 26a and the small circular protrusions 26b have the same height, which is, for example, several μm to several tens of μm (e.g., 50 μm). The diameter of the small circular protrusions 26b is, for example, several hundreds of μm (e.g., 800 μm). The portion of the wafer mounting surface 26 on which the seal band 26a and the small circular protrusions 26b are not provided is referred to as a reference surface 26c.

[0028] The first ceramic plate 21 incorporates an adsorption electrode 27. The adsorption electrode 27 is a planar electrode connected to an external DC power supply via a power supply member (not shown). The power supply member is electrically insulated from the cooling plate 30. When a DC voltage is applied to the adsorption electrode 27, the wafer W is electrostatically attracted and fixed to the wafer mounting surface 26 (specifically, the upper surfaces of the seal bands 26a and the small circular protrusions 26b). When the DC voltage is removed, the wafer W is released from the wafer mounting surface 26. The thickness of the first ceramic plate 21 above the adsorption electrode 27 is preferably 0.5 mm or more. If the first ceramic plate 21 loses its original characteristics due to aging or other reasons, the upper surface of the first ceramic plate 21 (including the wafer mounting surface 26) may be ground and then a wafer mounting surface may be re-formed on the ground surface, as described below. This process is easily performed if the thickness of the upper surface of the adsorption electrode 27 is 0.5 mm or more. The thickness of the first ceramic plate 21 above the chucking electrode 27 is preferably 2 mm or less. The chucking electrode 27 may be a mesh electrode or a printed electrode.

[0029] The first ceramic plate 21 has a volume resistivity that allows it to exert a JR force. The volume resistivity of the first ceramic plate 21 is, for example, 1×10 9 More than 1×10 12 It is preferable that the resistance is Ωcm or less. The operating temperature can be set appropriately depending on the type of wafer processing, for example, within the range of 25°C to 400°C. Since the first ceramic plate 21 uses JR force to attract the wafer W, a sufficient attracting force can be obtained even with a lower applied voltage than when Coulomb force is used (for example, about 3 kV for Coulomb force, compared to about 500 V for JR force). Therefore, the first ceramic plate 21 does not require as high a dielectric strength (dielectric breakdown strength) as when Coulomb force is used. Examples of the first ceramic plate 21 include an aluminum nitride plate and a low-resistivity alumina plate, with an aluminum nitride plate being preferred.

[0030] The second ceramic plate 22 is a ceramic disk having the same diameter as the first ceramic plate 21 as the bonding surface of the first ceramic plate 21, and includes a built-in heater electrode 28. The heater electrode 28 is a resistance heating element formed such that, in a plan view, wiring runs from one of a pair of terminals across the entire wafer mounting surface 26 to the other of the pair of terminals. The pair of terminals is connected to an external heater power supply via a power supply member (not shown). The power supply member is electrically insulated from the cooling plate 30. When power is supplied to the heater electrode 28 from the heater power supply, the heater electrode 28 generates heat and heats the wafer W on the wafer mounting surface 26. The withstand voltage of the second ceramic plate 22 is preferably higher than that of the first ceramic plate 21. This allows the thickness between the chucking electrode 27 and the heater electrode 28 to be reduced. When the first ceramic plate 21 is an aluminum nitride plate (with a dielectric strength of about 15 kV / mm), the second ceramic plate 22 is preferably an alumina plate, particularly an alumina plate with a high dielectric strength (for example, an alumina plate with a dielectric strength of 70 kV / mm or more). Examples of alumina plates with a dielectric strength of 70 kV / mm or more include high-purity (for example, 99.5 mass% or more) alumina plates shown in Example 5 and Comparative Examples 1 and 3 of Japanese Patent No. 5,972,630 and Experimental Examples 1 to 10 of Japanese Patent No. 6,373,212.

[0031] The third ceramic plate 23 is a ceramic circular plate having a step on its outer periphery, with the diameter of its upper portion being the same as that of the second ceramic plate 22 and the diameter of its lower portion being larger than that of the second ceramic plate 22. The third ceramic plate 23 is made of, for example, a material (such as an AlN sintered body) having a higher thermal conductivity than the second ceramic plate 22.

[0032] The first ceramic plate 21 has a first affected layer 21a on the side in contact with the first amorphous layer 24, and the second ceramic plate 22 has a second affected layer 22a on the side in contact with the first amorphous layer 24. When the first affected layer 21a is measured by XRD, for example, a peak that is broader than that of the portion of the first ceramic plate 21 other than the first affected layer 21a but a sharper peak than that of the first amorphous layer 24 appears. When the second affected layer 22a is measured by XRD, for example, a peak that is broader than that of the portion of the second ceramic plate 22 other than the second affected layer 22a appears, but a sharper peak than that of the first amorphous layer 24 appears. In an enlarged cross-sectional image of the ceramic plate stack 20 taken by TEM, the first affected layer 21a is observed to have a different morphology from that of the portion of the first ceramic plate 21 other than the first affected layer 21a, and the second affected layer 22a is observed to have a different morphology from that of the portion of the second ceramic plate 22 other than the second affected layer 22a. The thickness of the first and second affected layers 21a, 22a is preferably 10 nm or more, and more preferably 100 nm or more and 1 μm or less.

[0033] The second ceramic plate 22 has a third affected layer 22b on the side in contact with the second amorphous layer 25, and the third ceramic plate 23 has a fourth affected layer 23b on the side in contact with the second amorphous layer 25. When the third affected layer 22b is measured by XRD, for example, a broader peak appears compared to the portion of the second ceramic plate 22 other than the third affected layer 22b, but a sharper peak appears compared to the second amorphous layer 25. When the fourth affected layer 23b is measured by XRD, for example, a broader peak appears compared to the portion of the third ceramic plate 23 other than the fourth affected layer 23b, but a sharper peak appears compared to the second amorphous layer 25. In an enlarged cross-sectional image of the ceramic plate stack 20 taken by TEM, the third affected layer 22b is observed to have a different morphology from the portion of the second ceramic plate 22 other than the third affected layer 22b, and the fourth affected layer 23b is observed to have a different morphology from the portion of the third ceramic plate 23 other than the fourth affected layer 23b. The thickness of the third and fourth affected layers 22b, 23b is preferably 10 nm or more, and more preferably 100 nm or more and 1 μm or less.

[0034] The cooling plate 30 is a circular plate with good thermal conductivity (having a diameter equal to or larger than the diameter of the lower portion of the third ceramic plate 23 of the ceramic plate stack 20). A refrigerant flow path 32 through which a refrigerant circulates is formed inside the cooling plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant flow path 32 is formed in a single stroke across the entire cooling plate 30 in a plan view, from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port, respectively, of an external refrigerant device (not shown). The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, and is temperature-adjusted before being supplied again from the supply port to one end of the refrigerant flow path 32. The cooling plate 30 may also be used as an RF electrode.

[0035] Examples of materials for the cooling plate 30 include metal materials and composite materials of metal and ceramic. Examples of metal materials include Al, Ti, Mo, and alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMC) and ceramic matrix composites (CMC). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also known as SiSiCTi), a material in which porous SiC is impregnated with Al and / or Si, and a composite material of Al2O3 and TiC. It is preferable to select a material for the cooling plate 30 that has a thermal expansion coefficient close to that of the material of the third ceramic plate 23.

[0036] The adhesive sheet 40 is a circular double-sided adhesive tape that bonds the lower surface of the ceramic plate stack 20 to the upper surface of the cooling plate 30. Examples of materials for the adhesive sheet 40 include epoxy resin, acrylic resin, and silicone resin. Note that a metal bonding layer may be used instead of the adhesive sheet 40.

[0037] Next, an example of how the semiconductor manufacturing equipment component 10 configured as described above is described. First, with the semiconductor manufacturing equipment component 10 installed in a chamber (not shown), a wafer W is placed on the wafer mounting surface 26. The chamber is then depressurized using a vacuum pump to a predetermined vacuum level, and a DC voltage is applied to the attraction electrode 27 of the ceramic plate stack 20 to generate an electrostatic attraction force, thereby attracting and fixing the wafer W to the wafer mounting surface 26 (specifically, the upper surfaces of the seal bands 26a and the small circular protrusions 26b). Next, a reactive gas atmosphere at a predetermined pressure (e.g., several tens to several hundreds of Pa) is created in the chamber. In this state, a high-frequency voltage is applied between an upper electrode (not shown) installed in the ceiling of the chamber and the cooling plate 30 of the semiconductor manufacturing equipment component 10 to generate plasma. The surface of the wafer W is processed by the generated plasma. A coolant is circulated through the coolant flow path 32 of the cooling plate 30. Furthermore, power is supplied to the heater electrode 28 to heat the wafer W as needed.

[0038] Next, a manufacturing example of the ceramic plate stack 20 will be described. First, the first ceramic plate 21 and the second ceramic plate 22 are manufactured. For example, the first ceramic plate 21 is manufactured by hot-press firing a molded body containing ceramic powder (e.g., aluminum nitride powder) in which the chucking electrodes 27 are embedded. This allows the first ceramic plate 21 to be made into a dense body. The second ceramic plate 22 is manufactured by hot-press firing a molded body containing ceramic powder (e.g., alumina powder) in which the heater electrodes 28 are embedded (see, for example, Example 5 and Comparative Examples 1 and 3 of Japanese Patent No. 5,972,630 and Experimental Examples 1 to 10 of Japanese Patent No. 6,373,212). This allows the second ceramic plate 22 to be made into a dense body. The third ceramic plate 23 is manufactured by hot-press firing a molded body containing ceramic powder (e.g., aluminum nitride powder). This allows the third ceramic plate 23 to be made into a dense body. At this stage, the first to third ceramic plates 21 to 23 do not have any deteriorated layers.

[0039] Next, the first ceramic plate 21 is subjected to lapping using a polishing apparatus 50 shown in FIG. 4. The polishing apparatus 50 includes a large-diameter disc-shaped polishing table 52 equipped with a polishing pad 54, a small-diameter disc-shaped carrier 56, and a pipe 58 for supplying a slurry containing abrasive grains to the polishing pad 54. The polishing table 52 has a shaft at the center of its underside, which is rotated by a drive motor (not shown), causing it to rotate about its axis (spin). The carrier 56 has a shaft at the center of its upper surface, which is rotated by a drive motor (not shown), causing it to rotate about its axis (spin). The carrier 56 is positioned off-center of the polishing table 52. To polish the first ceramic plate 21 using this polishing apparatus 50, the first ceramic plate 21 is attached to the underside of the carrier 56, and the first ceramic plate 21 is sandwiched between the polishing pad 54 of the polishing table 52 and the carrier 56. A slurry containing abrasive grains is then supplied to the polishing pad 54 from the pipe 58. As a result, slurry is supplied between the first ceramic plate 21 and the polishing pad 54 of the polishing table 52. In this state, the first ceramic plate 21 is pressed against the polishing pad 54 by the carrier 56, while the polishing table 52 and the carrier 56 are rotated to perform polishing. The polishing conditions are set so that the surface roughness (arithmetic mean roughness) Ra of the underside of the first ceramic plate 21 is 1 nm or less. The surface roughness (arithmetic mean roughness) Ra of the polished surface is measured using a non-contact surface roughness meter in accordance with the ISO 25178 standard. In addition, a first affected layer 21a is formed on the polished surface side of the first ceramic plate 21.

[0040] The second ceramic plate 22 is subjected to lapping on both the upper and lower surfaces using a polishing device 50 in the same manner as the first ceramic plate 21. As a result, the surface roughness Ra of both surfaces of the second ceramic plate 22 becomes 1 nm or less. In addition, second and third affected layers 22a and 22b are formed on both surfaces of the second ceramic plate 22.

[0041] The smaller-diameter surface of the third ceramic plate 23 is subjected to lapping using a polishing device 50 in the same manner as the first ceramic plate 21. As a result, the surface roughness Ra of the polished surface of the third ceramic plate 23 becomes 1 nm or less. In addition, a fourth affected layer 23b is formed on the polished surface of the third ceramic plate 23.

[0042] Next, the surface (polished surface) of the first ceramic plate 21 on which the first damaged layer 21a is formed and the surface (polished surface) of the second ceramic plate 22 on which the second damaged layer 22a is formed are subjected to surface activation treatment (high-speed electron beam (FAB) or plasma activation treatment) under high vacuum. The FAB conditions are appropriately adjusted within the range of, for example, a voltage of 0.5 to 2 kV, a current of 50 to 200 mA, and an irradiation time of 30 to 300 seconds. As a result, oxides and adsorbed molecules are removed from the surface of the first ceramic plate 21 on which the first damaged layer 21a is formed and the surface of the second ceramic plate 22 on which the second damaged layer 22a is formed, forming amorphous layers and activating the plates. Then, while maintaining the high vacuum condition, the first ceramic plate 21 and the second ceramic plate 22 are overlapped with each other so that the surface on which the first damaged layer 21a is formed and the surface on which the second damaged layer 22a is formed face each other, and they are bonded under pressure (direct bonding). The load during the pressurization is set to, for example, 0.1 to 50 kN. As a result, a bonded body in which the first ceramic plate 21 and the second ceramic plate 22 are bonded together is obtained.

[0043] The surface (polished surface) of the second ceramic plate 22 on which the third damaged layer 22b is formed and the surface (polished surface) of the third ceramic plate 23 on which the fourth damaged layer 23b is formed are subjected to surface activation treatment (high-speed electron beam (FAB) or plasma activation treatment) under high vacuum. This removes oxides and adsorbed molecules from the surface of the second ceramic plate 22 on which the third damaged layer 22b is formed and the surface of the third ceramic plate 23 on which the fourth damaged layer 23b is formed, forming amorphous layers and activating the plates. Then, while maintaining the high vacuum condition, the second ceramic plate 22 and the third ceramic plate 23 are stacked so that the surface on which the third damaged layer 22b is formed and the surface on which the fourth damaged layer 23b is formed face each other, and are bonded under pressure (direct bonding). The FAB conditions and the load applied during pressing are as described above. This results in a ceramic plate stack 20.

[0044] In the semiconductor manufacturing equipment member 10 described above, the volume resistivity of the first ceramic plate 21 having a wafer mounting surface on its upper surface is a volume resistivity that can exert JR force (for example, 1×10 9 More than 1×10 12 Ωcm or less). Here, the Coulomb force is inversely proportional to the square of the thickness of the upper side of the chucking electrode 27 of the first ceramic plate 21 (the distance d between the wafer W and the chucking electrode 27), but the JR force is not directly related to the distance d. Therefore, in the semiconductor manufacturing equipment member 10 using the JR force, the required precision for the thickness between the chucking electrode 27 and the wafer mounting surface 26 is lower than in the case where the Coulomb force is used. In addition, since the first amorphous layer 24 is present between the first ceramic plate 21 and the second ceramic plate 22, the bonding strength between the two plates 21 and 22 is relatively high. Since the second amorphous layer 25 is also present between the second ceramic plate 22 and the third ceramic plate 23, the bonding strength between the two plates 22 and 23 is also relatively high.

[0045] Furthermore, the thickness of the first ceramic plate 21 above the chucking electrode 27 is preferably 0.5 mm or more. If the first ceramic plate 21 loses its original characteristics due to aging or other reasons, the upper surface (including the wafer mounting surface 26) of the first ceramic plate 21 may be ground down to just before the chucking electrode 27, and then the wafer mounting surface may be formed again on the ground surface (see FIG. 9, which will be described later). This can be easily performed if the thickness of the upper surface of the chucking electrode 27 is 0.5 mm or more.

[0046] Furthermore, the volume resistivity of the first ceramic plate 21 is 1×10 9 More than 1×10 12 It is preferable that the electrical resistance is Ωcm or less. This allows the semiconductor manufacturing equipment member 10 to easily exert JR force.

[0047] Furthermore, it is preferable that the first ceramic plate 21 is an aluminum nitride plate and the second ceramic plate 22 is an alumina plate. This allows the first ceramic plate 21 to easily exert JR force, and the second ceramic plate 22 to easily exhibit electrical insulation performance. Examples of electrical insulation performance include high volume resistivity and high dielectric strength.

[0048] Furthermore, since the third ceramic plate 23 is made of a material (for example, an AlN sintered body) having a higher thermal conductivity than the second ceramic plate 22, the uniformity of heat distribution and heat removal of the wafer W are improved.

[0049] Furthermore, the semiconductor manufacturing equipment member 10 utilizes a laminate of the first and second ceramic plates 21, 22. Therefore, ceramic plates with different properties can be used as the first and second ceramic plates 21, 22. This makes it easier to adapt the semiconductor manufacturing equipment member 10 to the characteristics required.

[0050] It goes without saying that the present invention is not limited to the above-described embodiment, and can be embodied in various forms as long as they fall within the technical scope of the present invention.

[0051] For example, in the semiconductor manufacturing equipment component 10 described above, the ceramic plate stack 20 may have a refrigerant flow path 70 at a position facing the amorphous layer 25 of the second ceramic plate 22, as shown in FIG. 5 . Alternatively, the ceramic plate stack 20 may have a refrigerant flow path 70 at a position facing the amorphous layer 25 of the third ceramic plate 23, as shown in FIG. 6 . In FIGS. 5 and 6 , the same components as those in the above-described embodiment are denoted by the same reference numerals. The refrigerant flow path 70 is formed in a single stroke from one end (inlet) to the other end (outlet) across the entire wafer mounting surface 26 in a plan view. One end and the other end of the refrigerant flow path 70 are connected to a supply port and a recovery port of an external refrigerant device (not shown), respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 70 passes through the refrigerant flow path 70, returns from the other end of the refrigerant flow path 70 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 70.

[0052] In the semiconductor manufacturing equipment member 10 described above, the ceramic plate stack 20 may have a gas flow path 80 at a position facing the amorphous layer 25 of the second ceramic plate 22, as shown in FIG. 7 . Alternatively, the ceramic plate stack 20 may have a gas flow path 80 at a position facing the amorphous layer 25 of the third ceramic plate 23, as shown in FIG. 8 . In FIGS. 7 and 8 , the same components as those in the above-described embodiment are denoted by the same reference numerals. The gas flow path 80 is an annular flow path that is concentric with the ceramic plate stack 20. The ceramic plate stack 20 includes a gas supply path 81 that is provided so as to communicate with the gas flow path 80 from the underside of the cooling plate 30, and gas ejection paths 82 that open from multiple locations of the gas flow path 80 to the reference surface 26 c of the wafer mounting surface 26. Gas (e.g., a thermally conductive gas such as He gas) supplied from gas supply path 81 to gas flow path 80 is filled from gas ejection path 82 into the space below wafer W (the space surrounded by the lower surface of wafer W, seal band 26a, small circular protrusions 26b, and reference surface 26c). The filled gas improves thermal conduction between wafer W and wafer mounting surface 26.

[0053] In the above-described embodiment, when the first ceramic plate 21 loses its original characteristics due to aging or the like, the semiconductor manufacturing equipment member 10 can be recycled and reused by the method for recycling the semiconductor manufacturing equipment member 10 shown in Figures 9 to 11. In Figures 9 to 11, the same components as those in the above-described embodiment are denoted by the same reference numerals. For convenience, the bonding sheet 40 and the cooling plate 30 are omitted in Figures 9 to 11.

[0054] For example, in FIG. 9, the upper surface (including the wafer mounting surface 26) of the first ceramic plate 21 of the semiconductor manufacturing equipment component 10 (FIG. 9A) is machined up to the chucking electrode 27 (FIG. 9B). As a result, a machined surface from which the wafer mounting surface 26 has been removed is formed on the first ceramic plate 21. Next, the machined surface of the first ceramic plate 21 is further machined to form a new wafer mounting surface 126 (seal band 126a, small circular protrusions 126b, and reference surface 126c) (FIG. 9C). This results in a reusable semiconductor manufacturing equipment component 110. The machining method is not particularly limited, but examples include grinding and polishing. Other machining methods include blasting and laser machining. By masking the wafer mounting surface 26 before performing the blasting, the seal band 26a and small circular protrusions 26b that constitute the wafer mounting surface 26 can be selectively removed. The new wafer placement surface 126 (seal band 126a, small circular protrusion 126b, and reference surface 126c) can be formed by blasting or laser processing.

[0055] In FIG. 10, the upper surface (including the wafer mounting surface 26) of the first ceramic plate 21 of the semiconductor manufacturing equipment component 10 (FIG. 10A) is machined up to the chucking electrode 27 (FIG. 10B). This removes the wafer mounting surface 26, forming a machined surface on the first ceramic plate 21. Next, a recycled ceramic plate 221 with a volume resistivity sufficient to exert the Johnsen-Rahbek force is prepared (FIG. 10C). The recycled ceramic plate 221 has a wafer mounting surface 226 (seal band 226a, small circular protrusions 226b, and reference surface 226c) pre-formed on its upper surface. Next, the machined surface of the first ceramic plate 21 and the lower surface of the recycled ceramic plate 221 are lapped and polished. After surface activation, the two plates are bonded together (direct bonding, FIG. 10D). After bonding, an amorphous layer 224 is formed between the first ceramic plate 21 and the recycled ceramic plate 221. This results in a reusable semiconductor manufacturing equipment component 210. The ceramic plate 221 for recycling may not have the wafer mounting surface 226. In this case, the ceramic plate 221 for recycling may be bonded to the processed surface of the first ceramic plate 21, and then the wafer mounting surface 226 may be formed on the upper surface of the ceramic plate 221 for recycling. The processing method is not particularly limited, and examples include grinding or polishing. Other processing methods include blasting and laser processing. The ceramic plate 221 for recycling may have any volume resistivity sufficient to exert the Johnsen-Rahbek force. However, to reproduce the performance of the semiconductor manufacturing equipment component 10, it is preferable that the ceramic plate 221 for recycling have the same composition as the first ceramic plate 21. The wafer mounting surface 226 can be formed by blasting, laser processing, or the like.

[0056] In FIG. 11, the first ceramic plate 21 of the semiconductor manufacturing equipment component 10 (FIG. 11A) is machined and removed to expose the second ceramic plate 22 (FIG. 11B). Here, the first amorphous layer 24 is machined and removed along with the first ceramic plate 21 (and the second affected layer 22a (see FIG. 3) may also be removed). This results in a machined surface (exposed surface) on the second ceramic plate 22. Next, a reclaimed ceramic plate 321 is prepared (FIG. 11C), which has a volume resistivity sufficient to exert the Johnsen-Rahbek force and an embedded chucking electrode 327. The reclaimed ceramic plate 321 has a wafer mounting surface 326 (seal band 326a, small circular protrusions 326b, and reference surface 326c) pre-formed on its upper surface. The exposed machined surface of the second ceramic plate 22 and the underside of the reclaimed ceramic plate 321 are then lapped and polished. After surface activation of the polished surfaces, the two are bonded together (direct bonding, FIG. 11D). After bonding, an amorphous layer 324 is formed between the reclaimed ceramic plate 321 and the second ceramic plate 22. This results in a reusable semiconductor manufacturing equipment component 310. The reclaimed ceramic plate 321 may not have a wafer mounting surface 326. In this case, the reclaimed ceramic plate 321 is bonded to the exposed processed surface of the second ceramic plate 22, and then the wafer mounting surface 326 is formed on the upper surface of the reclaimed ceramic plate 321. The processing method is not particularly limited, but examples include grinding or polishing. Other processing methods include blasting and laser processing. The reclaimed ceramic plate 221 may have any volume resistivity sufficient to exert the Johnsen-Rahbek force. However, to reproduce the performance of the semiconductor manufacturing equipment component 10, it is preferable that the reclaimed ceramic plate 221 have the same composition as the first ceramic plate 21. The wafer mounting surface 326 can be formed by blasting, laser processing, or the like.

[0057] In the ceramic plate stack 20 of the semiconductor manufacturing equipment member 10 described above, the third ceramic plate 23 is formed from a material having a higher thermal conductivity than the second ceramic plate 22, but the material is not limited to this. For example, the third ceramic plate 23 may be formed from a material having a lower purity than the second ceramic plate 22 (for example, an alumina sintered body with a purity of 90 to 95%). This allows the cost of the third ceramic plate 23 to be kept low.

[0058] The ceramic plate stack 20 of the semiconductor manufacturing equipment member 10 described above includes the third ceramic plate 23, but the third ceramic plate 23 may not be included.

[0059] In the semiconductor manufacturing equipment member 10 described above, the heater electrode 28 is embedded in the second ceramic plate 22, but instead of or in addition to the heater electrode 28, an RF electrode may be embedded.

[0060] In the semiconductor manufacturing equipment member 10 described above, a resistance heating element wired across the entire wafer mounting surface 26 is used as the heater electrode 28. However, for example, the wafer mounting surface 26 may be divided into multiple zones, and a heater electrode may be embedded in each zone so that power can be controlled independently.

[0061] In the semiconductor manufacturing equipment member 10 described above, at least one of the side surface of the ceramic plate stack 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be coated with an insulating film. Examples of the insulating film include a thermally sprayed film of alumina, yttria, or the like. [Explanation of symbols]

[0062] 10 Semiconductor manufacturing equipment member, 20 Ceramic plate laminate, 21 First ceramic plate, 21a First affected layer, 22 Second ceramic plate, 22a Second affected layer, 22b Third affected layer, 23 Third ceramic plate, 23b Fourth affected layer, 24 First amorphous layer, 25 Second amorphous layer, 26 Wafer mounting surface, 26a Seal band, 26b Small circular protrusion, 26c Reference surface, 27 Adsorption electrode, 28 Heater electrode, 30 Cooling plate, 32 Coolant flow path, 40 Adhesive sheet, 50 Polishing device, 52 Polishing table, 54 Polishing pad, 56 Carrier, 58 Pipe, 70 Coolant flow path, 80 Gas flow path, 81 Gas supply path, 82 Gas ejection path.

Claims

1. a first ceramic plate having a wafer mounting surface on its upper surface and incorporating an adsorption electrode; a second ceramic plate disposed on a lower surface of the first ceramic plate; a first amorphous layer present between the first ceramic plate and the second ceramic plate; Equipped with the first ceramic plate has a volume resistivity capable of exerting a Johnsen-Rahbek force; Components for semiconductor manufacturing equipment.

2. a thickness of the first ceramic plate above the chucking electrode is 0.5 mm or more; The semiconductor manufacturing equipment member according to claim 1 .

3. The volume resistivity of the first ceramic plate is 1×10 9 1x10 or more 12 Ωcm or less, The semiconductor manufacturing equipment member according to claim 1 or 2.

4. the first ceramic plate is an aluminum nitride plate; the second ceramic plate is an alumina plate; The semiconductor manufacturing equipment member according to claim 1 or 2.

5. 3. The semiconductor manufacturing equipment member according to claim 1 or 2, a first affected layer present on a side of the first ceramic plate that contacts the first amorphous layer; a second affected layer present on a side of the second ceramic plate that contacts the first amorphous layer; A semiconductor manufacturing equipment component comprising:

6. 3. The semiconductor manufacturing equipment member according to claim 1 or 2, a third ceramic plate disposed on a lower surface of the second ceramic plate; a second amorphous layer present between the second ceramic plate and the third ceramic plate; A semiconductor manufacturing equipment component comprising:

7. a coolant flow path through which a coolant flows or a gas flow path through which a gas is supplied to the wafer mounting surface is provided at a position of the second ceramic plate facing the second amorphous layer or at a position of the third ceramic plate facing the second amorphous layer; The semiconductor manufacturing equipment member according to claim 6.

8. 7. The semiconductor manufacturing equipment member according to claim 6, a third affected layer present on a side of the second ceramic plate that contacts the second amorphous layer; a fourth affected layer present on a side of the third ceramic plate that contacts the second amorphous layer; A semiconductor manufacturing equipment component comprising:

9. (a) processing an upper surface of the first ceramic plate of the semiconductor manufacturing equipment member according to claim 1 or 2 up to a position just before the chucking electrode to form a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; (b) further processing the processed surface to form a new wafer mounting surface; A method for recycling semiconductor manufacturing equipment components, comprising:

10. (a) processing an upper surface of the first ceramic plate of the semiconductor manufacturing equipment member according to claim 1 or 2 up to a position just before the chucking electrode to form a processed surface on the first ceramic plate from which the wafer mounting surface has been removed; (b) directly bonding a ceramic plate for regeneration having a volume resistivity capable of exerting the Johnsen-Rahbek force to the processed surface; A method for recycling semiconductor manufacturing equipment components, comprising:

11. (a) processing the first ceramic plate of the semiconductor manufacturing equipment member according to claim 1 or 2 to remove the second ceramic plate so as to expose the second ceramic plate, thereby forming a processed surface on the second ceramic plate; (b) directly bonding a ceramic plate for regeneration, which has a volume resistivity capable of exerting the Johnsen-Rahbek force and a built-in chucking electrode, to the processed surface; A method for recycling semiconductor manufacturing equipment components, comprising:

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