Semiconductor manufacturing equipment member and regeneration method thereof

Abstract

To provide a semiconductor manufacturing equipment member that can suppress heat generation when RF is applied and also has other required performance characteristics.SOLUTION: A semiconductor manufacturing equipment member includes a first ceramic portion having an upper surface that has a wafer mounting surface and a lower surface located opposite the upper surface, a second ceramic portion bonded to the lower surface of the first ceramic portion, an amorphous layer present at the bonding interface between the first ceramic portion and the second ceramic portion, and a high-frequency electrode disposed inside the first ceramic portion or between the first ceramic portion and the second ceramic portion, and the first ceramic part has a smaller dielectric tangent (tanδ) than the second ceramic portion.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor manufacturing equipment member and a method for recycling the same. [Background technology]

[0002] Conventionally, semiconductor manufacturing equipment components used for wafer holding, temperature control, transport, etc. have been known. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract the wafer by electrostatic force. Some semiconductor manufacturing equipment components have a high-frequency electrode (RF electrode) embedded in a ceramic substrate, and use this RF electrode to generate plasma.

[0003] A known example of such a semiconductor manufacturing equipment component is a ceramic substrate having an upper surface with a wafer mounting surface and a lower surface opposite the upper surface, and incorporating an RF electrode. The wafer mounting surface can be formed, for example, by the upper end surfaces of multiple protrusions provided on the upper surface of the ceramic substrate.

[0004] In recent years, high-power, high-speed etching equipment has been used to perform high-aspect-ratio microfabrication in the manufacture of multilayer 3D NAND and other devices. Materials for semiconductor manufacturing equipment components used in such etching equipment are required to have low RF loss, high dielectric constant, and resistance to dielectric breakdown. Furthermore, a low tan δ (i.e., dielectric loss tangent) is also required to suppress heat generation when RF is applied.

[0005] Therefore, Patent Document 1 proposes using a composite sintered body comprising aluminum oxide, silicon carbide, and a magnesium-aluminum composite oxide having a spinel crystal structure as a material for forming a ceramic substrate for semiconductor manufacturing equipment components.

[0006] Patent Document 2 states that the dielectric loss tangent tanδ at frequencies of 1 to 20 GHz is 1×10-4 The following yttria sintered body is described.

[0007] Patent Document 3 states that the dielectric loss tangent tanδ at a frequency of 1 MHz is 5×10 -4 The following alumina sintered body is described. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 7227954 [Patent Document 2] Patent No. 5466831 [Patent Document 3] Patent No. 5421092 Summary of the Invention [Problem to be solved by the invention]

[0009] The materials proposed in Patent Documents 1 to 3 have a small dielectric loss tangent, which allows them to suppress heat generation when RF is applied. On the other hand, there are cases where components for semiconductor manufacturing equipment are required to have performance other than a small dielectric loss tangent, such as high thermal uniformity and high heat removal. In addition to having a small dielectric loss tangent, the materials described in Patent Documents 1 to 3 are also described as having a high relative dielectric constant and high withstand voltage, but there are limits to the properties that can be combined.

[0010] Furthermore, if the quality of a semiconductor manufacturing equipment component deteriorates, the deteriorated semiconductor manufacturing equipment component can be discarded. However, from the perspective of reducing waste, making effective use of resources, and promoting a circular economy, it is desirable to be able to repair and regenerate semiconductor manufacturing equipment components.

[0011] In view of the above circumstances, an object of the present invention is to provide, in one embodiment, a semiconductor manufacturing equipment component that is capable of suppressing heat generation when RF is applied and also capable of satisfying other required performances. Also, an object of the present invention is to provide, in another embodiment, a method for recycling a semiconductor manufacturing equipment component. [Means for solving the problem]

[0012] The present inventors have conducted extensive research to solve the above problems and have created the present invention, which is exemplified below. [Aspect 1] A semiconductor manufacturing equipment component comprising: a first ceramic part having an upper surface that has a wafer mounting surface and a lower surface located opposite the upper surface; a second ceramic part bonded to the lower surface of the first ceramic part; a first amorphous layer present at the bonding interface between the first ceramic part and the second ceramic part; and a high-frequency electrode disposed inside the first ceramic part or between the first ceramic part and the second ceramic part, wherein the first ceramic part has a smaller dielectric loss tangent (tanδ) than the second ceramic part. [Aspect 2] The dielectric loss tangent (tanδ) of the first ceramic part at a measurement frequency of 1 MHz is 1×10 -3 A semiconductor manufacturing equipment member according to aspect 1, wherein: [Aspect 3] 3. The semiconductor manufacturing equipment member according to aspect 1 or 2, wherein the first ceramic portion is a plate having a plurality of protrusions on the upper surface, the protrusions having the wafer mounting surface. [Aspect 4] 4. The member for a semiconductor manufacturing equipment according to any one of Aspects 1 to 3, wherein the second ceramic portion has a higher thermal conductivity than the first ceramic portion. [Aspect 5] A semiconductor manufacturing equipment member according to any one of aspects 1 to 4, a first affected layer present on a side of the first ceramic portion that contacts the first amorphous layer; a second affected layer present on a side of the second ceramic portion that contacts the first amorphous layer; A semiconductor manufacturing equipment component comprising: [Aspect 6] A semiconductor manufacturing equipment member according to any one of aspects 1 to 5, a third ceramic portion joined to a lower surface of the second ceramic portion; a second amorphous layer present at a bonding interface between the second ceramic portion and the third ceramic portion; A semiconductor manufacturing equipment component comprising: [Aspect 7] a refrigerant flow path through which a refrigerant flows or a gas flow path for supplying a gas to the wafer mounting surface is provided at a position of the second ceramic part facing the second amorphous layer or at a position of the third ceramic part facing the second amorphous layer; A member for semiconductor manufacturing equipment according to embodiment 6. [Aspect 8] The semiconductor manufacturing equipment member according to aspect 6 or 7, a third affected layer present on a side of the second ceramic portion that contacts the second amorphous layer; a fourth affected layer present on a side of the third ceramic portion that contacts the second amorphous layer; A semiconductor manufacturing equipment component comprising: [Aspect 9] processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment member according to any one of aspects 1 to 8 to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed; and further processing the processed surface to form a new wafer-mounting surface. [Aspect 10] processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment member according to any one of aspects 1 to 8 to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed; a step of directly bonding a ceramic part for recycling, which has a smaller dielectric tangent (tanδ) than the second ceramic part, to the processed surface; A method for recycling semiconductor manufacturing equipment components, comprising: [Aspect 11] a step of processing the first ceramic portion of the semiconductor manufacturing equipment member according to any one of aspects 1 to 8, removing the first ceramic portion so as to expose the second ceramic portion, and forming a processed surface on the second ceramic portion; a step of directly bonding a ceramic part for recycling, which has a smaller dielectric tangent (tanδ) than the second ceramic part, to the processed surface of the second ceramic part; A method for recycling semiconductor manufacturing equipment components, comprising: [Effects of the Invention]

[0013] A semiconductor manufacturing equipment member according to one embodiment of the present invention includes a first ceramic portion having a small dielectric dissipation factor (tanδ), thereby suppressing heat generation when RF is applied. Furthermore, the semiconductor manufacturing equipment member includes a second ceramic portion having a large dielectric dissipation factor (tanδ), which allows the semiconductor manufacturing equipment member to exhibit characteristics different from those of the first ceramic portion. The material of the second ceramic portion can be appropriately changed depending on the required performance. Therefore, the semiconductor manufacturing equipment member can not only suppress heat generation when RF is applied, but also satisfy other required performance requirements. For example, by constructing the second ceramic portion from a material with high thermal conductivity, it is possible to achieve both high thermal uniformity and high heat dissipation.

[0014] Furthermore, even if the quality of the semiconductor manufacturing equipment component deteriorates due to shedding of ceramic particles that make up the protrusions on the wafer-mounting surface, the component can be repaired and recycled without having to be newly manufactured from scratch. Therefore, this recycling method significantly contributes to reducing waste, making effective use of resources, and promoting a circular economy. [Brief explanation of the drawings]

[0015] [Figure 1A] 1 is an example of a schematic partial vertical cross-sectional view of a semiconductor manufacturing equipment member according to embodiment A of the present invention. [Figure 1B-1] 10 is an example of a schematic partial vertical cross-sectional view of a semiconductor manufacturing equipment member according to embodiment B of the present invention. [Figure 1B-2] 10 is a schematic partial vertical cross-sectional view of another example of a semiconductor manufacturing equipment member according to embodiment B of the present invention. [Figure 2] FIG. 1B is a schematic partial enlarged view of the part surrounded by a bold frame shown in FIG. 1A. [Figure 3] 1 is a schematic plan view of a wafer-mounting surface of a semiconductor manufacturing equipment member according to embodiment A of the present invention. FIG. [Figure 4] 1A to 1C are diagrams for explaining an example of a method for manufacturing a semiconductor manufacturing equipment member. [Figure 5A] FIG. 2 is a diagram illustrating a reproducing method A according to one embodiment of the present invention. [Figure 5B] FIG. 10 is a diagram illustrating a reproducing method B according to one embodiment of the present invention. [Figure 5C] FIG. 10 is a diagram illustrating a reproducing method C according to one embodiment of the present invention. [Figure 6] FIG. 1 is a schematic perspective view of a polishing apparatus for performing lapping. DETAILED DESCRIPTION OF THE INVENTION

[0016] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when a semiconductor manufacturing equipment component is placed on a horizontal surface with the wafer-mounting surface facing up, and do not represent an absolute positional relationship. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0017] <1. Basic structure of semiconductor manufacturing equipment components> A semiconductor manufacturing equipment member according to one embodiment of the present invention includes a first ceramic part having an upper surface with a wafer mounting surface and a lower surface located opposite the upper surface, a second ceramic part bonded to the lower surface of the first ceramic part, a first amorphous layer present at the bonding interface between the first ceramic part and the second ceramic part, and a high-frequency electrode disposed inside the first ceramic part or between the first ceramic part and the second ceramic part, wherein the first ceramic part has a smaller dielectric loss tangent (tan δ) than the second ceramic part. This semiconductor manufacturing equipment member can be used, for example, when performing processes such as CVD or etching on a wafer W using plasma.

[0018] In one embodiment, the first ceramic part can be provided in the form of a plate having a plurality of protrusions on its upper surface, the protrusions having a wafer-receiving surface.

[0019] The first ceramic part has a smaller dielectric loss tangent (tan δ) (typically, the dielectric loss tangent (tan δ) at measurement frequencies of 1 MHz and 13.56 MHz) than the second ceramic part, which makes it possible to suppress heat generation when high frequency is applied to the high frequency electrode. Since the first ceramic part has a wafer mounting surface, heat generation in the first ceramic part is suppressed, which makes it possible to suppress temperature rise of the wafer.

[0020] Since the high-frequency electrode is prone to heat generation when placed in the second ceramic part, which has a large dielectric tangent (tan δ), it is preferable that it be placed inside the first ceramic part or between the first and second ceramic parts, and from the standpoint of heat generation suppression effect, it is more preferable that it be built into the first ceramic part.

[0021] The upper limit of the dielectric tangent (tanδ) of the first ceramic part is 1×10 at a measurement frequency of 1MHz. -3 Preferably, it is 5 x 10 or less. -4 More preferably, it is 2×10 or less. -4Although there is no particular lower limit for the dielectric loss tangent (tan δ) of the first ceramic portion, from the viewpoint of ease of availability, it is preferable that the lower limit be 1×10 -4 Therefore, the dielectric loss tangent (tan δ) of the first ceramic portion is preferably 1×10 or more at a measurement frequency of 1 MHz, for example. -4 More than 1×10 -3 Preferably, it is 1×10 or less. -4 5x10 or more -4 More preferably, it is 1×10 or less. -4 Over 2×10 -4 Even more preferably, the following:

[0022] The dielectric loss tangent (tanδ) at a measurement frequency of 1 MHz is measured by the resonance method in accordance with JIS C2138:2007 at a temperature of 25°C and a relative humidity of 50%, using, for example, a DAC-ASM-7 device manufactured by Soken Denki Co., Ltd. The dielectric loss tangent (tanδ) is measured on test pieces taken from the first ceramic part and the second ceramic part. If it is difficult to take test pieces, test pieces made of the same material as the first ceramic part and the second ceramic part may be prepared and used for measurement.

[0023] Dielectric loss tangent (tanδ) is 1×10 at a measurement frequency of 1MHz -3 The ceramics described below can be any known ceramics that satisfy the dielectric loss tangent requirements, including, for example, the ceramics described in Patent Documents 1 to 3. More specifically, they include alumina, aluminum nitride, yttria, and quartz, which have low dielectric loss tangents. The first ceramic portion may contain one type of ceramic, or a combination of two or more types of ceramics. The dielectric loss tangent (tanδ) of the first ceramic portion as a whole at a measurement frequency of 1 MHz should be smaller than that of the second ceramic portion, and the first ceramic portion may partially contain a ceramic having a dielectric loss tangent (tanδ) larger than that of the second ceramic portion.

[0024] The second ceramic part has a larger dielectric loss tangent (tanδ) (typically, the dielectric loss tangent (tanδ) at a measurement frequency of 1 MHz) than the first ceramic part. For example, the dielectric loss tangent (tanδ) of the second ceramic part at a measurement frequency of 1 MHz is 1×10 -3 May be greater than 1 x 10 -3 super 1×10 -2 May be less than 1 x 10 -3 super 1×10 -1 May be less than 1 x 10 -3 It may be greater than or equal to 1.

[0025] Furthermore, from the viewpoint of facilitating the dissipation of heat generated in the first ceramic portion, it is preferable that the second ceramic portion have a higher thermal conductivity than the first ceramic portion. Specifically, the thermal conductivity at 20°C is preferably 50 W / (m·K) or higher, more preferably 70 W / (m·K) or higher, and even more preferably 90 W / (m·K) or higher. There is no particular upper limit to the thermal conductivity of the second ceramic portion, but from the viewpoint of availability, the thermal conductivity at 20°C is preferably 150 W / (m·K) or lower, more preferably 120 W / (m·K) or lower, and even more preferably 100 W / (m·K) or lower. Therefore, the thermal conductivity of the second ceramic portion at 20°C is preferably, for example, 50 to 150 W / (m·K), more preferably 70 to 120 W / (m·K), and even more preferably 90 to 100 W / (m·K).

[0026] The thermal conductivity value is measured by the laser flash method (JIS R1611-2010).

[0027] Examples of ceramics that form the second ceramic portion include alumina and aluminum nitride. The second ceramic portion may contain one type of ceramic or a combination of two or more types of ceramics.

[0028] The dielectric dissipation factor (tanδ) of the second ceramic portion as a whole must be larger than that of the first ceramic portion, and the second ceramic portion may be partially composed of ceramics whose dielectric dissipation factor (tanδ) is equal to or smaller than that of the first ceramic portion.

[0029] The first ceramic part and the second ceramic part are preferably bonded via a first amorphous layer. In this case, the bonding layer between the first ceramic part and the second ceramic part can be made extremely thin, thereby reducing the thermal resistance between the first ceramic part and the second ceramic part. In this case, the first ceramic part may have a first altered layer present on the side in contact with the first amorphous layer, and the second ceramic part may have a second altered layer present on the side in contact with the first amorphous layer.

[0030] Furthermore, a third ceramic part may be bonded to the underside of the second ceramic part. In this case, the second ceramic part and the third ceramic part are preferably bonded via a second amorphous layer. In this case, the second ceramic part may have a third altered layer present on the side in contact with the second amorphous layer, and the third ceramic part may have a fourth altered layer present on the side in contact with the second amorphous layer.

[0031] There is no particular limitation on the dielectric loss tangent (tanδ) of the third ceramic part. However, from the viewpoint of ease of availability, the dielectric loss tangent (tanδ) (typically, the dielectric loss tangent (tanδ) at a measurement frequency of 1 MHz) may be larger than that of the first ceramic part. For example, the dielectric loss tangent (tanδ) of the third ceramic part at a measurement frequency of 1 MHz may be 1×10 -3 It may be super.

[0032] Examples of ceramics that can be used to form the third ceramic portion include alumina and aluminum nitride. Among these, aluminum nitride is preferred due to its high thermal conductivity. The third ceramic portion may contain one type of ceramic or a combination of two or more types of ceramics. It is preferable that the dielectric loss tangent (tanδ) of the third ceramic portion as a whole is larger than that of the first ceramic portion. However, the third ceramic portion may contain ceramics whose dielectric loss tangent (tanδ) is equal to or smaller than that of the first ceramic portion.

[0033] In one embodiment, a refrigerant flow path through which a refrigerant flows or a gas flow path for supplying gas to the wafer mounting surface can be provided at a position of the second ceramic part facing the second amorphous layer and / or at a position of the third ceramic part facing the second amorphous layer.

[0034] When the first ceramic part and the second ceramic part are joined via a first amorphous layer, the first amorphous layer preferably contains at least one element constituting the first ceramic part and at least one element constituting the second ceramic part. Similarly, when the second ceramic part and the third ceramic part are joined via a second amorphous layer, the second amorphous layer preferably contains at least one element constituting the second ceramic part and at least one element constituting the third ceramic part.

[0035] When a longitudinal cross section of a semiconductor manufacturing equipment component near the interface between the first and second ceramic parts (the second and third ceramic parts) is observed with a transmission electron microscope (TEM) at 4 million magnifications, the first amorphous layer (the second amorphous layer) is observed as a thin strip. The first amorphous layer (the second amorphous layer) may be formed as a single layer or as multiple layers (e.g., three layers). The average thickness of the first amorphous layer (the second amorphous layer) is preferably 0.1 nm or more, more preferably 1 nm or more, to enhance the bonding strength between the first and second ceramic parts (the second and third ceramic parts). Furthermore, the average thickness of the first amorphous layer (the second amorphous layer) is preferably 30 nm or less, more preferably 20 nm or less, to prevent the incorporation of different materials. Therefore, the average thickness of the first amorphous layer (second amorphous layer) is, for example, preferably 0.1 nm or more and 30 nm or less, and more preferably 1 nm or more and 20 nm or less. When the first amorphous layer (second amorphous layer) is composed of multiple layers, the thickness of the first amorphous layer (second amorphous layer) refers to the total thickness of the multiple layers.

[0036] The average thickness of the first amorphous layer (second amorphous layer) at the bonding interface between the first ceramic part and the second ceramic part (the second ceramic part and the third ceramic part) is measured by TEM observation using the following procedure. On a TEM photograph (magnification: 4,000,000 times) of one field of view in a vertical cross section including the bonding interface, the thickness of the first amorphous layer (second amorphous layer) is measured at five locations at 10 nm intervals along the bonding interface, and the average thickness of the first amorphous layer (second amorphous layer) in one field of view is determined. This thickness measurement by TEM observation is performed evenly across five fields of view, including near the center, periphery, and radius center when the semiconductor manufacturing equipment component is viewed in plan. The average thickness of the first amorphous layer (second amorphous layer) in the five fields of view is then taken as the measured value.

[0037] The fact that the thin strip observed by TEM is an amorphous layer can be confirmed by observing, when an X-ray diffraction pattern is obtained by XRD for the thin strip, a broader peak is observed inside the thin strip than in the part of the first ceramic part (second ceramic part) that is sufficiently distant from the bonding interface.

[0038] It can be confirmed by EDS (Energy Dispersive X-ray Spectroscopy) or EPMA (Electron Probe Micro Analyzer) that the first amorphous layer (second amorphous layer) contains at least one element constituting the first ceramic portion and the second ceramic portion (second ceramic portion and third ceramic portion) and at least one element constituting the ceramic plate 70. In a preferred embodiment, the first amorphous layer (second amorphous layer) contains at least one amorphous material (e.g., amorphous yttria, amorphous aluminum nitride, amorphous alumina, etc.) constituting the first ceramic portion and the second ceramic portion (second ceramic portion and third ceramic portion).

[0039] The first altered layer is present on the side of the first ceramic part that contacts the first amorphous layer, and the second altered layer is present on the side of the second ceramic part that contacts the first amorphous layer. In the TEM photograph mentioned above, they are observed as layered discolored areas adjacent to the aforementioned thin band-like portion. The thickness of the first and second altered layers is preferably 10 nm or more, more preferably 100 nm or more and 1 μm or less. The presence of the first altered layer (second altered layer) can be confirmed by observing, when an X-ray diffraction pattern is obtained by XRD near the bonding interface, a peak adjacent to the aforementioned thin band-like portion that is sharper than the first amorphous layer but broader than the portion of the first ceramic part (second ceramic part) sufficiently distant from the bonding interface.

[0040] The third altered layer is present on the side of the second ceramic part that contacts the second amorphous layer, and the fourth altered layer is present on the side of the third ceramic part that contacts the second amorphous layer. In the TEM photograph mentioned above, they are observed as layered discolored areas adjacent to the aforementioned thin band-like portion. The thickness of the third and fourth altered layers is preferably 10 nm or more, more preferably 100 nm or more and 1 μm or less. The presence of the third altered layer (fourth altered layer) can be confirmed by observing, when an X-ray diffraction pattern is obtained by XRD near the bonding interface, a peak adjacent to the aforementioned thin band-like portion that is sharper than the second amorphous layer but broader than the portion of the second ceramic part (third ceramic part) sufficiently distant from the bonding interface.

[0041] 2. Specific Embodiments of Semiconductor Manufacturing Equipment Components (2-1. Embodiment A) 1A, the semiconductor manufacturing equipment member 10A includes a ceramic plate 70 having an upper surface 71 with a plurality of protrusions 72 on which a wafer W can be placed and a lower surface 73 located opposite the upper surface 71, a ceramic substrate 20 bonded to the lower surface 73 of the ceramic plate 70, an amorphous layer 80 present at the bonding interface between the ceramic plate 70 and the ceramic substrate 20, an electrostatic chucking electrode 26a embedded in the ceramic plate 70, and a high-frequency electrode 26b disposed inside the ceramic plate 70 or between the ceramic plate 70 and the ceramic substrate 20. The semiconductor manufacturing equipment member 10A also includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded via a bonding layer 40.

[0042] In embodiment A, the ceramic plate 70 corresponds to the first ceramic portion described above, and the ceramic substrate 20 corresponds to the second ceramic portion described above. The amorphous layer 80 corresponds to the first amorphous layer described above. The ceramic plate 70 has a smaller dielectric loss tangent (tan δ) than the ceramic substrate 20, and therefore can suppress heat generation when a high frequency is applied to the high-frequency electrode 26b.

[0043] The ceramic substrate 20 includes a central portion 201 having a circular upper surface 21 in a planar view, and an outer peripheral portion 202 having an annular upper surface 27 in a planar view, located around the central portion 201. The central portion 201 of the ceramic substrate 20 may have a diameter of 130 to 450 mm and a thickness of 1 to 5 mm, for example. The protrusions 72 may have a height of 5 to 100 μm, for example. A wafer W can be placed on the upper surface 71 of a ceramic plate 70 bonded to the upper surface 21 of the central portion 201. A focus ring (not shown) can be placed on the upper surface 27 of the outer peripheral portion 202 of the ceramic substrate 20. The upper surface 27 of the outer peripheral portion 202 is one step lower than the upper surface 21 of the central portion 201. The lower surfaces 23 of the central portion 201 and the outer peripheral portion 202 may be flush with each other. The ceramic substrate 20 may have the central portion 201 but not the outer peripheral portion 202, that is, may not have the lower upper surface 27.

[0044] The upper surface 71 of the ceramic plate 70 is provided with a plurality of protrusions 72 for placing a wafer W thereon, and the upper surfaces 71a of the protrusions 72 form the wafer-mounting surface. The upper surface 71 may also have a seal band 75 formed along its outer edge, in which case the upper surface 71c of the seal band 75 can also form the wafer-mounting surface. It is preferable that the seal band 75 and the plurality of protrusions 72 be of the same height. As shown in FIG. 3, in one embodiment, the upper surface 71 of the ceramic plate 70 is formed with an annular seal band 75 along its outer edge, and the plurality of protrusions 72 are formed over the entire inner surface of the seal band 75.

[0045] 2 is a schematic enlarged view of the portion enclosed by the bold frame in FIG. 1A, showing a schematic structure of protrusions 72 provided on an upper surface 71 of a ceramic plate 70. The number density of the protrusions 72 per unit area in a plan view is, for example, 1 to 150 pieces / mm 2 The number of pieces can be 10 to 150 pieces / mm. 2 The shape of the protrusions 72 is not limited, but may be, for example, a columnar shape such as a cylinder or a rectangular pillar. The height h of the protrusions 72 is, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 72 is, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm. Here, the diameter d of the protrusions 72 refers to the circle-equivalent diameter when the protrusions 72 are viewed from above. The portion of the upper surface 71 of the ceramic plate 70 on which the seal band 75 and the protrusions 72 are not provided is referred to as the reference surface 71b.

[0046] At least the upper surfaces 71a of the plurality of protrusions 72 may be covered with a coating film. Similarly, at least the upper surface 71c of the seal band 75 may be covered with a coating film. Examples of the coating film include a coating film containing at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0047] The electrostatic chucking electrode 26a is a planar electrode used as an electrostatic chucking electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26a is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter (LPF) may be disposed along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26a, the wafer W is electrostatically attracted and fixed to the wafer mounting surface—specifically, the upper surface 71c of the seal band 75 and the upper surfaces 71a of the protrusions 72—by electrostatic attraction. When the DC voltage is removed, the wafer W is released from the wafer mounting surface. The electrode 26a may be embedded in either the ceramic plate 70 or the ceramic substrate 20, but is preferably embedded in a position where the electrode 26a will remain when the semiconductor manufacturing equipment component 10A is reclaimed.

[0048] The high-frequency electrode 26b is an RF electrode for generating plasma and is connected to an external RF power supply via a power supply member (not shown). The electrode 26b is made of a material containing, for example, W, Mo, WC, MoC, etc. A high-pass filter (HPF) may be disposed midway along the power supply member.

[0049] In addition to these electrodes, another electrode may be built into the ceramic plate 70 or the ceramic substrate 20. For example, a heater electrode (resistance heating element) may be built in. In this case, a heater power supply is connected to the heater electrode. The other electrode may be built in as a single layer, or in two or more layers spaced apart.

[0050] The base plate 30 may be, for example, disk-shaped. The base plate 30 may have an annular flange on its lower surface, which is used to clamp the semiconductor manufacturing equipment member 10A to a jig in the chamber. The thickness of the base plate 30 may be 20 to 40 mm, typically 25 to 35 mm. The base plate 30 is connected to a radio frequency (RF) power source and can also be used as an RF electrode.

[0051] The base plate 30 may be a circular plate (having the same diameter as or larger than the ceramic substrate 20) with good electrical and thermal conductivity. A refrigerant flow path 32 through which a refrigerant circulates may be formed within the base plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant flow path 32 may be formed, for example, in a single stroke across the entire base plate 30 in a plan view from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port, respectively, of an external refrigerant device (not shown). The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0052] The base plate 30 can be made of, for example, a metal material or a composite material of metal and ceramic. Examples of metal materials include Al, Ti, Mo, and alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also called SiSiCTi), a material in which porous SiC is impregnated with Al and / or Si, and a composite material of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient similar to that of the material for the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, the base plate 30 is preferably made of SiSiCTi or AlSiC, which have a thermal expansion coefficient similar to that of alumina.

[0053] As shown in FIG. 1A , the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be formed, for example, by a metal layer made of solder or a metal brazing material. The bonding layer 40 is formed, for example, by thermal compression bonding (TCB). TCB is a known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of the metal layer. The resin bonding layer may be formed, for example, by a cured product of a silicone resin adhesive, an epoxy resin adhesive, an acrylic resin adhesive, or a urethane resin adhesive. Furthermore, by directly bonding the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the base plate 30, the bonding layer 40 can be made of an amorphous layer.

[0054] At least one of the side surface of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be covered with an insulating film 35. Examples of the insulating film 35 include a thermally sprayed film of alumina, yttria, or the like.

[0055] The semiconductor manufacturing equipment member 10A may have multiple holes penetrating the ceramic plate 70 and the ceramic substrate 20 in the vertical direction. Examples of such holes include multiple gas holes 50 opening in the upper surface 71 and lift pin holes for inserting lift pins that move the wafer W up and down relative to the upper surface 21. Multiple gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see FIG. 3 ). The gas holes 50 communicate with a gas flow path provided inside the base plate 30 and can supply a thermally conductive gas, such as He gas, that has passed through the gas flow path. Typically, the gas holes 50 are provided so as to open to a portion of the upper surface 71 where the seal band 75 and multiple protrusions 72 are not provided (reference surface 71b). The gas holes 50 are also formed at a position that does not overlap with the electrodes 26a and 26b. When a thermally conductive gas is supplied to the gas holes 50, the thermally conductive gas fills the space behind the wafer W placed on the upper surface 71. A plug 55 having a gas flow path may be embedded in the gas hole 50. A plurality of lift pin holes may be provided at equal intervals along concentric circles on the upper surface 71 when the upper surface 71 is viewed in plan.

[0056] (2-2. Embodiment B) 1B-1 and 1B-2, the semiconductor manufacturing equipment member 10B has a two-layer structure of a first ceramic substrate 20a and a second ceramic substrate 20b, whereas the semiconductor manufacturing equipment member 10A has a single-layer ceramic substrate 20. More specifically, the semiconductor manufacturing equipment member 10B includes a first ceramic substrate 20a bonded to a lower surface 73 of a ceramic plate 70, a first amorphous layer 80a present at the bonding interface between the ceramic plate 70 and the first ceramic substrate 20a, a second ceramic substrate 20b bonded to a lower surface 23a of the first ceramic substrate 20a, a second amorphous layer 80b present at the bonding interface between the first ceramic substrate 20a and the second ceramic substrate 20b, an electrostatic chucking electrode 26a built in the ceramic plate 70, and a high-frequency electrode 26b located inside the ceramic plate 70 or between the ceramic plate 70 and the ceramic substrate 20. The semiconductor manufacturing equipment member 10B also includes a base plate 30 located on the lower surface 23b side of the second ceramic substrate 20b and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded together via a bonding layer 40.

[0057] In embodiment B, the ceramic plate 70 corresponds to the first ceramic portion described above, the first ceramic substrate 20a corresponds to the second ceramic portion described above, and the second ceramic substrate 20b corresponds to the third ceramic portion described above. The first amorphous layer 80a corresponds to the first amorphous layer described above, and the second amorphous layer 80b corresponds to the second amorphous layer described above. The ceramic plate 70 has a smaller dielectric tangent (tan δ) than the ceramic substrate 20a, and thus can suppress heat generation when a high frequency is applied to the high frequency electrode 26b.

[0058] In embodiment B, as shown in FIG. 1B-1, a refrigerant flow path 28 through which a refrigerant flows may be provided in a position of the first ceramic substrate 20a facing the second amorphous layer 80b and / or a position of the second ceramic substrate 20b facing the second amorphous layer 80b. The refrigerant flow path 28 can be formed, for example, in a single stroke from one end (inlet) to the other end (outlet) across the entire wafer mounting surface in a plan view. A supply port and a recovery port of an external refrigerant device (not shown) can be connected to one end and the other end of the refrigerant flow path 28, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 28 passes through the refrigerant flow path 28, returns from the other end of the refrigerant flow path 28 to the recovery port of the external refrigerant device, and is temperature-adjusted before being supplied again from the supply port to one end of the refrigerant flow path 28.

[0059] In addition, in embodiment B, as shown in FIG. 1B-2, a gas flow path 29 for supplying gas to the wafer mounting surface may be provided at a position of the first ceramic substrate 20a facing the second amorphous layer 80b and / or at a position of the second ceramic substrate 20b facing the second amorphous layer 80b. The gas flow path 29 may be an annular flow path concentric with the first ceramic substrate 20a in a planar view. In this case, the semiconductor manufacturing equipment member 10B may include a gas inlet path 29a extending from the lower surface of the base plate 30 to the gas flow path 29, and gas supply paths 29b extending from multiple locations on the gas flow path 29 to gas supply ports 74 provided in the reference surface 71b. The gas (e.g., a thermally conductive gas such as He gas) supplied from the gas inlet path 29a to the gas flow path 29 passes through the gas supply path 29b and fills the space below the wafer W. The filled gas improves thermal conduction between the wafer W and the wafer mounting surface.

[0060] Among the reference numerals shown in FIGS. 1B-1 and 1B-2, the same reference numerals as those in FIGS. 1A and 2 are as described in the description of embodiment A, and therefore, redundant description will be omitted.

[0061] <2. How to use semiconductor manufacturing equipment parts> Next, a method of using a semiconductor manufacturing equipment member according to one embodiment of the present invention will be described using semiconductor manufacturing equipment member 10A as an example. First, semiconductor manufacturing equipment member 10A is placed in a chamber (not shown). A focus ring is placed on upper surface 27 of semiconductor manufacturing equipment member 10A, and a disk-shaped wafer W is placed on the wafer mounting surface, i.e., upper surface 71a of protrusion 72 and upper surface 71c of seal band 75. The chamber is then depressurized using a vacuum pump to adjust the chamber to a predetermined vacuum level, and a voltage is applied to electrode 26a to generate an electrostatic adsorption force, thereby adsorbing and fixing wafer W to the wafer mounting surface.

[0062] Next, a process gas is supplied from a shower head (not shown) to create a reactive gas atmosphere at a predetermined pressure (several tens to several hundreds of Pa) inside the chamber. In this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) provided on the ceiling inside the chamber and the high-frequency electrode 26b of the semiconductor manufacturing equipment member 10A. This generates plasma between the wafer W and the shower head. The plasma is then used to process the wafer W (by performing CVD film formation or etching).

[0063] A refrigerant circulates through the refrigerant flow path 32 of the base plate 30. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant flow path 32 via refrigerant piping, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0064] A gas flow path (not shown) is formed inside the base plate 30, and a backside gas can be introduced from a gas cylinder (not shown). A thermally conductive gas (e.g., He gas) can be used as the backside gas. After passing through the gas flow path inside the base plate 30, the backside gas flows out through the gas holes 50 and fills the space on the backside of the wafer W.

[0065] The focus ring also wears out as the wafers W are plasma processed. However, since the focus ring is thicker than the wafers W, the focus ring is replaced after processing a plurality of wafers W.

[0066] The semiconductor manufacturing equipment member 10B can also be used in a similar manner.

[0067] <3. Manufacturing methods for semiconductor manufacturing equipment components> Next, a method for manufacturing a semiconductor manufacturing equipment member according to one embodiment of the present invention will be described with reference to FIG. 4, using the semiconductor manufacturing equipment member 10A shown in FIG. 1A as an example. First, a disk-shaped ceramic sintered body 120, which is the basis for the ceramic plate 70, and a disk-shaped ceramic sintered body 121, which is the basis for the ceramic substrate 20, are each produced by hot-press sintering a ceramic powder compact (FIG. 4A). The ceramic sintered body 120 has a smaller dielectric loss tangent (tan δ) than the ceramic sintered body 121. The compact may be produced by stacking multiple tape compacts, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 has built-in electrodes 26a and 26b.

[0068] Next, the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are polished to form flat surfaces. There are no particular limitations on the polishing method, but lapping is preferred, for example. The flat surfaces preferably have a surface roughness (arithmetic mean roughness) Ra of 1 nm or less (e.g., 0.2 to 1 nm) measured with a non-contact surface roughness meter in accordance with ISO 25178.

[0069] For example, a polishing apparatus 60 shown in FIG. 6 can be used for lapping. The polishing apparatus 60 includes a large-diameter disc-shaped polishing platen 62 equipped with a polishing pad 64, a small-diameter disc-shaped carrier 66, and a pipe 68 for supplying a slurry containing abrasive grains to the polishing pad 64. The polishing platen 62 includes a shaft 67 at the center of its lower surface, which is rotated by a drive motor (not shown) to rotate around its axis (spin). The carrier 66 includes a shaft 69 at the center of its upper surface, which is rotated by a drive motor (not shown) to rotate around its axis (spin). The carrier 66 is positioned off-center of the polishing platen 62.

[0070] To polish the underside of the ceramic sintered body 120 using this polishing apparatus 60, the ceramic sintered body 120 is attached to the underside of the carrier 66, and the ceramic sintered body 120 is sandwiched between the polishing pad 64 of the polishing platen 62 and the carrier 66 so that the underside of the ceramic sintered body 120 comes into contact with the polishing pad 64. Then, a slurry containing abrasive grains is supplied from the pipe 68 to the polishing pad 64. This supplies the slurry between the ceramic sintered body 120 and the polishing pad 64 of the polishing platen 62. In this state, the polishing platen 62 and the carrier 66 are rotated while the carrier 66 presses the ceramic sintered body 120 against the polishing pad 64, thereby performing polishing. A modified layer is formed on the underside of the ceramic sintered body 120 due to polishing.

[0071] The upper surface of the ceramic sintered body 121 can also be lapped in a similar manner. A modified layer is also formed on the upper surface of the ceramic sintered body 121 by the lapping.

[0072] Next, the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are subjected to surface activation treatment (fast atom beam (FAB) or plasma activation treatment) under high vacuum. The FAB conditions are set, for example, as follows: voltage 0.5 to 2 kV, current 50 to 200 mA, and irradiation time 30 to 300 seconds. This removes oxides and adsorbed molecules from the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121, and also forms an amorphous layer on these surfaces, activating them. Next, while maintaining the high vacuum condition, the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are stacked so that their lower surface faces the upper surface, and are directly bonded while applying pressure, preferably at room temperature. The load applied during pressing can be set, for example, to 0.1 to 50 kN. This results in a ceramic bonded body 122 in which the ceramic sintered body 120 and the ceramic sintered body 121 are bonded via an amorphous layer ( FIG. 4B ).

[0073] Next, the plurality of protrusions 72 and the seal band 75 are formed on the upper surface of the ceramic bonded body 122 by laser processing (FIG. 4C). The plurality of protrusions 72 and the seal band 75 may be formed after the ceramic bonded body 122 and the base plate 30 are bonded together.

[0074] In parallel with this, two MMC disk members 131 and 136 are fabricated (FIG. 4D). Then, grooves 132 that will eventually become the coolant flow paths 32 are formed in the lower surface of the upper MMC disk member 131 by machining (FIG. 4E). Through-holes 133 for introducing the coolant and through-holes 134 for discharging the coolant are drilled in the lower MMC disk member 136. When the ceramic sintered body 121 that forms the lower layer of the ceramic bonded body 122 is made of alumina, the MMC disk members 131 and 136 are preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is roughly the same as that of SiSiCTi or AlSiC.

[0075] The SiSiCTi disk member can be fabricated, for example, as follows: First, silicon carbide, metallic Si, and metallic Ti are mixed to produce a powder mixture. Next, the resulting powder mixture is uniaxially pressed to produce a disk-shaped compact, which is then hot-press sintered in an inert atmosphere to obtain the SiSiCTi disk member.

[0076] Next, a metal bonding material 135 is placed between the lower surface of the upper MMC disk member 131 and the upper surface of the lower MMC disk member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disk member 131. The ceramic bonded body 122 is then placed on the metal bonding material 137 placed on the upper surface of the upper MMC disk member 131. This results in a laminate 110 in which the lower MMC disk member 136, the metal bonding material 135, the upper MMC disk member 131, the metal bonding material 137, and the ceramic bonded body 122 are stacked in this order from bottom to top (FIG. 4F). The laminate 110 is then heated and pressurized (TCB) to obtain a bonded body. The bonded body is formed by bonding the ceramic bonded body 122 to the upper surface of the MMC block 130, which will be the base plate 30, via a metal bonding layer. The MMC block 130 is formed by joining an upper MMC disk member 131 and a lower MMC disk member 136 via a metal joining layer. The MMC block 130 has a coolant flow path 32, a coolant inlet 36, and a coolant outlet 38.

[0077] TCB is performed, for example, as follows. That is, the laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, a temperature equal to or higher than the solidus temperature minus 20°C and lower than the solidus temperature), and then returned to room temperature. This causes the metal bonding material to become a metal bonding layer. An Al-Mg based bonding material or an Al-Si-Mg based bonding material can be used as the metal bonding material. For example, when TCB is performed using an Al-Si-Mg based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of about 100 μm.

[0078] Next, the outer periphery of the ceramic bonded body 122 is cut to form a step, thereby forming a ceramic substrate 20 having a central portion 201 and an outer periphery 202. In this way, a semiconductor manufacturing equipment member 10A is obtained (FIG. 4G).

[0079] 1 is shown as an integrated product, it may have a structure in which two members are bonded with a metal bonding layer as shown in FIG. 4G, or a structure in which three or more members are bonded with a metal bonding layer. When forming the bonding layer 40 using the metal bonding material 137, the insulating film 35 can be formed on the base plate 30 by thermal spraying either before or after bonding to the ceramic substrate 20. When forming the bonding layer 40 using a resin adhesive sheet, the resin melts, so the insulating film 35 is formed by thermal spraying before bonding to the ceramic bonded body 122.

[0080] The above describes an exemplary method for manufacturing the semiconductor manufacturing equipment component 10A shown in FIG. 1A. When manufacturing the semiconductor manufacturing equipment component 10B shown in FIGS. 1B-1 and 1B-2, instead of the disk-shaped ceramic sintered body 121 that forms the ceramic substrate 20, a disk-shaped first ceramic sintered body that forms the first ceramic substrate 20a and a disk-shaped second ceramic sintered body that forms the second ceramic substrate 20b are prepared. Then, grooves that form the refrigerant flow path 28 or the gas flow path 29 are formed in the first ceramic sintered body and / or the second ceramic sintered body by machining, and then the two are directly bonded together using the procedure described above to produce a ceramic bonded body. Furthermore, through holes that form the gas supply path 29b can be formed in the ceramic sintered body 120 and the ceramic bonded body by machining. Furthermore, when manufacturing the base plate 30, through holes that will become the gas introduction passages 29a can be formed in the upper MMC disk member 131 and the lower MMC disk member 136 by machining.

[0081] <4. Methods for recycling semiconductor manufacturing equipment components> According to one embodiment of the present invention, a method for recycling semiconductor manufacturing equipment components is provided. Even if the quality of a semiconductor manufacturing equipment component deteriorates due to, for example, shedding of ceramic particles that constitute the protrusions on the wafer-mounting surface, by using this recycling method, the semiconductor manufacturing equipment component can be reused without being discarded. Several examples of the recycling method for semiconductor manufacturing equipment components according to the present invention will be described with reference to the drawings.

[0082] (4-1. Playback method A) A regeneration method A according to one embodiment of the present invention includes a step 1 of processing an upper surface of a first ceramic part of a semiconductor manufacturing equipment member according to one embodiment of the present invention to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed; and step 2 of further processing the processed surface to form a new wafer-mounting surface.

[0083] Referring to FIG. 5A, for example, when reclaiming the semiconductor manufacturing equipment component 10A shown in FIG. 1A using the reclaiming method A, first, the upper surface 71 of the ceramic plate 70 is processed to form a processed surface 90 on the ceramic plate 70 from which the wafer mounting surface has been removed (step 1). The processing method is not particularly limited, but examples include grinding or polishing. Other processing methods include blasting. By performing the blasting after masking the reference surface 71b, the multiple protrusions 72 and seal band 75 constituting the wafer mounting surface can be selectively removed. Furthermore, although the electrodes 26a and even 26b may be removed in step 1, removing them increases the labor required for reclaiming. Therefore, it is preferable not to remove any of the electrodes unless there is a specific reason, such as the purpose of providing electrodes with different specifications.

[0084] Next, the processing surface 90 is subjected to laser processing or blast processing to form a plurality of protrusions 72 and a seal band 75 (wafer mounting surface) (step 2). The positions, shapes, and dimensions of the plurality of protrusions 72 and the seal band 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment member 10A before refurbishment, but may be changed as appropriate.

[0085] Regeneration method A is advantageous in that it is a simple method for regenerating semiconductor manufacturing equipment components. It also has the advantage of being able to completely maintain the material properties before and after regeneration. However, the thickness of the ceramic plate 70 after regeneration is thinner than before regeneration. Therefore, there is a limit to the number of times it can be regenerated.

[0086] (4-2. Playback method B) A regeneration method B according to one embodiment of the present invention includes a step 1 of processing an upper surface of a first ceramic part of a semiconductor manufacturing equipment member according to one embodiment of the present invention to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed; Step 2: directly bonding a ceramic part for recycling, which has a smaller dielectric tangent (tanδ) than the second ceramic part, to the processed surface; Includes.

[0087] Referring to FIG. 5B, for example, when reclaiming the semiconductor manufacturing equipment member 10A shown in FIG. 1A using the reclaiming method B, first, the upper surface 71 of the ceramic plate 70 is processed to form a processed surface 90 on the ceramic plate 70 from which the wafer mounting surface has been removed (step 1). There are no particular limitations on the processing method, but examples include grinding or polishing. Other processing methods include blasting and laser processing. By performing the blasting after masking the reference surface 71b, it is also possible to selectively remove the multiple protrusions 72 and seal band 75 that make up the wafer mounting surface.

[0088] Next, the processed surface 90 of the ceramic plate 70 and the underside of the recycled ceramic plate 79 are directly bonded (preferably by room temperature bonding) (step 2). The direct bonding method is as described above. There is no problem if the recycled ceramic plate 79 has a smaller dielectric tangent (tan δ) than the ceramic substrate 20. However, in order to reproduce the performance of the semiconductor manufacturing equipment member 10A, it is preferable that the recycled ceramic plate 79 be made of the same material as the ceramic plate 70.

[0089] Prior to direct bonding, it is preferable to polish the processed surface 90 of the ceramic plate 70 and the underside of the ceramic plate for recycling 79. There are no particular limitations on the polishing method, but lapping is preferred, for example. It is preferable that the processed surface 90 of the ceramic plate 70 and the underside of the ceramic plate for recycling 79 have a surface roughness (arithmetic mean roughness) Ra of 1 nm or less (e.g., 0.2 to 1 nm) measured with a non-contact surface roughness meter in accordance with ISO 25178.

[0090] Before or after direct bonding, a plurality of protrusions 72 and a seal band 75 (wafer mounting surface) can be formed by laser processing on the upper surface of the recycling ceramic plate 79. The positions, shapes, and dimensions of the plurality of protrusions 72 and the seal band 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment member 10A before recycling, but may be changed as appropriate.

[0091] According to the regeneration method B, since the regenerated ceramic plate 79 can be used with a desired thickness, it is possible to make the total thickness of the ceramic plate 70 and the regenerated ceramic plate 79 in the semiconductor manufacturing equipment member 10A after regeneration match the thickness of the ceramic plate 70 before regeneration. Therefore, there is no particular limit to the number of times that the regeneration can be performed.

[0092] (4-3. Playback method C) A regeneration method C according to one embodiment of the present invention includes a step 1 of processing a first ceramic portion of a semiconductor manufacturing equipment member according to one embodiment of the present invention to remove the first ceramic portion so as to expose a second ceramic portion, and forming a processed surface on the second ceramic portion; A step 2 of directly bonding a ceramic part for recycling, which has a smaller dielectric tangent (tanδ) than the second ceramic part, to the processed surface of the second ceramic part; Includes.

[0093] Referring to FIG. 5C, for example, when the semiconductor manufacturing equipment member 10A shown in FIG. 1A is regenerated by the regeneration method C, the ceramic plate 70 is first processed and removed to expose the ceramic substrate 20. This forms a processed surface 90 on the ceramic substrate 20 (step 1). The electrodes 26a and 26b are also removed by step 1. There are no particular limitations on the processing method, but examples include grinding or polishing. Other processing methods include blasting and laser processing.

[0094] Next, the processed surface 90 of the ceramic substrate 20 and the underside of the recycled ceramic plate 79 are directly bonded (preferably by room temperature bonding) (step 2). The direct bonding method is as described above. The recycled ceramic plate 79 incorporates electrodes 26a and 26b. The electrodes 26a and 26b incorporated in the recycled ceramic plate 79 can have the same specifications as the ceramic plate 70 before recycling, or they may have different specifications. There is no problem if the recycled ceramic plate 79 has a smaller dielectric tangent (tanδ) than the ceramic substrate 20, but in order to reproduce the performance of the semiconductor manufacturing equipment member 10A, it is preferable that the recycled ceramic plate 79 be made of the same material as the ceramic plate 70.

[0095] Prior to direct bonding, it is preferable to polish the processed surface 90 of the ceramic substrate 20 and the underside of the ceramic plate 79 for recycling. There are no particular limitations on the polishing method, but lapping is preferred, for example. It is preferable that the processed surface 90 of the ceramic plate 70 and the underside of the ceramic plate 79 for recycling have a surface roughness (arithmetic mean roughness) Ra of 1 nm or less (e.g., 0.2 to 1 nm) measured with a non-contact surface roughness meter in accordance with ISO 25178.

[0096] Before or after direct bonding, a plurality of protrusions 72 and a seal band 75 (wafer mounting surface) can be formed by laser processing on the upper surface of the recycling ceramic plate 79. The positions, shapes, and dimensions of the plurality of protrusions 72 and the seal band 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment member 10A before recycling, but may be changed as appropriate.

[0097] According to regeneration method C, the ceramic plate 70 is completely removed from the semiconductor manufacturing equipment component 10A before regeneration, so the ceramic plate 79 to be regenerated does not need to be selected taking into consideration the material of the ceramic plate 70 in the semiconductor manufacturing equipment component 10A before regeneration. This allows for a wider range of options for the ceramic plate 79 to be regenerated. Therefore, regeneration method C is advantageous when a semiconductor manufacturing equipment component with different performance than the semiconductor manufacturing equipment component 10A before regeneration is desired. [Explanation of symbols]

[0098] 10A: Semiconductor manufacturing equipment components 10B: Semiconductor manufacturing equipment components 20: Ceramic substrate 20a: First ceramic substrate 20b: second ceramic substrate 21:Top surface 23: Bottom surface 23a: Bottom surface 23b: Bottom surface 26a: Electrostatic adsorption electrode 26b: High frequency electrode 27:Top surface 28: Coolant flow path 29: Gas flow path 29a: Gas inlet 29b: Gas supply line 30: Base plate 31:Top surface 32: Coolant flow path 35: insulating film 36: Refrigerant introduction section 38: Refrigerant discharge part 40: Bonding layer 50: Gas hole 55: Plug 60: Polishing equipment 62: Polishing plate 64: Polishing pad 66: Career 67: Shaft 68: Pipe 69: Shaft 70: Ceramic plate 71:Top surface 71a:Top surface 71b: Reference plane 71c:Top surface 72: Protrusion 73: Bottom surface 74: Gas supply port 75: Seal band 79: Recycled ceramic plate 80: Amorphous layer 80a: First amorphous layer 80b: second amorphous layer 90: Machining surface 110: Laminate 120: Sintered ceramics 121: Sintered ceramics 122: Ceramic joints 130: MMC block 131:MMC disc member 132: Groove 133:Through hole 134:Through hole 135: Metal bonding material 136:MMC disk member 137:Metal bonding material 201: Central part 202: Outer periphery

Claims

1. A semiconductor manufacturing equipment member comprising: a first ceramic part having an upper surface that has a wafer mounting surface and a lower surface located opposite the upper surface; a second ceramic part bonded to the lower surface of the first ceramic part; a first amorphous layer present at a bonding interface between the first ceramic part and the second ceramic part; and a high-frequency electrode disposed inside the first ceramic part or between the first ceramic part and the second ceramic part, wherein the first ceramic part has a smaller dielectric loss tangent (tan δ) than the second ceramic part.

2. The dielectric loss tangent (tanδ) of the first ceramic part at a measurement frequency of 1 MHz is 1 x 10 -3 2. The semiconductor manufacturing equipment member according to claim 1, wherein:

3. 3. The semiconductor manufacturing equipment member according to claim 1, wherein the first ceramic portion is a plate having a plurality of protrusions on the upper surface thereof, the protrusions having the wafer mounting surface.

4. 3. The semiconductor manufacturing equipment member according to claim 1, wherein the second ceramic portion has a higher thermal conductivity than the first ceramic portion.

5. 3. The semiconductor manufacturing equipment member according to claim 1 or 2, a first affected layer present on a side of the first ceramic portion that contacts the first amorphous layer; a second affected layer present on a side of the second ceramic portion that contacts the first amorphous layer; A semiconductor manufacturing equipment component comprising:

6. 3. The semiconductor manufacturing equipment member according to claim 1 or 2, a third ceramic portion joined to a lower surface of the second ceramic portion; a second amorphous layer present at a bonding interface between the second ceramic portion and the third ceramic portion; A semiconductor manufacturing equipment component comprising:

7. a refrigerant flow path through which a refrigerant flows or a gas flow path for supplying a gas to the wafer mounting surface is provided at a position of the second ceramic portion facing the second amorphous layer or at a position of the third ceramic portion facing the second amorphous layer. The semiconductor manufacturing equipment member according to claim 6.

8. 7. The semiconductor manufacturing equipment member according to claim 6, a third affected layer present on a side of the second ceramic portion that contacts the second amorphous layer; a fourth affected layer present on a side of the third ceramic portion that contacts the second amorphous layer; A semiconductor manufacturing equipment component comprising:

9. a step of processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment member according to claim 1 to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed; and further processing the processed surface to form a new wafer-mounting surface.

10. a step of processing the upper surface of the first ceramic part of the semiconductor manufacturing equipment member according to claim 1 to form a processed surface on the first ceramic part from which the wafer mounting surface has been removed; a step of directly bonding a ceramic part for regeneration, which has a smaller dielectric tangent (tanδ) than the second ceramic part, to the processed surface; A method for recycling semiconductor manufacturing equipment components, comprising:

11. a step of processing the first ceramic portion of the semiconductor manufacturing equipment member according to claim 1 to remove the first ceramic portion so as to expose the second ceramic portion, and forming a processed surface on the second ceramic portion; a step of directly bonding a ceramic part for recycling, which has a smaller dielectric tangent (tanδ) than the second ceramic part, to the processed surface of the second ceramic part; A method for recycling semiconductor manufacturing equipment components, comprising:

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