Test measurement device and signal processing method

Abstract

To remove jitters from waveforms.SOLUTION: A test measurement device 130 includes: one or more ports 132 connected to a device under test (DUT) 150 having one or more clock signals and one or more power supply rails; one or more analog-digital converters (ADC) 136 for receiving a signal from a DUT 150 and converting it to waveform data; a user interface 144 for enabling a user to input one or more frequency pairs; and one or more processors 140. The test measurement device determines a time interval error between a received edge time and an expected time, constitutes a filter on the basis of the start and halt frequencies of each of one or more of frequency pairs, filters the reception edge and generates a clock waveform, reconstructs waveform data using the clock waveform, and generates a reconstructed waveform.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] The present disclosure relates to a test and measurement instrument that can utilize time interval errors to identify, isolate, and remove sources of jitter affecting reference clocks and data. [Background technology]

[0002] In high-speed electronic systems, operating frequencies can reach values ​​up to tens of GHz, with multiple power rails powering a variety of high-speed loads. As supply voltages get smaller and switching speeds get faster, maintaining power and signal integrity in extreme sub-micrometer technologies presents a challenging challenge for system designers.

[0003] Signal quality (SI) analysis focuses on the performance of the transmitter, reference clock, channel, and receiver in terms of bit error rate (BER).Power integrity (PI) focuses on the ability of the power distribution network (PDN) to provide constant, clean power rails and low impedance return paths. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2023 / 0251699 [Patent Document 2] Patent Publication No. 2021-511513 [Non-patent literature]

[0005] [Non-Patent Document 1] "Digital Power Management Analysis" introduction site, Tektronix, [online], [Retrieved July 26, 2025], Internet <https: / / www.tek.com / en / datasheet / digital-power-management-and-analysis-software-enabling-power-integrity-analysis> [Non-patent document 2] "Digital Power Management / Analysis Software - Power Integrity Analysis Compatible" introduction site, Tektronix, [online], [Retrieved July 26, 2025], Internet <https: / / www.tek.com / ja / datasheet / digital-power-management-and-analysis-software-enabling-power-integrity-analysis> Summary of the Invention [Problem to be solved by the invention]

[0006] Users can benefit from knowing the interdependence of PI and SI and whether PI is affecting signal quality. The PDN (power distribution network) can introduce noise and jitter. Circuit structures and components such as voltage regulator modules, on-chip packages, pins, traces, vias, and connectors affect the impedance of the PDN and therefore the quality of the power delivered.

[0007] While SI and PI groups within a company often work as separate teams, finding high-speed serial jitter related issues requires understanding both the power quality and signal quality domains, as power rails and serial data reside on the same board structure.

[0008] System-on-chip (SoC) designs have many circuits on a single chip that affect the high-speed serial (HSS) section of the SoC. Understanding the effect each circuit has on the HSS signal allows you to identify and remove the effect of one or more circuit elements, observe their impact on the HSS signal, and pinpoint the source of jitter.

[0009] Power rail outputs affect reference clocks, manifesting as power jitter (PJ) and other jitter components on clock or data signals. In chip designs, clock aggressors sweeping a frequency range can impact reference clocks with high jitter components. Power supply fluctuations due to multiple rails outputting to PDN loads can cause signal quality degradation and lead to bit errors, which can affect the functionality of high-speed signals. In some cases, eight or more aggressors can act on a clock lane. By precisely identifying the jitter on the victim clock lane, designers can adjust the jitter accordingly. [Means for solving the problem]

[0010] Embodiments of the present application provide test and measurement equipment and methods for identifying, isolating, and removing power supply jitter affecting a reference clock. The effect on the reference clock affects the accuracy of a data signal. Embodiments of the present application use the time interval error (TIE) between the received and expected edges of the clock to identify and list sources of jitter. These embodiments generate a TIE spectrum plot, allowing users to view the aggressor components and frequency components generated by the aggressors. These embodiments allow users to identify multiple frequency ranges of multiple aggressor signals, such as multiple power rails. Multiple filter method embodiments can be applied to a signal to remove jitter from multiple sources. For example, multiple filters can be used to remove different PJ components at different frequencies on the TIE waveform data. [Brief explanation of the drawings]

[0011] [Figure 1] Figure 1 shows an example of measuring TIE and jitter peak-to-peak. [Figure 2] Figure 2 shows a diagram of the sources of noise components in a device under test. [Figure 3] Figure 3 shows the effect of power-supply noise on the output of a differential driver. [Figure 4] Figure 4 shows the clock distribution network in a system-on-chip (SoC) system with n clocks. [Figure 5] FIG. 5 shows an embodiment of an interface that allows new measurements and their configuration. [Figure 6] Figure 6 shows the corrected clock edges extracted from the high-speed data obtained from the embodiment. [Figure 7] FIG. 7 illustrates an embodiment of a flowchart of a method for generating adjusted clock edges that account for power supply induced jitter. [Figure 8]FIG. 8 shows a reference clock and a time interval error (TIE) corrected clock used to reconstruct clock edges in an embodiment. [Figure 9] Figure 9 shows a zoomed-in view of the TIE trend before and after filtering. [Figure 10] FIG. 10 shows an example of a TIE spectrum showing a 100 kHz sinusoidal component. [Figure 11] FIG. 11 shows the TIE in which the 100 kHz component is removed by applying the embodiment. [Figure 12] FIG. 12 shows the improvement in eye width by applying the embodiment. [Figure 13] Figure 13 shows the TIE spectrum filtered at two frequency pairs. [Figure 14] Figure 14 shows the resulting signal with clock jitter removed and the resulting improvement in the TIE histogram. [Figure 15] FIG. 15 shows an embodiment of a test and measurement device. DETAILED DESCRIPTION OF THE INVENTION

[0012] Figure 1 shows a diagram of time interval error. The main causes of time interval error are output signal delays, changes in the slope of the transition edge, and shifts in the bias point of the transistor. In Figure 1, a signal is transitioning from "low" to "high." The dark solid line 10 indicates the expected edge. The dashed line on the low side, indicated by 12, is the early edge, and the dashed line, indicated by 16, is the late edge. The difference between the earliest and latest edges, indicated by arrow 14, is the peak-to-peak jitter. Transient Error (TIE) is indicated by arrow 18. TIE affects timing margins and can cause violations of system setup and hold times.

[0013] Figure 2 shows the various types of noise components that can originate from the power supply and affect serial data. Power distribution network (PDN) noise on power rails can couple to adjacent signal traces through crosstalk. Crosstalk occurs when noise-induced voltage fluctuations affect adjacent traces, causing signal integrity issues. These distortions can affect data reliability and synchronization.

[0014] As shown in FIG. 2, voltage regulator modules (VRMs), such as first regulator 22 and second regulator 24, can be subject to self-aggression noise. In this context, a component that contains or generates noise constitutes an aggressor, and a component that is affected by the noise constitutes a victim. With "self-aggression" noise, these components can be subject to noise generated within themselves. Aggressors can generate noise that does not affect the aggressor itself, but affects components surrounding the aggressor. Aggressor 26 can include, for example, a power rail, and component 28 can include a clock, which can be subject to noise from a power rail coupled to the clock.

[0015] Figure 3 shows another example of how power supply jitter can occur. The system 36 draws current i(t) from the same power supply as the differential driver. The PDN generates noise components, which can cause the V DD The voltage at the PDN lanes fluctuates, which affects the output. Rnoise (t) and v noise (t) affects the output load of the system.

[0016] Figure 4 illustrates how a reference clock can suffer from these effects. It shows the victim system reference clock 46 in a clock bank 40 with a swept frequency range, the first through nth high-speed serial (HSS) devices 51, and the first through nth clocks 50. The curved arrows indicate the coupling effect from these lines onto the reference clock line. The reference clock and clock bank signals enter a clock recovery module, such as a phase-locked loop (PLL). The resulting output reference clock 48 suffers further from the effects of the first through nth HSS clocks 52. In one example, the reference clock is 125 MHz and the clock aggressor is 10 MHz. The 10 MHz signal impacts the reference clocks 48 and beyond after clock recovery.

[0017] Embodiments of the present application allow a user to perform tests on a device under test (DUT), such as a system on a chip (SoC), to identify aggressors. The test and measurement instrument includes one or more processors that can remove noise components from aggressors, adjust a reference clock, and reconstruct a data stream. These embodiments also provide a user with a visualization that shows the noise components and their removal.

[0018] FIG. 5 shows an embodiment of a test and measurement instrument user interface that allows a user to specify aggressors (here in the form of power rails) and remove noise components from the aggressors. On the left side of FIG. 5, panel 56 allows a user to select DPM and specify the number of power rails (see Non-Patent Document 1). This panel also describes power supply jitter (PJ), also known as power supply-induced jitter (PSIJ). A second panel 58 allows a user to set the start and stop frequencies for each power rail. In this description, the start and stop frequencies for each power rail are referred to as a "frequency pair." The method described below repeats for the number of frequency pairs. After the method is set up and running, the resulting clock is adjusted.

[0019] FIG. 6 shows a jittery data signal at 60. A jittery clock 62 is recovered from the data signal. By filtering the jittery clock edges, this process produces corrected clock edges. The adjusted clock 64 allows the test and measurement instrument to reconstruct the data signal. The difference between the vertical markers of the jittery clock 62 and the adjusted clock can be seen, for example, in regions 66.

[0020] FIG. 7 illustrates an embodiment of a method for adjusting a clock and reconstructing a waveform. The process begins by receiving a reference clock with aggressor components that affect the reference clock. The clock edges are recovered at 72, and clock and data recovery (CDR) is performed at 74. Clock and data recovery recovers clock edges from the waveform itself when no clock accompanies the data signal. This recovered clock is used to calculate the time-to-interval (TIE) between the received edge and the recovered clock edge at 76, where the TIE is the original TIE before filtering. In one embodiment, the process interpolates between the filtered edges to obtain the corrected clock edges.

[0021] The method applies a notch filter at 80 to adjust and compensate the clock edges using the start and stop frequency pairs for at least one aggressor at 78. This process repeats the process of designing a filter, applying the filter, generating compensated clock edges, and reconstructing the edges until all frequency pairs are utilized. The iterative filtering process may include adjusting the clock edges from the previous step with each new filter. Once this process has been performed for all frequency pairs at 82, the process also adjusts the TIE for each edge, as described below. This provides a user with a visual display of the change in TIE caused by the removal of power supply jitter.

[0022] This process adjusts the clock edge at 86, but newCLK[i] = old_edges[i] - filtered TIE[i] where i runs from 1 to the number of edges. Using the corrected clock edges, the process reconstructs the data. In one embodiment, reconstructing the data means that each cycle in the data must be zoomed in or out based on the adjusted clock edges. To maintain the same sample rate, the data during that cycle must be resampled.

[0023] Figures 8-14 show the results of this process. Figure 8 shows waveform 92, original reference clock 94, and reconstructed clock 96. These results demonstrate significant results. Figure 9 shows a zoomed-in view of the TIE time trend 98 and filtered TIE trend 100. Figure 10 shows the TIE spectrum of the signal, showing a 100 kHz sinusoidal component 102. Figure 10 shows the input TIE spectrum 106 and the reconstructed TIE spectrum 108 after removing the sinusoidal component.

[0024] Before removing the 100 kHz component, the power supply jitter was 649.9 ps. After removal, the power supply jitter was measured to be 47.05 ps. Figure 12 shows that the eye width increased from 3.290 ns at 110 to 3.549 ns at 112.

[0025] In addition to removing one jitter component, FIG. 13 shows that two frequency pairs (one between 9.5 MHz and 10.5 MHz, and the other between 19.5 MHz and 20.5 MHz) are removed.

[0026] 14 shows the signal spectrum 118 and histogram 120 before power supply jitter removal, and the spectrum 122 and histogram 124 after power supply jitter removal. It can be seen that the TIE histogram transitions from being deterministic based on the jitter input to a Gaussian distribution.

[0027] Allowing the user to view the TIE spectrum before and after applying the filter, side-by-side or together on the user interface, acts as a powerful validation feature during the process. The test and measurement equipment can display these improved results compared to the previous waveform for all jitter components such as total jitter, power supply jitter (PJ), deterministic jitter (DJ), and random jitter (RJ).

[0028] FIG. 15 is a block diagram of a test and measurement instrument 130, such as an oscilloscope, for implementing embodiments of the present disclosure. The test and measurement instrument 130 may also be an example of the measurement instrument described above. The test and measurement instrument 130 has one or more test ports 132 for receiving any electrical signal. The ports 132 may include receivers, transmitters, and transceivers. The test ports 132 receive signals from an attached device, such as a DUT 150, a circuit, a discrete device or set of devices, or other object under test, for example, through a probe or test fixture. In some embodiments, the DUT 150 is an HSS data generating device, and power rails are present and HSS data is coupled to the test ports 132. Each test port 132 may represent a channel of the test and measurement instrument 130. As described above, one or more power rails from the DUT 150 may be coupled to the test and measurement instrument 130 through one or more channels, and one or more HSS data outputs may be coupled to the test and measurement instrument 130 through other channels. Test port 132 is connected to one or more processors 140 for processing signals or waveforms received at port 132. For simplicity of explanation, only one processor 140 is shown in Figure 15, but those skilled in the art will appreciate that multiple processors of various types may be used in combination rather than a single processor 140.

[0029] The test port 132 and one or more processors 140 may also be connected to a sampler track / hold unit 134, which samples and holds the input signal so that an analog-to-digital converter (ADC) 136 can convert the signal into digital samples that are stored in an acquisition memory 138.

[0030] The processor 140 may also be connected to a measurement unit 146 within the test and measurement instrument 130. The measurement unit 146 may include individual functions for performing the measurements and correlation operations described above. For example, the measurement unit 146 may include any component or computational function capable of measuring characteristics of a signal received through the test port 132 in either or both the time and frequency domains. For example, the measurement unit may include functions or processes for measuring ripple, for creating a TIE spectrum from received HSS data, and for creating a spectrum from PJ data as described above. Once these measurement functions are completed, the one or more processors 140 may coordinate and evaluate these measurement functions with measurements generated from the DUT 150.

[0031] The visualization unit 148 assembles various displays generated from the measurements and analysis performed by the measurement unit 146 and sends them to the display 144 for display on the test and measurement instrument 130. In some cases, the display may be remote from the test and measurement instrument 130 itself. Visualizations may include displays such as eye diagrams, one or more spectra (including spectra based on two or more aligned measurements over the same frequency range), histograms, and data reports (which may present measurement data in numerical form). Each of these visualization types has been described and illustrated in detail above.

[0032] Additionally, filtering function 145 may also operate as described above, where the filtering function applies a filter to a particular waveform at a particular frequency, and as described above, this filtering has the effect of simulating the results of reducing the effect that certain factors may have on each other, such as noise on a power rail affecting the HSS data.

[0033] One or more processors 140 may be configured to execute instructions from memory 138, which represents all memory structures within the test and measurement instrument, including working memory and acquisition memory. One or more processors 140 may perform any method or associated steps indicated by such instructions, such as displaying measured values ​​of coupled devices in accordance with embodiments of the disclosed technology. One or more processors 140 may perform the functions described above with reference to measurement unit 146, visualization unit 148, or filter 145, or one or more processors 140 may perform such functions in conjunction with yet another processor. Memory 138 may be implemented as processor cache, random access memory (RAM), read-only memory (ROM), solid-state memory, a hard disk drive, or any other form of memory. Memory 138 serves as a medium for storing data, computer program products, and other instructions.

[0034] The user input 142 is coupled to the one or more processors 140. The user input 142 may include a keyboard, mouse, trackball, touchscreen, or any other control device available to a user in conjunction with a user interface (UI) on the display 144. The user interface on the display 144 may present a menu to the user, such as that shown in FIG. 5. The display 144 may be a digital screen or any other monitor for displaying waveforms, measurements, and other data to the user. The display 144 may also include a user input mechanism, such as a touchscreen. While the components of the test and measurement instrument 130 are depicted as being integrated within the test and measurement instrument 130, those skilled in the art will appreciate that any of these components may be external to the test and measurement instrument 130 and may be coupled to the test and measurement instrument 130 in any conventional manner (e.g., via wired or wireless communication media or mechanisms). For example, in some embodiments, the display 144 may be remote from the test and measurement instrument 130.

[0035] Aspects of the disclosed technology may operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The terms "controller" or "processor" herein contemplate microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology may be implemented with computer-usable data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data types. Computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, etc. Those skilled in the art will appreciate that the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed technology, and such data structures are considered within the scope of the computer-executable instructions and computer-usable data described herein.

[0036] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As used herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0037] "Computer storage media" means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) and other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage and other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable medium implemented in any technology. "Computer storage media" excludes signals themselves and transitory forms of signal transmission.

[0038] A communication medium means any medium usable for communicating computer-readable information. By way of example, and not limitation, communication media may include coaxial cable, fiber optic cable, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals. Example

[0039] The following examples are provided to aid in understanding the technology disclosed in this application. Embodiments of the technology may include one or more of the examples described below, and any combination thereof.

[0040] Example 1 is a test and measurement apparatus comprising one or more ports for connecting to a device under test (DUT) having one or more clock signals and one or more power rails, one or more analog-to-digital converters (ADCs) that receive signals from the DUT and convert them into waveform data consisting of digital samples at a specific sampling rate, a user interface that allows a user to input one or more frequency pairs, and one or more processors, wherein the one or more processors are configured to execute a program that causes the one or more processors to perform the following processes: determining a time interval error between the time of a received edge in the signal and an expected time of the received edge; designing a filter based on the start frequency and stop frequency of each of the one or more frequency pairs; filtering the received edges to generate filtered edges; generating corrected clock edges from the filtered edges to generate a clock waveform; and reconstructing waveform data using the clock waveform of the corrected clock edges to generate a reconstructed waveform.

[0041] Example 2 is the test and measurement instrument of Example 1, wherein the start frequency and the stop frequency comprise lower and upper limits of operating frequencies for each of the one or more power rails.

[0042] Example 3 is the test and measurement instrument of either Example 1 or Example 2, wherein the program that causes the one or more processors to perform the process of filtering the received edges includes a program for applying a filter to the received edges in turn for each of the one or more frequency pairs.

[0043] Example 4 is the test and measurement instrument of any of Examples 1 to 3, wherein the program that causes the one or more processors to filter the received edges includes a program for applying a plurality of filters to remove different power supply jitter components at different frequencies.

[0044] Example 5 is a test and measurement instrument of any of Examples 1 to 4, wherein the program that causes the one or more processors to apply a filter includes program for applying a notch filter to the received edge.

[0045] Example 6 is a test and measurement instrument according to any one of Examples 1 to 5, wherein the program causing the one or more processors to perform a process of reconstructing the corrected clock edges includes a process of interpolating between the filtered edges to obtain the corrected clock edges.

[0046] Example 7 is the test and measurement instrument of any of Examples 1 to 6, wherein the program that causes the one or more processors to perform a process of reconstructing the waveform data includes a process of zooming in or zooming out the data for each cycle of the clock in accordance with the corrected clock edge, and a process of resampling the data to maintain the original sampling rate.

[0047] Example 8 is the test and measurement instrument of any of Examples 1 to 7, wherein the processor is further configured to generate spectral plots of the time interval error before and after removing one or more power supply noise components for one or more frequencies, and display the spectral plots together on the user interface.

[0048] Example 9 is the test and measurement instrument of any of Examples 1 to 8, wherein the processor is further configured to cause one or more processors to repeat a program that causes the one or more processors to repeat a filter configuring process, a filter applying process, a generating process, and a constructing process for each of the one or more frequency pairs.

[0049] Example 10 is a method including the steps of: presenting a user interface to a user to allow the user to set a start frequency and a stop frequency as a frequency pair for one or more aggressor signals; receiving a data signal with a test and measurement instrument; determining a time interval error between the time of a received clock edge of the data signal and the expected time of the received clock edge; defining a filter using the start frequency and the stop frequency for each of the one or more frequency pairs; filtering the received edge using the filter to generate a filtered edge; reconstructing a corrected clock edge from the filtered edge to generate a clock waveform; and reconstructing waveform data using the clock waveform of the corrected clock edge to generate a reconstructed waveform.

[0050] Example 11 is the method of example 10, wherein defining the filter using the start frequency and the stop frequency includes defining a notch filter using the start frequency and the stop frequency.

[0051] Example 12 is the method of any of Examples 10 or 11, wherein the process of reconstructing the corrected clock edges includes a process of interpolating between the filtered edges to obtain the corrected clock edges.

[0052] Example 13 is a method of any of Examples 10 to 12, wherein the process of reconstructing the waveform data includes a process of zooming in or out on the data for each cycle of the clock, and a process of resampling the data to maintain the original sampling rate.

[0053] Example 14 is the method of any of Examples 10 to 13, further comprising generating spectral plots of the time interval error before and after removing one or more power supply noise components for one or more frequencies, and displaying the spectral plots together on the user interface.

[0054] Example 15 is the test and measurement instrument of any of Examples 10 to 14, wherein filtering the received edges includes applying multiple filters to remove different power supply jitter components at different frequencies.

[0055] Example 16 is the method of any of Examples 10 to 15, further comprising repeating the filter definition process, the filtering process, the generating process, and the constructing process for each of one or more frequency pairs.

[0056] Additionally, the description of this application refers to specific features. It should be understood that the disclosure herein includes all possible combinations of these specific features. When a specific feature is disclosed in connection with a particular aspect or example, that feature can also be used in connection with other aspects and examples, to the extent possible.

[0057] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, unless the circumstances do not preclude this possibility.

[0058] All features disclosed in the specification, claims, abstract and drawings, and all steps in any disclosed method or process, may be combined in any combination, except where at least some of such features or steps are mutually exclusive combinations. Each feature disclosed in the specification, abstract, claims and drawings may be replaced by an alternative feature serving the same, equivalent or similar purpose, unless expressly stated otherwise.

[0059] Although specific embodiments of the invention have been illustrated and described for purposes of illustration, it will be appreciated that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims. [Explanation of symbols]

[0060] 130 Test and measurement equipment 132 Test Port 134 Sampler Track / Hold Unit 136 Analog-to-Digital Converter (ADC) 138 Acquisition Memory 140 processors 142 User Input Section 144 Display / User Interface (UI) 145 Filters / Filtering Functions 146 measurement units 148 Visualization Unit 150 Devices Under Test (DUT)

Claims

1. 1. A test and measurement device comprising: one or more ports for connecting to a device under test (DUT) having one or more clock signals and one or more power rails; one or more analog-to-digital converters (ADCs) that receive and convert signals from the DUT into waveform data comprised of digital samples at a particular sampling rate; a user interface that allows a user to input one or more frequency pairs; one or more processors wherein the one or more processors: determining a time interval error between the time of a received edge in said signal and the expected time of said received edge; configuring a filter based on the start and stop frequencies of each of the one or more frequency pairs; filtering the received edges to generate filtered edges; generating corrected clock edges from the filtered edges to generate a clock waveform; reconstructing waveform data using the clock waveform of the corrected clock edges to generate a reconstructed waveform; a test and measurement instrument configured to execute a program that causes the one or more processors to:

2. 2. The test and measurement instrument of claim 1, wherein the start frequency and the stop frequency comprise lower and upper limits of operating frequencies for each of the one or more power rails.

3. 2. The test and measurement instrument of claim 1, wherein the program causing the one or more processors to filter the received edges includes program for applying multiple filters to remove different power supply jitter components at different frequencies.

4. 2. The test and measurement instrument of claim 1, wherein the program causing the one or more processors to perform a process for reconstructing the corrected clock edges includes a process for interpolating between the filtered edges to obtain the corrected clock edges.

5. The program causing the one or more processors to perform a process of reconstructing the waveform data comprises: zooming in or out on the data for each cycle of the clock in response to the corrected clock edge; The process of resampling the data to maintain the original sampling rate.

10. The test and measurement instrument of claim 1, comprising:

6. 10. The test and measurement instrument of claim 1, wherein the processors are further configured to cause one or more processors to repeat a program that causes the one or more processors to repeat a filter configuring process, a filter applying process, a generating process, and a constructing process for each of the one or more frequency pairs.

7. presenting a user interface to a user to allow the user to set start and stop frequencies as frequency pairs for one or more aggressor signals; receiving a data signal at a test and measurement instrument; determining a time interval error between the time of a received clock edge of the data signal and the expected time of the received clock edge; defining a filter using a start frequency and a stop frequency for each of one or more frequency pairs; filtering the received edges using the filter to generate filtered edges; reconstructing the corrected clock edges from the filtered edges to generate a clock waveform; reconstructing waveform data using the clock waveform of the corrected clock edges to generate a reconstructed waveform; A signal processing method comprising:

8. 8. A method of signal processing as claimed in claim 7, wherein defining the filter using the start frequency and the stop frequency comprises defining a notch filter using the start frequency and the stop frequency.

9. 8. A method of signal processing as claimed in claim 7, wherein reconstructing the corrected clock edges comprises interpolating between the filtered edges to obtain the corrected clock edges.

10. The process of reconstructing the waveform data is as follows: Zooming in or out on the data for each cycle of the clock; The process of resampling the data to maintain the original sampling rate.

8. The signal processing method of claim 7, comprising:

Images