Semiconductor device

Abstract

To solve a problem of increase in the number of pixels associated with high definition of a display device to cause increase in the number of gate lines and the number of signal lines; when the number of gate lines and the number of signal lines increase, it becomes difficult to mount, by bonding and the like, an IC chip which has a drive circuit for driving the number of gate lines and the number of signal lines thereby to increase manufacturing cost.SOLUTION: A semiconductor device comprises a pixel part and a drive circuit for driving the pixel part on the same substrate, in which at least a part of the drive circuit is constituted by a thin film transistor using an oxide semiconductor sandwiched by gate electrodes vertically. The semiconductor device comprises a channel protection layer provided between the oxide semiconductor and the gate electrode provided above the oxide semiconductor. By providing the pixel part and the drive circuit on the same substrate, manufacturing cost is reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are , amorphous silicon, and polycrystalline silicon. Thin film transistors using silicon have low field effect mobility, but are suitable for enlarging the area of ​​glass substrates. On the other hand, thin film transistors using polycrystalline silicon have a field effect mobility of Although it is expensive, it requires a crystallization process such as laser annealing, which is necessary for enlarging the area of ​​glass substrates. It has the characteristic that it does not necessarily adapt.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-G Thin film transistors were fabricated using a-Zn-O oxide semiconductors and used as switches for image display devices. Patent Documents 1 and 2 disclose techniques used in chip elements and the like. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-096055 Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors with a channel formation region in an oxide semiconductor are made of amorphous silicon. The oxide semiconductor film has a higher field effect mobility than the thin film transistors used in the previous study. Film formation is possible at temperatures below 300°C using methods such as sputtering, and polycrystalline silicon The manufacturing process is simpler than that of thin film transistors using SiO2.

[0006] Using such oxide semiconductors, thin film transistors can be formed on glass substrates, plastic substrates, etc. and displays such as liquid crystal displays, electroluminescent displays, or electronic paper. It is expected to be applied to display devices.

[0007] Furthermore, when the display area of ​​the display device is enlarged, the number of pixels increases, and the number of gate lines and signal lines also increases. In addition, as display devices become more highly precise, the number of pixels increases, and the number of gate lines and signal As the number of gate lines and signal lines increases, the number of drivers required to drive them also increases. It has become difficult to mount IC chips with operating circuits by bonding, etc., and manufacturing costs have risen. The number of cases increases.

[0008] Therefore, a thin film transistor using an oxide semiconductor is used for at least a part of the driving circuit that drives the pixel portion. One object is to reduce manufacturing costs by using transistors.

[0009] At least a part of the driving circuit that drives the pixel section is made of a thin film transistor that uses an oxide semiconductor. When using a thin film transistor, the thin film transistor must have high dynamic characteristics (on-state characteristics) and frequency characteristics (f The thin film transistor with high dynamic characteristics (ON characteristics) is required. It is another object of the present invention to provide a driver circuit that can be driven at high speed.

[0010] Furthermore, one embodiment of the present invention is a thin film transistor having high reliability, in which an oxide semiconductor layer is used for a channel. It is an object of the present invention to provide a semiconductor device including a starter. [Means for solving the problem]

[0011] Gate electrodes are provided above and below the oxide semiconductor layer, improving the on-state characteristics and reliability of the thin film transistor. Achieve the above.

[0012] In addition, the threshold voltage can be controlled by controlling the gate voltage applied to the upper and lower gate electrodes. The upper and lower gate electrodes may be electrically connected to each other to have the same potential. The gate electrodes may be connected to separate wirings to have different potentials. By applying a voltage to one side to control the threshold voltage, the threshold voltage can be set to zero or By bringing the driving voltage closer to the threshold voltage, power consumption can be reduced. By applying a positive voltage, it can function as an enhancement type transistor. It is also possible to make the transistor function as a depletion type transistor by making the threshold voltage negative.

[0013] For example, a combination of enhancement and depletion type transistors An inverter circuit (hereinafter referred to as an EDMOS circuit) can be configured using this and used in a drive circuit. The drive circuit has at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above EDMOS circuit. It is preferable to use a thin film transistor that can pass a large amount of ON current for the layer. A recessed type transistor or a thin film transistor having gate electrodes above and below an oxide semiconductor layer A transistor is used.

[0014] Fabricating thin-film transistors with different structures on the same substrate without significantly increasing the number of processes For example, a drive circuit for high-speed operation can be provided with gate electrodes above and below the oxide semiconductor layer. The EDMOS circuit is constructed using thin film transistors with electrodes, and the pixel section is made of oxide semiconductor. A thin film transistor having a gate electrode only below the body layer may also be used.

[0015] If the threshold voltage of the n-channel TFT is positive, it is called an enhancement type transistor. When the threshold voltage of the n-channel TFT is negative, it is called a depletion-type transistor. This definition will be followed throughout the specification.

[0016] In addition, the material of the gate electrode provided above the oxide semiconductor layer is not particularly limited as long as it is a conductive film. Not specified, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), W, Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scandium The element selected from the group consisting of Sc, Cr, and Cr, or an alloy containing the above-mentioned elements as components, is used. The gate electrode is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. Cut.

[0017] In addition, the gate electrode provided above the oxide semiconductor layer is made of the same material as the pixel electrode (transparent For example, in the case of a transmission type display device, a transparent conductive film can be used. In the same process as the process of forming the pixel electrode electrically connected to the thin film transistor, The gate electrode can be formed above the semiconductor layer. Without increasing the number of gate electrodes, a thin-film transistor with gate electrodes above and below the oxide semiconductor layer can be formed. In addition, by providing a gate electrode above the oxide semiconductor layer, Bias-thermal stress test (hereinafter referred to as BT test) for investigating the reliability of thin film transistors The change in the threshold voltage of the thin film transistor before and after BT stress was measured. That is, by providing a gate electrode above the oxide semiconductor layer, , the reliability can be improved.

[0018] One of the configurations of the invention disclosed in this specification is a first gate electrode on an insulating surface. a first insulating layer above the gate electrode; an oxide semiconductor layer above the first insulating layer; a channel protection layer in contact with the oxide semiconductor layer, a source electrode or a drain electrode above the oxide semiconductor layer, and a second insulating layer covering the source electrode or the drain electrode; and a second gate electrode above the second insulating layer. and a second insulating layer in contact with the channel protection layer. do.

[0019] The above configuration solves at least one of the above problems.

[0020] In the above structure, the width of the second gate electrode is made wider than the width of the oxide semiconductor layer. A gate voltage can be applied to the entire oxide semiconductor layer from the second gate electrode.

[0021] Alternatively, in the above configuration, the width of the first gate electrode is narrower than the width of the second gate electrode. By doing so, the area overlapping with the source electrode or drain electrode is reduced, thereby reducing the parasitic capacitance. Furthermore, the width of the first gate electrode is wider than the width of the channel protection layer. The width of the gate electrode of 2 is made narrower than the width of the channel protection layer, so that the source electrode or the drain electrode It may be configured so that it does not overlap with the rain electrode to further reduce the parasitic capacitance.

[0022] In the above structure, a barrier layer may be provided between the source electrode or the drain electrode and the oxide semiconductor layer. By providing a buffer layer, the source electrode (or drain electrode) The contact resistance between the oxide semiconductor layer and the insulating film can be reduced.

[0023] In addition, another aspect of the present invention has a pixel section and a driving circuit, and the pixel section has at least a first oxide a first thin film transistor having an oxide semiconductor layer, and a driving circuit having at least a second oxide semiconductor layer; a second thin film transistor having a compound semiconductor layer and a third thin film transistor having a third oxide semiconductor layer; a third thin film transistor; and an EDMOS circuit having a third oxide a first gate electrode below the oxide semiconductor layer and a source electrode above the third oxide semiconductor layer; The third oxide semiconductor layer has a drain electrode and a second gate electrode above the third oxide semiconductor layer. The oxide semiconductor layer has a channel protection layer between the second gate electrode and the channel protection layer. It is a semiconductor device that is in contact with the substrate.

[0024] In the above structure, the first thin film transistor in the pixel portion is electrically connected to the pixel electrode, By using the same material for the electrode as for the second gate electrode of the drive circuit, the number of processes can be reduced. It can be made.

[0025] In the above structure, the first thin film transistor in the pixel portion is electrically connected to the pixel electrode, The electrode is made of a material different from that of the second gate electrode of the driving circuit. For example, the pixel electrode is made of a transparent conductive film. By using an aluminum film as the second gate electrode, Resistance can be reduced.

[0026] In the above structure, the source electrode or the drain electrode and the third oxide semiconductor layer By providing a buffer layer, the source electrode (or drain electrode) The contact resistance between the electrode and the oxide semiconductor layer can be reduced.

[0027] The third thin film transistor of the driving circuit has a third oxide semiconductor layer interposed between the first insulating layer and the third thin film transistor. and overlapping the first gate electrode via the second insulating layer, and overlapping the second gate electrode via the second insulating layer. This is a so-called dual gate structure.

[0028] In addition, the first gate electrode and the second gate electrode are electrically connected and set to the same potential. Gate voltages are applied from above and below to the oxide semiconductor layer disposed between the first gate electrode and the second gate electrode. Pressure can be applied.

[0029] In addition, when the first gate electrode and the second gate electrode are set to different potentials, the electric potential of the TFT is Properties such as threshold voltage can be controlled.

[0030] In addition to liquid crystal display devices, semiconductor devices having driver circuits include light emitting devices using light emitting elements. Examples of such display devices include optical display devices and display devices that use electrophoretic display elements and are also called electronic paper. do.

[0031] In this specification, the term "display device" refers to an image display device, a light-emitting device, or a light It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0032] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel In the element part, the gate electrode of a thin film transistor and the source wiring of another transistor, The gate electrode has a portion for electrically connecting the gate electrode or drain wiring.

[0033] In addition, thin film transistors are easily damaged by static electricity, so the gate line or source It is preferable to provide a protection circuit for protecting the driver circuit on the same substrate as the line. is preferably configured using a nonlinear element using an oxide semiconductor.

[0034] The oxide semiconductor used in this specification is InMO3(ZnO) m Thin (m>0) A thin film is formed, and a thin film transistor is fabricated using the thin film as the semiconductor layer. , Ga, Fe, Ni, Mn, and Co. For example, M can be Ga (gallium), or Ga and Ni or Ga and Fe. In addition to Ga, the above-mentioned metal elements may be contained. In addition to the metal elements contained as M, Fe, Ni and other transition metal elements are included as impurity elements. or an oxide of the transition metal. Among them, those containing Ga as M are also called In-Ga-Zn-O based non-single crystal films.

[0035] The crystalline structure of the In-Ga-Zn-O non-single crystal film is formed by sputtering and then heated at 200°C Even if the treatment is carried out at 500°C, typically 300 to 400°C for 10 to 100 minutes, an amorphous structure is not obtained. is observed in the XRD analysis.

[0036] Oxide semiconductors, such as In-Ga-Zn-O non-single crystal films, have an energy gap ( Since the oxide semiconductor layer has a wide Eg, even if two gate electrodes are provided above and below the oxide semiconductor layer, The increase in current can be suppressed.

[0037] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, in this specification, specific names are not used as matters for identifying the invention. This does not indicate

[0038] In addition, terms used in this specification that express degrees, such as "roughly," "almost," and "degree" etc. is a reasonable deviation from the terminology, slightly altered so that the end result does not change significantly. These terms include deviations of at least ±5% of the somewhat modified terms. should be interpreted as such, but this deviation does not negate the meaning of the term, which is somewhat altered. This is subject to the following conditions. [Effects of the Invention]

[0039] Peripheral circuits such as gate line driver circuits or source line driver circuits, or pixel areas, are divided into two parts, one above the other. By forming a thin film transistor using an oxide semiconductor between the gate electrodes, Reduce manufacturing costs.

[0040] In addition, thin film transistors using oxide semiconductors sandwiched between two gate electrodes on the top and bottom In the BT test, the change in the threshold voltage of the thin film transistor before and after BT stress was measured. That is, the oxide semiconductor sandwiched between two gate electrodes on the top and bottom can be The thin film transistors used can improve reliability. [Brief explanation of the drawings]

[0041] [Figure 1] 1A is a cross-sectional view showing an example of the display device of the first embodiment; FIG. 1B is a cross-sectional view showing another example of the display device of the first embodiment; FIG. 1C is a cross-sectional view showing another example of the display device of the first embodiment. [Figure 2] 1A is a cross-sectional view of a semiconductor device according to a second embodiment, FIG. 1B is an equivalent circuit diagram, and FIG. 1C is a top view. [Figure 3] FIG. 10 is a block diagram illustrating a display device according to a third embodiment. [Figure 4] 10A and 10B illustrate an arrangement of wirings, input terminals, and the like in a display device according to Embodiment 3. [Figure 5] FIG. 2 is a block diagram illustrating a configuration of a shift register circuit. [Figure 6] FIG. 1 is a diagram showing an example of a flip-flop circuit. [Figure 7] FIG. 1 is a diagram showing a layout diagram (top view) of a flip-flop circuit. [Figure 8] FIG. 4 is a timing chart for explaining the operation of the shift register circuit. [Figure 9] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 10] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 11] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 12] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 13] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 14] 10A to 10C illustrate a semiconductor device according to Embodiment 4. [Figure 15] 10A to 10C illustrate a semiconductor device according to Embodiment 4. [Figure 16] 10A to 10C illustrate a semiconductor device according to Embodiment 4. [Figure 17] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment. [Figure 18] FIG. 10 illustrates a pixel equivalent circuit of the semiconductor device of Embodiment 6. [Figure 19] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a sixth embodiment. [Figure 20] 13A and 13B are a top view and a cross-sectional view illustrating a semiconductor device of Embodiment 7. [Figure 21] 10A and 10B are a top view and a cross-sectional view illustrating a semiconductor device of Embodiment 6. [Figure 22] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment. [Figure 23] FIG. 1 is an external view showing an example of an electronic device. [Figure 24] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 25] FIG. 1 is an external view showing an example of a mobile phone. [Figure 26] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0042] The embodiments are described below.

[0043] (Embodiment 1) FIG. 1A shows a thin film transistor 430 used in a driver circuit and a second thin film transistor 431 used in a pixel portion. 1A shows an example in which the transistor 170 is provided on the same substrate. FIG.

[0044] The pixel section and the driver circuit are formed on the same substrate, and the pixel section is arranged in a matrix. The pixel electrode is formed using the second thin film transistor 170, which is an enhancement type transistor. The voltage applied to the second thin film transistor 110 is turned on and off. The gate 170 uses an oxide semiconductor layer 103 and has an on-off ratio of 10 9 Because it is more than This improves display contrast and reduces power consumption due to low leakage current. The on-off ratio is the ratio of the off current to the on current (I ON / I OFF ) and the larger it is, the better the switching characteristics are, and the better the display contrast is. The on-state current is the current that flows between the source electrode and the The off-state current is the current that flows between the drain and the transistor. Sometimes, it refers to the current that flows between the source and drain electrodes. For example, in an n-type transistor, In the case of a transistor, when the gate voltage is lower than the threshold voltage of the transistor, the source electrode and This is the current flowing between the drain electrode and the pixel electrode. To realize this driving, it is preferable to use an enhancement type transistor in the pixel portion. In addition, 101 is a gate electrode, 104a and 104b are a source region and a drain region, 105a denotes a first electrode, 105b denotes a second electrode layer, and 107 denotes a protective insulating layer.

[0045] In the driver circuit, a first gate electrode 401 and an oxide semiconductor layer 405 are provided below the oxide semiconductor layer 405. A thin film transistor having an electrode 470 functioning as a second gate electrode above the semiconductor layer 405. At least one transistor 430 is used. The electrode 47 functions as the second gate electrode. 0 can also be called a back gate electrode. By forming a back gate electrode, Bias-thermal stress test (hereinafter referred to as BT test) is used to check the reliability of transistors. In this case, the amount of change in the threshold voltage of a thin film transistor before and after BT stress is reduced. It is possible.

[0046] The structure of the thin film transistor 430 will be described with reference to FIG. A first gate electrode 401 provided on the plate 400 is covered with a first gate insulating layer 403. An oxide semiconductor layer 40 is formed on the first gate insulating layer 403 overlapping the first gate electrode 401. A channel protective layer 418 is provided over the oxide semiconductor layer 405. The first wiring 409 or the second wiring 410 is provided. An insulating layer 412 is provided on and in contact with the wiring 410. A second gate electrode The electrode 470 functions as a

[0047] The material of the first gate insulating layer 403 is an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, etc.). Silicon, silicon nitride oxide, etc.) can be used, and a single layer or a laminated structure made of these materials can be used. The fabrication method is a vapor phase growth method such as plasma CVD or thermal CVD, or sputtering. In this embodiment, the first gate insulating layer is formed by a first insulating film. The first layer is a silicon nitride film made by plasma CVD, and the second layer is a silicon oxide film made by plasma CVD. The first layer of the silicon nitride film is a layered structure. When using a material that may cause hillocks, it has the effect of preventing the occurrence of hillocks. The silicon nitride film formed by the plasma CVD method is dense and can be used as the first gate insulating film. This can prevent pinholes from occurring. Furthermore, the first gate insulating layer is made of nitride. When a silicon film is used, impurities from the glass substrate, such as mobile ions of sodium, diffuse. This can prevent the oxide semiconductor from being diffused and entering the oxide semiconductor that will be formed later. In either the case of a layered structure or a single-layer structure, the first gate insulating layer 403 The film thickness is set to 50 nm or more and 500 nm or less.

[0048] The oxide semiconductor layer 405 is, for example, In2O3:Ga2O3:ZnO=1:1:1. Using a target (In:Ga:Zn=1:1:0.5), argon gas was used for sputtering. The film is formed under the conditions of a flow rate of 10 sccm and oxygen of 5 sccm. Therefore, the first gate insulating layer 403 and the oxide semiconductor layer 405 are formed without being exposed to the air. Note that when the oxide semiconductor film is exposed to the air, Before the first gate electrode is formed, argon gas is introduced to generate plasma by reverse sputtering. Dust adhering to the surface of the insulating layer 403 may be removed.

[0049] In addition, a source region or a drain region 404 is formed between the oxide semiconductor layer 405 and the first wiring 409. 406a is provided between the oxide semiconductor layer 405 and the second wiring 410. The source and drain regions 406a and 406b are formed as a channel. It is also formed on the protective layer 418, and for example, between the channel protective layer 418 and the first wiring 409 A source or drain region 406a is provided. This source or drain region The oxide semiconductor layer can also be considered as a buffer layer provided between the wiring and the oxide semiconductor layer.

[0050] In this embodiment, the source and drain regions 406a and 406b are made of In-Ga-Z The oxide semiconductor layer 405 is formed under different conditions from the oxide semiconductor layer 405. For example, the oxide semiconductor layer formed by sputtering is an oxide semiconductor layer with lower resistance. The source region or the gate electrode formed with the oxide semiconductor film obtained under the condition of the nitrogen gas flow rate of 40 sccm The drain regions 406a and 406b have n-type conductivity and have an activation energy (ΔE) In this embodiment, the source region or the drain region is 0.01 eV or more and 0.1 eV or less. The layer regions 406a and 406b are layers formed of In-Ga-Zn-O based non-single crystal films. The source region or drain region is assumed to contain at least an amorphous component. 406a and 406b may contain crystal grains (nanocrystals) in the amorphous structure. The crystal grains (nanocrystals) in the source and drain regions 406a and 406b have a diameter of It is 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0051] The thin film transistor 430 has a channel protection layer 418 and an insulating layer 412 stacked together to form a second gate electrode. It functions as an insulating layer. The material of the channel protection layer 418 is an inorganic material (silicon oxide, nitride, etc.). Silicon nitride, silicon oxynitride, silicon nitride oxide, etc.) can be used. Vapor deposition methods such as plasma CVD and thermal CVD, and sputtering methods can be used. In this embodiment, a silicon oxide film obtained by sputtering is used as the channel protection layer 418. There are.

[0052] The insulating layer 412 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, an alumina oxide film, or a silicon nitride film. Aluminum, aluminum nitride, tantalum oxide film, hafnium oxide film, hafnium oxynitride film A single layer or a laminated structure made of these materials can be used. In this embodiment, the insulating layer 412 is a silicon nitride film obtained by a plasma CVD method. The stack of the channel protection layer 418 and the insulating layer 412 functions as a second gate insulating layer. Therefore, the materials and film thicknesses are important for the electrical characteristics of the thin film transistor 430. For example, gate voltages are applied from above and below the oxide semiconductor layer 405 to generate substantially the same electric field. When it is desired to provide the compound semiconductor layer 405, the first layer is a stack of a silicon nitride film and a silicon oxide film. 1, a silicon oxide film (channel protection layer 418), and a silicon nitride film (insulation It is preferable that the thicknesses of the second gate insulating layers (layer 412) are approximately the same. In order to obtain desired electrical characteristics such as a threshold voltage, different gate electrodes are formed on the top and bottom of the oxide semiconductor layer 405. When a gate voltage is applied to the oxide semiconductor layer 405 to apply a different electric field, the first gate By appropriately adjusting the material and film thickness of the first gate insulating layer and the second gate insulating layer, a desired The electrical characteristics of the thin film transistor 430 can be obtained.

[0053] The first gate electrode 401 and the electrode 470 functioning as the second gate electrode are electrically connected to each other. When the oxide semiconductor layer is at the same potential, a gate voltage is applied from above and below the oxide semiconductor layer. Since a large current can be applied to the transistor in the ON state, the current flowing in the ON state can be increased.

[0054] Also, a control signal line for shifting the threshold voltage to the negative side is connected to the first gate electrode 401. , or the electrode 470 that functions as the second gate electrode. This makes it possible to obtain a depletion-type TFT.

[0055] A control signal line for shifting the threshold voltage to the positive side is connected to the first gate electrode 401, Alternatively, it may be electrically connected to either one of the electrodes 470 that functions as the second gate electrode. This makes it possible to make an enhancement-type TFT.

[0056] The combination of two thin film transistors used in the driving circuit is not particularly limited. A thin film transistor with a gate electrode is used as a depletion type TFT, and two gates A thin film transistor having a gate electrode may be used as an enhancement type TFT. In this case, the gate electrodes are arranged above and below the oxide semiconductor layer as thin film transistors in the pixel section. The structure shall have each of these.

[0057] In addition, as a thin film transistor in a pixel portion, a gate electrode is provided above and below the oxide semiconductor layer. The gate electrode is made of oxide semiconductor as an enhancement type TFT of the driving circuit. The gate electrode is a depletion-type TFT for the drive circuit. A structure in which electrodes are provided above and below the oxide semiconductor layer may be used. A control signal line for controlling the value voltage is electrically connected to either the upper or lower gate electrode. The gate electrode connected thereto controls the threshold voltage.

[0058] In FIG. 1A, the electrode 470 functioning as the second gate electrode is The same material as the pixel electrode 110, for example, in the case of a transmission type liquid crystal display device, is used. The number of steps is reduced, but there is no particular limitation. The width of the electrode 470 is wider than the width of the first gate electrode 401, and the width of the oxide semiconductor layer 405 However, the width of the first gate electrode 401 is not limited to the above. It is wider than the width of the channel protection layer 418 (width in the channel direction).

[0059] FIG. 1B shows an example in which the material and width of the second gate electrode are different from those in FIG. 1A. (B) shows a pixel portion in which a thin film transistor 170 connected to an organic or inorganic light emitting element is provided. 1 is an example of a display device having

[0060] In FIG. 1B, an electrode functioning as a second gate electrode of the thin film transistor 432 The material of 471 is metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (N d), scandium (Sc), or an alloy containing the above elements) The width of the electrode 471 in the cross section is set to the width of the electrode functioning as the second gate electrode in FIG. The width of the electrode 471 is narrower than that of the oxide semiconductor layer 405. By narrowing the gap, the first wiring 409 and the second wiring 410 overlap with the insulating layer 412 interposed therebetween. However, the area required for the MOSFET can be reduced, and the parasitic capacitance can be reduced. ), the width of the electrode 471 is wider than the width of the channel protection layer 418.

[0061] The light-emitting element has at least a first electrode 472, a light-emitting layer 475, and a second electrode 474. In FIG. 1B, the electrode 471 is made of the same material as the first electrode 472 of the pixel portion, for example, The number of steps is reduced by using aluminum or the like, but there is no particular limitation. In B), the insulating layer 473 serves as a partition wall for insulating the first electrodes of adjacent pixels. It works like this.

[0062] FIG. 1C shows an example in which the material and width of the second gate electrode are different from those in FIG. 1A. In (C), the electrode 47 functions as the second gate electrode of the thin film transistor 433. The material of 6 is metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd) , scandium (Sc), or an alloy containing the above elements) The width of the second gate electrode in cross section is narrower than that in FIG. 1(B). By narrowing the width of the first wiring 409 and the second wiring 410, the insulating layer 412 is formed. This prevents overlapping and further reduces parasitic capacitance. The width of the electrode 476 shown in C) is narrower than the width of the channel protection layer 418. When forming the electrode 476, the resist mask edge is removed by wet etching or the like. It is preferable to carry out the process so that both ends of the electrode 476 are positioned inside the ) uses a metal material different from that of the pixel electrode 110, This will add one more photolithography process and one more mask.

[0063] Gate line driver circuits or source line drivers used in liquid crystal displays, light-emitting displays, and electronic paper The oxide film sandwiched between two gate electrodes on the top and bottom of the peripheral circuits such as the driving circuit or the pixel section Thin film transistors made of semiconductors are used, enabling high speed operation and low power consumption. Furthermore, both the pixel section and the driver circuit can be formed on the same substrate without significantly increasing the number of processes. By providing various circuits other than the pixel portion on the same substrate, it is possible to This can reduce the manufacturing costs of the display device.

[0064] (Embodiment 2) In the first embodiment, one thin film transistor is described as the thin film transistor of the drive circuit. However, here, two n-channel thin film transistors are used to form the inverter circuit of the driver circuit. The thin film transistor shown in FIG. Since the thin film transistor 430 is the same as that shown in FIG. 1(A) of the first embodiment, the same parts are used. The explanation will be given using symbols.

[0065] The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. When two n-channel TFTs are combined to form an inverter circuit, When forming a combination of a ment type transistor and a depletion type transistor ( Hereafter referred to as EDMOS circuit) and when formed by enhancement type transistors (hereinafter referred to as EEMOS circuit).

[0066] The cross-sectional structure of the inverter circuit of the driver circuit is shown in Figure 2(A). The first thin film transistor 430 is a dual-gate type, and the second thin film transistor 431 is a bottom-gate type thin film transistor. It is a film transistor, and wiring is provided on the semiconductor layer via a source region or a drain region. This is an example of a thin film transistor.

[0067] In FIG. 2A, a first gate electrode 401 and a gate electrode 402 are provided on a substrate 400. The first gate electrode 401 and the gate electrode 402 are made of molybdenum, titanium, chromium, or the like. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a laminated layer using a material or an alloy material containing these as the main component. do.

[0068] For example, the two-layer laminate structure of the first gate electrode 401 and the gate electrode 402 may be Al. Two-layer laminate structure with a molybdenum layer on a aluminum layer, or a molybdenum layer on a copper layer or a titanium nitride or tantalum nitride layer on a copper layer. Preferably, the titanium nitride layer and the molybdenum layer are laminated together to form a two-layer structure. The copper oxide layer containing Ca is laminated on the copper layer containing Ca as a barrier layer, and the copper oxide layer containing Mg is laminated on the copper layer containing Mg as a barrier layer. There is also a laminated structure of copper oxide containing Mg as a barrier layer. a tungsten layer or tungsten nitride layer and an aluminum-silicon alloy or aluminum It is preferable to use a laminated layer in which an alloy layer of aluminum and titanium is laminated with a titanium nitride layer or a titanium layer. I wish.

[0069] Also, on the first gate insulating layer 403 covering the first gate electrode 401 and the gate electrode 402 An oxide semiconductor layer 405 and a second oxide semiconductor layer 407 are provided on the first oxide semiconductor layer 404 .

[0070] A channel protective layer 418 is provided over the oxide semiconductor layer 405. The second wiring 410 is provided, and the second wiring 410 is connected to the contact formed in the first gate insulating layer 403. It is directly connected to the gate electrode 402 through a contact hole 404. Even if the contact hole 404 is formed after the first gate insulating layer 403 is formed, Alternatively, after forming the channel protection layer 418 and the second channel protection layer 419, the contact A hole 404 may be formed. A third wiring is formed on the second oxide semiconductor layer 407. 411 will be established.

[0071] The thin film transistor 430 includes a first gate electrode 401 and a first gate insulating layer 403. The first wiring 409 is formed by a first gate electrode 401 and an oxide semiconductor layer 405 overlapping the first gate electrode 401. This power supply line is a power supply line to which a negative voltage VDL is applied (negative power supply line). It may also be a power supply line (ground power supply line).

[0072] The second thin film transistor 431 includes a gate electrode 402 and a first gate insulating layer 40 a second oxide semiconductor layer 407 overlapping the gate electrode 402 via a third wiring 4 Reference numeral 11 denotes a power supply line (positive power supply line) to which a positive voltage VDH is applied.

[0073] In addition, between the second oxide semiconductor layer 407 and the second wiring 410, + providing a layer 408a; Between the second oxide semiconductor layer 407 and the third wiring 411, + A layer 408b is provided. Between the channel protection layer 418 and the second wiring 410, a source region or a drain region 406 is formed. b is provided between the channel protection layer 418 and the first wiring 409. A drain region 406a is provided.

[0074] FIG. 2C shows a top view of the inverter circuit of the driver circuit. The cross section taken along line Z1-Z2 corresponds to FIG. 2(A).

[0075] The equivalent circuit of the EDMOS circuit is shown in Figure 2(B). 2(B), and the thin film transistor 430 is an enhancement type n-channel transistor. The second thin film transistor 431 is a depletion type n-channel transistor. This is an example of a star.

[0076] In order to make the thin film transistor 430 an enhancement type n-channel transistor, In this embodiment, the channel protective layer 418 and the insulating layer 412 are formed over the oxide semiconductor layer 405. An electrode 470 that functions as a second gate electrode is provided on the insulating layer 412. The threshold voltage of the thin film transistor 430 is controlled by the voltage applied to the electrode 470, which functions as an electrode. Perform value control.

[0077] 2A and 2C, the second wiring 410 is connected to the first gate insulating layer 403. 4 shows an example in which the gate electrode 402 is directly connected to the contact hole 404 formed in the However, this is not particularly limited, and a connecting electrode may be separately provided to connect the second wiring 410 and the gate electrode 402. They may also be electrically connected.

[0078] This embodiment mode can be freely combined with Embodiment Mode 1.

[0079] (Embodiment 3) In this embodiment, a display device will be described with reference to block diagrams and the like.

[0080] FIG. 3A shows an example of a block diagram of an active matrix liquid crystal display device. The liquid crystal display device shown in (A) has a pixel section having a plurality of pixels each having a display element on a substrate 300. 301, a scanning line driving circuit 302 that controls the scanning lines connected to the gate electrodes of each pixel, and a signal line driver circuit 303 that controls input of a video signal to a selected pixel.

[0081] FIG. 3B shows an example of a block diagram of an active matrix light-emitting display device. The light-emitting display device shown in (B) has a pixel section having a plurality of pixels each having a display element on a substrate 310. 311, and a first scanning line driving circuit 31 that controls the scanning lines connected to the gate electrodes of the pixels. The second and second scanning line driver circuits 313 control the input of video signals to selected pixels. A signal line driving circuit 314 is provided. When two TFTs are arranged, one for the light-transistor and the other for current control, as shown in Figure 3(B), In the light-emitting display device shown in FIG. 1, a first scanning line connected to a gate electrode of a switching TFT The signal to be input to the first scanning line driving circuit 312 is generated by the first scanning line driving circuit 313, and the gate voltage of the current control TFT is generated by the first scanning line driving circuit 314. A signal to be input to the second scanning line connected to the electrode is generated by the second scanning line driving circuit 313. However, the signal input to the first scanning line and the signal input to the second scanning line are input to the same It may be configured to be generated by a scanning line driver circuit. Depending on the number of TFTs, the first scan line used to control the operation of the switching element is In this case, the signals input to the plurality of first scanning lines may be All of these may be generated by one scanning line driving circuit, or multiple scanning line driving circuits may be provided. It may be generated by each of these.

[0082] Here, the scanning line driver circuit 302, the first scanning line driver circuit 312, the second scanning line A driver circuit 313 and signal line driver circuits 303 and 314 are fabricated in a display device. However, the scanning line driver circuit 302, the first scanning line driver circuit 312, or the second scanning line driver circuit A part of the signal line driver circuit 303, 313 may be implemented by a semiconductor device such as an IC. A part of 14 may be implemented as a semiconductor device such as an IC.

[0083] FIG. 4 shows a signal input terminal 321, a scanning line 323, a signal line 324, and a non-transitory The positional relationship between the protection circuits 334, 335, and 336 including linear elements and the pixel section 327 will be explained. On a substrate 320 having an insulating surface, scan lines 323 and signal lines 324 are arranged crossing each other. The pixel section 327 is configured by placing the pixel section 30 shown in FIG. 1 and pixel section 311.

[0084] The pixel section 301 is connected to a signal line driving circuit 303 and includes a plurality of signal lines S arranged in a column direction. 1 to Sm (not shown) are connected to the signal line driving circuit 303, and the scanning line driving circuit 302 A plurality of scanning lines G1 to Gn (not shown) are arranged extending in the row direction from the The matrix is ​​connected to the driving circuit 302 and corresponds to the signal lines S1 to Sm and the scanning lines G1 to Gn. The pixel array has a plurality of pixels (not shown) arranged in a grid pattern. Each pixel is connected to a signal line Sj( signal lines S1 to Sm), scanning lines Gi (any one of scanning lines G1 to Gn) ) is connected.

[0085] The pixel section 327 is configured by arranging a plurality of pixels 328 in a matrix. 8 is a pixel TFT 329 connected to the scanning line 323 and the signal line 324, a storage capacitor 330, a pixel It is configured to include a base electrode 331 .

[0086] In the pixel configuration shown here, the storage capacitor 330 has one electrode and a pixel TFT 329 is connected, and the other electrode is connected to the capacitance line 332. 331 drives display elements (liquid crystal elements, light emitting elements, contrast media (electronic ink), etc.) The other electrodes of these display elements are connected to a common terminal 333. are.

[0087] The protection circuit 335 is disposed between the pixel section 327 and the signal line input terminal 322 . In addition, the protection circuit 334 is disposed between the scanning line driving circuit and the pixel section 327. In this embodiment, a plurality of protection circuits are provided to protect the scanning lines 323, the signal lines 324, and the capacitive bus lines. 337 due to static electricity or other reasons, so that the pixel TFT 329 and other components are not destroyed. Therefore, when a surge voltage is applied to the protection circuit, the common wiring The capacitor is configured to allow electric charge to escape.

[0088] In this embodiment, a protection circuit 334 is provided on the scanning line 323 side, and a protection circuit 33 is provided on the signal line 324 side. 5, an example is shown in which a protection circuit 336 is provided on a capacitive bus line 337. The position of the scanning line driver circuit is not limited to this. In this case, the protection circuit 334 does not need to be provided on the scanning line 323 side.

[0089] By using the TFTs shown in the first embodiment or the second embodiment in each of these circuits, , has the following advantages:

[0090] The drive circuit is roughly divided into a logic circuit section and a switch section or buffer section. The TFT provided in the switch is preferably configured to be capable of controlling the threshold voltage. It is preferable that the TFT provided in the pixel section or the buffer section has a large on-state current. Alternatively, a driver circuit having the TFT shown in Embodiment 2 may be provided in the logic circuit portion. It is possible to control the threshold voltage of the TFT, and the on / off of the TFT provided in the switch section or buffer section Furthermore, the area occupied by the drive circuit can be reduced, allowing for a narrow It also contributes to framing.

[0091] The shift register circuit that constitutes the scanning line driving circuit will be described below.

[0092] The shift register circuit shown in FIG. 5 has a plurality of flip-flop circuits 351, and line 352, control signal line 353, control signal line 354, control signal line 355, control signal line 356 , and a reset line 357.

[0093] As shown in the shift register circuit of FIG. 5, in the flip-flop circuit 351, the input of the first stage A start pulse SSP is input to the input terminal IN via the control signal line 352, and the next stage and onward The input terminal IN of the flip-flop circuit 351 is connected to the output signal terminal S of the previous stage. OUT is connected In addition, the reset terminal RES of the Nth stage (N is a natural number) is The output signal terminal S of the flip-flop circuit out and connected via reset wire 357 The clock terminal CLK of the Nth stage flip-flop circuit 351 is connected to the control signal line 35 Assuming that the first clock signal CLK1 is input via 3, the (N+1)th stage The clock terminal CLK of the flip-flop circuit 351 is connected to the first control signal line 354. The clock signal CLK2 of the (N+2)th stage is input. The clock terminal CLK of 351 receives the third clock signal CL via a control signal line 355. K3 is input to the clock terminal of the (N+3)th flip-flop circuit 351. A fourth clock signal CLK4 is input to CLK via a control signal line 356. The clock terminal CLK of the (N+4)th flip-flop circuit 351 receives a control signal A first clock signal CLK1 is input via a line 353. The flip-flop circuit 351 has a gate output terminal G out Therefore, the Nth stage flip-flop circuit Output SRoutN.

[0094] Although the connection between the flip-flop circuit 351 and the power supply and power supply line is not shown, Each flip-flop circuit 351 is supplied with a power supply potential Vdd and a power supply potential GND via a power supply line. is being supplied.

[0095] The power supply potential described in this specification corresponds to the potential difference when the reference potential is 0V. Therefore, the power supply potential is sometimes called the power supply voltage, and vice versa. There are also.

[0096] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, those that are connected electrically are also included. Electrically connected means that there is an object between A and B that has some kind of electrical effect. When this happens, A and B are roughly the same node via the object. In the case of the MOS transistor, A and B are connected via a switching element such as a TFT. When A and B are at roughly the same potential due to conduction of the resistor, or when A and B are connected via a resistor, The potential difference across the resistor element does not affect the operation of the circuit including A and B. When considering the circuit operation, A and B can be considered as the same node and the difference This indicates a situation where it is not possible to do so.

[0097] Next, in FIG. 6, the flip-flop circuit 351 included in the shift register circuit shown in FIG. The flip-flop circuit 351 shown in FIG. 6 includes a logic circuit portion 361 and a switch. The logic circuit section 361 has TFTs 363 to 368. The switch section 362 also includes TFTs 369 to 372. The circuit section is a section that outputs signals to the switch section, which is the subsequent circuit, in response to signals input from the outside. The switch section is a circuit for switching the input signal from the external and control circuit sections. The switching of the TFT on or off in response to the signal input to the TFT. This is a circuit for outputting a current according to the noise and structure.

[0098] In the flip-flop circuit 351, the input terminal in is connected to the gate terminal of the TFT 364, and The reset terminal RES is connected to the gate terminal of the TFT363. The clock terminal CLK is connected to the first terminal of the TFT 369 and the The power supply line to which the power supply potential Vdd is supplied is connected to the first terminal of the TFT371. 364 and the gate terminal and second terminal of the TFT 366. The power supply line to which the source potential GND is supplied is the second terminal of TFT363 and the second terminal of TFT365. , the second terminal of the TFT 367, the second terminal of the TFT 368, the second terminal of the TFT 370, and T It is connected to the second terminal of TFT372. It is also connected to the first terminal of TFT363, TFT364 the second terminal of TFT365, the first terminal of TFT368, the gate terminal of TFT369 The gate terminal of the TFT 371 and the gate terminal of the TFT 366 are connected to each other. The first terminal is the gate terminal of the TFT365, the first terminal of the TFT367, the first terminal of the TFT368 terminal, the gate terminal of the TFT 370, and the gate terminal of the TFT 372. Also, the gate output terminal G out is the second terminal of TFT369 and the first terminal of TFT370 Connected to output signal terminal S out is the second terminal of TFT371 and TFT37 2 is connected to the first terminal.

[0099] In this case, the TFTs 363 to 372 are all N-type TFTs. We will explain the following.

[0100] The TFT has at least three terminals including a gate, a drain, and a source. The element has a channel forming region between the drain region and the source region, and the drain region A current can flow through the source region, the channel forming region, and the source region. The and drain may be interchanged depending on the TFT structure and operating conditions. It is difficult to identify which is the source and which is the drain. The regions that function as the source and drain are not called the source or drain, but are called, for example, These are referred to as the first terminal and the second terminal. In this case, the terminal that functions as the gate is In this case, it is referred to as the gate terminal.

[0101] Next, an example of a layout diagram of the flip-flop circuit 351 shown in FIG. 6 is shown in FIG.

[0102] The flip-flop circuit of FIG. 7 includes a power supply line 381 to which a power supply potential Vdd is supplied, a reset Line 382, ​​control signal line 353, control signal line 354, control signal line 355, control signal line 356 , a control signal line 383, a power supply line 384 to which a power supply potential GND is supplied, a logic circuit unit 361, and The logic circuit section 361 has TFTs 363 to 368. The switch section 362 also includes TFTs 369 to 372. In Figure 7, the gate output terminal G out Wiring connected to output signal terminal S out connected to The wiring is also shown.

[0103] In FIG. 7, a semiconductor layer 385, a first wiring layer 386, a second wiring layer 387, a third wiring The first wiring layer 386 is shown as follows: The second wiring layer 387 is formed from a layer that forms a gate electrode, and the second wiring layer 388 is formed from a layer that forms a source electrode of the TFT. The third wiring layer 388 is formed from a layer that forms a drain electrode. However, the present invention is not limited to this, and may be applied to, for example, the third wiring layer. The layer 388 may be formed as a wiring layer separate from the layer forming the pixel electrode.

[0104] The connections between the circuit elements in FIG. 7 are as explained in FIG. 6. Since the figure shows a flip-flop circuit to which the first clock signal is input, Connections to control signal lines 354 to 356 are not shown.

[0105] In the layout diagram of the flip-flop circuit in FIG. 7, the TF By controlling the threshold voltage of T366 or TFT367, the EDMOS circuit 373 Typically, the TFT 366 is a depression type, and the TFT 36 7 is configured as an enhancement type EDMOS circuit 373, and the switch section 362 has The TFTs 369 to 372 are dual gate type TFTs or depletion type TFTs. In FIG. 6, the TFT 366 and the TFT The FT367 is different from the EDMOS circuit shown in Figure 2 in that it is a depletion-type TFT gate electrode. The connection position is different.

[0106] TFT366 or TFT367 is formed as a dual gate type TFT, and the back gate By controlling the potential of the electrodes, it is possible to produce either a depletion-type TFT or an enhancement-type It can be a TFT.

[0107] In FIG. 7, the control gate electrode is connected to the back gate electrode for controlling the threshold voltage of the TFT366. A control signal line 390 is provided separately to make the TFT 366 a depletion type. The potential of the back gate electrode is the power supply potential V applied to the gate electrode. This is a different potential from the power supply line 381 to which dd is supplied.

[0108] In FIG. 7, TFTs 369 to 372 are dual-gate TFTs, and In this example, the back gate electrode and the gate electrode are at the same potential. The power supply potential Vdd applied to the power supply line is the same potential as that of the power supply line.

[0109] In this way, the TFTs arranged in the pixel portion and the driving circuit of the display device are formed on the oxide semiconductor layer. The TFT can be formed only with an n-channel TFT.

[0110] In addition, the TFT 366 in the logic circuit section 361 flows a current in response to the power supply potential Vdd. The TFT366 is a dual-gate TFT or a depletion-type TFT. By increasing the current flowing through the TFT, the TFT's performance can be improved without any degradation. It is possible to achieve miniaturization.

[0111] In addition, in the TFT that constitutes the switch section 362, the amount of current flowing through the TFT is increased. , and can be switched on and off quickly without degrading performance. The area occupied by the TFT can be reduced. The area occupied by the TFTs 369 to 369 in the switch section 362 can also be reduced. As shown in the figure, the TFT 372 has a semiconductor layer 385 connected to a first wiring layer 386 and a third wiring layer 387. The layout is sandwiched between 388 to form a dual gate TFT.

[0112] 7, the dual gate TFT has a semiconductor layer 385 and a first wiring layer 386. The third wiring layer 386 is connected to the first wiring layer 386 through a contact hole 389 and has the same potential. Although an example in which the wiring layer 388 is sandwiched between the wiring layer 388 and the wiring layer 388 has been shown, the present invention is not limited to this configuration. For example, a control signal line may be provided separately for the third wiring layer 388, and the potential of the third wiring layer 388 may be controlled. may be configured to be controlled independently from the first wiring layer 386.

[0113] In the layout diagram of the flip-flop circuit shown in FIG. The channel forming region of FT372 may be U-shaped (or horseshoe-shaped). In addition, in Figure 7, the size of each TFT is set to be equal, but the output voltage may vary depending on the size of the load in the subsequent stage. Force signal terminal S out or gate output terminal G out The size of each TFT connected to You may change it.

[0114] Next, the operation of the shift register circuit shown in FIG. 5 will be explained using the timing chart shown in FIG. 8 shows the control signal lines 352 to 356 shown in FIG. The start pulse SSP, the first clock signal CLK1 to the fourth clock signal CLK2 are supplied respectively. Signal CLK4 and output signal terminals S of the first to fifth stage flip-flop circuits out mosquito 8. In the explanation of FIG. 8, Sout1 to Sout5 output from 6 and 7, the same symbols as those assigned to the respective elements are used.

[0115] Note that FIG. 8 shows a case where each TFT in the flip-flop circuit is an N-type TFT. 1 is a timing chart showing the first clock signal CLK1 to the fourth clock signal CLK2. CLK4 is configured to be shifted by 1 / 4 wavelength (one section divided by dotted lines) as shown in the figure. It is as follows.

[0116] First, during the period T1, the first stage flip-flop circuit receives a start pulse SSP is input at H level, and the logic circuit section 361 switches the TFTs 369 and 371 of the switch section. is turned on, and the TFT 370 and the TFT 372 are turned off. At this time, the first clock signal Since CLK1 is at L level, Sout1 is at L level.

[0117] During the period T1, the flip-flop circuits from the second stage onwards have a signal at the IN terminal. Since no input is input, it does not operate and outputs L level. The explanation will be given assuming that each flip-flop circuit in the soft register circuit outputs an L level. cormorant.

[0118] Next, in the period T2, in the first stage flip-flop circuit, the logic The logic circuit unit 361 controls the switch unit 362. In the period T2, the first clock signal C Since LK1 is at H level, Sout1 is at H level. In the first flip-flop circuit, Sout1 is input to the IN terminal at a H level, and the logic circuit The TFT 361 turns on the TFT 369 and TFT 371 of the switch section, and the TFT 370 and TFT At this time, the second clock signal CLK2 is at the L level, so S out2 is at L level.

[0119] During the period T2, the flip-flop circuits from the third stage onwards have a signal at the IN terminal. Since no input is received, the L level is output without operating.

[0120] Next, during the period T3, the first stage flip-flop circuit maintains the state of the period T2. The logic circuit unit 361 controls the switch unit 362 so that , the first clock signal CLK1 is at H level, and Sout1 is at H level. During the period T3, in the second stage flip-flop circuit, the logic circuit section 361 controls the switch unit 362. In the period T3, the second clock signal CLK2 is Since the signal Sout2 is at the H level, the third flip-flop in the period T3 In the flop circuit, Sout2 is input to the IN terminal at H level, and the logic circuit unit 361 switches to the The TFTs 369 and 371 of the switch are turned on, and the TFTs 370 and 372 are turned off. At this time, the third clock signal CLK3 is at the L level, so Sout3 is at the L level. do.

[0121] During the period T3, the flip-flop circuits from the fourth stage onwards have a signal at the IN terminal. Since no input is received, the L level is output without operating.

[0122] Next, during the period T4, the first stage flip-flop circuit maintains the state of the period T3. The logic circuit unit 361 controls the switch unit 362 so that In this case, the first clock signal CLK1 is at L level, and Sout1 is at L level. During the period T4, the second stage flip-flop circuit maintains the state of the period T3. The logic circuit unit 361 controls the switch unit 362 in this manner. , the second clock signal CLK2 is at H level, and Sout2 is at H level. During the period T4, in the third stage flip-flop circuit, the logic circuit section 361 controls the switch unit 362. In the period T4, the third clock signal CLK3 is Since the signal Sout3 is at the H level, the fourth flip-flop in the period T4 In the flop circuit, Sout3 is input to the IN terminal at a H level, and the logic circuit unit 361 switches to the The TFTs 369 and 371 of the switch unit 362 are turned on, and the TFTs 370 and 37 At this time, the fourth clock signal CLK4 is at the L level, so t4 is at L level.

[0123] During the period T4, the flip-flop circuits from the fifth stage onwards have a signal at the IN terminal. Since no input is received, the L level is output without operating.

[0124] Next, during the period T5, the second stage flip-flop circuit maintains the state of the period T3. The logic circuit unit 361 controls the switch unit 362 so that In this case, the second clock signal CLK2 is at L level, and Sout2 is at L level. In addition, during the period T5, the third stage flip-flop circuit maintains the state of the period T4. The logic circuit unit 361 controls the switch unit 362 in this manner. , the third clock signal CLK3 is at H level, and Sout3 is at H level. In the period T5, the fourth stage flip-flop circuit is connected to the logic circuit unit 3 in the same manner as in the period T4. 61 controls the switch unit 362. During the period T5, the fourth clock signal CLK4 is H Since Sout4 is at H level, the flip-flops from the 5th stage onwards The circuit has the same wiring relationship as the first to fourth flip-flop circuits, and the input The signal timing is similar, so a description thereof will be omitted.

[0125] As shown in the shift register circuit in Figure 5, Sout4 is the first stage flip-flop circuit. During the period T5, Sout4 becomes H level, and this signal The reset signal is input to the reset terminal RES of the flip-flop circuit in the second stage. By this, the TFT 369 and the TFT 371 of the switch section 362 are turned off, and the TFT 3 Then, Sout1 of the first stage flip-flop circuit is turned on. will output an L level until the next start pulse SSP is input.

[0126] By the operation explained above, the flip-flops in the second and subsequent stages can be The logic circuit is reset based on the reset signal output from the drop circuit, As shown in ut1 to Sout5, the waveform of the clock signal is shifted by 1 / 4 wavelength. The shift register circuit can output the following signal.

[0127] In addition, as a flip-flop circuit, enhancement type and depletion type are used in the logic circuit section. The switch section is equipped with a dual-gate TFT and an EDMOS TFT. By adopting this configuration, the amount of current flowing through the TFTs constituting the logic circuit section 361 can be increased. It is possible to reduce the area occupied by the TFT and the amount of light generated by the TFT without reducing the performance. In addition, the area occupied by the circuit configured by the switch unit 362 can be reduced. In TFTs, the amount of current flowing through the TFT is increased, allowing for fast on / off switching. Therefore, the area occupied by the TFT and the size of the TFT can be reduced without degrading the performance. Therefore, the area occupied by the circuit formed by T can be reduced. It is possible to achieve edge reduction, miniaturization, and high performance.

[0128] In addition, a latch circuit, a level shifter circuit, etc. may be provided in the signal line driver circuit shown in FIG. A buffer section is provided at the final stage of sending signals from the signal line driver circuit to the pixel section, and the amplified signals are The signal is sent from the signal line driver circuit to the pixel section. T, typically a dual-gate TFT or a depletion-type TFT Therefore, it is possible to reduce the area of ​​the TFT, and the area occupied by the signal line driving circuit. Therefore, it is possible to achieve a display device with a narrower frame, smaller size, and higher performance. The shift register, which is part of the signal line driver circuit, is required to operate at high speed. It is preferable to mount it on the display device using C or the like.

[0129] This embodiment mode can be freely combined with Embodiment Mode 1 or 2. Cut.

[0130] (Fourth embodiment) In this embodiment, a manufacturing process of a display device including the thin film transistor described in Embodiment 1 will be described. This will be explained with reference to FIGS. 9 to 16.

[0131] In FIG. 9(A), a light-transmitting substrate 100 is made of barium borosilicate glass or aluminum. A glass substrate such as borosilicate glass can be used.

[0132] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary portions are removed by etching to form wiring and electrodes (gate The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 are formed. At this time, the edge is formed so that at least the end of the gate electrode layer 101 has a tapered shape. The cross-sectional view at this stage is shown in Figure 9(A). In FIG. 11, the oxide semiconductor film, the channel protection layer, and the The source electrode, the drain electrode, the contact hole, and the pixel electrode are indicated by dashed lines. When using spin coating to form a resist mask, in order to improve the uniformity of the resist film, In this case, a large amount of resist material and a large amount of developer are used, resulting in a large amount of waste material. When the substrate becomes larger, the film formation method using spin coating requires a mechanism to rotate the large substrate. This is disadvantageous for mass production because it requires a large scale process, and there is a large amount of loss of liquid material and waste liquid. When spin-coating a rectangular substrate, circular irregularities around the rotation axis tend to occur in the coating film. Therefore, selective printing is performed using a droplet ejection method such as the inkjet method or a screen printing method. It is preferable to form a resist material film on the substrate and then expose the film to light to form a resist mask. By selectively forming a resist material film, the amount of resist material used can be reduced. This allows for significant cost reductions, and the 1000mm x 1200mm and 1100mm x 125mm sizes are available. It can also accommodate large area substrates such as 1150mm x 1300mm.

[0133] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc ) or alloys containing the above elements or combinations of the above elements It is formed from an alloy film containing the above elements or a nitride film containing the above elements. It is desirable to form it from a low-resistance conductive material such as Al (Al) or copper (Cu), but Al alone is Because of problems such as poor heat resistance and susceptibility to corrosion, it is recommended to combine it with a heat-resistant conductive material. The heat-resistant conductive material is titanium (Ti), tantalum (Ta), tungsten (Tb), W, Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Scandium (S c) Use an element selected from

[0134] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode layer 101. The film thickness of 02 is set to 50 to 250 nm using a sputtering method or the like.

[0135] For example, a silicon oxide film is used as the gate insulating layer 102 by sputtering, and the thickness is 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. Silicon oxide nitride film, silicon nitride film, aluminum oxide film, tantalum oxide film, It may be formed as a single layer or a laminated structure made of these materials using other insulating films such as a film. good.

[0136] Before the oxide semiconductor film is formed, a reverse process in which argon gas is introduced to generate plasma is performed. It is preferable to perform sputtering to remove dust adhering to the surface of the gate insulating layer. Instead of the argon atmosphere, nitrogen, helium, etc. may be used. It may be carried out in an atmosphere containing oxygen, hydrogen, NO, etc. 2. It may be carried out in an atmosphere containing CF4 or the like.

[0137] Next, a first oxide semiconductor film (a first In- After the plasma treatment, the first Depositing an In-Ga-Zn-O based non-single crystal film creates a gate insulating layer and a semiconductor film. It is useful in that it does not attract dust or moisture. Here, an 8-inch diameter In, Ga, and The oxide semiconductor target containing Zn (In2O3:Ga2O3:ZnO=1:1:1) The distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, and the DC voltage was The film is formed under an argon or oxygen atmosphere with a 0.5 kW power source. The use of In-Ga- is preferable because it reduces dust and makes the film thickness distribution uniform. The thickness of the Zn—O-based non-single crystal film is set to 5 nm to 200 nm. The thickness of the n-Ga-Zn-O based non-single crystal film is set to 100 nm.

[0138] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0139] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0140] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0141] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0142] Next, a channel is formed in the region of the first In-Ga-Zn-O based non-single crystal film that overlaps the channel forming region. The channel protection layer 133 is also made of the first In-Ga-Zn-O based non-metallic compound. The thin film may be formed by successively depositing the single crystal film without exposing it to the air. If the film is continuously formed without being exposed to the atmosphere, productivity will be improved.

[0143] The channel protection layer 133 may be made of an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, silicon nitride, silicon nitride, silicon dioxide ... The manufacturing method can be plasma CVD or thermal CVD. Any vapor deposition method or sputtering method can be used. The channel protection layer 133 is formed by The shape is processed by etching later. Here, a silicon oxide film is formed by sputtering. The channel protection layer is formed by etching using a photolithography mask. When the channel protection layer 133 is etched, the first In-Ga- The Zn-O non-single crystal film functions as an etching stopper, preventing the gate insulating film from thinning. This can prevent this.

[0144] Next, a second In—Ga—Zn—O-based non-single-crystal film is formed on the first In—Ga—Zn—O-based non-single-crystal film and the channel protection layer 133. The oxide semiconductor film (in this embodiment, the second In-Ga-Zn-O based non-single-crystal film) is Here, the substrate is In2O3:Ga2O3:ZnO=1:1:1. The deposition conditions were a pressure of 0.4 Pa, a power of 500 W, and a deposition temperature of room temperature. The temperature was raised and argon gas was introduced at a flow rate of 40 sccm to perform sputtering deposition. Although a target with a ZnO content of 1:1:1 was intentionally used, Immediately after deposition, an In-Ga-Zn-O based non-single crystal film containing crystal grains of 1 nm to 10 nm in size was formed. The target component ratio and deposition pressure (0.1 Pa to 2.0 Pa) may be , power (250W~3000W: 8 inch φ), temperature (room temperature ~ 100℃), reactive sputter By appropriately adjusting the deposition conditions of the crystal grains, the presence or absence of crystal grains, the density of the crystal grains, and the diameter size can be controlled. Therefore, it can be said that the thickness can be adjusted in the range of 1 nm to 10 nm. The thickness of the crystal film is set to 5 nm to 20 nm. Of course, if the film contains crystal grains, the included In this embodiment, the size of the crystal grains formed in the second In-Ga The thickness of the Zn—O-based non-single crystal film is set to 5 nm.

[0145] The first In-Ga-Zn-O based non-single-crystal film is For example, the film formation conditions for the second In-Ga-Zn-O based non-single crystal film are different from those for the first In-Ga-Zn-O based non-single crystal film. The ratio of the oxygen gas flow rate to the argon gas flow rate in the first In-Ga-Zn-O system non-single The conditions for forming the crystal film are such that the oxygen gas flow rate accounts for a large proportion. The deposition conditions for the In-Ga-Zn-O non-single crystal film in 2 are: rare gas (argon or helium) etc.) atmosphere (or oxygen gas 10% or less, argon gas 90% or more), and The conditions for forming the n-Ga-Zn-O non-single crystal film were an oxygen atmosphere (or an oxygen gas flow rate of 1000 MPa). (The flow rate of the gas should be larger than that of the gas flow rate.)

[0146] The second In-Ga-Zn-O non-single crystal film was deposited in the chamber where the reverse sputtering was performed previously. The same chamber as the previous reverse sputtering may be used, or a different chamber may be used. The film may be formed using a bar.

[0147] Next, a third photolithography step is performed to form a resist mask. Etching of the Ga-Zn-O non-single crystal film and the second In-Ga-Zn-O non-single crystal film Here, the unnecessary layer is removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Ltd.). The oxide semiconductor film 109 is a first In-Ga-Zn-O based non-single-crystal film. Then, the oxide semiconductor film 111, which is a second In—Ga—Zn—O-based non-single-crystal film, is formed. The etching here is not limited to wet etching, but also uses dry etching. The top view at this stage is shown in FIG. 9(B). The top view at this stage is shown in FIG. In FIG. 12, the source electrode and the drain electrode, which will be formed later, and the contact The holes and pixel electrodes are indicated by dashed lines.

[0148] Next, a fourth photolithography step is performed to form a resist mask and etch the By removing unnecessary portions of the gate insulating layer 102, wiring and electrodes made of the same material as the gate electrode layer are formed. A contact hole is formed that reaches the layer. This contact hole is connected to the conductive film that will be formed later. For example, in the driver circuit section, the gate electrode layer and the source electrode layer are directly connected. Alternatively, the thin film transistor directly contacts the drain electrode layer, and the gate wiring of the terminal portion is electrically connected to the thin film transistor. When forming a connecting terminal, a contact hole is formed.

[0149] Next, a conductive film 13 made of a metal material is formed over the oxide semiconductor film 109 and the oxide semiconductor film 111. 2 is formed by sputtering or vacuum deposition. The top view at this stage is shown in Figure 9(C).

[0150] The material of the conductive film 132 is an element selected from Al, Cr, Ta, Ti, Mo, and W, or or an alloy containing the above elements as a component, or an alloy film of a combination of the above elements. In addition, when heat treatment is performed at 200 to 600°C, the heat resistance that can withstand this heat treatment is introduced. It is preferable to have a conductive film with Al as the only material. It is formed by combining it with a heat-resistant conductive material. The conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum. Elements selected from (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) or an alloy containing the above elements as components, or an alloy film containing a combination of the above elements, or It is formed from a nitride containing the above-mentioned elements as components.

[0151] Here, the conductive film 132 has a single-layer structure of a titanium film. Alternatively, a titanium film may be stacked on an aluminum film. A Ti film is layered on top of the Ti film, and an aluminum film containing Nd (Al-Nd) is layered on top of the Ti film. The conductive film 132 may be a silicon film, and a Ti film may be formed on top of the silicon film. Alternatively, the aluminum film may have a single layer structure containing the above.

[0152] Next, a fifth photolithography step is performed to form a resist mask 131 and etch the resist mask. The unnecessary portions are removed by etching to leave the first electrode 105a, the second electrode 105b, and the source electrode 105b. The drain and gate regions 104a and 104b are formed by etching. For example, the conductive film 132 is made of aluminum. When using aluminum film or aluminum alloy film, use a solution of phosphoric acid, acetic acid, and nitric acid. Here, wet etching can be performed using ammonia hydrogen peroxide (ammonia hydrogen peroxide). The conductive film 132 of the Ti film was removed by wet etching using ammonia:water (5:2:2). The first electrode 105a, the second electrode 105b, and the oxide semiconductor film 111 are removed by etching. The source and drain regions 104a and 104b are formed by etching. In the etching process, the channel protection layer 133 prevents the oxide semiconductor layer 103 from being etched. Since the oxide semiconductor layer 103 functions as a protective film, the oxide semiconductor layer 103 is not etched. In the semiconductor device, a first electrode 105a, a second electrode 105b, a source region or a drain region 10 4a and 104b are etched at the same time using an etching agent of ammonia hydrogen peroxide. The first electrode 105a, the second electrode 105b and the source or drain region 104a, 1 The edges of 04b are aligned and form a continuous structure. Therefore, etching is performed isotropically, and the edges of the first electrode 105a and the second electrode 105b are The resist mask 131 is recessed from the oxide semiconductor layer 103. a thin-film transistor having a channel protection layer 133 on the channel formation region; The cross section at this stage is shown in FIG. The top view without the resist mask 131 corresponds to FIG. 13. The pixel electrodes that are connected are shown by dashed lines.

[0153] A channel protection layer 133 is provided on a channel formation region of the oxide semiconductor layer 103. Therefore, damage (etching) to the channel formation region of the oxide semiconductor layer 103 during the process is prevented. This prevents film thinning and oxidation caused by plasma and etching materials during etching. This can improve the reliability of the thin film transistor 170.

[0154] Next, it is preferable to carry out a heat treatment at 200°C to 600°C, typically 300°C to 500°C. Here, the material is placed in a furnace and heat treated at 350°C for 1 hour in a nitrogen atmosphere. This heat treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal film. This releases the strain that inhibits carrier movement, so the heat treatment (including optical annealing) The timing of the heat treatment is important. There are no particular limitations as long as it is after the formation of the single crystal film, and it may be performed, for example, after the formation of the pixel electrode.

[0155] In the fifth photolithography step, the first electrode 105a and the second electrode The second terminal 122 made of the same material as 105b is left in the terminal portion. Electrically connected to the source wiring (the source wiring including the first electrode 105a and the second electrode 105b). It continues.

[0156] In addition, in the terminal portion, the connection electrode 120 is formed through a contact hole formed in the gate insulating film. It is directly connected to the first terminal 121 of the terminal portion through the The source wiring or drain wiring of the thin film transistor of the driving circuit is formed through the same process as described above. The wiring and the gate electrode are directly connected.

[0157] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a photomask, the number of photomasks can be reduced, simplifying the process and reducing costs. It is possible to streamline the process.

[0158] Next, the resist mask 131 is removed, and the protective insulating layer 10 covering the thin film transistor 170 is removed. The protective insulating layer 107 is formed by a silicon nitride film obtained by a sputtering method or the like, an oxide film, or the like. silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum nitride film, oxynitride film A single layer such as an aluminum oxide film or a tantalum oxide film or a laminate of these may be used. In some thin film transistors of the driving circuit, the protective insulating layer 107 is This serves as a gate insulating layer on which the second gate electrode is formed. The protective insulating layer 107 is a second gate insulating layer having a thickness of 50 to 400 nm. and the channel protection layer is made to have a total thickness approximately equal to the thickness of the first gate insulating film. The gate voltage can be applied from the upper and lower gate electrodes. When a silicon oxynitride film or a silicon nitride film is used as the layer 107, a protective insulating film is formed. After the formation of the layer 107, impurities such as mobile ions of sodium may be attached for some reason. It is possible to block the diffusion and penetration into the oxide semiconductor.

[0159] Next, a sixth photolithography step is performed to form a resist mask, and a protective insulating layer 1 A contact hole 125 reaching the second electrode 105b is formed by etching in step 07. Also, a contact hole 127 reaching the second terminal 122 is formed by etching here. The contact hole 126 reaching the connection electrode 120 can also be formed using the same resist mask. A cross-sectional view at this stage is shown in Figure 10(B).

[0160] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with a hydrochloric acid solution. However, etching of ITO in particular Residues tend to be generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0161] Next, a seventh photolithography step is performed to form a resist mask and apply etching. The unnecessary portions are removed to form the pixel electrode 110. In the process, the driving circuit uses the same material as the pixel electrode 110 for a part of the circuit, An electrode layer (back gate electrode) for controlling the threshold voltage is formed on the oxide semiconductor layer. The thin film transistor having a back gate electrode is the same as that shown in FIG. Therefore, detailed explanations will be omitted here.

[0162] In this seventh photolithography step, the gate insulating layer 10 in the capacitance section 2 and the protective insulating layer 107 as dielectrics, the capacitor wiring 108 and the pixel electrode 110 form a storage capacitor. In this case, the gate insulating layer 102 and the protective insulating layer 107 are used as dielectrics. In the example shown, the storage capacitor is formed by the capacitor wiring 108 and the pixel electrode 110, but this is not particularly limited. An electrode made of the same material as the source electrode or drain electrode is provided above the capacitance wiring. The electrode, the capacitance wiring, and the gate insulating layer 102 between them are configured as a dielectric. A storage capacitor may be formed and its electrode may be electrically connected to the pixel electrode.

[0163] In the seventh photolithography step, the first terminal and the second terminal are formed by resist. The transparent conductive films 128 and 129 formed on the terminal portions are left covered with a mask. 8 and 129 are electrodes or wiring used for connection with the FPC. The transparent conductive film 128 formed on the connected connection electrode 120 is connected to the input terminal of the gate wiring. The transparent conductive film 1 formed on the second terminal 122 serves as a terminal electrode for connection. Reference numeral 29 denotes a connection terminal electrode that functions as an input terminal for the source wiring.

[0164] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The top view at this stage corresponds to Figure 14.

[0165] 15(A1) and 15(A2) are top views of the gate wiring terminal portion at this stage. The cross-sectional views are shown in Fig. 15(A1) and Fig. 15(A2) along the line C1-C2. In FIG. 15(A1), a transparent insulating film formed on the protective insulating film 154 The conductive film 155 is a terminal electrode for connection that functions as an input terminal. ), the terminal portion includes a first terminal 151 made of the same material as the gate wiring, and a source The gate insulating layer 152 is formed between the gate electrode 153 and the gate wiring 154. The connection electrode 153 and the transparent conductive film 155 are electrically connected to each other. The electrodes are in direct contact with each other through contact holes provided in the electrodes, thereby providing electrical continuity.

[0166] 15(B1) and 15(B2) are a top view and a cross-sectional view of a source wiring terminal portion. Also, FIG. 15(B1) is taken along the line D1-D2 in FIG. 15(B2). In FIG. 15(B1), a transparent conductive film formed on the protective insulating film 154 is The conductive film 155 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, an electrode 156 made of the same material as the gate wiring is connected to the source wiring. The electrode overlaps the second terminal 150 to which it is electrically connected via a gate insulating layer 152. The electrode 156 is not electrically connected to the second terminal 150. For example, by setting the potential to floating, GND, 0V, etc., noise can be reduced. A capacitance for preventing static electricity or a capacitance for preventing static electricity can be formed. 0 is electrically connected to the transparent conductive film 155 via the protective insulating film 154.

[0167] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0168] In this way, seven photolithography processes were carried out using seven photomasks to create the bottom A pixel having a thin film transistor 170 which is a gate-type n-channel thin film transistor. The thin film transistor and storage capacitor can be completed. By arranging the pixels in a matrix corresponding to the active matrix type, For the sake of convenience, the present specification will discuss such a substrate. Such a substrate is called an active matrix substrate.

[0169] In addition, the connection electrodes are formed using the same material as the pixel electrodes, and the gate wiring and source wiring or drain wiring are When the structure is to be electrically connected to the drain wiring, a third photolithography process is performed. Since six photolithography steps can be omitted, six photomasks are used. a second thin film transistor, which is a bottom gate n-channel thin film transistor; The carrying capacity can be completed.

[0170] In addition, when the material of the second gate electrode is made different from the material of the pixel electrode as shown in FIG. 1(B), In this case, one photolithography step is added, and one photomask is added.

[0171] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0172] Furthermore, this embodiment is not limited to the pixel configuration of FIG. 14, and examples of top views different from those of FIG. This is shown in Figure 16. In Figure 16, no capacitance wiring is provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel. In this example, a storage capacitor is formed by stacking a protective insulating film and a gate insulating layer therebetween. The third terminal connected to the wiring and the capacitance wiring can be omitted. 14. The same parts as those in FIG. 14 will be described using the same reference numerals.

[0173] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0174] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0175] In addition, by increasing the normal vertical sync frequency by 1.5 times or more, preferably by 2 times or more, the video characteristics will be improved. A driving technique called double speed driving may be used to improve the above.

[0176] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0177] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0178] The n-channel transistor obtained in this embodiment is an In-Ga-Zn-O based non-single crystal The crystal film is used in the channel formation region and has good dynamic characteristics, so these driving technologies They can be combined.

[0179] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example, GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0180] The gate line driver circuit or source line driver circuit is formed by thin film transistors using oxide semiconductors. By forming a thin film transistor using a driving circuit, the manufacturing cost can be reduced. By directly connecting the gate electrode and the source wiring or the drain wiring, a contact hole is formed. Therefore, it is possible to provide a display device in which the number of driving circuits can be reduced and the area occupied by the driving circuits can be reduced.

[0181] Therefore, this embodiment makes it possible to provide a display device with high electrical characteristics and high reliability at low cost. It is possible.

[0182] This embodiment mode can be freely combined with embodiment mode 1, embodiment mode 2, or embodiment mode 3. It can be adjusted.

[0183] (Embodiment 5) In this embodiment, an example of electronic paper will be shown as a semiconductor device.

[0184] FIG. 17 shows an active matrix type electronic device as an example of a semiconductor device different from a liquid crystal display device. The thin film transistor 581 used in the pixel portion of the semiconductor device is It can be fabricated in the same manner as the thin film transistor of the pixel portion shown in the fourth embodiment, and is an In-Ga-Zn-O system The thin film transistor includes a non-single crystal film as a semiconductor layer. In this way, the pixel section and the driver circuit can be fabricated on the same substrate, reducing the manufacturing cost. Child paper can be realized.

[0185] The electronic paper in Figure 17 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0186] The thin film transistor 581 is a thin film transistor with a bottom gate structure, and the source electrode layer The drain electrode layer is formed on the first electrode layer 587 and the insulating layers 583, 584, and 585. The first electrode layer 587 and the second electrode layer 588 are in contact with each other and electrically connected. The cavity has a black area 590a and a white area 590b, and is filled with liquid around it. A spherical particle 589 containing a tee 594 is provided between a pair of substrates 580, 596, and the spherical particle The surroundings of the shaped particle 589 are filled with a filler 595 such as a resin (see FIG. 17).

[0187] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, also known as electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, auxiliary lights are not required. It consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the , a semiconductor device with a display function (simply a display device, or a semiconductor device equipped with a display device) from a radio wave source Even if the device (also called the body device) is moved away, the displayed image can be saved. become.

[0188] By using the TFT shown in the first embodiment, etc., the manufacturing cost of the semiconductor device can be reduced. Therefore, electronic paper can be produced.

[0189] This embodiment may be appropriately combined with the configuration described in the first or second embodiment. It is possible to implement.

[0190] (Embodiment 6) In this embodiment mode, a light-emitting display device is shown as an example of a semiconductor device. Here, a light-emitting element that uses electroluminescence is used as the element. Light-emitting devices that utilize electroluminescence are either organic or inorganic compounds. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. It's been discovered.

[0191] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0192] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0193] FIG. 18 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0194] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The n-type semiconductor uses an oxide semiconductor layer (In-Ga-Zn-O based non-single crystal film) in the channel formation region. 1 shows an example in which two channel-type transistors are used in one pixel.

[0195] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408 .

[0196] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0197] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0198] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input. In other words, the driving transistor 6402 is in the linear region when it is on. The driving transistor 6402 is operated in the linear region, so when it is in the on state, applies a voltage higher than the voltage of the power supply line 6407 to the gate of the driving transistor 6402. When the driving transistor 6402 is in an on state (power supply line A voltage equal to or higher than the voltage + Vth of the switching transistor 6401 is applied.

[0199] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By using the same pixel configuration as in FIG. 18, it is possible to use the same pixel configuration as in FIG.

[0200] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0201] Note that the pixel configuration shown in Fig. 18 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0202] Next, the structure of the light emitting element will be explained with reference to FIGS. 19(A), 19(B), and 19(C). Here, the case where the driving TFT is the thin film transistor 170 shown in FIG. 1(B) is taken as an example. The cross-sectional structure of the pixel will be described with reference to FIGS. 19(A), 19(B), and 19(C). The driving TFTs 7001, 7011, and 7021 used in the semiconductor device of the embodiment It can be fabricated in the same manner as the thin film transistor 170 shown in FIG. 1, and an In-Ga-Zn-O based non-single crystal film The thin film transistor has excellent electrical properties and includes a semiconductor layer.

[0203] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure in which light is emitted from the side surface. The present invention can also be applied to a light emitting element with an injection structure.

[0204] A light emitting element with a top emission structure will be described with reference to FIG.

[0205] In FIG. 19A, the driving TFT 7001 is the thin film transistor 170 shown in FIG. 1B. 7 is a cross-sectional view of a pixel when light emitted from a light-emitting element 7002 exits to the anode 7005 side. In FIG. 19A, a cathode 7003 of a light-emitting element 7002 and a driving TFT 7001 are They are electrically connected, and a light-emitting layer 7004 and an anode 7005 are stacked in this order on a cathode 7003. The cathode 7003 can be made of various conductive films that have a small work function and reflect light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers stacked. When it is made up of multiple layers, the cathode 7003 An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on top of each other in this order. It is not necessary to provide all of these layers. The insulating layer is formed using a conductive material, such as indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide containing titanium dioxide, indium oxide containing titanium dioxide, Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc A light-transmitting conductive film such as an indium tin oxide film or an indium tin oxide film containing silicon oxide is formed. You can use it.

[0206] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 19(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0207] Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is the cathode 7003. It is preferable to form them from the same material because this simplifies the process.

[0208] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. 011 is the thin film transistor 170 shown in FIG. 1A, and the light emitted from the light-emitting element 7012 19(B) shows a cross-sectional view of a pixel when light emitted from the driving A light-emitting element is formed on a light-transmitting conductive film 7017 electrically connected to the active TFT 7011. A cathode 7013 is formed on the cathode 7012, and a light-emitting layer 7014 and an anode 70 are formed on the cathode 7013. In addition, when the anode 7015 is transparent, a transparent insulating film 15 is formed on the anode 7015 so as to cover the anode. As shown in FIG. 7, a shielding film 7016 for reflecting or blocking light may be formed. 13, as in the case of FIG. 19(A), various conductive materials with small work functions can be used. However, the film thickness should be such that light can be transmitted (preferably 5 nm to 3 For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013. The light-emitting layer 7014 can be formed as a single layer, as in FIG. The anode may be formed of a single layer or a plurality of layers stacked together. 7015 does not need to transmit light, but as in FIG. 19(A), it is a conductive material having light-transmitting properties. The shielding film 7016 can be formed using a material such as a metal that reflects light. For example, a resin containing a black pigment can be used. You can also be there.

[0209] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 19B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0210] Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is the cathode 7013. It is preferable to form them from the same material because this simplifies the process.

[0211] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 is formed using a light-transmitting conductive material, similar to FIG. 19(A). It is possible.

[0212] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 19C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0213] Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is a conductive film 7027 It is preferable to form the gate electrode from the same material as the gate electrode because this simplifies the process. The second gate electrode provided on the compound semiconductor layer is made of the same material as the conductive film 7027 and the cathode 7023. By using this method to stack the layers, the process can be simplified and the wiring resistance can be reduced. This can be preferably reduced.

[0214] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0215] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which a light emitting element is connected is shown, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may also be such that FT is connected.

[0216] Note that the semiconductor device described in this embodiment mode has the same structure as that shown in FIGS. The present invention is not limited to the above-described configuration, and various modifications based on the disclosed technical idea are possible. do.

[0217] Next, the upper surface and the lower surface of a light-emitting display panel (also referred to as a light-emitting panel), which corresponds to one mode of a semiconductor device, The cross section will be explained using Fig. 21(A) and Fig. 21(B). Fig. 21(A) shows the first The thin film transistor and the light emitting element formed on the substrate are sandwiched between the second substrate and the substrate by a sealing material. 21(B) is a top view of the panel sealed by the HI in FIG. 21(A). This corresponds to a cross-sectional view.

[0218] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0219] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 21B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0220] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O based non-single crystal films as semiconductor layers. The highly reliable thin film transistor described in Embodiment 1 can be applied. In addition, the thin film transistor 4509 is a thin film transistor having a semiconductor layer as shown in Embodiment 1 and FIG. The gate electrodes are located above and below the gate electrode.

[0221] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0222] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0223] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0224] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0225] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0226] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film.

[0227] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0228] The second substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In that case, use a glass plate, plastic plate, polyester film or acrylic A light-transmitting material such as a film is used.

[0229] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used.

[0230] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0231] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A single crystal semiconductor substrate or a polycrystalline semiconductor film is formed on an insulating substrate. Alternatively, the signal line driver circuit may be implemented as a drive circuit formed by a thin film. Alternatively, only a part of the scanning line driver circuit or only a part of the scanning line driver circuit may be separately formed and mounted. This embodiment is not limited to the configurations of FIGS. 21(A) and 21(B).

[0232] A light-emitting display device in which the manufacturing cost is reduced by using the TFT described in Embodiment 1 etc. (Display panel) can be manufactured.

[0233] This embodiment may be appropriately combined with the configuration described in the first or second embodiment. It is possible to implement.

[0234] (Embodiment 7) In this embodiment mode, a top view and a cross section of a liquid crystal display panel, which corresponds to one mode of a semiconductor device, are shown. This will be explained with reference to Fig. 20(A1) and Fig. 20(B). Fig. 20(A1) shows the first substrate 4 The In-Ga-Zn-O based non-single crystal film formed on 001 as shown in the first embodiment is The thin film transistors 4010 and 4011 and the liquid crystal element 4013 are formed as layers on the second substrate. 20 is a top view of the panel sealed between the plate 4006 and the sealing material 4005. (B) corresponds to a cross-sectional view at MN in FIG. 20(A1).

[0235] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0236] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 20(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0237] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 20B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4022 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0238] The thin film transistors 4010 and 4011 are made of an In-Ga-Zn-O based non-single crystal film as a semiconductor layer. The thin film transistor described in Embodiment 1 can be applied. The transistor 4011 is a thin film transistor having a back gate electrode shown in FIG. 2(A) of the second embodiment. It is equivalent to a transistor.

[0239] The pixel electrode 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 400. The pixel electrode 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode 4030 and the counter electrode layer 4031 are formed corresponds to the liquid crystal element 4013. The insulating layers 4032 and 4033 functioning as alignment films are provided on the insulating layer 4031. A liquid crystal layer 4008 is sandwiched between 4032 and 4033 .

[0240] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0241] 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode layer 4031 A spherical spacer may be used. The counter electrode layer 4031 is , which is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 403 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 400 to the common potential line. Include in 5.

[0242] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs to It is optically isotropic, requiring no alignment treatment, and has little viewing angle dependency. stomach.

[0243] Although this embodiment is an example of a transmissive liquid crystal display device, a transflective liquid crystal display device may also be used. It can also be applied to a liquid crystal display device.

[0244] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. The colored layer and the electrode layer used for the display element are provided in this order, but the polarizing plate may be provided on the inner side of the substrate. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. It can be set appropriately depending on the material and manufacturing process conditions. A light-shielding film may be provided.

[0245] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the thin film transistor obtained in the first embodiment, a protective film or The insulating layer 4020 and the insulating layer 4021 are covered with insulating layers that function as planarizing insulating films. The protective film also prevents contamination by organic matter, metals, water vapor, and other polluting impurities floating in the air. The protective film is formed by sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitride A single layer or multilayer of an aluminum film, an aluminum oxynitride film, or an aluminum nitride oxide film In this embodiment, an example in which the protective film is formed by sputtering is shown. The method is not limited to this, and may be formed by various methods such as plasma CVD. In this case, this protective film functions as a second gate insulating layer, and a backgate is formed on the second gate insulating layer. The thin film transistor includes a gate.

[0246] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping

[0247] In addition, an insulating layer is formed as the second layer of the protective film. Then, a silicon nitride film is formed by sputtering. When a silicon nitride film is used as a protective film, Mobile ions such as thorium penetrate into the semiconductor region and change the electrical properties of the TFT. This second insulating layer also functions as a second gate insulating layer in part of the drive circuit. It functions as a marginal layer.

[0248] Therefore, when approximately the same gate voltage is applied to the oxide semiconductor layer from above and below, the second gate If the first insulating layer is a stack of layers of different materials, the first gate insulating layer is also a stack of layers of different materials. In this embodiment, in the driving circuit, A first gate insulator provided on a first gate electrode of a thin film transistor having a back gate The layer is a laminate of a silicon nitride film and a silicon oxide film, and the total film thickness is approximately the same as that of the insulating layer 4020. Do so.

[0249] After forming the protective film, the semiconductor layer may be annealed (at 300°C to 400°C). In addition, the back gate is formed after the protective film is formed.

[0250] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0251] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0252] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, The semiconductor layer may be annealed (at 300°C to 400°C) at the same time as the step of annealing. By combining the firing process of the edge layer 4021 with the annealing of the semiconductor layer, semiconductor devices can be efficiently manufactured. It becomes possible to do this.

[0253] The pixel electrode 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, acid Indium tin oxide containing titanium dioxide, indium tin oxide (hereinafter referred to as ITO), Translucent conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide Conductive materials can be used.

[0254] The pixel electrode 4030 and the counter electrode layer 4031 are made of a conductive polymer ( The conductive composition may be used to form the conductive layer. The pixel electrode has a sheet resistance of 10000Ω / □ or less and a light transmittance of 550nm. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0255] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0256] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0257] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode 403 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 401. The source electrode layer and the drain electrode layer are formed of the same conductive film as the source electrode layer and the drain electrode layer of the first transistor.

[0258] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0259] In addition, in FIG. 21(A1) and FIG. 21(A2), a signal line driver circuit 4003 is separately formed. 10, an example in which the first substrate 4001 is mounted is shown, but this embodiment is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or Alternatively, only a part of the scanning line driving circuit may be separately formed and mounted.

[0260] FIG. 22 shows a liquid crystal display module constructed as a semiconductor device using a TFT substrate 2600. An example is shown.

[0261] FIG. 22 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604, a colored layer 2605, and a polarizing plate 2606 are provided to form a display area. The coloring layer 2605 is necessary for color display. In the case of the RGB system, it contains red, green, A colored layer corresponding to each color of blue is provided for each pixel. On the outer side of the substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and the circuit board 2612 is , and connected to the wiring circuit section 2608 of the TFT substrate 2600 by a flexible wiring substrate 2609. It also incorporates external circuits such as a control circuit and a power supply circuit. The liquid crystal layer may be laminated with a retardation plate interposed therebetween.

[0262] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid Crystal Crystal mode, AFLC (AntiFerroelectric Liquid Liquid crystals such as LC (LCD) can be used.

[0263] By using the TFT shown in the first embodiment, etc., the manufacturing cost of the semiconductor device can be reduced. A liquid crystal display panel having such a structure can be manufactured.

[0264] This embodiment is applicable to the configuration described in the first, second, or third embodiment. It is possible to carry out any combination of these.

[0265] (Embodiment 8) The semiconductor device according to the disclosed invention can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), Examples include large game machines such as small game machines, mobile information terminals, sound reproduction devices, and pachinko machines. can be.

[0266] FIG. 23A shows an example of a mobile information terminal device 9200. 200 has a built-in computer and is capable of performing various data processing. As a portable information terminal device 9200 such as a PDA (Personal Digital Assistant) l Assistance).

[0267] The mobile information terminal device 9200 is composed of two housings, a housing 9201 and a housing 9203. The housing 9201 and the housing 9203 are foldably connected to each other at a connecting portion 9207. A display unit 9202 is incorporated in a housing 9201, and a keyboard is incorporated in a housing 9203. Of course, the configuration of the portable information terminal device 9200 is not limited to the above. However, as long as the device has a structure including at least a thin film transistor having a back gate electrode, Other auxiliary equipment may be provided as appropriate. By forming a pixel portion with a thin film transistor having high electrical characteristics, the manufacturing cost can be reduced. A portable information terminal device having the above can be realized.

[0268] 23B shows an example of a digital video camera 9500. The camera 9500 has a display unit 9503 built into a housing 9501, and various operation units. The configuration of the digital video camera 9500 is not particularly limited, and at least Any of these may be configured to include a thin film transistor having a back gate electrode. The driving circuit and the pixel section can be formed on the same substrate. This reduces manufacturing costs and enables the development of digital devices with thin film transistors with high electrical properties. A video camera can be realized.

[0269] FIG. 23C shows an example of a mobile phone 9100. The mobile phone 9100 has a housing. It consists of two housings, a body 9102 and a housing 9101, and can be folded by a connecting part 9103. The housing 9102 is connected to the display unit 9104 so as to be foldable. The housing 9101 is provided with operation keys 9106. is not particularly limited, and includes at least a thin film transistor having a back gate electrode. It is sufficient if other auxiliary equipment is provided on the same board. By forming the driver circuit and pixel section, manufacturing costs are reduced, and thin film transistors with high electrical properties are used. It is possible to realize a mobile phone having a transistor.

[0270] FIG. 23(D) shows an example of a portable computer 9400. The device 9400 includes a housing 9401 and a housing 9404 that are connected in an openable and closable manner. The display unit 9402 is incorporated in the device 01, and the housing 9404 is equipped with a keyboard 9403 and the like. The configuration of the computer 9400 is not particularly limited, and at least the back gate voltage It is sufficient if the device has a thin film transistor with a polarity, and other accessories are provided as appropriate. By forming the driver circuit and the pixel portion on the same substrate, the manufacturing cost can be reduced. This reduces costs and enables the realization of a computer having thin film transistors with excellent electrical properties.

[0271] FIG. 24(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0272] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display unit 9607 for displaying information output from 9610 may be provided.

[0273] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0274] FIG. 24B shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0275] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0276] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0277] FIG. 25(A) shows an example of a mobile phone 1000 different from the mobile phone of FIG. 23(C). The mobile phone 1000 includes a display unit 1002 built into a housing 1001, Operation buttons 1003, external connection port 1004, speaker 1005, microphone 1006, etc. It is equipped with:

[0278] The mobile phone 1000 shown in FIG. 25A displays a screen by touching the display unit 1002 with a finger or the like. You can input information. You can also make a call or send an email using the display. This can be done by touching 1002 with a finger or the like.

[0279] The screen of the display unit 1002 has three main modes. The first is a mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines the display mode and the input mode.

[0280] For example, when making a call or creating an email, the display unit 1002 is used for inputting characters. In this case, you can input characters displayed on the screen. In this case, it is possible to display a keyboard or number buttons on most of the screen of the display unit 1002. preferable.

[0281] The mobile phone 1000 also includes a sensor for detecting tilt, such as a gyro or acceleration sensor. By providing a detection device having the above, the orientation (portrait or landscape) of the mobile phone 1000 can be determined, The screen display on the display unit 1002 can be automatically switched.

[0282] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. The type of image displayed on the display unit 1002 can be selected by operating the operation button 1003. For example, the image signal to be displayed on the display unit can be switched by If the data is text data, the mode switches to display mode, and if the data is text data, the mode switches to input mode.

[0283] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays the If there is no input by touch operation on the display unit 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0284] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0285] FIG. 25B is also an example of a mobile phone. The mobile phone in FIG. 25B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9421. An operation button 9422, an external input terminal 9423, a microphone 9424, a speaker 9405, and The communication device 9420 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9420 having a telephone function in the two directions indicated by the arrows. Therefore, the display device 9410 and the communication device 9420 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9420 can be attached to each other along their long axes. When only the function is required, the display device 9410 is removed from the communication device 9420, and the display device The communication device 9420 and the display device 9410 can be used in wireless communication. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry.

[0286] (Embodiment 9) Here, a display device having a thin film transistor in which a wiring and an oxide semiconductor layer are in contact with each other is described. An example is shown in Figure 26. In Figure 26, the same parts as in Figure 2(A) are designated by the same reference numerals. I will explain.

[0287] The first thin film transistor 480 shown in FIG. 26 is a thin film transistor used in a driving circuit. A first wiring 409 and a second wiring 410 are provided in contact with the first oxide semiconductor layer 405. The first thin film transistor 480 is provided under the oxide semiconductor layer 405. The first gate electrode 401 and the channel protection layer 418 in contact with the first oxide semiconductor layer 405 an electrode 470 serving as a second gate electrode above the first oxide semiconductor layer 405; It has.

[0288] The second thin film transistor 481 is a bottom gate thin film transistor having a channel protection layer. a second channel protection layer 419 in contact with the second oxide semiconductor layer 407; In this example, a line 410 and a third wiring 411 are provided.

[0289] In the first thin film transistor 480 and the second thin film transistor 481, the first oxide The semiconductor layer 405 is connected to the first wiring 409, the second wiring 410, and the second oxide semiconductor. The contact areas between the conductor layer 407 and the second wiring 410 and the third wiring 411 are formed by plasma treatment. In this embodiment, before forming a conductive film to be a wiring, The oxide semiconductor layer (in this embodiment, an In-Ga-Zn-O based non-single-crystal film) is grown in an argon atmosphere. Plasma treatment is carried out under atmospheric pressure.

[0290] The plasma treatment may be performed using nitrogen, helium, or the like instead of an argon atmosphere. It may be performed in an argon atmosphere to which oxygen, hydrogen, N2O, etc. have been added. The treatment may be carried out in an atmosphere containing Cl2, CF4, etc.

[0291] The first oxide semiconductor layer 405 and the second oxide semiconductor layer 40 are modified by the plasma treatment. 7, a conductive film is formed to form a first wiring 409, a second wiring 410, and a third wiring 411. By this, the first oxide semiconductor layer 405, the second oxide semiconductor layer 407 and the first wiring 409, the contact resistance with the second wiring 410, and the third wiring 411 can be reduced.

[0292] In the semiconductor device of this embodiment, the wiring and the oxide semiconductor layer are in contact with each other. The number of steps can be reduced compared to the first embodiment.

[0293] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0294] 100 boards 101 gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 107 Protective insulation layer 108 Capacitance wiring 109 Oxide semiconductor film 110 pixel electrode 111 Second oxide semiconductor film 120 connecting electrode 121 First terminal 122 Second terminal 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Transparent conductive film 129 Transparent conductive film 131 Resist mask 132 Conductive film 133 Channel Protection Layer 150 Second terminal 151 First terminal 152 Gate insulating layer 153 Connecting electrode 154 Protective insulating film 155 Transparent conductive film 156 Electrode 170 Thin-Film Transistor 400 boards 401 Gate electrode 402 gate electrode 403 First gate insulating layer 404 Contact Hole 405 Oxide semiconductor layer 406a, 406b Source region or drain region 407 Oxide semiconductor layer 408a, 408b n + layer 409 Wiring 410 Wiring 411 Wiring 412 Insulating layer 418 Channel Protection Layer 419 Second Channel Protection Layer 430 Thin Film Transistor 431 Thin-film transistor 440 board 441 Gate electrode 442 gate electrode 443 Gate insulating layer 444 Contact Hole 445 Oxide semiconductor layer 447 Oxide semiconductor layer 449 Wiring 450 Wiring 451 Wiring 452 Protective layer 453 Connection Wiring 455 n+ layer 457 n+ layer 458 Channel Protection Layer 459 Channel Protection Layer 460 Thin Film Transistor 461 Thin-Film Transistor 480 Thin Film Transistors 481 Thin-Film Transistors

Claims

[Claim 1] a first gate electrode on the insulating surface; a first insulating layer above the first gate electrode; an oxide semiconductor layer above the first insulating layer; a second insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a source electrode or a drain electrode above the oxide semiconductor layer; a third insulating layer having a region covering the source electrode or the drain electrode; a second gate electrode above the third insulating layer; The third insulating layer has a region in contact with the second insulating layer.

Images