High-speed sampler

Abstract

To provide a regeneration circuit which increases a speed of a sampler and increases sensitivity of the sampler, and a method.SOLUTION: A regeneration circuit 150 includes a first transistor 250 coupled to an input 272 of a second inverting circuit 270, and a second transistor 255 coupled to an input 262 of a first inverting circuit 260, a third transistor 610 and a fourth transistor 620. A gate of the first transistor and a gate of the third transistor are coupled to a first input 160, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input 165. The regeneration circuit further includes a third switch 630 and a fourth switch 645. The third switch and the third transistor are coupled in series between a rail 280 and the second transistor, and the fourth switch and the fourth transistor are coupled in series between the rail and the second transistor.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of non-provisional patent application Ser. No. 17 / 805,211, filed with the United States Patent and Trademark Office on June 2, 2022, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes. [Background technology]

[0002] Field Aspects of the present disclosure relate generally to samplers, and more particularly to high-speed samplers.

[0003] background

[0003] High-speed samplers can be used in high-speed serializer / deserializer (SerDes) applications. For example, a sampler can be used in a high-speed SerDes to sample a high-speed signal received by a receiver. The sampler can include a regeneration circuit that provides regenerative feedback to the sampler to quickly capture data bits from the received signal. It is desirable to increase the speed of the sampler to sample signals at higher data rates and / or increase the sensitivity of the sampler to capture data bits from small signals. Summary of the Invention

[0004]

[0004] The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This "Summary" is not an extensive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the "Detailed Description" presented later.

[0005]

[0005] A first aspect relates to a regeneration circuit. The regeneration circuit includes a first inverting circuit having an input and an output, and a second inverting circuit having an input and an output. The regeneration circuit also includes a first transistor coupled to the input of the second inverting circuit, the first transistor having a gate coupled to the first input, and a second transistor coupled to the input of the first inverting circuit, the second transistor having a gate coupled to the second input. The regeneration circuit further includes a third transistor having a gate coupled to the first input, and a fourth transistor having a gate coupled to the second input. The regeneration circuit further includes a first switch, where the first switch and a third transistor are coupled in series between the first rail and the first transistor, and a second switch, where the second switch and a fourth transistor are coupled in series between the first rail and the second transistor.

[0006] A second aspect relates to a regeneration circuit. The regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, the first transistor having a gate coupled to the first input, and a second transistor coupled to the input of the first inverting circuit, the second transistor having a gate coupled to the second input. The regeneration circuit also includes a pull-up circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit, and a pull-down circuit coupled to the input of the first inverting circuit and the input of the second inverting circuit.

[0007]

[0007] A third aspect relates to a method of operating a regeneration circuit of a sampler, the regeneration circuit including a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, a second transistor coupled to the input of the first inverter circuit, a third transistor, and a fourth transistor. The method includes disabling regenerative feedback of the first inverter circuit and the second inverter circuit during a reset phase. The method also includes enabling regenerative feedback of the first inverter circuit and the second inverter circuit during a regeneration phase, driving a gate of the first transistor and a gate of the third transistor with a first voltage, driving a gate of the second transistor and a gate of the fourth transistor with a second voltage, and coupling the third transistor to the output of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit. [Brief explanation of the drawings]

[0008] [Figure 1] 1 illustrates an example of a sampler including an input circuit and a reproduction circuit according to certain aspects of the present disclosure. [Figure 2A]

[0009] 1 illustrates an exemplary implementation of an input circuit according to certain aspects of the present disclosure. [Figure 2B]

[0010] 1 illustrates an exemplary implementation of a regeneration circuit according to certain aspects of the present disclosure. [Figure 2C]

[0011] 1 illustrates another exemplary implementation of a regeneration circuit according to certain aspects of the present disclosure. [Figure 3A]

[0012] FIG. 4 is a timing diagram illustrating an example of a voltage output by an input circuit to a regeneration circuit, in accordance with certain aspects of the present disclosure. [Figure 3B]

[0013] FIG. 10 is a timing diagram illustrating another example of a voltage output by an input circuit to a regeneration circuit in accordance with certain aspects of the present disclosure. [Figure 4]

[0014] 1 illustrates an example of a regeneration circuit including a pull-up circuit in accordance with certain aspects of the present disclosure. [Figure 5A]

[0015] 1 illustrates an example of a regeneration circuit including a pull-down circuit in accordance with certain aspects of the present disclosure. [Figure 5B]

[0016] 1 illustrates another example of a regeneration circuit including a pull-down circuit in accordance with certain aspects of the present disclosure. [Figure 6]

[0017] 1 illustrates an example of a regeneration circuit including an input transistor that provides a pull-up path, in accordance with certain aspects of the present disclosure. [Figure 7]

[0018] 1 illustrates an exemplary implementation of an input transistor according to certain aspects of the present disclosure. [Figure 8]

[0019] 1 illustrates an exemplary implementation of a switch in a regeneration circuit in accordance with certain aspects of the present disclosure. [Figure 9A]

[0020] 1 illustrates an exemplary implementation of a first inverting circuit in a regeneration circuit according to certain aspects of the present disclosure. [Figure 9B]

[0021] 1 illustrates an exemplary implementation of a second inverting circuit in a regeneration circuit according to certain aspects of the present disclosure. [Figure 10]

[0022] 1 illustrates an exemplary implementation of a switch in an input circuit according to certain aspects of the present disclosure. [Figure 11]

[0023] 1 illustrates an example of a system in which certain aspects of the present disclosure may be used, according to certain aspects of the present disclosure. [Figure 12]

[0024] 1 is a flowchart illustrating a method of operating a regeneration circuit in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0025] The Detailed Description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The Detailed Description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010]

[0026] 1 illustrates an example of a sampler 110 according to certain aspects of the present disclosure. The sampler 110 may be used, for example, in a high-speed SerDes to sample an incoming data signal. The sampler 110 may also be referred to as a sense amplifier or by other terms. The sampler 110 includes an input circuit 120 and a recovery circuit 150. The input circuit 120 may also be referred to as an input stage or by other terms, and the recovery circuit 150 may also be referred to as a recovery stage, a latch (e.g., a cross-coupled latch), or by other terms.

[0011]

[0027] 1, input circuit 120 has a first input 130, a second input 135, a first output 140, and a second output 145. Regeneration circuit 150 has a first input 160, a second input 165, a first output 170, and a second output 175. The first input 160 of regeneration circuit 150 is coupled to the first input 140 of input circuit 120, and the second input 165 of regeneration circuit 150 is coupled to the second output 145 of input circuit 120.

[0012]

[0028] In this example, input circuit 120 is configured to receive a differential input signal (e.g., a differential data signal) including a first input voltage INP and a second input voltage INN. The first input voltage INP is received at first input 130, and the second input voltage INN is received at second input 135. The differential input signal may have a small differential voltage (i.e., a small difference between the first input voltage INP and the second input voltage INN) where the polarity of the differential voltage represents a bit value. In a SerDes example, sampler 110 may be integrated on a first chip coupled to a second chip via a link, and the sampler may receive the differential input signal from a transmitter on the second chip via the link.

[0013]

[0029] The input circuit 120 generates a first voltage DINT at a first output 140 and a second voltage NDINT at a second output 145 based on a first input voltage INP and a second input voltage INN. As described further below, the input circuit 120 is configured to set the first voltage DINT and the second voltage NDINT to a reset voltage (e.g., a supply voltage) during a reset phase and to change (e.g., discharge) the first voltage DINT and the second voltage NDINT at different rates based on the first input voltage INP and the second input voltage INN during a regeneration phase.

[0014]

[0030] The regeneration circuit 150 is configured to receive a first voltage DINT at a first input 160 and a second voltage NDINT at a second input 165. As described further below, during the regeneration phase, the regeneration circuit 150 is configured to convert the first voltage DINT and the second voltage NDINT into a differential output voltage using regeneration feedback. The differential output signal includes a first output voltage OUTP at a first output 170 and a second output voltage OUTN at a second output 175, with the polarity of the differential output voltage representing the captured (i.e., determined) bit value. It is desirable for the regeneration circuit 150 to quickly convert the first voltage DINT and the second voltage NDINT into a large differential output voltage (i.e., a large difference between the first output voltage OUTP and the second output voltage OUTN) during the regeneration phase to quickly determine the bit value for high-speed applications.

[0015]

[0031] The first output 170 and the second output 175 of the recovery circuit 150 may be coupled to a latch (not shown) configured to latch the captured bit values ​​from the sampler 110. The latch may include a set-reset (SR) latch or another type of latch.

[0016]

[0032] 2A illustrates an exemplary implementation of an input circuit 120 according to certain aspects. The input circuit 120 includes a first input transistor 210, a second input transistor 220, a first switch 230, a second switch 240, and a third switch 245. The second switch 240 is coupled between an upper rail 280 and the first input transistor 210, and the third switch 245 is coupled between the upper rail 280 and the second input transistor 220. The first input transistor 210 is coupled between the second switch 240 and a node 226, and the second input transistor 220 is coupled between the third switch 245 and the node 226. The first switch 230 is coupled between the node 226 and a lower rail 285. In one example, the upper rail 280 may provide a supply voltage VCC, and the lower rail 285 may be coupled to ground. Generally, the upper rail 280 is at a higher potential than the lower rail 285. The top rail 280 may also be referred to as a supply rail or by other terms.

[0017]

[0033] In the example shown in FIG. 2A , the first input transistor 210 is implemented with a first n-type field effect transistor (NFET), and the second input transistor 220 is implemented with a second NFET. It should be understood that the first input transistor 210 and the second input transistor 220 are not limited to NFETs and may be implemented with other types of transistors. In this example, a second switch 240 is coupled between an upper rail 280 and the drain of the first input transistor 210, and a first switch 230 is coupled between the source of the first input transistor 210 and a lower rail 285. The gate of the first input transistor 210 is coupled to the first input 130 of the input circuit 120 and thus receives the first input voltage INP. Also in this example, a third switch 245 is coupled between the upper rail 280 and the drain of the second input transistor 220, and the first switch 230 is coupled between the source of the second input transistor 220 and the lower rail 285. The gate of the second input transistor 220 is coupled to the second input 135 of the input circuit 120 and therefore receives the second input voltage INN.

[0018]

[0034] The first switch 230 has a control input 235 driven by a timing signal, the second switch 240 has a control input 242 driven by the timing signal, and the third switch 245 has a control input 247 driven by the timing signal. In one example, the first switch 230 is configured to be on when the timing signal is high and off when the timing signal is low, and each of the second switch 240 and the third switch 245 is configured to be on when the timing signal is low and off when the timing signal is high. In the example shown in FIG. 2A , the timing signal is a clock signal CLK. As used herein, a “clock signal” is a periodic signal that oscillates between a high logic state and a low logic state. In certain aspects, a high logic state (i.e., a logic state of one) may correspond to a voltage approximately equal to a supply voltage VCC, and a low logic state (i.e., a logic state of zero) may correspond to a voltage approximately equal to ground.

[0019]

[0035] As used herein, a "control input" of a switch is an input that controls the on / off state of the switch based on a signal (e.g., a voltage signal) at the control input. In examples where the switches are implemented with transistors, the control input is located at the gate of the transistor. In one example, the first switch 230 may be implemented using an NFET, and each of the second switch 240 and the third switch 245 may be implemented using a respective PFET. However, it should be understood that the present disclosure is not limited to this example.

[0020]

[0036] In this example, the first output 140 is coupled to a first node 222 between the second switch 240 and the first input transistor 210, and the second output 145 is coupled to a second node 224 between the third switch 245 and the second input transistor 220. As described above, the input circuit 120 outputs a first voltage DINT at the first output 140 and a second voltage NDINT at the second output 145. In the example of FIG. 1, the first output 140 is coupled to the drain of the first input transistor 210, and the second output 145 is coupled to the drain of the second input transistor 220.

[0021]

[0037] 2B shows an exemplary implementation of a regeneration circuit 150 according to certain aspects. In this example, the regeneration circuit 150 includes a first input transistor 250, a second input transistor 255, a first switch 290, a second switch 295, a first inverter circuit 260, and a second inverter circuit 270. As discussed further below, the first inverter circuit 260 and the second inverter circuit 270 are cross-coupled during the regeneration phase to provide regenerative feedback. As used herein, an "inverting circuit" is a circuit configured to invert a logic state (i.e., a logic level or logic value) at the input of the inverter circuit and output the inverted logic state at the output of the inverter circuit. The logic states can be represented by voltages, where a low voltage (e.g., near ground) can represent a logic state of zero and a high voltage (e.g., near a supply voltage) can represent a logic state of one. In certain aspects, an inverting circuit has a threshold voltage, such that when the voltage at the input of the inverting circuit falls below the threshold voltage, the output of the inverting circuit transitions from low to high, and when the voltage at the input of the inverting circuit exceeds the threshold voltage, the output of the inverting circuit transitions from high to low. Inverting circuits may also be referred to as inverters, inverting circuits, or other terms.

[0022]

[0038] The first inverting circuit 260 has an input 262, an output 264, a first supply terminal 266, and a second supply terminal 268. The second inverting circuit 270 has an input 272, an output 274, a first supply terminal 276, and a second supply terminal 278. The first supply terminal 266 of the first inverting circuit 260 and the first supply terminal 276 of the second inverting circuit 270 are coupled to an upper rail 280. The second supply terminal 268 of the first inverting circuit 260 and the second supply terminal 278 of the second inverting circuit 270 are coupled to a lower rail 285 (e.g., ground).

[0023]

[0039] A first switch 290 is coupled between an input 272 of the second inverter circuit 270 and an output 264 of the first inverter circuit 260, and a second switch 295 is coupled between the input 262 of the first inverter circuit 260 and an output 274 of the second inverter circuit 270. When the first switch 290 and the second switch 295 are turned on, the first inverter circuit 260 and the second inverter circuit 270 are cross-coupled, and the input 272 of the second inverter circuit 260 is coupled to the output 264 of the first inverter circuit 260 via the first switch 290, and the input 262 of the first inverter circuit 270 is coupled to the output 274 of the second inverter circuit 270 via the second switch 295. As described further below, the first switch 290 and the second switch 295 are turned on during the regeneration phase to enable regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270, and the first switch 290 and the second switch 295 are turned off during the reset phase to disable regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270. Each of the first switch 290 and the second switch 295 may be implemented using a respective transistor (e.g., a respective NFET), a respective transmission gate, or another type of switch.

[0024]

[0040] The first input transistor 250 is coupled between the input 272 of the second inverting circuit 270 and the lower rail 285. The gate of the first input transistor 250 is coupled to the first input 160 of the regeneration circuit 150. Thus, the gate of the first input transistor 250 is configured to receive a first voltage DINT (i.e., the first input signal to the regeneration circuit 150). In one example, the first input transistor 250 is configured to be turned on when the voltage DINT exceeds the threshold voltage of the first input transistor 250 and to be turned off when the voltage DINT falls below the threshold voltage of the first input transistor 250. In the example shown in FIG. 2B , the first input transistor 250 is implemented with an NFET, with the drain of the first input transistor 250 coupled to the input 272 of the second inverting circuit 270 and the source of the first input transistor 250 coupled to the lower rail 285. Additionally, a first switch 290 is coupled between the output 264 of the first inverting circuit 260 and the drain of the first input transistor 250. It should be understood that the first input transistor 250 may also be implemented using other types of transistors. In this example, the first output 170 is coupled to the output 264 of the first inverter circuit 260.

[0025]

[0041] The second input transistor 255 is coupled between the input 262 of the first inverting circuit 260 and the bottom rail 285. The gate of the second input transistor 255 is coupled to the second input 165 of the regeneration circuit 150. Thus, the gate of the second input transistor 255 is configured to receive a second voltage NDINT (i.e., the second input signal to the regeneration circuit 150). In one example, the second input transistor 255 is configured to be turned on when the voltage NDINT exceeds the threshold voltage of the second input transistor 255 and turned off when the voltage NDINT falls below the threshold voltage of the second input transistor 255. In the example shown in FIG. 2B , the second input transistor 255 is implemented with an NFET, with the drain of the second input transistor 255 coupled to the input 262 of the first inverting circuit 260 and the source of the second input transistor 255 coupled to the bottom rail 285. Additionally, a second switch 295 is coupled between the output 274 of the second inverting circuit 270 and the drain of the second input transistor 255. It should be understood that the second input transistor 255 may also be implemented using other types of transistors. In this example, the second output 175 is coupled to the output 274 of the second inverter circuit 270.

[0026]

[0042] 2B , the first switch 290 has a control input 292 driven by a timing signal, and the second switch 295 has a control input 297 driven by a timing signal (e.g., a clock signal CLK). In one example, the first switch 290 and the second switch 295 are configured to be on when the timing signal is high and off when the timing signal is low. Thus, in this example, when the first switch 230 of the input circuit 120 is on, the first switch 290 and the second switch 295 are on, and when the second switch 240 and the third switch 245 of the input circuit 120 are on, the first switch 290 and the second switch 295 are off. In examples where the first switch 290 and the second switch 295 are each implemented with a respective transistor, the control inputs 292 and 297 of each of the first switch 290 and the second switch 295 are located at the gates of the respective transistors. In one example, each of the first switch 290 and the second switch 295 may be implemented with a respective NFET.

[0027]

[0043] An exemplary operation of the sampler 110 will now be discussed in accordance with certain aspects.

[0028]

[0044] When a timing signal (e.g., clock signal CLK) is low, the sampler 110 is in a reset phase. In the reset phase, the first switch 230 of the input circuit 120 is turned off. As a result, the first switch 230 disconnects the first input transistor 210 and the second input transistor 220 of the input circuit 120 from the lower rail 285 (e.g., ground). The second switch 240 and the third switch 245 are turned on. As a result, the second switch 240 couples the first output 140 to the upper rail 280, and the third switch 245 couples the second output 145 to the upper rail 280. This causes the input circuit 120 to pull up the first output 140 and the second output 145 to the supply voltage VCC on the upper rail 280. Therefore, both the first voltage DINT input to the gate of the first input transistor 250 of the regeneration circuit 150 and the second voltage NDINT input to the gate of the second input transistor 255 of the regeneration circuit 150 are pulled up to VCC during the reset phase.

[0029]

[0045] Also during the reset phase, the first switch 290 and the second switch 295 of the regeneration circuit 150 are turned off. As a result, the regenerative feedback in the regeneration circuit 150 is disabled (i.e., the cross-coupling of the inverter circuits 260 and 270 is disconnected). In addition, because the voltages DINT and NDINT are both pulled up to the supply voltage VCC (assuming VCC is greater than the threshold voltage of the first input transistor 250 and the threshold voltage of the second input transistor 255), the first input transistor 250 and the second input transistor 255 of the regeneration circuit 150 are both turned on. As a result, the inputs 262 and 272 of the inverter circuits 260 and 270 are pulled low (e.g., to ground). This causes the outputs 264 and 274 of the inverter circuits 260 and 270 to be pulled high. In this example, the first output 170 and the second output 175 of the regeneration circuit 150 are also pulled high.

[0030]

[0046] When a timing signal (e.g., clock signal CLK) transitions from low to high, sampler 110 transitions to a recovery phase during which input circuit 120 senses a differential input signal (e.g., a differential data signal) at inputs 130 and 135 of input circuit 120. FIG. 3A shows an example of voltages DINT and NDINT during the recovery phase for the case where input voltage INP is higher than input voltage INN, which may represent a bit value of 1. In this example, the timing signal (e.g., clock signal CLK) transitions from low to high at time T1. Also in this example, first input transistor 250 and second input transistor 255 have the same threshold voltage 310 shown in FIG. 3.

[0031]

[0047] At time T1, the first switch 230 is turned on, and the second switch 240 and the third switch 245 are turned off. This allows the first input transistor 210 to pull down the voltage DINT based on the input voltage INP at the first input transistor 210, and the second input transistor 220 to pull down the voltage NDINT based on the input voltage INN at the second input transistor 220. In this example, the voltage DINT is pulled down (i.e., at a faster rate than the voltage NDINT because, in this example, the first input transistor 210 is driven by a higher voltage than the second input transistor 220 (i.e., INP>INN).

[0032]

[0048] At time T2, voltage DINT falls below threshold voltage 310, causing first input transistor 250 of regeneration circuit 150 to turn off. Because voltage NDINT is still above the threshold voltage at time T2, second input transistor 255 of regeneration circuit 150 is still on at time T2. Starting at time T2, the regenerative feedback of regeneration circuit 150 pulls first output 170 up and second output 175 down (e.g., pulls first output 170 toward supply voltage VCC and pulls second output 175 toward ground). The pull-up of first output 170 and the pull-down of second output 175 generate a differential output voltage at outputs 170 and 175, where output voltage OUTP is higher than output voltage OUTN, which may represent a bit value of 1.

[0033]

[0049] 3A shows the voltages DINT and NDINT when the input voltage INP is greater than the input voltage INN. FIG. 3B shows the voltages DINT and NDINT when the input voltage INN is greater than the input voltage INP. In this case, the voltage NDINT at the second output 145 of the input circuit 120 drops at a faster rate than the voltage DINT at the first output 140 of the input circuit 120 during the regeneration phase. As a result, the voltage NDINT falls below the threshold voltage 310 before the voltage DINT, causing the second input transistor 255 to turn off before the first input transistor 250. When this occurs, the regenerative feedback of the regeneration circuit 150 pulls the second output 175 up and the first output 170 down, resulting in a large differential output voltage where the output voltage OUTN is greater than the output voltage OUTP, which may represent a zero bit decision.

[0034]

[0050] In both cases, it is desirable for the reconstruction circuit 150 to quickly generate a large differential output voltage at outputs 170 and 175 during the reconstruction phase in order to quickly determine (i.e., capture) the bit value. A latch (e.g., an SR latch) coupled to outputs 170 and 175 of the reconstruction circuit 150 can latch the determined bit value as described above. When the timing signal transitions from high back to low, the sampler 110 re-enters the reset phase, resetting the sampler 110 for the next bit value.

[0035]

[0051] 2B , the first switch 290 and the second switch 295 are used to enable the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270 during the regeneration phase and to disable the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270 during the reset phase. The first switch 290 and the second switch 295 disable the regenerative feedback during the reset phase by disconnecting the cross-coupling of the first inverter circuit 260 and the second inverter circuit 270 when the first switch 290 and the second switch 295 are turned off. However, it should be understood that the present disclosure is not limited to this example. In general, the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270 can be enabled or disabled using one or more switches located at one or more locations within the regeneration circuit 150, and the one or more switches are controlled by a timing signal (e.g., the clock signal CLK).

[0036]

[0052] In this regard, FIG. 2C illustrates an exemplary implementation in which the regeneration circuit 150 includes a switch 296 coupled between the upper rail 280 and the power supply terminals 266 and 276 of the inverter circuits 260 and 270. In this example, the first switch 290 and the second switch 295 shown in FIG. 2B are omitted, and the output 264 of the first inverter circuit 260 is coupled to the first input transistor 250, and the output 274 of the second inverter circuit 270 is coupled to the second input transistor 255. The switch 296 may be implemented using a PFET and has a control input 298 driven by an inverse of a timing signal (e.g., the inverse clock signal CLKb). In this example, the switch 296 is configured to be turned off during the reset phase and turned on during the regeneration phase. Turning the switch 296 off during the reset phase removes power from the upper rail 280 to the inverter circuits 260 and 270, thereby disabling the regenerative feedback of the first inverter circuit 260 and the second inverter circuit 270. It should be understood that the present disclosure is not limited to the examples shown in FIGS. 2B and 2C.

[0037]

[0053] 4 illustrates an example in which the regeneration circuit 150 further includes a pull-up circuit 405, according to certain aspects. The pull-up circuit 405 is configured to provide an additional pull-up path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. The pull-up circuit 405 includes a first pull-up transistor 410 and a second pull-up transistor 420, according to certain aspects of the present disclosure.

[0038]

[0054] 4, first pullup transistor 410 is implemented with a first PFET, and second pullup transistor 420 is implemented with a second PFET. The source of first pullup transistor 410 is coupled to rail 280, the drain of first pullup transistor 410 is coupled to input 262 of first inverter circuit 260, and the gate of first pullup transistor 410 is coupled to output 264 of first inverter circuit 260. The source of second pullup transistor 420 is coupled to rail 280, the drain of second pullup transistor 420 is coupled to input 272 of second inverter circuit 270, and the gate of second pullup transistor 420 is coupled to output 274 of second inverter circuit 270.

[0039]

[0055] An exemplary operation of the pull-up circuit 405 will now be discussed in accordance with certain aspects.

[0040]

[0056] If the voltage DINT falls faster than the voltage NDINT during the regeneration phase (e.g., if INP>INN at inputs 130 and 135 of input circuit 120), first input transistor 250 turns off before second input transistor 255. This triggers the regenerative feedback of regeneration circuit 150 to pull up first output 170 and pull down second output 175. Because the gate of second pullup transistor 420 is coupled to second output 175, the pulldown of second output 175 turns on second pullup transistor 420. This causes second pullup transistor 420 to pull up input 272 of second inverter circuit 270 toward supply voltage VCC on rail 280, which helps second inverter circuit 270 drive output 274 of second inverter circuit 270 low. Because the output 274 of the second inverter circuit 270 is coupled to the second output 175, driving the output 274 of the second inverter circuit 270 low helps to pull down the second output 175 further, thereby increasing the regeneration gain of the regeneration circuit 150. Thus, in this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input 272 of the second inverter circuit 270 during the regeneration phase, which increases the regeneration gain.

[0041]

[0057] If voltage NDINT falls faster than voltage DINT during the regeneration phase (e.g., if INN > INP at inputs 130 and 135 of input circuit 120), second input transistor 255 turns off before first input transistor 250. This triggers the regenerative feedback of regeneration circuit 150, pulling second output 175 up and first output 170 down. Because the gate of first pullup transistor 410 is coupled to first output 170, the pulldown of first output 170 turns on first pullup transistor 410. This causes first pullup transistor 410 to pull up input 262 of first inverter circuit 260 toward supply voltage VCC on rail 280, which helps first inverter circuit 260 drive output 264 of first inverter circuit 260 low. Because the output 264 of the first inverter circuit 260 is coupled to the first output 170, driving the output 264 of the first inverter circuit 260 lower helps to pull down the first output 170 further, thereby increasing the regeneration gain of the regeneration circuit 150. Thus, in this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input 262 of the first inverter circuit 260 during the regeneration phase, which increases the regeneration gain.

[0042]

[0058] Thus, the pull-up circuit 405 is configured to provide an additional pull-up path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. The pull-up path is between the rail 280 and the input 272 of the second inverter circuit 270 when the voltage DINT falls faster than the voltage NDINT (e.g., when INP>INN), and the pull-up path is between the rail 280 and the input 262 of the first inverter circuit 260 when the voltage NDINT falls faster than the voltage DINT (e.g., when INN>INP).

[0043]

[0059] To further increase the regeneration gain of the regeneration circuit 150, a pull-down circuit can be added to the regeneration circuit 150. In this regard, FIG. 5A illustrates an example in which the regeneration circuit 150 further includes a pull-down circuit 505 according to certain embodiments. The pull-down circuit 505 is configured to provide an additional pull-down path during the regeneration phase, which increases the signal strength at the outputs 170 and 175 of the regeneration circuit 150, to increase the regeneration gain of the regeneration circuit 150. The pull-down circuit 505 can be used in combination with the pull-up circuit 405 to increase the regeneration gain, as described further below. The pull-down circuit 505 includes a first pull-down transistor 510 and a second pull-down transistor 520 according to certain embodiments of the present disclosure.

[0044]

[0060] 5A, the first pull-down transistor 510 is implemented with a first NFET, and the second pull-down transistor 520 is implemented with a second NFET. The drain of the first pull-down transistor 510 is coupled to the input 262 of the first inverter circuit 260, the source of the first pull-down transistor 510 is coupled to the lower rail 285 (e.g., ground), and the gate of the first pull-down transistor 510 is coupled to the input 272 and the first output 170 of the second inverter circuit 270. The drain of the second pull-down transistor 520 is coupled to the input 272 of the second inverter circuit 270, the source of the second pull-down transistor 520 is coupled to the lower rail 285, and the gate of the second pull-down transistor 520 is coupled to the input 262 and the second output 175 of the first inverter circuit 260. In other words, the first pull-down transistor 510 and the second pull-down transistor 520 are cross-coupled.

[0045]

[0061] An exemplary operation of the pull-down circuit 505 will now be discussed in accordance with certain aspects.

[0046]

[0062] If voltage DINT falls faster than voltage NDINT during the regeneration phase (e.g., if INP>INN at inputs 130 and 135 of input circuit 120), first input transistor 250 turns off before second input transistor 255. This triggers the regenerative feedback of regeneration circuit 150 to pull first output 170 up and pull second output 175 down. Because the gate of first pull-down transistor 510 is coupled to first output 170, the pull-up of first output 170 turns on first pull-down transistor 510. This causes first pull-down transistor 510 to pull down input 262 of first inverter circuit 260, which helps first inverter circuit 260 drive output 264 high. Because the output 264 of the first inverter circuit 260 is coupled to the first output 170, driving the output 264 of the first inverter circuit 260 high helps to further pull up the first output 170, thereby increasing the regeneration gain. Thus, in this case, the pull-down circuit 505 provides an additional pull-down path between the input 262 of the first inverter circuit 260 and the lower rail 285 (e.g., ground) during the regeneration phase, which increases the regeneration gain.

[0047]

[0063] If voltage NDINT falls faster than voltage DINT during the regeneration phase (e.g., if INN > INP at inputs 130 and 135 of input circuit 120), second input transistor 255 turns off before first input transistor 250. This triggers the regenerative feedback of regeneration circuit 150 to pull second output 175 up and pull first output 170 down. Because the gate of second pull-down transistor 520 is coupled to second output 175, the pull-up of second output 175 turns on second pull-down transistor 520. This causes second pull-down transistor 520 to pull down input 272 of second inverter circuit 270, which helps second inverter circuit 270 drive output 274 high. Because the output 274 of the second inverter circuit 270 is coupled to the second output 175, driving the output 274 of the second inverter circuit 270 high helps to further pull up the second output 175, thereby increasing the regeneration gain. Thus, in this case, the pull-down circuit 505 provides an additional pull-down path between the input 272 of the second inverter circuit 270 and the lower rail 285 (e.g., ground) during the regeneration phase, which increases the regeneration gain.

[0048]

[0064] Thus, the pull-down circuit 505 is configured to provide an additional pull-down path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. The pull-down path is between the input 262 of the first inverting circuit 260 and the lower rail 285 (e.g., ground) when the voltage DINT falls faster than the voltage NDINT (e.g., when INP>INN), and the pull-down path is between the input 272 of the second inverting circuit 270 when the voltage NDINT falls faster than the voltage DINT (e.g., when INN>INP).

[0049]

[0065] The pull-down circuit 505 can be used in combination with the pull-up circuit 405 to increase the regeneration gain of the regeneration circuit 150, which increases the signal strength at the outputs 170 and 175 of the regeneration circuit 150. For example, when the voltage DINT falls faster than the voltage NDINT (e.g., INP > INN), the pull-up circuit 405 provides an additional pull-up path to pull up the input 272 of the second inverting circuit 270, while the pull-down circuit 505 provides an additional pull-down path to pull down the input 262 of the first inverting circuit 260. When the voltage NDINT falls faster than the voltage DINT (e.g., INN > INP), the pull-up circuit 405 provides an additional pull-up path to pull up the input 272 of the second inverting circuit 270, while the pull-down circuit 505 provides an additional pull-down path to pull down the input 262 of the first inverting circuit 260. Thus, in these embodiments, depending on which of the voltages DINT and NDINT falls faster, and therefore depending on the input voltages INP and INN of the input circuit 120, the pull-up circuit 405 pulls up one input of the inverting circuits 260 and 270, and the pull-down circuit 505 pulls down the other input of the inverting circuits 260 and 270.

[0050]

[0066] Another advantage of pull-up circuit 405 and pull-down circuit 505 is that they continue to provide regenerative gain during the initial portion of the reset phase before input transistors 250 and 255 are turned on (i.e., before input circuit 120 raises voltages DINT and NDINT above the threshold voltages of input transistors 250 and 255). This is because pull-up circuit 405 and pull-down circuit 505 continue to provide additional pull-up and pull-down paths even after switches 290 and 295 are turned off by a timing signal (e.g., clock signal CLK). The continued regenerative gain during the initial portion of the reset phase allows the differential output voltage of regenerative circuit 150 to continue increasing to better determine the corresponding bit value.

[0051]

[0067] It should be understood that pull-down circuit 505 is not limited to the exemplary implementation shown in Figure 5A. In this regard, Figure 5B shows another exemplary implementation in which a gate of first pull-down transistor 510 is coupled to output 264 of first inverting circuit 260 and a gate of second pull-down transistor 520 is coupled to output 274 of second inverting circuit 270. Similar to the exemplary implementation shown in Figure 5A, pull-down transistors 510 and 520 in this example provide additional pull-down paths to increase regenerative gain.

[0052]

[0068] As described above, pull-up circuit 405 increases the regeneration gain of regeneration circuit 150 by providing an additional pull-up path during the regeneration phase. Increasing the size (e.g., channel width) of pull-up transistors 410 and 420 can increase the strength of the pull-up path and further increase the regeneration gain of regeneration circuit 150. However, increasing the size of pull-up transistors 410 and 420 increases the reset time of regeneration circuit 150, as discussed further below, resulting in a trade-off between regeneration and reset.

[0053]

[0069] At the beginning of the reset phase, input circuit 120 raises voltages DINT and NDINT, which are input to input transistors 250 and 255 of regeneration circuit 150. When voltages DINT and NDINT rise to the threshold voltages of input transistors 250 and 255, input transistors 250 and 255 turn on and pull both inputs 262 and 272 of inverter circuits 260 and 270 low. However, one of pull-up transistors 410 and 420 is initially on and resists the ability of input transistors 250 and 255 to pull both inputs 262 and 272 of inverter circuits 260 and 270 low, which increases the reset time. Increasing the size of pull-up transistors 410 and 420 to further increase regeneration gain exacerbates this problem by making it more difficult for input transistors 250 and 255 to pull both inputs 262 and 272 of inverter circuits 260 and 270 low to reset regeneration circuit 150. Thus, there is a tradeoff between regeneration and reset associated with pull-up transistors 410 and 420 .

[0054]

[0070] 6 illustrates an example in which the regeneration circuit 150 further includes a third input transistor 610 and a fourth input transistor 620, which mitigate the trade-off between regeneration and reset and increase sensitivity, as further described below. In this example, the regeneration circuit 150 also includes a third switch 630 and a fourth switch 640.

[0055]

[0071] 6, the third input transistor 610 is implemented with a respective PFET, the source of the third input transistor 610 is coupled to the rail 280, and the third switch 630 is coupled between the drain of the third input transistor 610 and the first input transistor 250. In the example of FIG. 6, the third input transistor 610 is implemented with a respective PFET, the source of the third input transistor 610 is coupled to the rail 280, and the third switch 630 is coupled between the drain of the third input transistor 610 and the first input transistor 250. In the example where the third input transistor 610 is implemented with a respective PFET, the third input transistor 610 may be configured to turn on when the first voltage DINT falls below VCC-Vt3, where Vt3 is the threshold voltage of the third input transistor 610.

[0056]

[0072] The third switch 630 has a control input 635 coupled to the input 262 of the first inverting circuit 260. In particular aspects, the third switch 630 is configured to turn on when the voltage at the control input 635 falls below a threshold of the third switch 630 and to turn off when the voltage at the control input 635 exceeds a threshold of the third switch 630, as described further below. The third switch 630 may be implemented with a respective PFET or with another type of switch.

[0057]

[0073] The gate of the fourth input transistor 620 is coupled to the second input 165 of the regeneration circuit 150 and therefore receives the second voltage NDINT. The fourth input transistor 620 and the fourth switch 640 are coupled in series between the rail 280 and the second output 175 of the regeneration circuit 150. In the example of FIG. 6, the fourth input transistors 620 are implemented with respective PFETs, the sources of the fourth input transistors 620 are coupled to the rail 280, and the fourth switch 640 is coupled between the drains of the fourth input transistors 620 and the second input transistor 255. In examples where the fourth input transistors 620 are implemented with respective PFETs, the fourth input transistors 620 may be configured to turn on when the second voltage NDINT falls below VCC-Vt4, where Vt4 is the threshold voltage of the fourth input transistor 620. In certain aspects, Vt3 and Vt4 may be approximately equal.

[0058]

[0074] The fourth switch 640 has a control input 645 coupled to the input 272 of the second inverting circuit 270. In particular aspects, the fourth switch 640 is configured to turn on when the voltage at the control input 645 falls below a threshold of the fourth switch 640 and to turn off when the voltage at the control input 645 exceeds a threshold of the fourth switch 640, as described further below. The fourth switch 640 may be implemented with a respective PFET or with another type of switch.

[0059]

[0075] An exemplary operation of the exemplary playback circuit 150 shown in FIG. 6 will now be discussed in accordance with certain aspects.

[0060]

[0076] During the reset phase, input circuit 120 pulls voltages DINT and NDINT to supply voltage VCC, as discussed above. This turns on first input transistor 250 and second input transistor 255 of reconstruction circuit 150, and pulls inputs 262 and 272 of inverter circuits 260 and 270 low. This, in turn, turns off third and fourth input transistors 610 and 620 of reconstruction circuit 150 because these transistors are implemented with PFETs. Thus, in this example, inputs 262 and 272 of inverter circuits 260 and 270 are reset low (e.g., near ground). Additionally, third switch 630 and fourth switch 640 are both on because input transistors 610 and 620 pull control inputs 635 and 645 of third and fourth switches 630 and 640 low during the reset phase.

[0061]

[0077] When sampler 110 transitions to the playback phase, a timing signal (e.g., clock signal CLK) turns on first switch 290 and second switch 295, enabling a playback feedback loop through inverter circuits 260 and 270. At the start of the playback phase, first input transistor 250 and second input transistor 255 are both on, and third and fourth input transistors 610 and 620 are both off. In addition, third switch 630 and fourth switch 640 are both on.

[0062]

[0078] When the input voltage INP is higher than the input voltage INN, the first voltage DINT decreases (i.e., discharges) at a faster rate than the second voltage NDINT. This causes the first input transistor 250 to turn off before the second input transistor 255, and the third input transistor 610 to turn on before the fourth input transistor 620. Turning off the first input transistor 250 triggers the regenerative feedback of the regeneration circuit 150 to pull up the first output 170 and pull down the second output 175 (e.g., pulling the first output 170 toward the supply voltage VCC and the second output 175 toward ground). Turning on the third input transistor 610 causes the third input transistor 610 to pull up the first output 170 through the (turned on) third switch 630. Thus, in this case, the third input transistor 610 and the third switch 630 provide an additional pull-up path for pulling up the first output 170, which increases the regenerative gain.

[0063]

[0079] Because the control input 645 of the fourth switch 640 is coupled to the first output 170, the pull-up of the first output 170 turns off the fourth switch 640. This prevents the fourth input transistor 620 from pulling up the second output 175 when the fourth input transistor 620 finally turns on (i.e., when NDINT falls below VCC-Vt4), allowing the regeneration of the regeneration circuit 150 to pull the second output 175 low.

[0064]

[0080] When the input voltage INN is higher than the input voltage INP, the second voltage NDINT decreases (i.e., discharges) at a faster rate than the first voltage DINT. This causes the second input transistor 255 to turn off before the first input transistor 250 and the fourth input transistor 620 to turn on before the third input transistor 610. Turning off the second input transistor 255 triggers the regenerative feedback of the regeneration circuit 150 to pull up the second output 175 and pull down the first output 170 (e.g., pulling the second output 175 toward the supply voltage VCC and the first output 170 toward ground). Turning on the fourth input transistor 620 causes the fourth input transistor 620 to pull up the second output 175 through the (turned on) fourth switch 640. Thus, in this case, the fourth input transistor 620 and the fourth switch 640 provide an additional pull-up path for pulling up the second output 175, which increases the regenerative gain.

[0065]

[0081] Because the control input 635 of the third switch 630 is coupled to the second output 175, the pull-up of the second output 175 turns off the third switch 630. This prevents the third input transistor 610 from pulling up the first output 170 when the third input transistor 610 finally turns on (i.e., when DINT falls below VCC-Vt3), allowing the regeneration of the regeneration circuit 150 to pull the first output 170 low.

[0066]

[0082] Thus, the third input transistor 610 and the fourth input transistor 620 provide an additional pull-up path during the regeneration phase, increasing the regeneration gain of the regeneration circuit 150. When the voltage DINT falls faster than the voltage NDINT (e.g., INP>INN), the third input transistor 610 provides an additional pull-up path between the first output 170 and the rail 280 via the third switch 630. When the voltage NDINT falls faster than the voltage DINT (e.g., INN>INP), the fourth input transistor 620 provides an additional pull-up path between the second output 175 and the rail 280 via the fourth switch 640.

[0067]

[0083] The third input transistor 610 and the fourth input transistor 620 allow the regeneration circuit 150 to achieve higher regeneration gain without having to increase the size (e.g., channel width) of the first pull-up transistor 410 and the second pull-up transistor 420, thereby easing the trade-off between regeneration and reset associated with the pull-up transistors 410 and 420. This is because the third input transistor 610 and the fourth input transistor 620 provide an additional pull-up path during the regeneration phase in parallel with the additional pull-up path provided by the pull-up transistors 410 and 420. This increases the regeneration pull-up strength in the regeneration circuit 150 without having to increase the size of the first pull-up transistor 410 and the second pull-up transistor 420.

[0068]

[0084] Additionally, input circuit 120 turns off both third input transistor 610 and fourth input transistor 620 during the reset phase, allowing first input transistor 250 and second input transistor 255 to pull inputs 262 and 272 of both inverter circuits 260 and 270 low during the reset phase, resetting regeneration circuit 150. This is because input circuit 120 pulls voltages DINT and NDINT to supply voltage VCC during the reset phase, which turns off both third input transistor 610 and fourth input transistor 620. Once input circuit 120 turns off third input transistor 610 and fourth input transistor 620 during the reset phase, these transistors no longer resist the ability of first input transistor 250 and second input transistor 255 to pull inputs 262 and 272 of both inverter circuits 260 and 270 low during the reset phase. This further mitigates the trade-off between regeneration and reset.

[0069]

[0085] The third input transistor 610 and the fourth input transistor 620 also increase the sensitivity of the sampler 110 because the gates of the third input transistor 610 and the fourth input transistor 620 are driven by voltages DINT and NDINT, respectively, which are generated based on the sensed input voltages INP and INN, respectively.

[0070]

[0086] 6, the third switch 630 is coupled between the third input transistor 610 and the first input transistor 250. However, it should be understood that the present disclosure is not limited to this example. For example, in some implementations, the third switch 630 may be coupled between the third input transistor 610 and the top rail 280, and the third input transistor 610 may be coupled between the third switch 630 and the first input transistor 250. In general, the third input transistor 610 and the third switch 630 are coupled in series between the top rail 280 and the first input transistor 250, with either the third input transistor 610 or the third switch 630 being on the upper side. Also, in some implementations, the fourth switch 640 may be coupled between the fourth input transistor 620 and the top rail 280, and the fourth input transistor 620 may be coupled between the fourth switch 640 and the second input transistor 255. Generally, the fourth input transistor 620 and the fourth switch 640 are coupled in series between the upper rail 280 and the second input transistor 255, with either the fourth input transistor 620 or the fourth switch 640 on the upper side.

[0071]

[0087] 7 shows exemplary implementations of the third switch 630 and the fourth switch 640. In this example, the third switch 630 is implemented with a first PFET 710 coupled between the drain of the third input transistor 610 and the first input transistor 250, with the gate of the first PFET 710 coupled to the input 262 of the first inverter circuit 260. Also in this example, the fourth switch 640 includes a second PFET 720 coupled between the drain of the fourth input transistor 620 and the second input transistor 255, with the gate of the second PFET 720 coupled to the input 272 of the second inverter circuit 270. It should be understood that the third switch 630 and the fourth switch 640 are not limited to the exemplary implementation shown in FIG. 7, and that each of the third switch 630 and the fourth switch 640 may be implemented with another type of transistor, a transmission gate, or another type of switch.

[0072]

[0088] 8 shows an example in which first switch 290 is implemented with a first NFET 810 and second switch 295 is implemented with a second NFET 820. In this example, one of the source and drain of first NFET 810 is coupled to first input transistor 250 (e.g., the drain of first input transistor 250), the other of the source and drain of first NFET 810 is coupled to output 264 of first inverter circuit 260, and the gate of first NFET 810 is coupled to control input 292 for receiving a timing signal (e.g., clock signal CLK). One of the source and drain of second NFET 820 is coupled to second input transistor 255 (e.g., the drain of second input transistor 255), the other of the source and drain of second NFET 820 is coupled to output 274 of second inverter circuit 270, and the gate of second NFET 820 is coupled to control input 297 for receiving a timing signal (e.g., clock signal CLK). In this example, the first switch 290 and the second switch 295 are on when the timing signal is high and off when the timing signal is low. It should be understood that the first switch 290 and the second switch 295 are not limited to the exemplary implementation shown in FIG. 8 and that each of the first switch 290 and the second switch 295 may be implemented with another type of transistor, a transmission gate, or another type of switch.

[0073]

[0089] In the example shown in FIGS. 4-8 , the regeneration circuit 150 includes a first switch 290 and a second switch 295 for enabling the regenerative feedback of the inverter circuits 260 and 270 during the regeneration phase and for disabling the regenerative feedback of the inverter circuits 260 and 270 during the reset phase. However, it should be understood that the present disclosure is not limited to this example. For example, in other implementations, the first switch 290 and the second switch 295 may be omitted and the switch 296 shown in FIG. 2C may be used to enable or disable the regenerative feedback of the inverter circuits 260 and 270. In this example, the output 264 of the first inverter circuit 260 is coupled to the first input transistor 250, and the output 274 of the second inverter circuit 270 is coupled to the second input transistor 255. In general, one or more switches may be located in one or more locations within the regeneration circuit 150 to enable or disable the regenerative feedback of the inverter circuits 260 and 270.

[0074]

[0090] 9A shows an exemplary implementation of a first inverter circuit 260 according to certain aspects. In this example, the first inverter circuit 260 is a complementary inverter circuit including a PFET 910 and an NFET 920. The source of the PFET 910 is coupled to a first supply terminal 266, the drain of the PFET 910 is coupled to an output 264, and the gate of the PFET 910 is coupled to an input 262. The drain of the NFET 920 is coupled to the output 264, the gate of the NFET 920 is coupled to the input 262, and the source of the NFET 920 is coupled to a second supply terminal 268. It should be understood that the first inverter circuit 260 is not limited to the example shown in FIG. 9A .

[0075]

[0091] 9B shows an exemplary implementation of second inverting circuit 270 according to certain aspects. In this example, second inverting circuit 270 is a complementary inverting circuit including PFET 930 and NFET 940. A source of PFET 930 is coupled to a first supply terminal 276, a drain of PFET 930 is coupled to an output 274, and a gate of PFET 930 is coupled to an input 272. A drain of NFET 940 is coupled to an output 274, a gate of NFET 940 is coupled to an input 272, and a source of NFET 940 is coupled to a second supply terminal 278. It should be understood that second inverting circuit 270 is not limited to the example shown in FIG.

[0076]

[0092] 10 shows an exemplary implementation of first switch 230, second switch 240, and third switch 245 in input circuit 120, according to certain aspects. In this example, first switch 230 is implemented with an NFET 1010, the drain of which is coupled to the sources of input transistors 210 and 220, the gate of which is coupled to control input 235, and the source of which is coupled to lower rail 285 (e.g., ground). Second switch 240 is implemented with a first PFET 1015, the source of which is coupled to upper rail 280, the gate of which is coupled to control input 242, and the drain of which is coupled to the drain of first input transistor 210. The third switch 245 is implemented with a second PFET 1020, with the source of the second PFET 1020 coupled to the upper rail 280, the gate of the second PFET 1020 coupled to the control input 247, and the drain of the second PFET 1020 coupled to the drain of the second input transistor 220. In this example, the first switch 230 is on when the timing signal is high and off when the timing signal is low. Also in this example, the second switch 240 and the third switch 245 are on when the timing signal is low and off when the timing signal is high. It should be understood that the first switch 230, the second switch 240, and the third switch 245 are not limited to the exemplary implementation shown in FIG. 10 .

[0077]

[0093] 11 illustrates an example of a system 1105 in which aspects of the present disclosure may be used. In this example, the system 1105 includes a first chip 1110 and a second chip 1115, and SerDes may be used for communication between the first chip 1110 and the second chip 1115. The first chip 1110 includes a serializer 1120, a driver 1130, a first output pin 1140, and a second output pin 1142. The second chip 1115 includes a first receive pin 1150, a second receive pin 1152, a receiver 1160, a sampler 110, a latch 1170, and a deserializer 1180.

[0078]

[0094] In this example, a first chip 1110 and a second chip 1115 are coupled via a differential serial link including a first line 1144 and a second line 1146. The first line 1144 is coupled between a first output pin 1140 and a first receive pin 1150, and the second line 1146 is coupled between a second output pin 1142 and a second receive pin 1152. Each of the first line 1144 and the second line 1146 may be implemented as a metal line, wire, or the like on a substrate (e.g., a printed circuit board).

[0079]

[0095] On the first chip 1110, a serializer 1120 is configured to receive a parallel data stream (e.g., from a processor on the first chip 1110) and convert the parallel data stream to a serial data stream, which is output at an output 1125 of the serializer 1120. A driver 1130 has an input 1132 coupled to the output 1125 of the serializer 1120, a first output 1134 coupled to a first output pin 1140, and a second output 1136 coupled to a second output pin 1142. The driver 1130 is configured to receive the serial data stream, convert the serial data stream to a differential signal, and drive a first line 1144 and a second line 1146 of a differential serial link with the differential data signal to transmit the differential signal to the second chip 1115. It should be understood that the first chip 1110 may include additional components not shown in FIG. 11 (e.g., an impedance matching network coupled to output pins 1140 and 1142, a pre-driver coupled between the serializer 1120 and the driver 1130, etc.).

[0080]

[0096] On the second chip 1115, a receiver 1160 has a first input 1162 coupled to the first receive pin 1150, a second input 1164 coupled to the second receive pin 1152, a first output 1166 coupled to the first input 130 of the sampler 110, and a second output 1168 coupled to the second input 135 of the sampler 110. The receiver 1160 may include at least one of an amplifier and an equalizer (e.g., to compensate for frequency-dependent signal attenuation between the first chip 1110 and the second chip 1115). The sampler 110 receives a differential signal from the receiver 1160 and makes bit decisions based on the differential signal, as described above.

[0081]

[0097] 11 , a first output 170 of sampler 110 is coupled to a first input 1172 of latch 1170, and a second output 175 of sampler 110 is coupled to a second input 1174 of latch 1170. Latch 1170 has an output 1176 coupled to an input 1182 of deserializer 1180. Latch 1170 is configured to latch bit decisions from sampler 110 and output corresponding bits to deserializer 1180. Deserializer 1180 is configured to convert the bits into a parallel data stream, which may be output to one or more components (not shown) on second chip 1115 for further processing. It should be understood that second chip 1115 may include additional components not shown in FIG. 11 (e.g., an impedance matching network coupled to receive pins 1150 and 1152, a clock recovery circuit, etc.).

[0082]

[0098] 11, the second chip 1115 also includes a timing signal circuit 1190 configured to generate a timing signal (e.g., a clock signal CLK) for the sampler 110 and output the timing signal at an output 1194. The output 1194 may be coupled to control inputs of switches 230, 240, and 245 in the input circuit 120 and to control inputs of switches 290 and 295 in the recovery circuit 150 of the sampler 110.

[0083]

[0099] In certain aspects, timing signal circuit 1190 may use clock data recovery to recover a timing signal (e.g., clock signal CLK) based on the bit decisions of sampler 110. Input 1192 of timing signal circuit 1190 may be coupled to the output of latch 1170 (as shown in the example of FIG. 11 ) or may be coupled to one or both of outputs 170 and 175 of sampler 110 to receive the bit decisions.

[0084]

[0100] In certain aspects, timing signal circuit 1190 may include a clock generator, which may include a phase locked loop (PLL), a delay locked loop (DLL), an oscillator, or any combination thereof, to generate a timing signal (e.g., clock signal CLK). It should be understood that timing signal circuit 1190 may be implemented using various types of clock generators.

[0085]

[0101] 12 illustrates a method 1200 of operating a recovery circuit of a sampler according to certain embodiments. The recovery circuit (e.g., recovery circuit 150) includes a first inverting circuit (e.g., first inverting circuit 260) having an input and an output, a second inverting circuit (e.g., second inverting circuit 270) having an input and an output, a first transistor (e.g., first input transistor 250) coupled to the input of the second inverting circuit, a second transistor (e.g., second input transistor 255) coupled to the input of the first inverting circuit, a third transistor (e.g., third input transistor 610), and a fourth transistor (e.g., fourth input transistor 620).

[0086]

[0102] In block 1210, during the reset phase, regenerative feedback of the first inverter circuit and the second inverter circuit is disabled. For example, disabling the regenerative feedback of the first inverter circuit and the second inverter circuit may include decoupling the output of the first inverter circuit from the first transistor and decoupling the output of the second inverter circuit from the second transistor. For example, the output of the first inverter circuit may be decoupled from the first transistor by turning off the first switch 290 (e.g., using a timing signal), and the output of the second inverter circuit may be decoupled from the second transistor by turning off the second switch 295 (e.g., using a timing signal). In another example, disabling the regenerative feedback of the first inverter circuit and the second inverter circuit may include turning off the switch 296 shown in FIG. 2C .

[0087]

[0103] In block 1220, during the regeneration phase, regenerative feedback of the first inverter circuit and the second inverter circuit is enabled. For example, enabling the regenerative feedback of the first inverter circuit and the second inverter circuit may include coupling an output of the first inverter circuit to a first transistor and coupling an output of the second inverter circuit to a second transistor. For example, the output of the first inverter circuit may be coupled to the first transistor by turning on a first switch 290 (e.g., using a timing signal), and the output of the second inverter circuit may be coupled to the second transistor by turning on a second switch 295 (e.g., using a timing signal). In another example, enabling the regenerative feedback of the first inverter circuit and the second inverter circuit may include turning on switch 296 shown in FIG. 2C .

[0088]

[0104] In block 1230, during the regeneration phase, the gate of the first transistor and the gate of the third transistor are driven with a first voltage. For example, the input circuit 120 may drive the gate of the first transistor and the gate of the third transistor with a first voltage DINT.

[0089]

[0105] In block 1240, during the regeneration phase, the gate of the second transistor and the gate of the fourth transistor are driven with a second voltage. For example, the input circuit 120 may drive the gate of the second transistor and the gate of the fourth transistor with a second voltage NDINT.

[0090]

[0106] In block 1250, during the regeneration phase, the third transistor is coupled to the output of the first inverter circuit or the fourth transistor is coupled to the output of the second inverter circuit. For example, the third switch 630 can couple the third transistor to the output of the first inverter circuit, or the fourth switch 640 can couple the fourth transistor to the output of the second inverter circuit.

[0091]

[0107] In certain aspects, during the regeneration phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate. For example, the first rate can be based on a first input signal (e.g., INP) to the sampler, and the second rate can be based on a second input signal (e.g., INN) to the sampler. In one example, the first input transistor 210 of the input circuit 120 can discharge the first node 222 based on the first input signal INP to decrease the first voltage DINT at the first rate, and the second input transistor 220 of the input circuit 120 can discharge the second node 224 based on the second input signal INN to decrease the second voltage NDINT at the second rate. In this example, the gate of the first input transistor 210 can be driven by the first input signal INP, and the gate of the second input transistor 220 can be driven by the second input signal INN.

[0092]

[0108] In certain aspects, if the first input signal is greater than the second input signal (e.g., INP>INN), the first rate is greater than the second rate, and if the second input signal is greater than the first input signal (e.g., INN>INP), the second rate is greater than the first rate.

[0093]

[0109] In certain aspects, coupling the third transistor to the output of the first inverting circuit or coupling the fourth transistor to the output of the second inverting circuit includes coupling the third transistor to the output of the first inverting circuit based on a voltage at an input of the first inverting circuit or coupling the fourth transistor to the output of the second inverting circuit based on a voltage at an input of the second inverting circuit. For example, the control input 635 of the third switch 630 may be coupled to the input 262 of the first inverting circuit 260, and the control input 645 of the fourth switch 640 may be coupled to the input 272 of the second inverting circuit 270.

[0094]

[0110] The method 1200 may also include pulling up the first voltage and the second voltage to a supply voltage during the reset phase. For example, the first voltage DINT and the second voltage NDINT may be pulled up to the supply voltage VCC by turning on the second switch 240 and the third switch 245 of the input circuit 120 during the reset phase.

[0095]

[0111] The following numbered clauses describe example implementations.

[0112] Article 1.

[0113] a first inverter circuit having an input and an output;

[0114] a second inverter circuit having an input and an output;

[0115] a first transistor coupled to the input of the second inverter circuit, the gate of the first transistor being coupled to the first input;

[0116] a second transistor coupled to the input of the first inverter circuit, the gate of the second transistor being coupled to the second input;

[0117] a third transistor, the gate of the third transistor being coupled to the first input; and

[0118] a fourth transistor, the gate of the fourth transistor being coupled to the second input; and

[0119] a first switch, the first switch and a third transistor being coupled in series between the first rail and the first transistor;

[0120] a second switch, the second switch and a fourth transistor coupled in series between the first rail and the second transistor.

[0121] Article 2.

[0122] a first switch coupled between the drain of the third transistor and the drain of the first transistor;

[0123] 10. The regeneration circuit of claim 1, wherein a second switch is coupled between the drain of the fourth transistor and the drain of the second transistor.

[0124] Article 3.

[0125] a source of the third transistor coupled to the first rail;

[0126] the source of the fourth transistor is coupled to the first rail;

[0127] the source of the first transistor is coupled to the second rail;

[0128] 3. The regeneration circuit of clause 2, wherein the source of the second transistor is coupled to the second rail.

[0129] Clause 4. The regeneration circuit of clause 3, wherein the second rail is coupled to ground.

[0130] Article 5.

[0131] the first transistor comprises a first n-type field effect transistor (NFET);

[0132] the second transistor comprises a second NFET;

[0133] the third transistor comprises a first p-type field effect transistor (PFET);

[0134] 5. The regeneration circuit of any one of clauses 1 to 4, wherein the fourth transistor comprises a second PFET.

[0135] Article 6.

[0136] a first switch having a control input coupled to the input of the first inverter circuit;

[0137] 6. The regeneration circuit of any one of clauses 1 to 5, wherein the second switch has a control input coupled to the input of the second inverting circuit.

[0138] Article 7.

[0139] the first switch comprises a first p-type field effect transistor (PFET) having a gate coupled to the input of the first inverter circuit;

[0140] 7. The regeneration circuit of clause 6, wherein the second switch comprises a second PFET having a gate coupled to the input of the second inverting circuit.

[0141] Article 8.

[0142] a third switch coupled between the first transistor and the output of the first inverter circuit;

[0143] 8. The regeneration circuit of any one of clauses 1 to 7, further comprising: a fourth switch coupled between the second transistor and the output of the second inverting circuit.

[0144] Article 9.

[0145] a third switch having a control input configured to receive a timing signal;

[0146] 9. The regeneration circuit of claim 8, wherein the fourth switch has a control input configured to receive a timing signal.

[0147] Clause 10. The regeneration circuit of clause 9, wherein the timing signal comprises a clock signal.

[0148] Article 11.

[0149] a first inverter circuit having an input and an output;

[0150] a second inverter circuit having an input and an output;

[0151] a first transistor coupled to the input of the second inverter circuit, the gate of the first transistor being coupled to the first input;

[0152] a second transistor coupled to the input of the first inverter circuit, the gate of the second transistor being coupled to the second input;

[0153] a pull-up circuit coupled to the input of the first inverter circuit and the input of the second inverter circuit;

[0154] a pull-down circuit coupled to an input of the first inverter circuit and an input of the second inverter circuit.

[0155] Clause 12. The pull-up circuit

[0156] a third transistor coupled between the input of the first inverter circuit and the rail, the gate of the third transistor being coupled to the output of the first inverter circuit;

[0157] and a fourth transistor coupled between the input of the second inverting circuit and the rail, the gate of the fourth transistor being coupled to the output of the second inverting circuit.

[0158] Article 13.

[0159] the third transistor comprises a first p-type field effect transistor (PFET);

[0160] 13. The regeneration circuit of claim 12, wherein the fourth transistor comprises a second PFET.

[0161] Article 14.

[0162] the source of the first PFET is coupled to the rail and the drain of the first PFET is coupled to the input of the first inverter circuit;

[0163] 14. The regeneration circuit of clause 13, wherein the source of the second PFET is coupled to the rail and the drain of the second PFET is coupled to the input of the second inverting circuit.

[0164] Clause 15. The pull-down circuit

[0165] a third transistor coupled between the input of the first inverter circuit and a rail, the gate of the third transistor being coupled to the input of the second inverter circuit or the output of the first inverter circuit;

[0166] 12. The regeneration circuit of claim 11, comprising: a fourth transistor coupled between the input of the second inverting circuit and the rail, the gate of the fourth transistor being coupled to the input of the first inverting circuit or the output of the second inverting circuit.

[0167] Article 16.

[0168] the third transistor comprises a first n-type field effect transistor (NFET);

[0169] 16. The regeneration circuit of clause 15, wherein the fourth transistor comprises a second NFET.

[0170] Article 17.

[0171] the drain of the first NFET is coupled to the input of the first inverter circuit and the source of the first NFET is coupled to the rail;

[0172] 17. The regeneration circuit of clause 16, wherein the drain of the second NFET is coupled to the input of the second inverting circuit and the source of the second NFET is coupled to the rail.

[0173] Clause 18. The regeneration circuit of any one of clauses 15 to 17, wherein the rail is coupled to ground.

[0174] Article 19.

[0175] a first switch coupled between the first transistor and the output of the first inverter circuit;

[0176] 19. The regeneration circuit of any one of clauses 11 to 18, comprising: a second switch coupled between the second transistor and the output of the second inverting circuit.

[0177] Article 20.

[0178] a first switch having a control input configured to receive a timing signal;

[0179] 20. The regeneration circuit of clause 19, wherein the second switch has a control input configured to receive a timing signal.

[0180] Clause 21. A method of operating a regeneration circuit of a sampler, the regeneration circuit including a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, a second transistor coupled to the input of the first inverting circuit, a third transistor, and a fourth transistor, the method comprising:

[0181] During the reset phase,

[0182] Disabling regenerative feedback of the first inverter circuit and the second inverter circuit;

[0183] During the regeneration phase,

[0184] enabling regenerative feedback of the first inverter circuit and the second inverter circuit;

[0185] driving a gate of the first transistor and a gate of the third transistor with a first voltage;

[0186] driving the gate of the second transistor and the gate of the fourth transistor with a second voltage;

[0187] coupling a third transistor to the output of the first inverting circuit or coupling a fourth transistor to the output of the second inverting circuit.

[0188] Clause 22. The method of clause 21, wherein during the regeneration phase, the first voltage is decreased at a first rate and the second voltage is decreased at a second rate, the first rate being different from the second rate.

[0189] Clause 23. The method of clause 22, wherein the first rate is based on a first input signal to the sampler and the second rate is based on a second input signal to the sampler.

[0190] Clause 24. The method of clause 23, wherein the first rate is greater than the second rate when the first input signal is greater than the second input signal, and the second rate is greater than the first rate when the second input signal is greater than the first input signal.

[0191] Clause 25. Coupling a third transistor to the output of the first inverting circuit or coupling a fourth transistor to the output of the second inverting circuit

[0192] coupling a third transistor to the output of the first inverter circuit when the first rate is greater than the second rate;

[0193] 25. The method of any one of clauses 22-24, comprising coupling a fourth transistor to the output of the second inverting circuit if the second rate is greater than the first rate.

[0194] Clause 26. Coupling a third transistor to the output of the first inverting circuit or coupling a fourth transistor to the output of the second inverting circuit

[0195] 26. The method of any one of clauses 22-25, comprising coupling a third transistor to an output of the first inverting circuit based on a voltage at an input of the first inverting circuit, or coupling a fourth transistor to an output of the second inverting circuit based on a voltage at an input of the second inverting circuit.

[0196] Clause 27. The method of any one of clauses 21 to 26, further comprising pulling up the first voltage and the second voltage to a supply voltage during the reset phase.

[0197] Article 28.

[0198] the first transistor comprises a first n-type field effect transistor (NFET);

[0199] the second transistor comprises a second NFET;

[0200] the third transistor comprises a first p-type field effect transistor (PFET);

[0201] 28. The method of any one of clauses 21-27, wherein the fourth transistor comprises a second PFET.

[0202] Article 29.

[0203] Disabling the regenerative feedback of the first inverter circuit and the second inverter circuit;

[0204] decoupling the output of the first inverter circuit from the first transistor;

[0205] decoupling the output of the second inverter circuit from the second transistor;

[0206] Enabling regenerative feedback of the first inverter circuit and the second inverter circuit;

[0207] coupling an output of the first inverter circuit to a first transistor;

[0208] 29. The method of any one of clauses 21-28, comprising coupling an output of the second inverting circuit to a second transistor.

[0209] Clause 30. The pull-down circuit

[0210] a fifth transistor coupled between the input of the first inverter circuit and the second rail, the gate of the fifth transistor being coupled to the input of the second inverter circuit or the output of the first inverter circuit;

[0211] 15. The method of any one of clauses 12 to 14, comprising a sixth transistor coupled between the input of the second inverting circuit and the second rail, the gate of the sixth transistor being coupled to the input of the first inverting circuit or the output of the second inverting circuit.

[0212] Article 31.

[0213] the fifth transistor comprises a first n-type field effect transistor (NFET);

[0214] 31. The regeneration circuit of clause 30, wherein the sixth transistor comprises a second NFET.

[0215] Article 32.

[0216] the drain of the first NFET is coupled to the input of the first inverter circuit and the source of the first NFET is coupled to the rail;

[0217] 32. The regeneration circuit of clause 31, wherein the drain of the second NFET is coupled to the input of the second inverting circuit and the source of the second NFET is coupled to the rail.

[0218] Clause 33. The regeneration circuit of any one of clauses 30 to 32, wherein the second rail is coupled to ground.

[0096]

[0219] It is to be understood that this disclosure is not limited to the exemplary terminology used above to describe aspects of the disclosure.

[0097]

[0220] Any reference herein to an element using a designation such as "first," "second," etc. generally does not limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not imply that only two elements may be employed or that the first element must precede the second element. Furthermore, it should be understood that the designations "first," "second," etc. in this specification do not necessarily align with the designations "first," "second," etc. in the claims.

[0098]

[0221] Within the scope of this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "about," as used herein in connection with a stated value or property, is intended to indicate within 10% of the stated value or property.

[0099]

[0222] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a first inverter circuit having an input and an output; a second inverter circuit having an input and an output; a first transistor coupled to the input of the second inverter circuit, the gate of the first transistor being coupled to a first input; a second transistor coupled to the input of the first inverter circuit, the gate of the second transistor being coupled to a second input; a third transistor, the gate of the third transistor being coupled to the first input; a fourth transistor, the gate of the fourth transistor being coupled to the second input; and a first switch, the first switch and the third transistor being coupled in series between a first rail and the first transistor; a second switch, the second switch and the fourth transistor being coupled in series between the first rail and the second transistor.

2. the first switch is coupled between the drain of the third transistor and the drain of the first transistor; 2. The regeneration circuit of claim 1, wherein the second switch is coupled between the drain of the fourth transistor and the drain of the second transistor.

3. the source of the third transistor is coupled to the first rail; the source of the fourth transistor is coupled to the first rail; the source of the first transistor is coupled to a second rail; 3. The regeneration circuit of claim 2, wherein the source of the second transistor is coupled to the second rail.

4. 4. The regeneration circuit of claim 3, wherein the second rail is coupled to ground.

5. the first transistor comprises a first n-type field effect transistor (NFET); the second transistor comprises a second NFET; the third transistor comprises a first p-type field effect transistor (PFET); 2. The regeneration circuit of claim 1, wherein the fourth transistor comprises a second PFET.

6. 2. The regeneration circuit of claim 1, wherein the first switch has a control input coupled to the input of the first inverter circuit, and the second switch has a control input coupled to the input of the second inverter circuit.

7. the first switch comprises a first p-type field effect transistor (PFET) having a gate coupled to the input of the first inverter circuit; 7. The regeneration circuit of claim 6, wherein the second switch comprises a second PFET having a gate coupled to the input of the second inverting circuit.

8. a third switch coupled between the first transistor and the output of the first inverter circuit; 2. The regeneration circuit of claim 1, further comprising: a fourth switch coupled between the second transistor and the output of the second inverter circuit.

9. 9. The regeneration circuit of claim 8, wherein the third switch has a control input configured to receive a timing signal, and the fourth switch has a control input configured to receive the timing signal.

10. 10. The regeneration circuit of claim 9, wherein the timing signal comprises a clock signal.

11. a first inverter circuit having an input and an output; a second inverter circuit having an input and an output; a first transistor coupled to the input of the second inverter circuit, the gate of the first transistor being coupled to a first input; a second transistor coupled to the input of the first inverter circuit, the gate of the second transistor being coupled to a second input; a pull-up circuit coupled to the input of the first inverter circuit and the input of the second inverter circuit; a pull-down circuit coupled to the input of the first inverter circuit and to the input of the second inverter circuit.

12. The pull-up circuit a third transistor coupled between the input of the first inverter circuit and a rail, the gate of the third transistor being coupled to the output of the first inverter circuit; a fourth transistor coupled between the input of the second inverter circuit and the rail, the gate of the fourth transistor being coupled to the output of the second inverter circuit.

13. 13. The regeneration circuit of claim 12, wherein the third transistor comprises a first p-type field effect transistor (PFET); and the fourth transistor comprises a second PFET.

14. the source of the first PFET is coupled to the rail and the drain of the first PFET is coupled to the input of the first inverter circuit; 14. The regeneration circuit of claim 13, wherein the source of the second PFET is coupled to the rail and the drain of the second PFET is coupled to the input of the second inverting circuit.

15. The pull-down circuit a third transistor coupled between the input of the first inverter circuit and a rail, the gate of the third transistor being coupled to the input of the second inverter circuit or the output of the first inverter circuit; a fourth transistor coupled between the input of the second inverter circuit and the rail, the gate of the fourth transistor being coupled to the input of the first inverter circuit or the output of the second inverter circuit.

16. 16. The regeneration circuit of claim 15, wherein the third transistor comprises a first n-type field effect transistor (NFET); and the fourth transistor comprises a second NFET.

17. the drain of the first NFET is coupled to the input of the first inverter circuit and the source of the first NFET is coupled to the rail; 17. The regeneration circuit of claim 16, wherein the drain of the second NFET is coupled to the input of the second inverter circuit and the source of the second NFET is coupled to the rail.

18. 16. The regeneration circuit of claim 15, wherein the rail is coupled to ground.

19. a first switch coupled between the first transistor and the output of the first inverter circuit; 12. The regeneration circuit of claim 11, comprising: a second switch coupled between the second transistor and the output of the second inverter circuit.

20. 20. The regeneration circuit of claim 19, wherein the first switch has a control input configured to receive a timing signal, and the second switch has a control input configured to receive the timing signal.

21. 1. A method of operating a recovery circuit of a sampler, the recovery circuit including a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, a second transistor coupled to the input of the first inverting circuit, a third transistor, and a fourth transistor, the method comprising: During the reset phase, disabling regenerative feedback of the first inverter circuit and the second inverter circuit; During the regeneration phase, enabling the regenerative feedback of the first inverter circuit and the second inverter circuit; driving a gate of the first transistor and a gate of the third transistor with a first voltage; driving the gate of the second transistor and the gate of the fourth transistor with a second voltage; coupling the third transistor to the output of the first inverting circuit or coupling the fourth transistor to the output of the second inverting circuit.

22. 22. The method of claim 21, wherein during the regeneration phase, the first voltage decreases at a first rate and the second voltage decreases at a second rate, the first rate being different from the second rate.

23. 23. The method of claim 22, wherein the first rate is based on a first input signal to the sampler and the second rate is based on a second input signal to the sampler.

24. 24. The method of claim 23, wherein the first rate is greater than the second rate when the first input signal is greater than the second input signal, and the second rate is greater than the first rate when the second input signal is greater than the first input signal.

25. Coupling the third transistor to the output of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit coupling the third transistor to the output of the first inverter circuit when the first rate is greater than the second rate; 23. The method of claim 22, comprising coupling the fourth transistor to the output of the second inverter circuit if the second rate is greater than the first rate.

26. Coupling the third transistor to the output of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit 23. The method of claim 22, comprising coupling the third transistor to the output of the first inverting circuit based on a voltage at the input of the first inverting circuit or coupling the fourth transistor to the output of the second inverting circuit based on a voltage at the input of the second inverting circuit.

27. 22. The method of claim 21, further comprising pulling up the first voltage and the second voltage to a supply voltage during the reset phase.

28. the first transistor comprises a first n-type field effect transistor (NFET); the second transistor comprises a second NFET; the third transistor comprises a first p-type field effect transistor (PFET); 22. The method of claim 21 , wherein the fourth transistor comprises a second PFET.

29. Disabling the regenerative feedback of the first inverter circuit and the second inverter circuit decoupling the output of the first inverter circuit from the first transistor; decoupling the output of the second inverter circuit from the second transistor; Enabling the regenerative feedback of the first inverter circuit and the second inverter circuit includes: coupling the output of the first inverter circuit to the first transistor; and coupling the output of the second inverter circuit to the second transistor.

Images