Cyclic development of metal oxide based photoresist for etch stop deterrence

Abstract

SOLUTION: Provided are processes for development of photopatterned metal or metal oxide-based thin film photoresists post-EUV exposure for removal of non-volatile species and preventing etch stop. Repeated cycles of alternating treatment with an etchant and an oxidizing agent, or treatment with an etchant followed by treatment with a rinsing solution, are effective techniques for removal of the undesired unexposed portion of a photoresist.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Incorporation by Reference A PCT application is being filed concurrently herewith as part of this application, and each application identified in that concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process involving photolithography. Generally, this process involves depositing material onto a wafer and patterning the material using lithographic techniques to form the structural features (e.g., transistors and circuits) of the semiconductor device. Typical photolithography process steps known in the art include preparing a substrate, applying a photoresist, such as by spin coating, exposing the photoresist to light in a desired pattern to render the exposed areas of the photoresist somewhat soluble in a developer, developing by applying a developer to remove either the exposed or unexposed areas of the photoresist, and subsequent processing, such as by etching or material deposition, to form features on the areas of the substrate where the photoresist was removed.

[0003] One challenge in fabricating devices with such small features is the ability to reliably and reproducibly form photolithography masks of sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. The fact that the light has a wavelength significantly longer than the desired size of the features to be fabricated on the semiconductor substrate creates inherent problems. Achieving feature sizes smaller than the wavelength of light requires the use of complex resolution enhancement techniques, such as multi-patterning. Therefore, significant interest and research effort has been focused on developing photolithography techniques that use short-wavelength light, such as extreme ultraviolet (EUV) light, with wavelengths of 10 nm to 15 nm, e.g., 13.5 nm.

[0004] However, EUV photolithography processes can present challenges, such as power degradation and light loss during patterning. Conventional organic chemically amplified resists (CARs), similar to those used in 193 nm UV lithography, have potential drawbacks when used with EUV lithography due to their low absorption coefficients, particularly in the EUV region, and the potential for blurring or line-edge roughness due to diffusion of photoactivated species. Furthermore, to provide the etch resistance necessary to pattern underlying device layers, small features patterned with conventional CAR materials can result in high aspect ratios that risk pattern collapse. Therefore, there remains a need for improved EUV photoresist materials with properties such as reduced thickness, greater absorbance, and greater etch resistance.

[0005] The background description provided herein is intended to provide a general overview of the present technology. Work by the currently named inventors within the scope of what is described in this background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present technology. Summary of the Invention

[0006] A process is provided for the development of metal or metal oxide-based thin film photoresists after EUV exposure to remove non-volatile species and prevent etch stop. Repeated cycles of alternating treatment with an etchant and an oxidant, or treatment with an etchant followed by a cleaning agent, are effective techniques for removing the unwanted unexposed portions of the photoresist.

[0007] Accordingly, in a first aspect, the present invention encompasses a method for processing a semiconductor substrate. In some embodiments, the method includes providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber, and developing the photopatterned metal-containing resist to form a resist mask by selectively removing portions of the photopatterned metal-containing resist by exposing the photopatterned metal-containing resist to at least one cycle comprising alternatingly delivered pulses of an etchant and a pulse of an oxidizer.

[0008] In some embodiments, the etchant pulse and the oxidizer pulse are separated in time.

[0009] In some embodiments, the pedestal is at a first temperature during the pulse of etchant, and an oxidizer is delivered to the process chamber at a second temperature.

[0010] In some embodiments, the pedestal is at a first temperature during the pulse of etchant, and the pedestal is at a second temperature during the pulse of oxidant.

[0011] In some embodiments, the duration of the etchant pulse is from about 1 to about 120 seconds, and the duration of the oxidizer pulse is from about 1 to about 120 seconds.

[0012] In some embodiments, the first temperature is from about -60°C to about 120°C.

[0013] In some embodiments, the second temperature is from about 20°C to about 150°C.

[0014] In some embodiments, the second temperature is from about 50°C to about 250°C.

[0015] In some embodiments, non-volatile by-products of the pulse of etchant are removed from the photopatterned metal-containing resist.

[0016] In some embodiments, the photopatterned metal-containing resist is an organometallic oxide, a metal oxide, a metal, or an organometallic.

[0017] In some embodiments, the metal oxide is tin oxide.

[0018] In some embodiments, the etchant is a halide etchant.

[0019] In some embodiments, the halide etchant is a hydrogen halide, hydrogen gas and a halogen gas, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a combination thereof.

[0020] In some embodiments, the halide etchant is hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof.

[0021] In some embodiments, the etchant is an etchant plasma.

[0022] In some embodiments, the etchant plasma is generated remotely.

[0023] In some embodiments, the oxidizing agent is oxygen, ozone, hydrogen peroxide, water, nitrous oxide, nitric oxide, nitrogen dioxide, nitric acid, sulfur dioxide, chlorine, fluorine, bromine, iodine, or a combination thereof.

[0024] In some embodiments, the oxidizer is a gaseous oxidizer of water and oxygen or chlorine.

[0025] In some embodiments, the oxidizer is an oxidizer plasma.

[0026] In some embodiments, the oxidizer plasma is generated remotely.

[0027] In some embodiments, the method also includes exposing the photopatterned metal-containing resist to an inert plasma gas.

[0028] In some embodiments, the method also includes purging the process chamber with an inert gas between pulses of the etchant and the oxidizer, or after cycles of pulses of the etchant and the oxidizer.

[0029] In some embodiments, developing the photo-patterned metal-containing resist by exposure to alternating pulses of an etchant and an oxidant is dry developing the photo-patterned metal-containing resist.

[0030] In some embodiments, developing the photo-patterned metal-containing resist by exposure to alternating pulses of an etchant and an oxidant is wet developing the photo-patterned metal-containing resist.

[0031] In some embodiments, each cycle has the same etchant pulse duration.

[0032] In a second aspect, the invention encompasses a method of processing a semiconductor substrate. In some embodiments, the method includes providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber, and developing the photopatterned metal-containing resist to form a resist mask by exposing the photopatterned metal-containing resist to an etchant followed by exposure to a cleaning agent to selectively remove portions of the photopatterned metal-containing resist.

[0033] In some embodiments, the cleaning agent is water, methanol, ethanol, isopropanol, acetone, acetonitrile, tetrahydrofuran, dimethyl sulfide, or a combination thereof.

[0034] In some embodiments, the pedestal temperature is from about 10° C. to about 50° C. during exposure to the cleaning agent.

[0035] In some embodiments, the cleaning agent is a supercritical fluid.

[0036] In some embodiments, the supercritical fluid is a low surface tension supercritical liquid.

[0037] In some embodiments, the low surface tension supercritical liquid is carbon dioxide, sulfur dioxide, dimethyl ether, or a combination thereof.

[0038] In some embodiments, the process chamber pressure is from about 5 psi to about 3,000 psi during exposure to the cleaning agent.

[0039] In some embodiments, non-volatile by-products from exposure to the etchant are removed from the photopatterned metal-containing resist.

[0040] In some embodiments, the photopatterned metal-containing resist is an organometallic oxide, a metal, a metal oxide, or an organometallic.

[0041] In some embodiments, the metal oxide is tin oxide.

[0042] In some embodiments, the etchant is a halide etchant.

[0043] In some embodiments, the halide etchant is a hydrogen halide, hydrogen gas and a halogen gas, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a combination thereof.

[0044] In some embodiments, the halide etchant is hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof.

[0045] In some embodiments, the etchant is an etchant plasma.

[0046] In some embodiments, the etchant plasma is generated remotely.

[0047] In a third aspect, the invention encompasses a method for facilitating atomic layer etching on a substrate. In some embodiments, the method includes providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber, and developing the photopatterned metal-containing resist to form a resist mask by selectively removing portions of the resist by exposing the photopatterned metal-containing resist to at least one cycle comprising alternating pulses of an etchant and a pulse of an oxidizer, thereby eliminating etch stopping due to non-volatile by-products of the etchant pulses.

[0048] In a fourth aspect, the invention encompasses a method of processing a semiconductor substrate. In some embodiments, the method includes providing a dry-deposited photo-patterned metal oxide EUV resist on a semiconductor substrate on a pedestal in a process chamber, and dry-developing the photo-patterned metal oxide EUV resist to form a resist hard mask by selectively removing non-EUV exposed portions of the EUV resist by exposing it to at least one cycle comprising alternatingly delivered pulses of an etchant and a pulse of an oxidizer.

[0049] In a fifth aspect, the invention encompasses an apparatus for developing a resist. In some embodiments, the apparatus includes a process chamber having a substrate support, a vacuum line coupled to the process chamber, etchant and oxidant lines coupled to the process chamber, and a controller configured with instructions for processing a semiconductor substrate, the instructions including code for providing a photopatterned metal-containing resist on the semiconductor substrate in the process chamber and developing the photopatterned metal-containing resist by selectively removing portions of the resist by exposing it to at least one cycle of alternatingly delivered etchant and oxidant pulses to form a resist mask.

[0050] In some embodiments, the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the controller configured with instructions including code for developing the photo-patterned metal-containing EUV resist has code for selectively removing EUV-unexposed portions of the EUV resist compared to EUV-exposed portions with at least one cycle of alternatingly delivered etchant and oxidizer pulses to form a resist mask.

[0051] In some embodiments, the apparatus also includes one or more heaters coupled to the substrate support, the one or more heaters including multiple independently controllable temperature control zones.

[0052] In some embodiments, the apparatus also includes a heated oxidant delivery line.

[0053]

[0054] These and other features of the disclosed embodiments are described in detail below with reference to the associated drawings. [Brief explanation of the drawings]

[0055] [Figure 1] FIG. 1 is a flow diagram of an exemplary cyclic method for depositing and developing photoresist, in accordance with certain disclosed embodiments.

[0056] [Figure 2] FIG. 2 is a diagram illustrating a pulse sequence for a hydrogen bromide (HBr) etchant and a chlorine (Cl 2 ) oxidizer for developing photoresist, according to certain disclosed embodiments.

[0057] [Figure 3A] FIG. 3A illustrates a graph of the effect of chlorine oxidizer on residual by-product thickness at varying temperatures, in accordance with certain disclosed embodiments.

[0058] [Figure 3B] FIG. 3B illustrates a graph of the effect of hydrogen bromide etchant on residual byproduct thickness when the total etchant exposure time is fixed but the etchant pulse duration for each cycle is varied, in accordance with certain disclosed embodiments.

[0059] [Figure 3C] FIG. 3C illustrates a graph of the effect of chlorine oxidizer on residual by-product thickness as oxidizer pulse duration is varied, in accordance with certain disclosed embodiments.

[0060] [Figure 4]FIG. 4 shows scanning electron microscope (SEM) images of a photopatterned substrate that underwent dry deposition with an etchant (single DD) compared to a photopatterned substrate that underwent cyclic dry development with an etchant and a chlorine oxidizer (cyclic DD) according to certain disclosed embodiments.

[0061] [Figure 5] FIG. 5 shows a graphical comparison of dry deposition with etchant (single DD) compared to cyclic dry development with etchant and air oxidizer (cyclic DD), according to certain disclosed embodiments.

[0062] [Figure 6] FIG. 6 is a flow diagram of an exemplary method for depositing and developing photoresist utilizing an etchant in conjunction with a cleaning agent, according to certain disclosed embodiments.

[0063] [Figure 7] FIG. 7 is a schematic diagram of an exemplary process station for maintaining a low-pressure environment suitable for carrying out methods in accordance with certain disclosed embodiments.

[0064] [Figure 8] FIG. 8 is a schematic diagram of an exemplary multi-station processing tool suitable for implementing various operations in accordance with certain disclosed embodiments.

[0065] [Figure 9] FIG. 9 is a cross-sectional schematic diagram of an exemplary inductively coupled plasma apparatus for implementing certain operations according to certain disclosed embodiments.

[0066] [Figure 10] FIG. 10 is a diagram illustrating a semiconductor process cluster tool architecture having a vacuum-integrated deposition and patterning module interfaced with a vacuum transfer module, suitable for implementing methods according to certain disclosed embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0067] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments.

[0068] The embodiments disclosed below describe the deposition of materials onto a substrate, such as a wafer, substrate, or other workpiece. The workpieces can be of various shapes, sizes, and materials. In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer at any of the many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. Unless otherwise specified, process details (e.g., flow rates, power levels, etc.) described herein relate to the processing of 300 mm diameter substrates or processing chambers configured to process 300 mm diameter substrates and that can be scaled for other sized substrates or chambers. In addition to semiconductor wafers, other workpieces that can be used in the embodiments disclosed herein include various articles, such as printed circuit boards. The processes and apparatus can be used in the fabrication of semiconductor devices, displays, LEDs, solar panels, and the like.

[0069] By halide is meant the anion of F, Cl, Br, or I.

[0070] As used herein, the term "about" means + / - 10% of any recited value, unless otherwise specified. As used herein, the term modifies any recited value, range of values, or one or more endpoints of a range.

[0071] As used herein, the terms "top," "bottom," "upper," "lower," "above," and "below" are used to provide relative relationships between structures. The use of these terms does not indicate or require that a particular structure must be located in a particular location within the device.

[0072] As used herein, the phrase at least one of A, B, and C should be interpreted in the sense of a logical (A or B or C) using a non-exclusive logical OR, and not in the sense of "at least one of A, at least one of B, and at least one of C."

[0073] "Atomic layer deposition" (ALD) refers to a vapor-phase deposition process in which deposition cycles, preferably multiple consecutive deposition cycles, are performed within a process chamber (i.e., a deposition chamber). Typically, during each cycle, a precursor is chemisorbed onto the deposition surface (i.e., the substrate assembly surface or a previously deposited underlying surface, such as material from a previous ALD cycle), forming a monolayer or quasi-monolayer that does not readily react with additional precursors (i.e., self-limiting reaction). Thereafter, if desired, a reactant (i.e., another precursor or reactant gas) can be introduced into the process chamber for use in converting the chemisorbed precursor to the desired material on the deposition surface. Typically, this reactant is capable of reacting with the already chemisorbed precursor. Additionally, a purge step can be utilized during each cycle to remove excess precursor from the process chamber after conversion of the chemisorbed precursor and / or to remove excess reactant and / or reaction by-products from the process chamber.

[0074] "Deposition" or "vapor deposition" refers to a process in which a metal layer is formed on one or more surfaces of a substrate from a vaporized precursor composition containing one or more metal-containing compounds. The metal-containing compounds are vaporized and directed toward and / or contacted with one or more surfaces of a substrate (i.e., a semiconductor substrate or semiconductor assembly) placed in a deposition chamber. Typically, the substrate is heated. These metal-containing compounds form a non-volatile, thin, uniform metal-containing layer on the surface of the substrate. One operation of the method is one cycle, and the process can be repeated as many times as necessary to obtain the desired metal thickness.

[0075] "Etchant" means any compound used to remove material, such as a layer, by-product, or contaminant, from a surface.

[0076] "Water" refers to materials that may include the substrate and substrate layer to be etched. In some embodiments, the substrate layer comprises an ashing hard mask such as spin-on carbon (SoC) or other materials, e.g., silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, the substrate layer may be a layer stack disposed on a substrate.

[0077] A "photopatterned metal-containing resist film" refers to a thin film that may include an organic metal-containing layer disposed on a substrate layer to be etched. The photopatterned metal-containing EUV resist film may have a thickness of about 5 nm to about 50 nm, or about 10 nm to about 30 nm. The photopatterned metal-containing EUV resist film may be provided in a process chamber after photopatterning in an EUV scanner and / or after PEB treatment, as described above. The photopatterned metal-containing EUV resist film includes non-EUV-exposed regions and EUV-exposed regions. The non-EUV-exposed regions of the photopatterned metal-containing EUV resist film can be removed in a dry development process by exposing them to a flow of dry development chemicals without applying a plasma. The dry development chemicals may include halide-containing chemicals, such as hydrogen halide or hydrogen and halogen gas. Removal of the non-EUV-exposed regions after development forms a resist mask. The resist mask can then be used to etch the substrate layer to provide the desired structure.

[0078] "By-product" means any compound that may be an impurity, decomposition product, or contaminant of the gas delivered to the deposition chamber.

[0079] "Delivery line" means any process equipment, such as piping, tubing, or conduit, that may be utilized to transport or convey gases (e.g., reactants and / or precursors). In semiconductor manufacturing processes, precursor delivery lines may be used to transport precursors to deposition chambers and may be formed from stainless steel or nickel alloys.

[0080] The present disclosure generally relates to the field of semiconductor processing. In some embodiments, the present disclosure is directed to a process and apparatus for developing photoresist (e.g., EUV-sensitive metal and / or metal oxide-containing photoresist) using 1) an etchant in combination with an oxidizer in a cyclic dry development process, or 2) an etchant in combination with a cleaning agent, to form a patterning mask in the context of EUV patterning. Such a process can advantageously widen the process window of dry development and / or extend the applicability of dry development to different metal or metal oxide-based photoresist systems.

[0081] Reference will be made in detail herein to specific embodiments of the present disclosure. Examples of specific embodiments are illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the disclosure to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0082] Patterning thin films in semiconductor processing is often a critical step in semiconductor fabrication. Patterning involves lithography. In traditional photolithography, such as 193 nm photolithography, patterns are printed by emitting photons from a photon source onto a mask and printing the pattern onto a light-sensitive photoresist, which causes a chemical reaction within the photoresist that, after development, removes certain portions of the photoresist to form the pattern.

[0083] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include the 22 nm, 16 nm, and beyond. For example, at the 16 nm node, the width of a typical via or line in a damascene structure is typically about 30 nm or less. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices drives lithography to improve resolution.

[0084] Extreme ultraviolet (EUV) lithography can extend lithography technology by moving to shorter imaging source wavelengths than are achievable with traditional photolithography methods. EUV sources with wavelengths of approximately 10-20 nm, or even 11-14 nm, such as 13.5 nm, can be used in cutting-edge lithography tools, also known as scanners. EUV radiation is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor, so it operates in a vacuum.

[0085] EUV lithography utilizes an EUV resist that is patterned to form a mask used to etch the underlying layer. The EUV resist may be a polymer-based chemically amplified resist (CAR) obtained by a liquid-based spin-on technique. An alternative to CAR is a directly photopatternable metal oxide-containing film, such as those available from Inpria, Corvallis, Oregon, and described in U.S. Patent Application Publication Nos. 2017 / 0102612, 2016 / 021660, and 2016 / 0116839, which are incorporated herein by reference at least for their disclosure of photopatternable metal oxide-containing films. Such films may be obtained by spin-on techniques or dry vapor deposition. Metal oxide-containing films can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum atmosphere providing patterning resolution of less than 30 nm, as described, for example, in U.S. Patent No. 9,996,004, issued June 12, 2018, and entitled "EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARD MASKS," and / or application PCT / US19 / 31618, filed May 9, 2019, and entitled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," the disclosures of which, at least pertaining to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks, are incorporated herein by reference. Generally, patterning involves exposing an EUV resist to EUV radiation to form a photopattern in the resist, followed by development to remove portions of the resist according to the photopattern and form the mask.

[0086] While this disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it should also be understood that it is applicable to other next-generation lithography techniques. In addition to EUV, which includes the standard 13.5 nm EUV wavelength currently in use and under development, the most relevant radiation sources for such lithography are DUV (deep UV), which generally refers to the use of 248 nm or 193 nm excimer laser sources; X-ray, formally including EUV in the lower energy range of the X-ray range; and e-beam, which can cover a wide energy range. Specific methods may depend on the specific materials and applications used in the semiconductor substrate and final semiconductor device. Therefore, the methods described in this application are merely exemplary of methods and materials that may be used in the present technology.

[0087] Directly photopatternable EUV resists can be composed of or contain metals and / or metal oxides mixed within organic components. Metals / metal oxides hold great promise in that they can enhance EUV photon absorption, generate secondary electrons, and / or exhibit high etch selectivity relative to underlying film stacks and device layers. To date, these resists have been developed using wet (solvent) techniques, which require the wafer to be moved onto a track where it is exposed to a developing solvent, dried, and baked. Wet development not only limits productivity but can also cause line collapse due to surface tension effects and / or delamination.

[0088] Dry development techniques have been proposed to overcome these problems by eliminating substrate delamination and interfacial breakdown. Dry development can improve performance (e.g., by preventing line collapse and delamination due to surface tension in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages may include the elimination of the use of organic solvent developers, reduced sensitivity to adhesion issues, increased EUV absorption due to improved dose efficiency, and elimination of solubility-based limitations. Dry development also offers additional tunability, potentially enabling further critical dimension (CD) control and scum removal.

[0089] Dry development presents its own challenges, including etch selectivity between unexposed and EUV-exposed resist materials, which can result in higher dose to size requirements for effective resist exposure when compared to wet development. Suboptimal selectivity can also lead to rounding of PR corners due to prolonged exposure under etching gases, which can increase line CD variability in the subsequent transfer etch step.

[0090] EUV resist development According to various aspects of the present disclosure, a photopatterned metal-containing photoresist is developed by exposure to a halide-containing chemical. An EUV-sensitive metal or metal oxide-containing film, such as an organotin oxide, is disposed on a semiconductor substrate. The EUV-sensitive metal or metal oxide-containing film is directly patterned by EUV exposure in a vacuum atmosphere. The pattern is then developed using a development chemical to form a resist mask. In some embodiments, the development chemical is a dry development chemical. In some embodiments, the dry development chemical includes hydrogen and a halide. Such dry development techniques can be performed using either a mild plasma (high pressure, low power) or a thermal process while flowing a hydrogen and halide dry development chemical. The present disclosure provides processes and apparatus configured to develop metal-containing resist as part of a resist mask formation process.

[0091] Metal and / or metal oxide photoresists are attractive material candidates for advanced photolithography. Their ability to function at higher resolution, higher etch selectivity, and lower doses allows for enhanced photoabsorption and secondary electron generation. After EUV exposure, wet development is conventionally applied to remove unwanted materials. However, this process can lead to increased defects due to surface tension-induced interface failure and / or line collapse.

[0092] Dry development helps overcome these problems by eliminating substrate delamination and interfacial failure. However, complete removal of the unwanted, unexposed portions of the photoresist depends on the generation of volatile, stable by-products of dry development. The volatility and stability of by-products from dry development can be affected by the organic ligands utilized in metal and / or metal oxide photoresist systems. In some cases, the by-products are non-volatile or volatile but unstable. When the by-products are volatile but unstable, they can further decompose into non-volatile species. Non-volatile by-products result in etch stops and incomplete development, increasing the risk of high surface roughness and defect formation.

[0093] An optional post-application bake (PAB) is performed after deposition of the EUV-patternable film and before EUV exposure. The PAB treatment can involve a combination of thermal treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV-patternable film, thereby reducing the EUV dose to develop a pattern in the EUV-patternable film. The PAB treatment temperature can be adjusted and optimized to increase the sensitivity of the EUV-patternable film. For example, the treatment temperature can be about 90°C to about 200°C, or about 150°C to about 190°C. In some embodiments, the PAB treatment can be performed at a pressure between atmospheric pressure and vacuum for a treatment duration of about 1 to 15 minutes, e.g., about 2 minutes. In some embodiments, the PAB treatment is performed at a temperature of about 100°C to 200°C for about 1 to 2 minutes.

[0094] The metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally speaking, EUV exposure causes changes in the chemical composition and crosslinking in the metal-containing EUV resist film, resulting in etch selectivity contrast that can be exploited in subsequent development.

[0095] The metal-containing EUV resist film can then be patterned by exposing regions of the film to EUV light, typically under relatively high vacuum. EUV devices and imaging methods useful herein include those known in the art. In particular, as described above, exposed areas of the film are formed by EUV patterning with altered physical or chemical properties compared to unexposed areas. For example, in exposed areas, cleavage of metal-carbon bonds can occur via beta-hydride elimination, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxides and bridging metal oxide moieties via metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to create chemical contrast for development as a negative resist. In general, the higher the number of beta-H groups in the alkyl group, the more sensitive the film. This can also be described as weaker Sn-C bonds with more branching. Following exposure, baking the metal-containing EUV resist film can result in further crosslinking of the metal oxide film. The difference in properties between the exposed and unexposed areas can be exploited in subsequent processing, such as dissolving the unexposed areas or depositing material in the exposed areas. For example, the pattern can be developed using dry methods to form a metal oxide-containing mask.

[0096] In particular, in various embodiments, hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed regions of the imaging layer, particularly when the exposure is carried out in a vacuum using EUV. However, removing the exposed imaging layer from vacuum to air or the controlled introduction of oxygen, ozone, HO, or water can oxidize the surface Sn-H to Sn-OH. The difference in properties between the exposed and unexposed regions can be exploited in subsequent processing, for example, by reacting the irradiated regions, the unirradiated regions, or both, with one or more reagents to selectively add or remove material from the imaging layer.

[0097] Without limiting the mechanism, function, or utility of the present technology, for example, 10 mJ / cm 2 ~100mJ / cm 2 EUV exposure at doses of 1000 nm leads to the cleavage of Sn-C bonds, which results in the loss of alkyl substituents, relieves steric hindrance, and allows the low-density film to collapse. In addition, the reactive metal-H bonds generated in the beta-hydride elimination reaction can react with neighboring active groups, such as hydroxyls, in the film, which can lead to further crosslinking and densification, creating chemical contrast between exposed and unexposed regions.

[0098] After exposing the metal-containing EUV resist film to EUV light, a photopatterned metal-containing EUV resist is provided, which includes EUV-exposed regions and EUV-unexposed regions.

[0099] An optional post-exposure bake (PEB) is performed to further enhance the etch selectivity contrast of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist can be thermally treated in the presence of various chemical species to promote crosslinking of the EUV-exposed regions, or can simply be baked on a hotplate in ambient air, for example, at 150°C to 250°C for 1 to 5 minutes (e.g., 190°C for 2 minutes).

[0100] In various embodiments, the bake strategy involves careful control of the bake atmosphere, the introduction of reactive gases, and / or the rate of increase in bake temperature. Examples of useful reactive gases include, for example, air, HO, HO vapor, CO, CO, O, O, CH, CHOH, N, H, NH, NO, NO, alcohol, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB process is designed to (1) drive complete evaporation of organic fragments generated during EUV exposure, (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure to metal hydroxides, and (3) promote crosslinking between adjacent Sn-OH groups to form a more densely crosslinked SnO-like network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. A PEB temperature that is too low can result in insufficient crosslinking, resulting in reduced chemical contrast for development at a given dose. Too high a PEB temperature can also result in adverse effects such as severe oxidation and film shrinkage in unexposed areas (in this example, areas removed by development of the patterned film to form the mask) and undesirable interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlayer, both of which can contribute to loss of chemical contrast due to insoluble scum and increased defect density. The PEB treatment temperature can be about 100°C to about 300°C, about 170°C to about 290°C, or about 200°C to about 240°C. In some embodiments, the PEB treatment can be performed at a pressure between atmospheric and vacuum for a treatment duration of about 1 to 15 minutes, e.g., about 2 minutes. In some embodiments, the PEB thermal treatment can be repeated to further enhance etch selectivity.

[0101] The photopatterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, either the exposed regions are removed (positive tone) or the unexposed regions are removed (negative tone). In some embodiments, development can include selective deposition of the photopatterned metal-containing EUV resist onto either the exposed or unexposed regions, followed by an etching operation. In various embodiments, these processes can be dry or wet processes. Development can be performed without applying a plasma in some embodiments. Alternatively, development can be performed with a flow of hydrogen and halides (e.g., H2, Cl2, and / or Br2) activated in a remote plasma source or by exposure to remote UV radiation. The photoresist for development can include elements selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The elements can have a high patterning radiation absorption cross section. In some embodiments, the elements can have a high EUV absorption cross section. In some embodiments, metal-containing EUV resists can have an overall absorption of greater than 30%, which in an all-dry lithography process allows for more efficient utilization of EUV photons and allows for the development of thicker and more EUV-opaque resists.

[0102] An example of a development process involves subjecting an organotin oxide-containing EUV-sensitive photoresist film (e.g., 10-30 nm thick, e.g., 20 nm) to an EUV exposure dose and a post-exposure bake, followed by development. The photoresist film may be deposited based on the gas-phase reaction of an organotin precursor, such as isopropyl(tris)(dimethylamino)tin, with water vapor, or may be a spin-on film containing tin clusters in an organic matrix.

[0103] The photopatterned metal-containing EUV resist is developed by exposure to a development chemical, which is a halide-containing chemical. In some embodiments, the development chemical includes hydrogen and a halide, such as a hydrogen halide (e.g., HBr or HCl) or hydrogen and a halogen gas (e.g., H and Cl). In some embodiments, the development chemical includes a hydrogen halide, hydrogen and a halogen gas, boron trichloride, or a combination thereof. The EUV resist can be developed by wet development using a halide-containing chemical or by dry development using a hydrogen halide-containing chemical. In embodiments in which the EUV resist is developed using wet development, the wet development can be combined with other wet processing operations, such as wet deposition (e.g., spin-on deposition) of a metal-containing EUV resist film. Alternatively, the wet development can be combined with other dry processing operations, such as vapor deposition (e.g., CVD) of a metal-containing EUV resist film. In embodiments in which the EUV resist is developed using dry development, the dry development can be combined with other dry processing operations, such as dry deposition (e.g., CVD) of a metal-containing EUV resist film. In alternative embodiments in which the EUV resist is developed using dry development, the dry development may be combined with other wet processing operations, such as wet deposition (e.g., spin-on deposition) of a metal-containing EUV resist film.

[0104] In some embodiments, semiconductor substrate processing may combine all dry steps, including vapor deposition film formation, EUV lithography patterning, and dry development. In fact, each of operations 102-112 of process 100 may be a dry processing operation. Such processing operations may avoid the material and production costs associated with wet processing operations, such as wet development. Dry processing may offer additional tunability, enabling better critical dimension (CD) control and scum removal. Wet processing generally involves moisture and / or oxygen, which more readily leads to scum formation. While wet development is limited by solubility and cluster size, dry development is not. Wet development is more prone to pattern collapse and delamination issues that dry development avoids. Additionally, using all dry processing operations may facilitate integration within interconnected vacuum processing chambers without exposure to and contamination from ambient air or trace contaminants contained in the ambient air. For example, the PEB heat treatment, in which the exposed regions undergo further cross-linking, may occur in the same chamber as development, although it will be appreciated that the PEB heat treatment may also be performed in a separate chamber.

[0105] The development process can be carried out by delivering developer chemicals in the liquid or vapor phase. In some embodiments, the dry development process can be carried out by using either a mild plasma (high pressure, low power) or thermal process while flowing a hydrogen halide-containing dry development chemical, such as HF, HCl, HBr, or HI. For example, dry development can be carried out with a thermal process using a dry development chemical, such as HCl or HBr. In some embodiments, the hydrogen halide-containing chemical can rapidly remove unexposed material, leaving a pattern of exposed film that can be transferred to an underlying layer by a plasma-based etching process, e.g., a conventional etching process.

[0106] In a thermal development process, the substrate is exposed to a development chemical (e.g., a Lewis acid) in a process chamber (e.g., an oven). In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a development chemical line may be coupled to the process chamber for delivering the development chemical to the process chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the chamber interior may be coated with a corrosion-resistant film, such as an organic polymer or inorganic coating. One such coating is polytetrafluoroethylene (PTFE), e.g., Teflon 1M. Such materials can be used in the thermal processes of the present disclosure without the risk of removal by plasma exposure.

[0107] In a thermal development process, the photopatterned metal-containing EUV resist is exposed to a development chemistry at a temperature that optimizes the etch selectivity between exposed and unexposed regions. Lower temperatures can increase the contrast in etch selectivity, while higher temperatures can decrease the contrast in etch selectivity. In some embodiments, the temperature can be about −60° C. to about 120° C., about −20° C. to about 60° C., or about −20° C. to about 20° C., e.g., about −10° C. The chamber pressure can be adjusted, and can affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the chamber pressure can be relatively low and without dilution, and the chamber pressure can be about 0.1 mTorr to about 300 mTorr, about 0.2 mTorr to about 100 mTorr, or about 0.5 mTorr to about 50 mTorr. In some embodiments, the chamber pressure may be about 20 mTorr to about 800 mTorr, or about 20 mTorr to about 500 mTorr, for example, about 300 mTorr. In some embodiments, the chamber pressure may be relatively high with high flow rates and accompanied by dilution, and the chamber pressure may be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The flow rate of the reactant can be adjusted, and the flow of the reactant can affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the flow of the reactant can be about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 100 sccm to about 1000 sccm, for example, about 500 sccm. At high flow rates, the flow of the reactant can be about 1 L to about 10 L. The duration of exposure can be adjusted during the thermal development process. The duration of exposure can depend on, among other factors, the amount of resist desired to be removed, the development chemistry, the amount of crosslinking in the resist, and the composition and properties of the resist, hi some embodiments, the duration of exposure can be from about 5 seconds to about 5 minutes, from about 10 seconds to about 3 minutes, or from about 10 seconds to about 1 minute.

[0108] The thermal development process can expose the photopatterned metal-containing EUV resist to certain halide-containing chemicals in the gas or liquid phase. In some embodiments, the development chemicals include hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. Hydrogen halides can include, but are not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halide can be HCl or HBr. Hydrogen and halogen gases can include, but are not limited to, hydrogen gas (H) mixed with F, Cl, Br, or I. Boron trichloride (BCl) can be used in combination with any of the aforementioned hydrogen halides or hydrogen and halogen gases. Organic halides can include, but are not limited to, C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z where x, y, and z are values ​​greater than or equal to 0. Acyl halides can include, but are not limited to, CHCOF, CHCOCl, CHCOBr, and CHCOI. Carbonyl halides can include, but are not limited to, COF, COCl, COBr, and COI. Thionyl halides can include, but are not limited to, SOF, SOCl, SoBr, and SOI. In some embodiments, the halide-containing chemicals can be flowed with or without an inert / carrier gas, such as He, Ne, Ar, Xe, and N.

[0109] In the formation of semiconductor devices, various layers can be selectively etched. Atomic layer etching can be used to provide highly selective etching. Atomic layer etching (ALE) provides a cyclic process. The cyclic process can have a first step of modifying a portion of the etched layer and a second step of removing the modified portion of the etched layer. Such ALE can modify a portion of the etched layer using a self-limiting process. The self-limiting process can modify several monolayers of the etched layer, forming a self-limiting layer. In such cases, removal of the modified portion of the etched layer can remove only a few atomic layers of the etched layer. As a result, many cycles are required to etch a substantial portion of the etched layer. Each cycle can be longer than 12 seconds. As a result, the ALE process can take a long time to etch a substantial portion of the etched layer.

[0110] ALE processes used to etch carbon-containing etch layers, such as amorphous carbon, use a low bias voltage. In such processes, a low bias voltage can be applied for several seconds to perform ALE while preventing or reducing sputtering caused by higher biases. Some drawbacks to such processes using a low bias are that such ALE processes are slow and the ions at low bias for ALE processes are not highly directional. Because the ions are not highly directional, the resulting features do not have a high aspect ratio (height to width).

[0111] Atomic layer etching processes are described in U.S. Patent No. 10,566,212 to Kanarik entitled "Designer Atomic Layer Etching," issued on February 18, 2020; U.S. Patent No. 10,763,083 to Yang et al. entitled "High Energy Atomic Layer Etching," issued on September 1, 2020; U.S. Patent Application Publication No. 2021 / 0005425 to Yang et al. entitled "Atomic Layer Etching and Smoothing of Refractory Metals and Other High Surface Binding Energy Materials," published on January 2, 2021; International Publication No. WO 2020 / 223152 to Yang et al. entitled "Atomic Layer Etching for Subtractive Metal Etch," published on November 5, 2020; and International Publication No. WO 2020 / 223152 to Yang et al. entitled "Fast Atomic Layer Etching for Subtractive Metal Etch," filed on March 22, 2022. No. 63 / 322,535, entitled "Etch," all of which are incorporated by reference for all purposes.

[0112] The thermal development process can be performed without plasma. By applying non-plasma thermal techniques, multiple wafers can be batch developed simultaneously in a low-cost thermal vacuum chamber / oven, significantly improving productivity. However, in some embodiments, the thermal development process may be followed by exposure to plasma. The subsequent plasma exposure may be for desorption, descumming, smoothing, or other processing operations.

[0113] In a plasma development process, the photopatterned metal-containing EUV resist is exposed to a development chemical containing radicals / ions of one or more gases. The process chamber for processing the semiconductor substrate may be a plasma generation chamber or may be coupled to a plasma generation chamber remote from the process chamber. In some embodiments, dry development may be performed by a remote plasma. The plasma generation chamber may be an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor using equipment and techniques known in the art. An electromagnetic field acts on one or more gases to generate a plasma in the plasma generation chamber. Ions and / or radicals from the remote plasma may interact with the photopatterned metal-containing EUV resist. In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a development chemical line may be coupled to the plasma generation chamber for delivering one or more gases to the plasma generation chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the interior of the process chamber may be coated with a corrosion-resistant film, such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), such as Teflon 1 M. Such materials can be used in the thermal processes of the present disclosure without risk of removal by plasma exposure.

[0114] In a plasma development process, the photopatterned metal-containing EUV resist is exposed to a remote plasma under conditions that optimize the etch selectivity between exposed and unexposed regions. The conditions can be optimized to generate a mild plasma, which can be characterized by high pressure and low power. The chamber pressure can be adjusted, and the chamber pressure can affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the chamber pressure can be about 5 mTorr or greater, or about 15 mTorr or greater. In some embodiments, the chamber pressure can be relatively high with high flow rates and dilution, and the chamber pressure can be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The RF power level can be adjusted, and the RF power can affect the etch selectivity, roughness, descum, and other characteristics of development. In some embodiments, the RF power can be about 1000 W or less, about 800 W or less, or about 500 W or less. The temperature can be adjusted, and the temperature can affect various aspects of development, such as etch selectivity. In some embodiments, the temperature may be about −60° C. to about 300° C., about 0° C. to about 300° C., or about 30° C. to about 120° C. The gas flow rate can be adjusted, and the gas flow can affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the gas flow rate is about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 200 sccm to about 1000 sccm, e.g., about 500 sccm. The duration of exposure can be adjusted in the plasma development process. The duration of exposure can depend, among other factors, on the amount of resist desired to be removed, the development chemistry, the amount of crosslinking in the resist, and the composition and properties of the resist. In some embodiments, the duration of exposure may be about 1 second to about 50 minutes, about 3 seconds to about 20 minutes, or about 10 seconds to about 6 minutes.

[0115] The plasma development process can expose the photopatterned metal-containing EUV resist to radicals of certain halide-containing gases. In some embodiments, the radicals are generated from a remote plasma source. For example, the plasma development can expose the photopatterned metal-containing EUV resist to radicals of hydrogen and halide gases generated from a remote plasma source. In some embodiments, the halide-containing gases include hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. The hydrogen halides can include, but are not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide can be HCl or HBr. The hydrogen and halogen gases can include, but are not limited to, hydrogen gas (H) mixed with fluorine gas (F), chlorine gas (Cl), bromine gas (Br), or iodine gas (I). Organic halides include, but are not limited to, C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z where x, y, and z are values ​​greater than or equal to 0. Acyl halides can include, but are not limited to, CH3COF, CH3COCl, CH3COBr, and CH3COI. Carbonyl halides can include, but are not limited to, COF2, COCl2, COBr2, and COI2. Thionyl halides can include, but are not limited to, SOF2, SOCl2, SoBr2, and SOI2. In some embodiments, the halide-containing gas can be flowed with or without an inert / carrier gas such as He, Ne, Ar, Xe, and N2.

[0116] In addition to or instead of plasma activation, activation of one or more gases in the dry development process can occur by photoactivation. In some embodiments, photoactivation can be achieved by exposure to ultraviolet (UV) radiation. For example, the process chamber may include a lamp, such as a UV lamp, configured to generate UV radiation. Exposing one or more gases to UV radiation can generate radicals of one or more gases that can be used for dry development of the photopatterned metal-containing EUV resist. Exposure of the one or more gases to UV radiation can occur without exposing the photopatterned resist to UV radiation. In other words, the photopatterned resist is invisible to the UV lamp. Therefore, the UV lamp may be remote from the process chamber or positioned to avoid exposing the photopatterned resist to UV radiation.

[0117] It will be understood that the aforementioned methods of thermal development, plasma development, and light-activated development may be combined with one another. Such development methods may be applied simultaneously or sequentially. The development method may be applied in a liquid or gas phase with a flow of dry development chemicals, in which case the dry development chemicals may be of the formula R x Z y where R=B, Al, Si, C, S, SO, x>0, Z=Cl, H, Br, F, CH4, and y>0. Development can result in positive or negative tone, and R x Z y The species selectively removes either the unexposed or exposed material, leaving behind the exposed or unexposed counterpart as a mask.

[0118] As described above, the etch selectivity during dry development can be adjusted by controlling process conditions such as temperature, pressure, gas flow, gas composition, and plasma power, among other adjustable process conditions. Adjusting the etch selectivity in a single step or multiple steps can achieve desired patterned characteristics. In some embodiments, the etch selectivity during dry development is adjusted over one or more steps, thereby affecting the EUV resist profile. More specifically, the amount of taper or re-entrant angle in the EUV resist profile can be controlled by applying development chemistries with different etch selectivities over one or more steps. Descum, photoresist rework, hardening, smoothing, and cleaning operations can also be adjusted according to the adjustable etch selectivity.

[0119] 1 shows a flow diagram of an exemplary method for depositing and developing photoresist, according to some embodiments. The operations of process 100 may be performed in a different order and / or with a different, fewer, or additional number of operations. One or more operations of process 100 may be performed using the apparatus described in any one of FIGS. 7-10. In some embodiments, the operations of process 100 may be implemented, at least in part, according to software stored on one or more non-transitory computer-readable media.

[0120] In operation 102 of process 100, a photopatterned metal-containing resist is provided. The resist may be deposited by a dry deposition process, such as a vapor deposition process, or by a wet process, such as a spin-on deposition process.

[0121] The photoresist may be a metal-containing EUV resist. The EUV-sensitive metal or metal oxide-containing film may be deposited on the semiconductor substrate by any suitable technique, including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the described process is demonstrated for organotin oxide-based EUV photoresist compositions, and is applicable to both commercially available spin-coatable formulations and formulations applied using dry vacuum deposition techniques, as further described below.

[0122] The semiconductor substrate can include any material structure suitable for photolithography processing, particularly for the production of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer having features ("underlying features") formed thereon that have an irregular surface topography. As referred to herein, a "surface" is the surface onto which a film of the present disclosure is deposited or the surface that is exposed to EUV during processing. The underlying features may include areas from which material has been removed (e.g., by etching) or to which material has been added (e.g., by deposition) during processing prior to performing the method of the present disclosure. Such pre-processing may include the method of the present disclosure or other processing methods in an iterative process in which two or more layers of features are formed on the substrate.

[0123] EUV-sensitive thin films can be deposited on semiconductor substrates, and such films can act as resists for subsequent EUV lithography and processing. Such EUV-sensitive thin films include materials that, upon exposure to EUV, undergo changes such as the loss of bulky pendant substituents bonded to metal atoms in a low-density M-OH-rich material, allowing crosslinking to a higher-density MOM-bonded metal oxide material. Through EUV patterning, areas of the film are formed that have altered physical or chemical properties compared to unexposed areas. These properties can be exploited in subsequent processing, such as to dissolve either the unexposed or exposed areas, or to selectively deposit materials in either the exposed or unexposed areas. In some embodiments, the unexposed film has a more hydrophobic surface than the exposed film under the conditions under which such subsequent processing is performed. For example, material removal may be achieved by exploiting differences in the film's chemical composition, density, and crosslinking. Removal can be achieved by wet or dry processes, as further described below.

[0124] In various embodiments, the thin film is an organometallic material, such as an organotin material including tin oxide, or other metal oxide material / moiety. The organometallic compound can be made by the vapor-phase reaction of an organometallic precursor with a reverse reactant. In various embodiments, the organometallic compound is formed by mixing a specific combination of organometallic precursors having bulky alkyl or fluoroalkyl groups with a reverse reactant and polymerizing the mixture in the vapor phase to generate a low-density EUV-sensitive material that deposits on the semiconductor substrate.

[0125] In various embodiments, the organometallic precursors include at least one alkyl group on each metal atom that can survive the gas phase reaction, but other ligands or ions coordinated to the metal atom can be replaced by counter-reactants. The organometallic precursors include those of the formula: M a R b L c (Formula 1) where M is an element with a high patterning radiation absorption cross section and R is C n H 2n+1 and the like, preferably n≧2; L is a ligand, ion, or other moiety that reacts with the reverse reactant; and a≧1, b≧1, and c≧1.

[0126] In various embodiments, M is 1×10 7 cm 2 M may be selected from the group consisting of, for example, tin, hafnium, tellurium, bismuth, indium, antimony, germanium, and combinations thereof. In some embodiments, M is tin. R may be, for example, a compound of the formula C n F x H (2n+1) In various embodiments, R has at least one beta hydrogen or beta fluorine. For example, R may be selected from the group consisting of ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L may be any moiety that is readily displaced by a reverse reactant to produce an M-OH moiety, such as a moiety selected from the group consisting of an amine (dialkylamino, monoalkylamino, etc.), an alkoxy, a carboxylate, a halogen, and mixtures thereof.

[0127] The organometallic precursor may be any of a wide variety of candidate metal organic precursors. For example, when M is tin, such precursors include t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(t-butoxy)tin compounds, such as t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0128] The reverse reactant has the ability to replace a reactive moiety, ligand, or ion (e.g., L in Formula 1 above) to link at least two metal atoms via a chemical bond. Reverse reactants can include water, peroxides (e.g., hydrogen peroxide), dihydroxy or polyhydroxy alcohols, fluorinated dihydroxy or polyhydroxy alcohols, fluorinated glycols, and other sources of hydroxyl moieties. In various embodiments, the reverse reactant reacts with the organometallic precursor by forming oxygen bridges between adjacent metal atoms. Other potential reverse reactants include hydrogen sulfide and hydrogen disulfide, which can bridge metal atoms via sulfur bridges.

[0129] In addition to the organometallic precursor and back-reactant, the thin film can include optional materials to modify the film's chemical or physical properties, such as to modify its sensitivity to EUV or to enhance its etch resistance. Such optional materials may be introduced, such as by doping during vapor formation, before deposition on the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, the introduction of a mild remote H plasma can replace some Sn-L bonds with Sn-H, thereby enhancing the reactivity of the resist under EUV.

[0130] In various embodiments, EUV-patternable films are fabricated and deposited on semiconductor substrates using vapor deposition equipment and processes known in the art. In such processes, polymerized organometallic materials are formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD using CVD components, as well as discontinuous ALD-like processes in which, for example, the metal precursor and the counter-reactant are separated in either time or space.

[0131] In general, the method includes mixing a vapor flow of an organometallic precursor with a vapor flow of a reverse reactant to form a polymerized organometallic material and depositing the organometallic material on a surface of a semiconductor substrate. In some embodiments, multiple organometallic precursors are included in the vapor flow. In some embodiments, multiple reverse reactants are included in the vapor flow. As will be appreciated by those skilled in the art, the mixing and deposition aspects of the process can occur simultaneously in a substantially continuous process.

[0132] In an exemplary continuous CVD process, two or more gas streams of a source of organometallic precursor and a reverse reactant are introduced into a deposition chamber of a CVD apparatus via separate inlet paths, where they mix and react in the gas phase to form a cohesive polymeric material (e.g., via metal-oxygen-metal bond formation). The gas streams can be introduced, for example, using separate injection inlets or a dual plenum showerhead. The apparatus is configured so that the flows of organometallic precursor and reverse reactant mix within the chamber, allowing them to react and form a polymerized organometallic material. Without limiting the mechanism, function, or utility of the present technology, it is believed that the product from such a gas-phase reaction becomes heavier in molecular weight as metal atoms are crosslinked by the reverse reactant, and is then condensed or, in some cases, deposited onto a semiconductor substrate. In various embodiments, the steric hindrance of the bulky alkyl groups prevents the formation of a densely packed network, resulting in a smooth, amorphous, low-density film.

[0133] CVD processes are typically performed at reduced pressures, such as between 10 milliTorr and 10 Torr. In some embodiments, the process is performed at between 0.5 and 2 Torr. In some embodiments, the temperature of the semiconductor substrate is equal to or less than the temperature of the reactant stream. For example, the substrate temperature can be between 0°C and 250°C, or between ambient temperature (e.g., 23°C) and 150°C. In various processes, deposition of the polymerized organometallic material onto the substrate occurs at a rate that is inversely proportional to the surface temperature.

[0134] In some embodiments, the EUV patternable film is fabricated and deposited on the semiconductor substrate using wet deposition equipment and processes known in the art, for example, an organometallic material is formed on the surface of the semiconductor substrate by spin coating.

[0135] The thickness of the EUV-patternable film formed on the surface of a semiconductor substrate can vary depending on the surface characteristics, materials used, and processing conditions. In various embodiments, the film thickness can range from 0.5 nm to 100 nm and can be thick enough to absorb a majority of the EUV light under EUV patterning conditions. EUV-patternable films can support absorption of 30% or more, thereby resulting in significantly fewer EUV photons available toward the bottom of the EUV-patternable film. High EUV absorption results in more crosslinking and densification near the top of the EUV-exposed film compared to the bottom of the EUV-exposed film. Insufficient crosslinking can make the resist more susceptible to lift-off or disintegration in wet development, whereas dry development does not present such a risk. All-dry lithography techniques can facilitate more efficient utilization of EUV photons with more opaque resist films. While efficient utilization of EUV photons can occur with EUV-patternable films with higher overall absorption, it will be understood that in some cases, EUV-patternable films may have less than about 30% absorption. For comparison, most other resist films have a maximum overall absorption of less than 30% (e.g., 10% or less, or 5% or less), thereby ensuring sufficient exposure of the resist material at the bottom of the resist film. In some embodiments, the film thickness is 10 nm to 40 nm, or 10 nm to 20 nm. Without limiting the mechanism, function, or utility of the present disclosure, it is believed that, unlike wet spin-coating processes of the art, the disclosed process has few limitations on the surface adhesion properties of the substrate and can therefore be applied to a wide variety of substrates. Furthermore, as discussed above, the deposited film closely conforms to surface features without "filling" or planarizing such features, which can provide advantages when forming a mask over a substrate, such as a substrate with underlying features.

[0136] Returning to FIG. 1 , in operation 104, the photopatterned metal-containing resist is exposed to a pulse of etchant. As used herein, pulse refers to a specific amount of gas flow for a specified period of time. In some embodiments, the etchant pulse duration is from about 1 to about 120 seconds. In some embodiments, the etchant pulse duration is from about 5 to about 30 seconds. In some embodiments, the etchant pulse duration is from about 1 to about 20 seconds. In some embodiments, the etchant flow rate is from about 50 to about 3,000 sccm.

[0137] In some embodiments, operation 104 is a thermal process and the etchant is delivered to the process chamber in the form of a gas. In other embodiments, the etchant may be delivered to the process chamber in the form of a plasma. The etchant plasma can include reactive species such as electrons, positive ions, neutral species, radicals, and other plasma species. In some embodiments, the etchant is a halide etchant such as hydrogen bromide or hydrogen chloride, or a mixture of hydrogen and a halogen, such as hydrogen and chlorine (Cl) or hydrogen and bromine (Br).

[0138] Operation 104 can be performed by using either a gentle plasma (high pressure, low power) or thermal process while flowing a dry development etchant such as BCl3 (boron trichloride) or other Lewis acids. In some embodiments, BCl3 can rapidly remove unexposed material, leaving a pattern of exposed film that can be transferred to an underlying layer by a plasma-based etching process, e.g., a conventional etching process.

[0139] Plasma processes include transformer-coupled plasma (TCP), inductively coupled plasma (ICP), or capacitively coupled plasma (CCP), using equipment and techniques known in the art. For example, the process can be performed at a pressure of >5 mT (e.g., >15 mT) and a power level of <1000 W (e.g., <500 W). The temperature can be 0-300°C (e.g., 30-120°C), with a flow rate of 100-1000 standard cubic centimeters per minute (sccm), e.g., about 500 sccm, for 1-3000 seconds (e.g., 10-600 seconds).

[0140] In a thermal development process, the substrate is exposed to a dry development chemical (e.g., a Lewis acid) in a vacuum chamber (e.g., an oven). A suitable chamber can include a vacuum line, a dry development chemical gas (e.g., BCl3) line, and a heater for temperature control. In some embodiments, the interior of the chamber can be coated with a corrosion-resistant film, such as an organic polymer or inorganic coating. One such coating is polytetrafluoroethylene (PTFE, e.g., Teflon 1M). Such materials can be used in the thermal processes of the present technology without the risk of removal by plasma exposure.

[0141] During the etchant pulse, the pressure in the process chamber may be from about 5 mTorr to about 1 Torr in some embodiments. In some embodiments, the pedestal temperature in the process chamber may be from about −60° C. to about 120° C. during the etchant pulse. Furthermore, by adjusting the gas flow, hydrogen-to-halogen ratio, pressure, temperature, or RF power, the etch selectivity between unexposed photoresist and EUV-exposed photoresist can be adjusted from 5:1 to greater than 50:1.

[0142] In operation 106, in some embodiments, an optional purge is performed by flowing an inert carrier gas through the process chamber after exposure to the etchant. The purge or carrier gas is selected to be non-reactive with the etchant. Gases such as helium, argon, nitrogen, or combinations thereof can be utilized.

[0143] In operation 108, the resist etched in operation 104 is cleaned with a pulse of oxidizing agent. The oxidizing agent is used to remove non-volatile by-products that may form during the etchant pulse, which form an undesired etch stop on the resist. The non-volatile by-products are etch-resistant residues that can interfere with further processing. In some embodiments, the non-volatile by-products are at the bottom of the unexposed photoresist. Treatment with the oxidizing agent can make the non-volatile by-products volatile, allowing further etching.

[0144] The oxidizing agent may be oxygen, ozone, hydrogen peroxide, water, nitrous oxide, nitric oxide, nitrogen dioxide, nitric acid, sulfur dioxide, chlorine, fluorine, bromine, iodine, or a combination thereof. In some embodiments, the oxidizing agent is air, water and oxygen, or chlorine (Cl2).

[0145] In some embodiments, operation 108 is a thermal process and the oxidizer is delivered to the process chamber in the form of a gas. In other embodiments, the oxidizer may be delivered to the process chamber in the form of a plasma. The etchant plasma can include reactive species such as electrons, positive ions, neutral species, radicals, and other plasma species.

[0146] In some embodiments, operation 108 is performed at a higher temperature than operation 104. The higher temperature can be achieved by delivering the oxidizer as a hot gas or by heating a pedestal in the process chamber to a second temperature higher than the first temperature utilized in operation 104. If delivered as a hot gas, the temperature of the gas can be from about 50°C to about 250°C. If the pedestal of the process chamber is heated due to the oxidizer pulse, the pedestal can be heated to a temperature of from about 20°C to about 150°C.

[0147] In operation 108, the oxidizer is pulsed at a specific flow rate for a specific duration. The pulse duration may be from about 1 to about 60 seconds. The ratio of oxidizer to etchant may be 1:1. In some embodiments, the oxidizer flow rate is from about 50 to about 3,000 sccm.

[0148] Operation 108 and operation 104 are temporally separate pulses, meaning temporally separated pulses. The pulse of etchant in operation 104 and the pulse of oxidizer delivered to the process chamber are one cycle. Cycle 114 can be repeated as many times as desired to completely remove by-products. Additionally, the delivery of etchant and oxidizer for each cycle may have the same pulse duration, or the pulse duration may vary after a specified number of cycles. The timing of a pulse sequence of an exemplary etchant HBr and an exemplary oxidizer Cl2 with an optional argon purge versus temperature is shown graphically in FIG. 2.

[0149] Returning to FIG. 1 , in operation 110, in some embodiments, an optional purge can be performed after one cycle of operations 104 and 108 by flowing an inert carrier gas through the process chamber. The purge gas or carrier gas is selected to be non-reactive with the etchant. Gases such as helium, argon, nitrogen, or combinations thereof can be utilized. If an optional purge is utilized after a cycle, the next cycle begins with exposure to the etchant, as indicated at 116.

[0150] A resist mask is formed in operation 112. A plasma can be utilized to aid in solidification of the exposed photoresist.

[0151] In some cases, residue or scum may remain after development. Residue may result from slow-etching components in less homogeneous EUV resist formulations, including those applied by spin-coating techniques. Such scum may contain high concentrations of metals, which can be problematic during subsequent pattern transfer.

[0152] Additionally or alternatively, after development, roughness may form on the sidewalls of features etched with the developed pattern, which may be due in part to stochastic or non-optimal Gaussian distribution of light resulting in partially or fully exposed material in areas where the resist should remain unexposed, or vice versa.

[0153] In some embodiments, dry development may be accompanied by a descumming / smoothing operation. In some embodiments, the descumming and smoothing operation may be an inert gas plasma desorption operation. For example, the inert gas plasma desorption operation may be a helium plasma desorption operation. The inert gas plasma desorption operation may be performed after dry development or may be performed repeatedly with dry development.

[0154] Various embodiments include combining all dry operations with vapor deposition, EUV lithography patterning, and dry development. Various other embodiments include a combination of wet and dry processing operations, for example, spin-on EUV photoresist (a wet process) can be combined with dry development or other wet or dry processes as described herein. Various post-deposition (or post-application) processes, such as bevel and backside cleaning, chamber cleaning, descumming, smoothing, and curing to modify and enhance film properties, and photoresist rework processes, are also described.

[0155] 3A-3C are graphs of several parameters of a particular embodiment of the method described herein. Figure 3A demonstrates that in the absence of an oxidizer, etch stop occurs, leaving a residual thickness of 10 nm of an initially 25 nm thick EUV-unexposed layer. Higher Cl2 oxidizer purge temperatures are more effective at removing by-products.

[0156] FIG. 3B shows that shorter pulses of HBr etchant in combination with Cl 2 oxidant pulses in the cyclic dry development process result in greater removal of by-products at a process temperature of 20° C. with a greater number of cycles.

[0157] FIG. 3C shows that a longer Cl 2 oxidizer purge time at a process temperature of 40° C. in combination with HBr etchant pulses in a cyclic dry development process is more effective in reducing residual thickness.

[0158] Figure 4 shows scanning electron microscope images of the patterned photoresist surface, comparing conventional dry development utilizing only etchant with a cyclic dry development process using successive alternating pulses of etchant and oxidant. HBr etchant was utilized under process conditions of 500 sccm flow rate, 300 mTorr pressure, and 20°C temperature. After applying five cycles of the cyclic dry development process, cleaner unexposed areas and better edge roughness in both open and dense areas are achieved.

[0159] Figure 5 shows the limitations of a single dry development process (HBr etchant only) and a cyclic process. For a 25 nm unexposed photoresist film, etch stop occurs at a residual thickness of less than 15 nm when using etchant only. In contrast, using a cyclic process (total time 240 seconds) removes much more of the unexposed photoresist film using either Cl2 or air oxidizer.

[0160] 6 shows a flow diagram of an exemplary alternative method for depositing and developing photoresist, according to some embodiments. The operations of process 200 may be performed in a different order and / or with a different, fewer, or additional number of operations. One or more operations of process 200 may be performed using the apparatus described in any one of FIGS. 7-10. In some embodiments, the operations of process 200 may be implemented, at least in part, according to software stored on one or more non-transitory computer-readable media.

[0161] In operation 202 of process 200, a photopatterned metal-containing resist is provided.

[0162] In operation 204, the photopatterned metal-containing resist is exposed to an etchant.

[0163] In operation 206, after treatment with the etchant, a cleaning agent is utilized to dissolve non-volatile by-products. In some embodiments, the cleaning agent may be a suitable polar solvent such as water, methanol, ethanol, isopropanol, acetone, acetonitrile, tetrahydrofuran, dimethyl sulfide, or a combination thereof. In some embodiments, the cleaning agent may be a supercritical fluid, such as a low surface tension supercritical liquid. Suitable liquids include, but are not limited to, carbon dioxide, sulfur dioxide, dimethyl ether, or a combination thereof.

[0164] During the cleaning process with the cleaning agent, the temperature of the pedestal in the process chamber is, in some embodiments, from about 10° C. to about 50° C. In some embodiments, the process chamber pressure is from about 5 psi to about 3,000 psi during exposure to the cleaning agent.

[0165] A resist mask is formed in operation 208. A plasma can be used to harden the exposed photoresist, improve surface roughness, and help remove scum.

[0166] The process conditions for the descumming and smoothing operations can be controlled during or after development. In some embodiments, the reactant flow can be about 50 sccm to about 1000 sccm, or about 100 sccm to about 500 sccm, e.g., about 500 sccm He. In some embodiments, the temperature can be about -60°C to about 120°C, about -20°C to about 60°C, or about 20°C to about 40°C, e.g., about 20°C. In some embodiments, the chamber pressure can be about 1 mTorr to about 300 mTorr, about 5 mTorr to about 100 mTorr, about 5 mTorr to about 20 mTorr, e.g., about 10 mTorr. The plasma power can be relatively low when the ion energy is high. In some embodiments, the plasma power can be about 50 W to about 1000 W, about 100 W to about 500 W, or about 100 W to about 300 W, e.g., about 300 W. In some embodiments, the wafer bias is about 10 V to about 500 V, about 50 V to about 300 V, for example, about 200 V. The plasma can be generated using a high RF frequency. In some embodiments, the RF frequency is 13.56 MHz. The duration of exposure to the inert gas plasma can be relatively short to avoid excessive exposure to UV radiation during plasma exposure. In some embodiments, the duration of exposure is about 0.5 seconds to about 5 seconds, about 1 second to about 3 seconds, for example, about 2 seconds.

[0167] The inert gas plasma treatment for descumming and cleaning of unexposed resist residue has the additional benefit of hardening and solidifying the exposed resist, thereby enhancing its hard mask function in subsequent etching of the underlying substrate. This resist solidification is achieved by exposing the EUV-exposed resist to UV radiation generated by the inert gas plasma, which can continue even after the bias is turned off and descumming / smoothing is complete. If descumming / smoothing is not required or performed, an inert gas plasma cure may be performed instead.

[0168] In some embodiments, inert gas plasma desorption descumming and smoothing can be used in conjunction with a wet development process. Wet development has been shown to have very high selectivity and exhibit a distinct on / off behavior, resulting in the inability of the wet development process to remove areas exposed by "stray" EUV photons. Residual residue remains after the wet development process, resulting in scumming and rough line edges and widths. Interestingly, due to the tunability of the dry development process, where etch rate and selectivity can be adjusted based on multiple knobs (e.g., time, temperature, pressure, gas / flow rates), inert gas plasma and / or dry development can be further applied to descum and smooth metal-containing resist lines by removing these partially exposed residues.

[0169] The descum and smoothing operations may be performed after wet or dry development.

[0170] Device The apparatus of the present disclosure is configured for developing EUV resist. The apparatus can be configured to perform other processing operations, such as deposition, bevel and backside cleaning, post-apply bake, EUV scan, post-exposure bake, photoresist rework, descum, smoothing, curing, and other operations. In some embodiments, the apparatus is configured to perform all drying operations. In some embodiments, the apparatus is configured to perform all wet operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus can include a single wafer chamber or multiple stations within the same process chamber. When there are multiple stations within the same process chamber, various processing operations, such as those described in this disclosure, can be performed in different stations within the same process chamber. For example, a PEB thermal treatment can be performed in one station and development can be performed in another station.

[0171] An apparatus configured for developing EUV resist includes a process chamber having a substrate support. The apparatus can include a vacuum line coupled to the process chamber for pressure control and a developer chemical line coupled to the process chamber for delivering a developer chemical. In some embodiments, the developer chemical includes a halide-containing gas or a radical of a halide-containing gas. In some embodiments, the process chamber is a plasma generation chamber or is coupled to a plasma generation chamber that functions as a remote plasma source. The plasma generation chamber can be an ICP, TCP, or CCP reactor. The apparatus can include one or more heaters for temperature control. Such heaters can be provided in the process chamber and / or in the substrate support.

[0172] In some embodiments, the process chamber interior is coated with a corrosion-resistant film, such as a polymer or inorganic coating. In one example, the process chamber interior is coated with anodized alumina. In another example, the process chamber interior is coated with yttrium oxide (YO).

[0173] In some embodiments, the process chamber is made of an inexpensive material such as plastic. The process chamber does not necessarily have to be made of metal or ceramic. The plastic material may be sufficient to withstand the halide-containing chemicals during development. Vacuum lines and / or development chemical lines may be coupled to the plastic chamber.

[0174] In some embodiments, the substrate support can be used to process a substrate using a temperature distribution having radial and azimuthal components. The substrate support may include multiple independently controllable temperature control zones positioned proximate to the substrate location above the temperature control zones. This allows one or more heaters in the substrate support to more precisely and locally control the temperature. The temperature control zones can be arranged in a predefined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern, to generate a desired temperature profile. In some embodiments, the temperature control zones can be spatially arranged within the electrostatic chuck to correct for azimuthal non-uniformities or local CD non-uniformities.

[0175] In some embodiments, the apparatus can further include a showerhead for delivering one or more gases to the process chamber. In some embodiments, the showerhead can deliver multiple separate gases to the reaction area while keeping the gases largely isolated within the showerhead. The showerhead can include multiple plenum volumes, which allows for isolation of precursor gases, carrier gases, developer gases, and cleaning gases, among other chemicals.

[0176] Removing water or moisture from the process chamber can facilitate the reaction of the photopatterned metal-containing EUV resist with the development chemicals. In some embodiments, a cold trap can be coupled to the process chamber to remove by-product water vapor. The cold trap can condense the by-product water vapor into liquid or solid form.

[0177] In some embodiments, the apparatus may further include a UV source, such as a UV lamp, and / or an IR source, such as an IR lamp, for resist curing and dehalogenation. The UV source and / or IR source can provide radiation exposure to cure the EUV resist. Additionally or alternatively, the UV source may assist in photoactivation of the development chemicals. Additionally or alternatively, the UV source may assist in halogen removal. Halogen residues may form on the semiconductor substrate or chamber surfaces, which can be removed by UV exposure.

[0178] 7 illustrates a schematic diagram of one embodiment of a process station 700 having a process chamber body 702 for maintaining a low-pressure environment suitable for implementing the described dry developing, cleaning, rework, descumming, and smoothing embodiments. Multiple process stations 700 may be included in a common low-pressure process tool environment. In some embodiments, one or more hardware parameters of the process stations 700 (including those described in detail below) may be programmably adjusted by one or more computer controllers 750.

[0179] The process stations can be configured as modules within a cluster tool. Figure 10 illustrates a semiconductor process cluster tool architecture having a vacuum-integrated deposition and patterning module suitable for practicing embodiments described herein. Such a cluster process tool architecture can include resist deposition, resist exposure (EUV scanner), resist development, and etch modules, as described above and further below with reference to Figures 9 and 10.

[0180] In some embodiments, certain processing functions, such as dry developing and etching, can be performed sequentially in the same module. Embodiments of the present disclosure are also directed to methods and apparatus for receiving a wafer including a photo-patterned EUV resist thin film layer disposed on a layer or layer stack to be etched into a dry developing / etching chamber following photo-patterning in an EUV scanner, dry developing the photo-patterned EUV resist thin film layer, and then etching the underlying layer using the patterned EUV resist as a mask, as described herein.

[0181] Returning to FIG. 7 , the process station 700 is in fluid communication with a reactant delivery system 701 for delivering process gases to a distribution showerhead 706. The reactant delivery system 701 includes a mixing vessel 704 for blending and / or adjusting the process gases delivered to the showerhead 706. One or more mixing vessel inlet valves 720 can control the introduction of process gases into the mixing vessel 704. If plasma exposure is used, the plasma can also be delivered to the showerhead 706 or can be generated at the process station 700. As noted above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0182] 7 includes an optional vaporization point 703 for vaporizing the liquid reactant supplied to the mixing vessel 704. In some embodiments, a liquid flow controller (LFC) can be provided upstream of the vaporization point 703 to control the mass flow rate of the liquid being vaporized and delivered to the process station 700. For example, the LFC can include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC can then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM.

[0183] The showerhead 706 distributes process gases toward the substrate 712. In the embodiment shown in Figure 7, the substrate 712 is shown positioned below the showerhead 706 and resting on a pedestal 708. The showerhead 706 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to the substrate 712.

[0184] In some implementations, the pedestal 708 can be raised or lowered to expose the substrate 712 to the volume between the substrate 712 and the showerhead 706. It will be appreciated that in some embodiments, the height of the pedestal can be programmatically adjusted by a suitable computer controller 750. In some embodiments, the showerhead 706 can have multiple plenum volumes with multiple temperature controls.

[0185] In some embodiments, the pedestal 708 may be temperature controlled via a heater 710. In some embodiments, the pedestal 708 may be heated to a temperature of greater than 0° C. to 300° C. or greater, e.g., 50-120° C., e.g., about 65-80° C., during non-plasma thermal exposure of the photopatterned resist to a hydrogen halide dry development chemistry, such as HBr or HCl, as described in disclosed embodiments. In some embodiments, the heater 710 of the pedestal 708 may include multiple independently controllable temperature control zones.

[0186] Additionally, in some embodiments, pressure control for the process station 700 may be provided by a butterfly valve 718. As shown in the embodiment of Figure 7, the butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control for the process station 700 may also be adjusted by varying the flow rate of one or more gases introduced to the process station 1200.

[0187] In some embodiments, the position of the showerhead 706 can be adjusted relative to the pedestal 708 to vary the volume between the substrate 712 and the showerhead 706. Furthermore, it will be appreciated that the vertical position of the pedestal 708 and / or the showerhead 706 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 may include a rotation axis for rotating the orientation of the substrate 712. It will be appreciated that in some embodiments, one or more of these exemplary adjustments may be implemented programmatically by one or more suitable computer controllers 750.

[0188] When plasma may be used, for example, in a mild plasma-based dry development embodiment and / or an etching operation performed in the same chamber, the showerhead 706 and pedestal 708 are in electrical communication with a radio frequency (RF) power source 714 and matching network 716 to power the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 714 and matching network 716 can be operated at any suitable power to form a plasma having a desired composition of radical species. An example of a suitable power is up to about 500 W.

[0189] In some embodiments, instructions for the controller 750 may be provided via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process step may be included in a corresponding recipe step of a process recipe. In some cases, process recipe steps may be arranged in sequence such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe step. For example, a recipe step may include instructions for setting a flow rate of a dry development chemical reactant gas, such as HBr or HCl, and a time delay instruction for the recipe step. In some embodiments, the controller 750 may include any of the features described below with respect to the system controller 850 of FIG. 8.

[0190] As described above, one or more process stations can be included in a multi-station processing tool. FIG. 8 shows a schematic diagram of one embodiment of a multi-station processing tool 800 including an inbound load lock 802 and an outbound load lock 804, either or both of which may include a remote plasma source. A robot 806 is configured to move wafers at atmospheric pressure from a cassette loaded via a pod 808 to the inbound load lock 802 through an atmospheric pressure port 810. The wafer is placed by the robot 806 on a pedestal 812 of the inbound load lock 802, the atmospheric pressure port 810 is closed, and the load lock is pumped down. If the inbound load lock 802 includes a remote plasma source, the wafer may undergo remote plasma processing to treat the silicon nitride surface within the load lock before being introduced into the processing chamber 814. Additionally, the wafer may also be heated in the inbound load lock 802, for example, to remove moisture and absorbed gases. Next, a chamber transfer port 816 to the processing chamber 814 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal in the first station shown in the reactor for processing. While the embodiment shown in Figure 8 includes a load lock, it will be understood that in some embodiments, the wafer may enter the process station directly.

[0191] The illustrated processing chamber 814 includes four process stations, numbered 1 through 4 in the embodiment shown in FIG. 8 . Each station has a heated pedestal (shown at 818 for station 1) and a gas line inlet. It will be understood that in some embodiments, each process station may have a different purpose or multiple purposes. For example, in some embodiments, a process station may be switchable between a dry development mode and an etch process mode. Additionally or alternatively, in some embodiments, the processing chamber 814 may include one or more corresponding pairs of dry development and etch process stations. While the illustrated processing chamber 814 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0192] FIG. 8 illustrates one embodiment of a wafer handling system 890 for transferring wafers within the processing chamber 814. In some embodiments, the wafer handling system 890 can transfer wafers between various process stations and / or between process stations and load locks. It will be understood that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 8 also illustrates one embodiment of a system controller 850 used to control the process conditions and hardware states of the process tool 800. The system controller 850 can include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 can include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0193] In some embodiments, system controller 850 controls all of the activity of process tool 800. System controller 850 executes system control software 858 stored on mass storage device 854, loaded into memory device 856, and executed on processor 852. Alternatively, control logic may be hard-coded into controller 850. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays, or FPGAs), or the like may be used for these purposes. In the following description, whenever "software" or "code" is used, functionally equivalent hard-coded logic may be used instead. System control software 858 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by process tool 800. System control software 858 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components used to perform the various process tool processes. The system control software 858 may be coded in any suitable computer-readable programming language.

[0194] In some embodiments, the system control software 858 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on the mass storage device 854 and / or memory device 856 associated with the system controller 850 may be used. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0195] The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal 818 and control the spacing between the substrate and other parts of the process tool 800 .

[0196] The process gas control program can include code for controlling the halide-containing gas composition (e.g., HBr or HCl gas as described herein) and flow rate to stabilize the pressure of the process station, and optionally, code for flowing gases to one or more process stations prior to deposition. The pressure control program can include code for controlling the pressure of the process station by, for example, adjusting a throttle valve in the exhaust system of the process station, gas flow to the process station, etc.

[0197] The heater control program may include code for controlling the current to a heating unit used to heat the substrate, or the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0198] The plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations in accordance with embodiments herein.

[0199] The pressure control program can include code for maintaining pressure in the reaction chamber according to embodiments herein.

[0200] In some embodiments, there may be a user interface associated with the system controller 850. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0201] In some embodiments, the parameters adjusted by the system controller 850 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe or may be entered using a user interface.

[0202] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 850 from various process tool sensors. Signals for controlling the process can be output at analog and digital output connections of the process tool 800. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain process conditions.

[0203] The system controller 850 can provide program instructions for carrying out the deposition process described above. The program instructions can control various process parameters such as DC power levels, RF bias power levels, pressure, temperature, etc. The instructions can control parameters for operating the development and / or etching processes according to various embodiments described herein.

[0204] System controller 850 typically includes one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs methods according to the disclosed embodiments. Machine-readable media containing instructions for controlling process operations according to the disclosed embodiments may be coupled to system controller 850.

[0205] In some embodiments, the system controller 850 is part of a system, such as may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after semiconductor wafer or substrate processing. Such electronics may be referred to as a "controller" and may control various components or subcomponents of one or more systems. The system controller 850 may be programmed to control any of the processes disclosed herein, depending on the processing conditions and / or type of system. Such processes may include process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer to and from tools and other transfer tools connected or interfaced with a particular system, and / or wafer transfer to and from load locks.

[0206] Broadly, system controller 850 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). Program instructions may be instructions communicated to system controller 850 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0207] In some embodiments, the system controller 850 may be part of, coupled to, or a combination of a computer integrated with or otherwise networked to the system. For example, the system controller 850 may be in the “cloud” or all or part of a fab host computer system. This allows for remote access to wafer processing. The computer may provide remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 850 receives instructions in the form of data. Such data may identify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that system controller 850 is configured to interface with or control. Thus, as described above, system controller 850 may be distributed, for example, by including one or more individual controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein).An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0208] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracker chamber or module, an EUV lithography chamber (scanner) or module, a development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0209] As noted above, depending on the process step or steps being performed by the tool, system controller 850 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0210] In certain embodiments, an inductively coupled plasma (ICP) reactor is described herein, which may be suitable for etching operations suitable for practicing some embodiments. Although an ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor may also be used.

[0211] 9 shows a schematic cross-sectional view of an inductively coupled plasma apparatus 900 suitable for performing certain embodiments or aspects of embodiments, such as dry development and / or etching. In other embodiments, other tools or tool types capable of performing the dry development and / or etching processes described herein may be used.

[0212] The inductively coupled plasma apparatus 900 includes an overall process chamber 924 structurally defined by a chamber wall 901 and a window 911. The chamber wall 901 can be fabricated from stainless steel, aluminum, or plastic. The window 911 can be fabricated from quartz or other dielectric materials. An optional internal plasma grid 950 divides the overall process chamber into an upper subchamber 902 and a lower subchamber 903. In many embodiments, the plasma grid 950 can be removed, thereby utilizing the chamber space consisting of the subchambers 902 and 903. A chuck 917 is positioned within the lower subchamber 903 near the bottom inner surface. The chuck 917 is configured to receive and hold a semiconductor wafer 919 on which etching and deposition processes are performed. If present, the chuck 917 can be an electrostatic chuck for supporting the wafer 919. In some embodiments, an edge ring (not shown) surrounds the chuck 917 and, if present on the chuck 917, has an upper surface that is approximately planar with the upper surface of the wafer 919. The chuck 917 also includes an electrostatic electrode for chucking and dechucking the wafer 919. A filter and DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting the wafer 919 from the chuck 917 may also be provided. The chuck 917 may be charged using an RF power supply 923. The RF power supply 923 is connected to a matching circuit 921 through connection 927. The matching circuit 921 is connected to the chuck 917 through connection 925. In this manner, the RF power supply 923 is connected to the chuck 917. In various embodiments, the bias power of the electrostatic chuck may be set to approximately 50 V or may be set to a different bias power depending on the process being performed in accordance with the disclosed embodiments. For example, the bias power may be between approximately 20 V and approximately 100 V, or between approximately 30 V and approximately 150 V.

[0213] The elements for plasma generation include a coil 933, positioned above the window 911. In some embodiments, a coil is not used in the disclosed embodiments. The coil 933 is fabricated from a conductive material and includes at least one full turn. The example coil 933 shown in FIG. 9 includes three turns. A cross section of the coil 933 is indicated by symbols, with the coil having an "X" extending into the page and the coil having a "●" extending out of the page. The elements for plasma generation also include an RF power supply 941 configured to provide RF power to the coil 933. Generally, the RF power supply 941 is connected to a matching circuit 939 through connection 945. The matching circuit 939 is connected to the coil 933 through connection 943. In this manner, the RF power supply 941 is connected to the coil 933. An optional Faraday shield 949 is positioned between the coil 933 and the window 911. The Faraday shield 949 may be maintained in a spaced apart relationship relative to the coil 933. In some embodiments, the Faraday shield 949 is positioned directly above the window 911. In some embodiments, the Faraday shield 949 is between the window 911 and the chuck 917. In some embodiments, the Faraday shield 949 is not maintained in a spaced apart relationship with respect to the coil 933. For example, the Faraday shield 949 may be directly below the window 911 with no gap. The coil 933, the Faraday shield 949, and the window 911 are each configured to be substantially parallel to one another. The Faraday shield 949 can prevent metals or other species from depositing on the window 911 of the process chamber 924.

[0214] Process gases can enter the process chamber through one or more main gas inlets 960 and / or one or more side gas inlets 970 positioned in the upper subchamber 902. Similarly, although not explicitly shown, similar gas inlets can be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a single-stage or two-stage mechanical dry pump and / or turbomolecular pump 940, can be used to draw process gases from the process chamber 924 and maintain pressure within the process chamber 924. For example, the vacuum pump can be used to evacuate the lower subchamber 903 during an ALD purge operation. A valve-controlled conduit can be used to fluidly connect the vacuum pump to the process chamber 924 to selectively control the application of the vacuum environment provided by the vacuum pump. This can be done using a closed-loop controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during plasma processing operations. Similarly, a vacuum pump and valve-controlled fluid connection to the capacitively coupled plasma processing chamber can also be used.

[0215] During operation of the apparatus 900, one or more process gases can be supplied through the gas inlets 960 and / or 970. In certain embodiments, process gases can be supplied only through the main gas inlet 960 or only through the side gas inlet 970. In some cases, the gas inlets shown in the figure can be replaced with more complex gas inlets, such as one or more showerheads. The Faraday shield 949 and / or optional grid 950 can include internal channels and holes that allow delivery of process gases to the process chamber 924. Either or both the Faraday shield 949 and optional grid 950 can function as showerheads for delivering process gases. In some embodiments, a liquid vaporization and delivery system can be positioned upstream of the process chamber 924, whereby liquid reactants or precursors are vaporized and the vaporized reactants or precursors are introduced into the process chamber 924 via the gas inlets 960 and / or 970.

[0216] Radio frequency power is supplied from RF power supply 941 to coil 933, causing RF current to flow through coil 933. The RF current flowing through coil 933 generates an electromagnetic field around coil 933. The electromagnetic field generates an induced current within upper subchamber 902. Physical and chemical interactions of the various generated ions and radicals with wafer 919 etch features in wafer 919 and selectively deposit layers on wafer 919.

[0217] When a plasma grid 950 is used such that both an upper subchamber 902 and a lower subchamber 903 are present, induced currents act on the gas present in the upper subchamber 902, generating an electron-ion plasma in the upper subchamber 902. The optional internal plasma grid 1450 limits the number of thermal electrons in the lower subchamber 903. In some embodiments, the apparatus 900 is designed and operated such that the plasma present in the lower subchamber 903 is an ion-ion plasma.

[0218] Both the upper electron-ion plasma and the lower ion-ion plasma can contain positive and negative ions, but the ion-ion plasma has a higher ratio of negative ions to positive ions. Volatile etching and / or deposition byproducts can be removed from the lower subchamber 903 through port 922. The chuck 917 disclosed herein can operate at high temperatures ranging from about 10°C to about 250°C. The temperature depends on the process operation and the specific recipe.

[0219] The apparatus 900 may be coupled to equipment (not shown) when installed in a clean room or fabrication facility. The equipment includes plumbing to provide process gases, vacuum, temperature control, and environmental particle control. These equipment are coupled to the apparatus 900 when installed in the target fabrication facility. Additionally, the apparatus 900 may be coupled to a transfer chamber that allows a robot to move semiconductor wafers in and out of the apparatus 900 using typical automated operations.

[0220] In some embodiments, a system controller 930 (which may include one or more physical or logical controllers) controls some or all of the operation of the process chamber 924. The system controller 930 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 900 includes a switching system for controlling flow rates and durations when the disclosed embodiments are implemented. In some embodiments, the apparatus 900 may have a switching time of up to about 500 ms, or up to about 750 ms. The switching time may depend on the flowing chemistry, the selected recipe, the reactor architecture, and other factors.

[0221] In some embodiments, the system controller 930 is part of a system, such as may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after semiconductor wafer or substrate processing. Such electronics may be integrated into the system controller 930 and control various components or subcomponents of one or more systems. The system controller may be programmed to control any of the processes disclosed herein, depending on the processing parameters and / or type of system. Such processes may include process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer to and from tools and other transfer tools connected or interfaced with a particular system, and / or wafer transfer to and from load locks.

[0222] Broadly, the system controller 930 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). The program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more processing steps in the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer die.

[0223] The system controller 930, in some embodiments, may be part of, coupled to, or a combination of a computer integrated with, coupled to, or otherwise networked to the system. For example, the controller may be in the “cloud” or all or part of a fab host computer system. This allows for remote access of wafer processing. The computer may provide remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the system controller 930 receives instructions in the form of data. Such data may identify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the system controller 930 may be distributed, for example, by including one or more individual controllers networked together and working together toward a common purpose (such as the processes and controls described herein).An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0224] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a tracker chamber or module, an EUV lithography chamber (scanner) or module, a dry develop chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0225] As noted above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0226] EUVL patterning can be performed using any suitable tool, often referred to as a scanner. The EUVL patterning tool may be a standalone device from which substrates are loaded and unloaded for deposition and etching as described herein. Alternatively, as described below, the EUVL patterning tool may be a module on a larger, multi-component tool. FIG. 10 illustrates a semiconductor process cluster tool architecture having vacuum-integrated deposition, EUV patterning, and dry develop / etch modules interfaced with a vacuum transfer module, suitable for carrying out the processes described herein. While the processes can be performed without such vacuum-integrated equipment, such equipment may be advantageous in some embodiments.

[0227] 10 illustrates a semiconductor process cluster tool architecture 1000 having a vacuum-integrated deposition and patterning module interfaced with a vacuum transfer module suitable for carrying out the processes described herein. The arrangement of transfer modules for "transferring" wafers between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum-integrated according to the requirements of a particular process. Other modules, such as for etching, can also be included in the cluster.

[0228] A vacuum transfer module (VTM) 1538 interfaces with four processing modules 1020a-1020d, which can be individually optimized to perform various fabrication processes. By way of example, processing modules 1020a-1020d can be implemented to perform deposition, evaporation, ELD, dry develop, etch, strip, and / or other semiconductor processes. For example, module 1020a can be an ALD reactor that can be operated to perform the non-plasma thermal atomic layer deposition described herein. It should be understood that the figures are not necessarily drawn to scale.

[0229] Airlocks 1042 and 1046, also known as load locks or transfer modules, interface with the VTM 1038 and patterning module 1040. This tool architecture allows workpieces, such as semiconductor substrates or wafers, to be transferred under vacuum to prevent reaction prior to exposure. The integration of the deposition module with the lithography tool is facilitated by the fact that EUVL also requires significantly reduced pressure, given the strong optical absorption of incident photons by ambient gases such as H2O and O2.

[0230] As noted above, this integrated architecture is just one possible embodiment of a tool for performing the described process. The process can also be performed using more conventional standalone EUVL scanners, and as a module, for example, a deposition reactor that lacks an integrated patterning module, either standalone or integrated in a cluster architecture with other tools such as etch, strip, etc.

[0231] Airlock 1042 may be an "outgoing" load lock, referring to the transfer of substrates from the VTM 1038 servicing deposition module 1020a to the patterning module 1040, and airlock 1046 may be an "incoming" load lock, referring to the transfer of substrates from the patterning module 1040 back to the VTM 1038. The incoming load lock 1046 may also provide an interface to the outside of the tool for substrate access and egress. Each process module has a facet that interfaces the module to the VTM 1038. For example, deposition process module 1020a has facet 1036. Within each facet, sensors, such as sensors 1-18 shown, are used to detect the passage of wafer 1026 as it moves between its respective stations. Patterning module 1040 and airlocks 1042 and 1046 may similarly include additional facets and sensors not shown.

[0232] The main VTM robot 1022 transfers wafers 1026 between modules, including airlocks 1042 and 1046. In one embodiment, the robot 1022 has one arm, and in another embodiment, the robot 1022 has two arms, each arm having an end effector 1024 that lifts a wafer, such as wafer 1026, for transfer. The front-end robot 1044 is used therein to transfer wafers 1026 from the output airlock 1042 to the patterning module 1040 and from the patterning module 1040 to the input airlock 1046. The front-end robot 1044 can also transfer wafers 1026 between the input load lock and the exterior of the tool for substrate access and egress. Because the input airlock module 1046 has the ability to adapt environments between atmospheric pressure and vacuum, wafers 1026 can move between the two pressure environments without damage.

[0233] It should be noted that EUVL tools typically operate at a higher vacuum than deposition tools. In this case, it is desirable to increase the vacuum environment of the substrate during transfer between the deposition tool and the EUVL tool to allow for degassing of the substrate before entering the patterning tool. The unloading airlock 1042 can provide this function by holding the transferred wafer at a low pressure no higher than the pressure in the patterning module 1040 for a period of time and venting the off-gassing, thereby preventing contamination of the optics of the patterning tool 1040 by off-gassing from the substrate. A suitable pressure for the venting off-gas airlock is 1E-8 Torr or less.

[0234] In some embodiments, a system controller 1050 (which may include one or more physical or logical controllers) controls some or all of the operation of the cluster tool and / or its separate modules. Note that the controller may be local to the cluster architecture, located outside the cluster architecture on the manufacturing floor, or located at a remote location and connected to the cluster architecture via a network. The system controller 1050 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the controller or provided over a network. In certain embodiments, the system controller executes system control software.

[0235] The system control software may include instructions for controlling the timing of application and / or magnitude of any aspect of tool or module operation. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components necessary to perform various process tool processes. The system control software may be coded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each stage of a semiconductor fabrication process may include one or more instructions executed by the system controller. For example, instructions for setting process conditions for condensation, deposition, vapor deposition, patterning, and / or etching stages may be included in the corresponding recipe stage.

[0236] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus can include process chambers for patterning, deposition, and etching, and a controller including instructions for forming the negative pattern mask. The instructions can include code for patterning features in a chemically amplified resist (CAR) on a semiconductor substrate by EUV exposure in the process chamber to expose a surface of the substrate, developing the photopatterned resist, and etching an underlying layer or layer stack using the patterned resist as a mask. The development can be performed using a halide-containing chemical.

[0237] It should be noted that the computer controlling the movement of the wafers may be local to the cluster architecture, may be located outside the cluster architecture on the manufacturing floor, or may be located at a remote location and connected to the cluster architecture via a network. The controller described above with respect to any of Figures 7, 8, or 9 may be implemented using the tool of Figure 10.

[0238] conclusion It will be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes will be suggested to those skilled in the art in light thereof. Various details have been omitted for clarity, but various design alternatives can be implemented. Accordingly, the examples are to be considered illustrative rather than restrictive, and the disclosure is not to be limited to the details given herein, but can be modified within the scope of the disclosure.

Claims

1. 1. A method for processing a semiconductor substrate, comprising: providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber; developing the photopatterned metal-containing resist to form a resist mask by selectively removing portions of the photopatterned metal-containing resist by exposing the photopatterned metal-containing resist to at least one cycle comprising alternating pulses of an etchant and a pulse of an oxidizer; A method comprising:

2. 10. The method of claim 1, The method wherein the pulse of the etchant and the pulse of the oxidizer are separated in time.

3. 10. The method of claim 1, The method, wherein the pedestal is at a first temperature during the pulse of the etchant and the oxidizer is delivered to the process chamber at a second temperature.

4. 10. The method of claim 1, The method, wherein the pedestal is at a first temperature during the pulse of the etchant and the pedestal is at a second temperature during the pulse of the oxidizer.

5. 10. The method of claim 1, The method, wherein the pulse of the etchant has a duration of about 1 to about 120 seconds and the pulse of the oxidizer has a duration of about 1 to about 120 seconds.

6. 4. The method of claim 3, The method, wherein the first temperature is from about -60°C to about 120°C.

7. 5. The method of claim 4, The method, wherein the second temperature is from about 20°C to about 150°C.

8. 4. The method of claim 3, The method wherein the second temperature is from about 50°C to about 250°C.

9. 10. The method of claim 1, A method wherein non-volatile by-products of the pulse of the etchant are removed from the photopatterned metal-containing resist.

10. 10. The method of claim 1, The method, wherein the photopatterned metal-containing resist comprises an organometallic oxide, a metal, a metal oxide, or an organometallic.

11. 11. The method of claim 10, The method wherein the metal oxide comprises tin oxide.

12. 10. The method of claim 1, The method wherein the etchant is a halide etchant.

13. 13. The method of claim 12, The method, wherein the halide etchant comprises a hydrogen halide, hydrogen gas and a halogen gas, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a combination thereof.

14. 13. The method of claim 12, The method, wherein the halide etchant comprises hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof.

15. 10. The method of claim 1, The method, wherein the etchant comprises an etchant plasma.

16. 16. The method of claim 15, The method wherein the etchant plasma is generated remotely.

17. 10. The method of claim 1, The method, wherein the oxidizing agent comprises oxygen, ozone, hydrogen peroxide, water, nitrous oxide, nitric oxide, nitrogen dioxide, nitric acid, sulfur dioxide, chlorine, fluorine, bromine, iodine, or a combination thereof.

18. 18. The method of claim 17, The method wherein the oxidant is a gaseous oxidant comprising water and oxygen or chlorine.

19. 10. The method of claim 1, The method, wherein the oxidizer comprises an oxidizer plasma.

20. 20. The method of claim 19, The method wherein the oxidizer plasma is generated remotely.

21. 10. The method of claim 1, The method further comprising exposing the photopatterned metal-containing resist to an inert plasma gas.

22. 10. The method of claim 1, The method further comprising purging the process chamber with an inert gas between the pulses of the etchant and the pulses of the oxidizer, or after cycles of the pulses of the etchant and the pulses of the oxidizer.

23. 10. The method of claim 1, The method, wherein developing the photopatterned metal-containing resist by exposing it to alternating pulses of an etchant and an oxidant comprises dry developing the photopatterned metal-containing resist.

24. 10. The method of claim 1, The method, wherein developing the photopatterned metal-containing resist by exposing it to alternating pulses of an etchant and an oxidant comprises wet developing the photopatterned metal-containing resist.

25. 10. The method of claim 1, The method wherein each cycle has the same etchant pulse duration.

26. 1. A method for processing a semiconductor substrate, comprising: providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber; developing the photopatterned metal-containing resist by exposing the photopatterned metal-containing resist to an etchant followed by a cleaning agent to selectively remove portions of the photopatterned metal-containing resist to form a resist mask; A method comprising:

27. 27. The method of claim 26, The method, wherein the cleaning agent comprises water, methanol, ethanol, isopropanol, acetone, acetonitrile, tetrahydrofuran, dimethyl sulfide, or a combination thereof.

28. 27. The method of claim 26, The method wherein the pedestal temperature is from about 10° C. to about 50° C. during exposure to said cleaning agent.

29. 27. The method of claim 26, The method, wherein the cleaning agent comprises a supercritical fluid.

30. 30. The method of claim 29, The method wherein the supercritical fluid is a low surface tension supercritical liquid.

31. 31. The method of claim 30, The method, wherein the low surface tension supercritical fluid comprises carbon dioxide, sulfur dioxide, dimethyl ether, or a combination thereof.

32. 30. The method of claim 29, The method wherein the process chamber pressure is from about 5 psi to about 3,000 psi during exposure to said cleaning material.

33. 27. The method of claim 26, A method wherein non-volatile by-products from exposure to an etchant are removed from said photopatterned metal-containing resist.

34. 27. The method of claim 26, The method, wherein the photopatterned metal-containing resist comprises an organometallic oxide, a metal, a metal oxide, or an organometallic.

35. 35. The method of claim 34, The method wherein the metal oxide comprises tin oxide.

36. 27. The method of claim 26, The method wherein the etchant is a halide etchant.

37. 37. The method of claim 36, The method, wherein the halide etchant comprises a hydrogen halide, hydrogen gas and a halogen gas, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a combination thereof.

38. 37. The method of claim 36, The method, wherein the halide etchant comprises hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof.

39. 27. The method of claim 26, The method, wherein the etchant comprises an etchant plasma.

40. 40. The method of claim 39, The method wherein the etchant plasma is generated remotely.

41. 1. A method for enhancing atomic layer etching on a substrate, comprising: providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber; developing the photopatterned metal-containing resist to form a resist mask by selectively removing portions of the resist by exposing the photopatterned metal-containing resist to at least one cycle comprising alternating pulses of an etchant and an oxidizer; Including, This eliminates etch stop due to non-volatile by-products of the etchant pulse. method.

42. 1. A method for processing a semiconductor substrate, comprising: providing a dry-deposited photopatterned metal oxide EUV resist on a semiconductor substrate on a pedestal in a process chamber; dry developing the photopatterned metal oxide EUV resist by selectively removing non-EUV exposed portions of the EUV resist by exposing it to at least one cycle comprising alternating pulses of an etchant and an oxidizer to form a resist hard mask; A method comprising:

43. An apparatus for developing a resist, comprising: a process chamber having a substrate support; a vacuum line coupled to the process chamber; an etchant and oxidant line coupled to the process chamber; 1. A controller configured with instructions for processing a semiconductor substrate, the instructions comprising: providing a photopatterned metal-containing resist on a semiconductor substrate in a process chamber; developing the photopatterned metal-containing resist by selectively removing portions of the resist by exposing it to at least one cycle of alternatingly delivered etchant and oxidant pulses to form a resist mask; and a controller containing the code for An apparatus comprising:

44. 44. The apparatus of claim 43, the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the controller configured with instructions including code for developing the photo-patterned metal-containing EUV resist includes code for selectively removing EUV-unexposed portions of the EUV resist compared to EUV-exposed portions with at least one cycle of alternatingly delivered etchant and oxidizer pulses to form a resist mask.

45. 44. The apparatus of claim 43, one or more heaters coupled to the substrate support, the one or more heaters including a plurality of independently controllable temperature control zones; The apparatus further comprises:

46. 46. ​​The apparatus of claim 45, The apparatus further comprising a heated oxidant delivery line.

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