Semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A structure extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersecting part where the structure body and the first conductor intersect with each other, the structure body includes a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator concentrically provided outside the third conductor. In a second intersecting part where the structure body and the second conductor intersect with each other, the structure body includes a first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator concentrically provided outside the third conductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), storage devices, and sensors have been used in a variety of electronic devices, including personal computers, smartphones, and digital cameras. These electronic components have been improving in various aspects, including miniaturization and reduced power consumption.

[0004] In particular, the amount of data handled by the electronic devices described above is increasing, and there is a demand for storage devices with large storage capacities. As a means for increasing storage capacity, for example, Patent Documents 1 and 2 disclose a NAND memory element with a three-dimensional structure that uses a metal oxide as a channel formation region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 3060 Brochure [Patent Document 2] Patent Publication No. 2018-207038 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a highly reliable storage device.An object of one embodiment of the present invention is to provide a storage device with a large storage capacity.An object of one embodiment of the present invention is to provide a novel storage device.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0007] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device having a structure extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction, the structure having a third conductor extending in the first direction, a first insulator adjacent to the third conductor, a first semiconductor adjacent to the first insulator, and a second insulator adjacent to the first semiconductor, and at a first intersection where the structure and the first conductor intersect, the structure has a second semiconductor adjacent to the second insulator, a third insulator adjacent to the second semiconductor, a functional body adjacent to the third insulator, and a fourth insulator adjacent to the functional body, and At a second intersection where the first and second semiconductors intersect, the structure has a fourth conductor adjacent to the second insulator, a second semiconductor adjacent to the fourth conductor, and a third insulator adjacent to the second semiconductor; at the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor, the third insulator, the functional body, and the fourth insulator are concentrically arranged outside the third conductor when viewed from the first direction; and at the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth conductor, the second semiconductor, and the third insulator are concentrically arranged outside the third conductor when viewed from the first direction.

[0009] The first direction is perpendicular to the second direction. The first intersection functions as a first transistor, and the second intersection functions as a second transistor and a capacitive element. At least one of the first semiconductor and the second semiconductor may be silicon.

[0010] The functional body can be an insulator or a semiconductor. For example, by using silicon nitride (an insulator containing nitrogen and silicon) as the functional body, the first transistor can be a MONOS type transistor. Also, by using silicon nitride (an insulator containing nitrogen and silicon) as the functional body, the first transistor can be an FG type transistor.

[0011] By injecting charge into the functional body, the threshold voltage of the first transistor can be increased, and the first transistor can be made a normally-off transistor. Therefore, the first transistor can be made a normally-off transistor, and the second transistor can be made a normally-on transistor.

[0012] At least one of the first semiconductor and the second semiconductor may be an oxide semiconductor, which preferably contains at least one of indium and zinc.

[0013] Another embodiment of the present invention is an electronic device including the above-described semiconductor device and at least one of an operation switch, a battery, and a display portion. [Effects of the Invention]

[0014] According to one embodiment of the present invention, a highly reliable storage device can be provided. Alternatively, a storage device with a large storage capacity can be provided. Alternatively, a novel storage device can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with a large storage capacity can be provided. Alternatively, a novel semiconductor device can be provided.

[0015] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0016] [Figure 1]1A and 1B are perspective and cross-sectional views of a memory cell. [Figure 2] 2A and 2B are cross-sectional views of a memory cell. [Figure 3] FIG. 3 is a perspective view of the structure. [Figure 4] 4A to 4C are equivalent circuit diagrams of a memory cell. [Figure 5] 5A and 5B are equivalent circuit diagrams of a memory cell. [Figure 6] FIG. 6 is a cross-sectional view of a memory string. [Figure 7] FIG. 7 is an equivalent circuit diagram of a memory string. [Figure 8] FIG. 8 is an equivalent circuit diagram of a memory string. [Figure 9] FIG. 9 is an equivalent circuit diagram of a memory string. [Figure 10] FIG. 10 is an equivalent circuit diagram of a memory string. [Figure 11] 11A and 11B are top views of a memory string. [Figure 12] 12A and 12B are cross-sectional views of a memory cell. [Figure 13] FIG. 13 is a cross-sectional view of a memory cell. [Figure 14] Figure 14A is a diagram explaining the classification of crystal structures, Figure 14B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 14C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 15] 15A and 15B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 16] 16A and 16B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 17] 17A and 17B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 18] 18A and 18B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 19] 19A and 19B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 20] 20A and 20B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 21] 21A and 21B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 22] 22A and 22B are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 23] FIG. 23 is a circuit diagram of the semiconductor device. [Figure 24] FIG. 24 is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 25] 25A and 25B are timing charts illustrating an example of the operation of the semiconductor device. [Figure 26] Fig. 26A is a perspective view illustrating an example of the configuration of a semiconductor device, Fig. 26B is a top view illustrating an example of the configuration of a semiconductor device, and Fig. 26C is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 27] Fig. 27A is a perspective view illustrating an example of the configuration of a semiconductor device, Fig. 27B is a top view illustrating an example of the configuration of a semiconductor device, and Fig. 27C is a cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 28] 28A and 28B are cross-sectional views illustrating a semiconductor device. [Figure 29] 29A and 29B are cross-sectional views illustrating a semiconductor device. [Figure 30] FIG. 30 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 31] FIG. 31 is a diagram illustrating a configuration example of a semiconductor device. [Figure 32] FIG. 32 is a diagram illustrating an example of constructing an information processing system using a plurality of storage devices. [Figure 33] FIG. 33 is a block diagram illustrating the CPU. [Figure 34] 34A and 34B are perspective views of the semiconductor device. [Figure 35] 35A and 35B are perspective views of the semiconductor device. [Figure 36] 36A and 36B are perspective views of the semiconductor device. [Figure 37] FIG. 37A is a perspective view showing an example of a semiconductor wafer, FIG. 37B is a perspective view showing an example of a chip, and FIGS. 37C and 37D are perspective views showing an example of an electronic component. [Figure 38] 38A and 38B are diagrams showing various storage devices by tier. [Figure 39] 39A to 39J are perspective views or schematic diagrams illustrating examples of electronic devices. [Figure 40] 40A to 40E are perspective views or schematic diagrams illustrating an example of an electronic device. [Figure 41] 41A to 41C are diagrams illustrating an example of an electronic device. [Figure 42] FIG. 42 is a diagram illustrating an example of the configuration of a computer system. [Figure 43] Figure 43 shows the hierarchical structure of IoT networks and trends in required specifications. [Figure 44] Figure 44 is an image diagram of factory automation. [Figure 45] Fig. 45A is a perspective conceptual diagram of a semiconductor device, and Fig. 45B is an equivalent circuit diagram of a memory cell. [Figure 46] FIG. 46 is a timing chart illustrating the operation of the 3D OSNAND string. [Figure 47] 47A is a diagram showing the Id-Vwg characteristics of the transistor WTr, and FIG. 47B is a diagram showing the relationship between the threshold voltage of the transistor WTr and Vpre. [Figure 48] 48A and 48B show the retention characteristics of a 3D OSNAND string. [Figure 49] 49A and 49B are diagrams showing simulation results of the retention characteristics of a memory cell. [Figure 50]FIG. 50 is a diagram showing the simulation results of the data held in the memory cell and the read current Irbl. DETAILED DESCRIPTION OF THE INVENTION

[0017] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0018] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the present specification discloses cases in which X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0019] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling its on and off states. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0020] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0021] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0022] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0023] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.

[0024] Furthermore, in this specification, etc., a "resistance element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0Ω. Therefore, in this specification, etc., a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, etc. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0025] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0026] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are the input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the transistor's conductivity type (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the transistor structure, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0027] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0028] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0029] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply high-level potentials," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply low-level potentials," the low-level potentials provided by both wirings do not have to be equal to each other.

[0030] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move, and the amount of current is expressed as a positive value. In other words, the direction in which negative carriers move is opposite to the direction of current, and the amount of current is expressed as a negative value. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0031] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0032] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0033] Furthermore, the positional relationship of the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, in this specification, terms indicating placement, such as "above" and "below," are sometimes used for convenience in describing the positional relationship of the components with reference to the drawings. Therefore, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the left (or right) surface of the conductor" by rotating the drawing by 90 degrees.

[0034] Similarly, in this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state where "electrode B is formed on insulating layer A," but does not exclude states such as "electrode B is formed below insulating layer A" or "electrode B is formed on the right (or left) side of insulating layer A."

[0035] Furthermore, in this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0037] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0038] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0039] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can, for example, increase the defect level density of the semiconductor, decrease carrier mobility, or decrease crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

[0040] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Examples include electrical switches and mechanical switches. In other words, the switch is not limited to a specific type as long as it can control a current.

[0041] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0043] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0044] As used herein, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. "Substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less. "Substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0045] In this specification and elsewhere, when referring to counting and measurement values, or to objects, methods, and events that can be converted into counting or measurement values, terms such as "identical," "same," "equal," or "uniform" are used, they include a margin of error of plus or minus 20%, unless otherwise specified.

[0046] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when a metal oxide is referred to as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0047] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0048] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0049] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0050] Note that the content described in the embodiments refers to the content described in each embodiment (or example) using various figures, or the content described using text in the specification.

[0051] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0052] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0053] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations, etc. may be included.

[0054] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol. For example, one of two wirings GL may be written as wiring GL[1], and the other as wiring GL[2].

[0055] (Embodiment 1) In this embodiment, a structural example and a manufacturing method example of a memory cell 100 that functions as a memory device according to one embodiment of the present invention will be described with reference to drawings.

[0056] <Storage device configuration example> FIG. 1A shows a perspective view of a memory cell 100 according to one embodiment of the present invention. The memory cell 100 is a memory device having a three-dimensional stacked structure. In FIG. 1A, a portion of the memory cell 100 is omitted to show the internal structure of the memory cell 100. Note that arrows indicating the X, Y, and Z directions may be added in the drawings. The X, Y, and Z directions are mutually orthogonal. In this specification and the like, one of the X, Y, and Z directions may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining may be referred to as the "third direction" or "third direction." Note that in the present embodiment and the like, the direction in which a structure 130 (described later) extends is defined as the Z direction.

[0057] FIG. 1B is a cross-sectional view showing a portion of memory cell 100 shown in FIG. 1A. FIG. 1B is a cross-sectional view of a portion of memory cell 100 as viewed from the Y direction. FIG. 1B is a cross-sectional view of an XZ plane passing through central axis 108. FIG. 2A is a cross-sectional view of portion A1-A2 indicated by a dashed line in FIG. 1B as viewed from the Z direction. FIG. 2B is a cross-sectional view of portion B1-B2 indicated by a dashed line in FIG. 1B as viewed from the Z direction.

[0058] The memory cell 100 has multiple insulators 101 arranged above a substrate (not shown). The multiple insulators 101 are stacked in order from the substrate side. In this embodiment and other embodiments, the i-th insulator 101 (i is an integer equal to or greater than 1) is referred to as insulator 101[i]. FIG. 1B shows insulator 101[i+1] arranged above insulator 101[i] and insulator 101[i+2] arranged above insulator 101[i+1]. In addition, a conductor 102 is located between insulator 101[i] and insulator 101[i+1], and a conductor 103 is located between insulator 101[i+1] and insulator 101[i+2]. Note that the insulators 101, conductor 102, and conductor 103 extend along the Y direction. The memory cell 100 also includes an insulator 121 that covers the side surfaces of the insulator 101, the conductor 102, and the conductor 103.

[0059] The memory cell 100 also has a structure 130. The structure 130 extends in the Z direction along the central axis 108. FIG. 3 shows a perspective view of the structure 130. The structure 130 has a columnar shape. In FIG. 3, part of the structure 130 is omitted to show the internal structure of the structure 130. A part of the structure 130 functions as part of the memory cell 100. As shown in FIGS. 1 and 3, the structure 130 has unevenness on its side surface extending in the Z direction.

[0060] In this embodiment, the outer peripheral shape of the structure 130 is shown as a circle when viewed from the Z direction, but the outer peripheral shape of the structure 130 does not have to be a circle. For example, it may be a polygon such as a triangle or a rectangle. Furthermore, the outer peripheral shape of the structure 130 may be formed by curves, or may be formed by a combination of curves and straight lines.

[0061] The structure 130 has a region (also referred to as "intersection R") that intersects with the conductor 102 and a region (also referred to as "intersection W") that intersects with the conductor 103. The structure 130 also includes an insulator 111, a functional body 112, an insulator 113, a semiconductor 114, a conductor 115, an insulator 116, a semiconductor 117, an insulator 118, and a conductor 119.

[0062] Specifically, the conductor 119 extends in the Z direction along the central axis 108, and the insulator 118 is provided adjacent to the conductor 119. Furthermore, the semiconductor 117 is provided adjacent to the insulator 118. Furthermore, the insulator 116 is provided adjacent to the semiconductor 117.

[0063] Furthermore, in the structure 130, at the intersection W, the semiconductor 114 is provided adjacent to the insulator 116, the insulator 113 is provided adjacent to the semiconductor 114, the functional body 112 is provided adjacent to the insulator 113, and the insulator 111 is provided adjacent to the functional body 112. FIG. 2A is a cross-sectional view of the intersection W in a direction perpendicular to the Z direction. At the intersection W, the insulator 111, the functional body 112, the insulator 113, the semiconductor 114, the insulator 116, the semiconductor 117, and the insulator 118 are provided concentrically outside the conductor 119.

[0064] Furthermore, in structure 130, conductor 115 is provided adjacent to insulator 116 at intersection R, semiconductor 114 is provided adjacent to conductor 115, and insulator 113 is provided adjacent to semiconductor 114. Figure 2B is a cross-sectional view of intersection R in a direction perpendicular to the Z direction. At intersection R, insulator 113, semiconductor 114, conductor 115, insulator 116, semiconductor 117, and insulator 118 are provided concentrically outside conductor 119.

[0065] At the intersection W, the insulator 111, the functioning body 112, the insulator 113, the semiconductor 114, and the conductor 103 function as a transistor WTr. Therefore, it can be said that the transistor WTr is formed at the intersection W.

[0066] At the intersection W, the conductor 103 functions as the gate electrode of the transistor WTr. Therefore, the insulator 111, the functional body 112, and the insulator 113 function as the gate insulator of the transistor WTr. The semiconductor 114 functions as a semiconductor in which the channel of the transistor WTr is formed.

[0067] Also, at the intersection W, the conductor 119 may function as a back gate electrode of the transistor WTr. Therefore, the insulator 116, the semiconductor 117, and the insulator 118 may function as a back gate insulator of the transistor WTr. Figure 2A is also a cross-sectional view of the transistor WTr as viewed from the Z direction.

[0068] At the intersection R, the conductor 119, the insulator 118, the semiconductor 117, the insulator 116, and the conductor 115 function as a transistor RTr. Furthermore, the conductor 115, the semiconductor 114, the insulator 113, and the conductor 102 function as a capacitance element Cs. Therefore, it can be said that the transistor RTr and the capacitance element Cs are formed at the intersection R.

[0069] At the intersection R, the conductor 115 functions as the gate electrode of the transistor RTr. Therefore, the insulator 116 functions as a gate insulator. The semiconductor 117 functions as a semiconductor in which the channel of the transistor RTr is formed. Furthermore, the conductor 119 may function as the back gate electrode of the transistor RTr. Therefore, the insulator 118 may function as the back gate insulator of the transistor RTr. FIG. 2B is also a cross-sectional view of the transistor RTr as viewed from the Z direction.

[0070] Furthermore, the functional body 112 of the transistor WTr can function as a charge storage layer. The threshold voltage of the transistor WTr can be controlled by storing charge in the functional body 112. For example, by increasing the threshold voltage of the transistor WTr, the transistor WTr can be made a normally-off transistor.

[0071] Charge can be injected into the functional body 112 from the conductor 103 via the insulator 111. In this case, the insulator 111 functions as an injection layer, and the insulator 113 functions as a block layer. Charge can also be injected into the functional body 112 from the semiconductor 114 via the insulator 113. In this case, the insulator 113 functions as an injection layer, and the insulator 111 functions as a block layer. It is preferable that the thickness of the injection layer when viewed from a direction perpendicular to the Z direction is thinner than that of the block layer.

[0072] When the insulator 111 is made of an oxide, the functional body 112 is made of a nitride, and the insulator 113 is made of an oxide, the transistor WTr can be called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor.

[0073] Furthermore, when n-type silicon or p-type silicon is used for the gate electrode in a MONOS transistor, it can be called a SONOS (Silicon Oxide Nitride Oxide Semiconductor) transistor.

[0074] Similarly, when tantalum nitride is used for the gate electrode and aluminum oxide is used for the block layer, the transistor can be called a TANOS (Tantalum nitride Aluminum oxide Nitride Oxide Semiconductor) type transistor.

[0075] When tantalum nitride is used for the gate electrode and hafnium oxide is used for the block layer, the transistor can be called a THNOS (Tantalum nitride Hafnium oxide Nitride Oxide Semiconductor) type transistor.

[0076] The functional body 112, which functions as a charge storage layer, is preferably made of a material having a smaller band gap than the insulators 111 and 113. For example, silicon oxide may be used for the insulators 111 and 113, and an insulator such as silicon nitride may be used for the functional body 112. When silicon nitride is used for the functional body 112, it is preferable to use silicon-rich silicon nitride. For example, when silicon nitride is used for the insulators 111 and 113, silicon nitride having a higher silicon content than the silicon nitride used for the insulators 111 and 113 may be used for the functional body 112.

[0077] The functional body 112 functioning as a charge storage layer may be a semiconductor. For example, a semiconductor such as silicon may be used as the functional body 112. A transistor WTr using a semiconductor for the functional body 112 can be called an FG (Floating Gate) type transistor.

[0078] Each of the insulator 111, the functional body 112, and the insulator 113 may be a laminate of multiple layers. For example, the insulator functioning as a block layer may be a laminate of silicon oxide and aluminum oxide.

[0079] 4A shows an equivalent circuit diagram of the memory cell 100. In FIG. 4A, one of the source and drain of the transistor WTr is electrically connected to the semiconductor 114, and the other of the source and drain is electrically connected to the gate of the transistor RTr. The gate of the transistor WTr is electrically connected to the conductor 103. The transistor WTr is a transistor having a charge storage layer between the gate and the semiconductor layer.

[0080] A part of the semiconductor 114 functions as a channel formation region of the transistor WTr. Another part of the semiconductor 114 functions as a source or drain of the transistor WTr. The semiconductor 114 can also function as an electrode or wiring. A part of the conductor 103 functions as a gate of the transistor WTr.

[0081] The transistor RTr shown in FIG. 4A is a transistor having a back gate. In this embodiment, a part of the conductor 119 functions as the back gate of the transistor RTr. Another part of the semiconductor 114 and the conductor 115 function as the gate of the transistor RTr. A part of the conductor 102 functions as the other electrode of the capacitance element Cs. A part of the semiconductor 117 functions as one of the source or drain of the transistor RTr. Another part of the semiconductor 117 functions as the other of the source or drain of the transistor RTr. The semiconductor 117 can also function as an electrode or wiring.

[0082] Furthermore, as shown in FIG. 4B, a back gate need not be provided in the transistor RTr. FIG. 4B corresponds to an equivalent circuit diagram of a memory cell 100B and a memory cell 100C, which will be described later. Furthermore, as shown in FIG. 4C, a back gate may be provided in the transistor WTr. While FIG. 4C shows an example of a circuit configuration in which the back gate of the transistor WTr is electrically connected to the conductor 119, a conductor other than the conductor 119 may be provided to electrically connect to the back gate of the transistor WTr. Alternatively, a circuit configuration such as that shown in FIG. 5A or 5B may be used.

[0083] The conductor 102 functions as one electrode of the capacitor Cs. Other parts of the conductor 115 and the semiconductor 114 function as the other electrode of the capacitor Cs. In this specification and the like, a node ND is a node where the gate of the transistor RTr, the other of the source or drain of the transistor WTr, and the other electrode of the capacitor Cs are electrically connected.

[0084] 6 shows a cross-sectional view of a memory string 200 including four memory cells 100 (memory cell 100[1] to memory cell 100[4]). The memory string 200 shown in FIG. 6 includes nine layers of insulators 101 (insulators 101[1] to insulator 101[9]), four layers of conductors 102 (conductors 102[1] to conductor 102[4]), and four layers of conductors 103 (conductors 103[1] to conductor 103[4]).

[0085] 7 shows an equivalent circuit diagram of the memory string 200. The memory string 200 has a configuration in which four memory cells 100 are connected in series. Therefore, the memory string 200 is a NAND type memory device.

[0086] In addition, in equivalent circuit diagrams, etc., "OS" may be added to the circuit symbol of a transistor to indicate that the transistor is an OS transistor. Similarly, "Si" may be added to the circuit symbol of a transistor to indicate that the transistor is a Si transistor (a transistor that uses silicon in the semiconductor layer in which the channel is formed). In Figure 7, the transistors WTr and RTr are shown to be OS transistors.

[0087] 7, the transistor WTr, the transistor RTr, and the capacitance element Cs of the memory cell 100[1] are shown as the transistor WTr[1], the transistor RTr[1], and the capacitance element Cs[1], respectively. The transistors WTr, the transistors RTr, and the capacitance elements Cs of the memory cells 100[2] to 100[4] are also shown in the same manner.

[0088] The number of memory cells 100 included in the memory string 200 is not limited to 4. If the number of memory cells 100 included in the memory string 200 is n, n may be an integer of 2 or more.

[0089] Furthermore, "a configuration in which multiple memory cells 100 are connected in series" refers to a configuration in which the drain (or source) of transistor WTr[k] included in memory cell 100[k] (k is an integer greater than or equal to 1 and less than or equal to n) is electrically connected to the source (or drain) of transistor WTr[k+1] included in memory cell 100[k+1], and the drain (or source) of transistor RTr[k] included in memory cell 100[k] is electrically connected to the source (or drain) of transistor RTr[k+1] included in memory cell 100[k+1].

[0090] The semiconductors in which the channels of the transistors WTr and RTr are formed can be single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0091] Note that the semiconductor used in the transistor may be a stack of semiconductors. When semiconductor layers are stacked, semiconductors having different crystalline states or different semiconductor materials may be used.

[0092] The semiconductor 114 and the semiconductor 117 may be made of the same material or different materials. For example, both the semiconductor 114 and the semiconductor 117 may be made of oxide semiconductors. Alternatively, both the semiconductor 114 and the semiconductor 117 may be made of silicon. Alternatively, the semiconductor 114 may be made of oxide semiconductor and the semiconductor 117 may be made of silicon. Alternatively, the semiconductor 114 may be made of silicon and the semiconductor 117 may be made of oxide semiconductor.

[0093] In particular, the transistor WTr is preferably a transistor using an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. When an OS transistor is used for the transistor WTr, charge written to the node ND (also referred to as a "storage node") can be retained for a long period of time. When an OS transistor is used as a transistor constituting a memory cell 100, the memory cell 100 can be called an "OS memory." Furthermore, a memory string 200 including the memory cell 100 can also be called an "OS memory."

[0094] A NAND-type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device with multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0095] The transistor RTr may be a transistor using silicon in a semiconductor layer in which a channel is formed (also referred to as a "Si transistor"). The transistor RTr may be formed of a Si transistor, and the transistor WTr may be formed of an OS transistor. FIG. 8 shows an equivalent circuit diagram of a memory string 200 in which an OS transistor is used as the transistor WTr and a Si transistor is used as the transistor RTr.

[0096] OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off, so OS memory can also be considered non-volatile memory.

[0097] Furthermore, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0098] Furthermore, because OS memory writes charge to nodes via OS transistors, it does not require the high voltages required by conventional flash memory, enabling high-speed write operations. Furthermore, OS memory does not require the erase operation required by flash memory before rewriting data. Furthermore, because no charge is injected or extracted from the floating gate or charge trapping layer, OS memory allows for virtually unlimited data write and read operations. OS memory is less susceptible to degradation than conventional flash memory, making it highly reliable.

[0099] In addition, unlike magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), OS memory does not undergo structural changes at the atomic level when data is rewritten. Therefore, OS memory has better rewrite endurance than magnetoresistive random access memory and resistive random access memory.

[0100] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory operates stably and has high reliability even in a high-temperature environment. Furthermore, an OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that operates stably and has high reliability even in a high-temperature environment can be realized.

[0101] 9, a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr depending on the purpose or application. Also, as shown in FIG. 10, Si transistors may be used for both the transistor WTr and the transistor RTr depending on the purpose or application.

[0102] By providing a plurality of memory cells 100 consecutively in the Z direction, as in the memory string 200, it is possible to increase the storage capacity per unit area.

[0103] Furthermore, if it is desired to increase the storage capacity of a semiconductor device using memory cells 100 or memory strings 200, multiple memory cells 100 or multiple memory strings 200 can be arranged in a staggered pattern (see FIG. 11A) or a grid pattern (see FIG. 11B). FIG. 11 is a top view of a memory string.

[0104] Table 1 shows a comparison between 3D NAND memory devices fabricated with Si transistors and 3D OS NAND memory devices.

[0105] [Table 1]

[0106] [Modification] Next, a description will be given of modified examples of the memory cell 100. The modified examples of the memory cell described below can be appropriately combined with other memory cells shown in this specification and the like.

[0107] 12A shows a cross-sectional view of memory cell 100A. Memory cell 100A is a modified example of memory cell 100. Therefore, in the present embodiment and the like, differences between memory cell 100A and memory cell 100 will be mainly described.

[0108] A memory cell according to one embodiment of the present invention may have, at the intersection R, a semiconductor 114 adjacent to an insulator 116, a conductor 115 adjacent to the semiconductor 114, and an insulator 113 adjacent to the conductor 115, as in the memory cell 100A shown in FIG. 12A.

[0109] In the memory cell 100A, the conductor 119, the insulator 118, the semiconductor 117, the insulator 116, the semiconductor 114, and the conductor 115 function as a transistor RTr. The semiconductor 114 may function as a gate electrode. The semiconductor 114 may also function as a gate insulator. The conductor 115, the insulator 113, and the conductor 102 function as a capacitance element Cs.

[0110] 12B shows a cross-sectional view of the memory cell 100B. The memory cell 100B is a modified example of the memory cell 100. As in the memory cell 100B, the formation of the conductor 119 functioning as a back gate may be omitted and the back gate may be filled with the insulator 118. By not providing the conductor 119, the manufacturing process can be simplified and the productivity of the memory device can be improved.

[0111] 13 shows a cross-sectional view of memory cell 100C. Memory cell 100C is a modified example of memory cell 100 and also a modified example of memory cell 100B. Like memory cell 100C, the formation of conductor 119 functioning as a back gate may be omitted, and the region where conductor 119 is to be formed may be left empty, leaving a cavity 120. By leaving the cavity empty without providing conductor 119, the manufacturing process can be simplified, and the productivity of the memory device can be further improved.

[0112] [Memory cell constituent materials] Next, constituent materials that can be used for the memory cell 100 and the like will be described.

[0113] [substrate] The memory cells 100 and the memory strings 200 can be provided on a substrate. Examples of the substrate include an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride (GaN). Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0114] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0115] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0116] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0117] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0118] Furthermore, the electrical characteristics of an OS transistor can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0119] In this specification and the like, the term "oxynitride" refers to a material that contains more oxygen than nitrogen as a main component. For example, "silicon oxynitride" refers to a material that contains more oxygen than nitrogen and that contains silicon, nitrogen, and oxygen. In this specification and the like, the term "nitride oxide" refers to a material that contains more nitrogen than oxygen as a main component. For example, "aluminum nitride oxide" refers to a material that contains more nitrogen than oxygen and that contains aluminum, nitrogen, and oxygen.

[0120] When an oxide semiconductor is used for the semiconductor 114 and / or the semiconductor 117, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 114 and / or the semiconductor 117, oxygen vacancies in the semiconductor 114 and / or the semiconductor 117 can be compensated for.

[0121] Furthermore, a single insulating layer made of the above-mentioned material may be used as the insulator, but a plurality of insulating layers made of the above-mentioned material may also be stacked.

[0122] For example, when an insulator is provided in contact with a conductor, it is preferable to use an insulator that has a function of suppressing oxygen permeation as the insulator in order to prevent oxidation of the conductor, such as hafnium oxide, aluminum oxide, or silicon nitride.

[0123] When an insulator is stacked adjacent to a conductor, it is preferable to use an insulator that has a function of suppressing oxygen permeation as the insulator in contact with the conductor. For example, an insulator in contact with the conductor may be formed using hafnium oxide, and an insulator in contact with the insulator using silicon oxynitride may be formed.

[0124] [conductor] The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0125] Furthermore, a conductive layer formed of the above-mentioned material may be used as a single layer as a conductor, or multiple conductive layers formed of the above-mentioned material may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0126] When an oxide semiconductor, which is a type of metal oxide, is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0127] In particular, a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed is preferably used as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0128] [Oxide semiconductor] A metal oxide (oxide semiconductor) that functions as a semiconductor is preferably used as the semiconductor 114 and / or the semiconductor 117. In particular, an oxide semiconductor is preferably used as the semiconductor 114. Oxide semiconductors that can be used in the memory cell 100 will be described below.

[0129] The oxide semiconductor preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0130] Here, we consider a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used for the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of two or more of the above elements.

[0131] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 14A. Fig. 14A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0132] As shown in Figure 14A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0133] The structure within the bold frame in Figure 14A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0134] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 14B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 14B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 14B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 14B is 500 nm.

[0135] As shown in Figure 14B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 14B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0136] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 14C. Figure 14C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 14C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0137] As shown in FIG. 14C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0138] [Oxide semiconductor structure] Note that oxide semiconductors may be classified differently from those shown in FIG. 14A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) and nanocrystalline oxide semiconductor (nc-OS). Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0139] Next, we will explain the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS.

[0140] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0141] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0142] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0143] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0144] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0145] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0146] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current and field-effect mobility of transistors. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in transistor semiconductor layers. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0147] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0148] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0149] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0150] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0151] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0152] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0153] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0154] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0155] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0156] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0157] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0158] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0159] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0160] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0161] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 100 . Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may be referred to as an i-type or substantially i-type.

[0162] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0163] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0164] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0165] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0166] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0167] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0168] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17atoms / cm 3 Do the following:

[0169] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0170] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0171] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 114 and the semiconductor 117 is not limited to the oxide semiconductors described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor 114 and the semiconductor 117. For example, a semiconductor of an element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may be used as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0172] In this specification, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0173] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0174] The semiconductor material used in the semiconductor device according to one embodiment of the present invention may be, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0175] [Film formation method] Conductors, insulators, and semiconductors can be formed using methods such as sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0176] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0177] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0178] The ALD method is also a film formation method that can reduce plasma damage to the workpiece, and because no plasma damage occurs during film formation, the ALD method also produces films with fewer defects.

[0179] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0180] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment compared to when forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0181] Alternatively, the ALD method may be used to deposit a film by sequentially introducing source gases into a chamber under atmospheric or reduced pressure and repeating this gas introduction sequence. For example, two or more source gases may be sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). To prevent mixing of the multiple source gases, an inert gas (e.g., argon or nitrogen) may be introduced simultaneously with or after the first source gas, followed by the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the second source gas is introduced. The first source gas adsorbs onto the substrate surface to form a first thin layer, which then reacts with the second source gas introduced later, forming a thin film. Repeating this gas introduction sequence multiple times until the desired thickness is achieved allows for the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment, making this method suitable for fabricating fine FETs.

[0182] Thermal CVD methods such as MOCVD and ALD can form a variety of films, including metal films, semiconductor films, and inorganic insulating films. For example, to form an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. Furthermore, the combinations are not limited to these; trimethylgallium can be replaced with triethylgallium (Ga(C2H5)3), and dimethylzinc can be replaced with diethylzinc (Zn(C2H5)2).

[0183] For example, when forming a hafnium oxide film using a film-forming system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizer. Other materials include tetrakis(ethylmethylamido)hafnium.

[0184] For example, when forming an aluminum oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizer. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0185] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be filmed, and radicals of oxidizing gas (O2, dinitrogen monoxide) are supplied to react with the adsorbed material.

[0186] For example, when forming a tungsten film using an ALD deposition system, WF6 gas and B2H6 gas are introduced in sequence and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced in sequence and repeatedly to form the tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0187] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film formation system using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, followed by Ga(CH3)3 gas and O3 gas, followed by GaO layer, followed by Zn(CH3)2 gas and O3 gas, followed by ZnO layer. Note that the order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O layers may also be formed using these gases. While HO gas obtained by bubbling water with an inert gas such as Ar may be used instead of O3 gas, it is preferable to use O3 gas, which does not contain H. Furthermore, In(CH3)3 gas may be replaced with In(C2H5)3 gas. Furthermore, Ga(CH3)3 gas may be replaced with Ga(C2H5)3 gas. Moreover, Zn(C2H5)2 gas may be used instead of Zn(CH3)2 gas.

[0188] <Example of how to make a memory device> Next, an example of a method for manufacturing the memory cell 100 will be described.

[0189] 15A is fabricated. The laminate 140 has an insulator 101, a conductor 102, and a conductor 103. The insulator 101[i] is disposed above a substrate (not shown), the conductor 102 is disposed on the insulator 101[i], the insulator 101[i+1] is disposed on the conductor 102, the conductor 103 is disposed on the insulator 101[i+1], and the insulator 101[i+2] is disposed on the conductor 103.

[0190] It is preferable that the insulator 101 is a material with a reduced concentration of impurities such as water or hydrogen. For example, the amount of hydrogen molecules desorbed per unit area of ​​the insulator 101 is 2×10 in the range of 50° C. to 500° C., as measured by thermal desorption spectroscopy (TDS). 15 molecules / cm 2 Less than 1 × 10 15 molecules / cm 2 Less than or equal to 5 × 10 14 molecules / cm 2 The insulator 101 may be an insulator that releases oxygen when heated. However, the materials that can be used for the insulator 101 are not limited to those described above.

[0191] The insulator 101 may have a stacked structure of multiple insulators. For example, the insulator 101 may be a stacked structure of hafnium oxide and silicon oxynitride. Of the multiple insulators that make up the insulator 101, it is preferable to use the insulator that has the above-mentioned function of suppressing oxygen permeation as the insulator that is in contact with the conductor 103.

[0192] Next, a resist mask is formed on the stack 140, and parts of the insulator 101, the conductor 103, and the conductor 102 are removed by etching using the resist mask to form an opening 131 in the stack 140 (see FIG. 15B).

[0193] The resist mask can be formed by, for example, lithography, printing, inkjet printing, or the like, as appropriate. When the resist mask is formed by the inkjet printing, a photomask is not used, which may reduce the manufacturing cost. Furthermore, the etching process may be a dry etching process, a wet etching process, or both. Processing by the dry etching process is suitable for fine processing.

[0194] In forming a resist mask by lithography, a resist is first formed, and then the resist is exposed to light through a photomask. The exposed region is then removed or left using a developer to form a resist mask.

[0195] Conductors, semiconductors, insulators, etc. can be processed into desired shapes by etching through the resist mask. For example, a resist mask can be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Immersion technology can also be used, in which exposure is performed by filling a liquid (e.g., water) between the substrate and the projection lens. Instead of the light described above, electron beams or ion beams can also be used. Note that when electron beams or ion beams are used, a photomask is not required. Note that the resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0196] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched, whereby a hard mask having a desired shape can be formed.

[0197] As a dry etching apparatus for performing an etching process using the dry etching method, for example, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0198] Next, a portion of the conductor 103 exposed on the side surface of the opening 131 is etched to recede the conductor 103 from the side surface of the opening 131 (see FIG. 16A). The etching of the conductor 103 may be performed under conditions that provide a selectivity with respect to the insulator 101 and the conductor 102.

[0199] Next, insulator 111 is formed along the side surface of opening 131 (see FIG. 16B). The surfaces of insulator 101, conductor 103, and conductor 102 exposed in opening 131 are covered with insulator 111. For example, silicon oxide is used as insulator 111. Note that insulator 111 may have a layered structure of multiple insulators.

[0200] Next, the function body 112 is formed along the surface of the insulator 111 (see FIG. 17A). For example, silicon nitride is used as the insulator 111. The function body 112 may have a laminated structure of a plurality of insulators.

[0201] Next, the insulator 111 and the functional body 112 are partially etched within the opening 131. The insulator 111 and the functional body 112 are etched except for the portions that overlap with the insulator 101 when viewed from the Z direction (see FIG. 17B).

[0202] Next, a portion of the conductor 102 exposed on the side surface of the opening 131 is etched to recede the conductor 102 from the side surface of the opening 131 (see FIG. 18A). The etching of the conductor 102 may be performed under conditions that provide a selectivity with respect to the insulator 101 and the conductor 103.

[0203] Next, insulator 113 is formed along the side surface of opening 131 (see FIG. 18B). The surfaces of insulator 101, insulator 111, functional body 112, and conductor 102 exposed in opening 131 are covered with insulator 113.

[0204] In the case where an oxide semiconductor is used for the semiconductor 114, for example, silicon oxide, silicon oxynitride, or the like can be used as appropriate for the insulator 113. By providing an insulator containing oxygen in contact with the semiconductor 114, oxygen vacancies in the semiconductor 114 can be reduced, and the reliability of the transistor can be improved.

[0205] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 113. The oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C. The insulator 113 may have a laminated structure of a plurality of insulators.

[0206] After the insulator 113 is formed, an oxygen-adding treatment, which will be described later, may be performed.

[0207] Next, the semiconductor 114 and the conductor 115 are formed along the side surface of the opening 131 (see FIG. 18B). In this embodiment, the semiconductor 114 is an oxide semiconductor having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition thereof.

[0208] The semiconductor material used for the semiconductor 114 may be, for example, a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these. The semiconductor material used for the semiconductor 114 may also be a metal oxide having a composition of In:Zn=5:1 or In:Zn=10:1, or a composition close to these. Indium oxide may also be used for the semiconductor 114.

[0209] The semiconductor 114 may also have a multi-layer structure. For example, the semiconductor 114 may be a stack of a metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or a composition close to these, and a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these.

[0210] Alternatively, the semiconductor 114 may have a three-layer structure in which a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:3, or In:Ga:Zn=10:1:3, or a composition close to these, is sandwiched between two layers of metal oxide having a composition of In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, or a composition close to these.

[0211] In addition, in the manufacturing process of the memory cell, it is preferable to perform heat treatment while the surface of the semiconductor 114 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the semiconductor 114, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0212] Note that by performing a treatment of supplying oxygen to the semiconductor 114 (also referred to as an “oxygen addition treatment”), oxygen vacancies in the semiconductor 114 are repaired by the supplied oxygen, in other words, “V O +O→null reaction can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the semiconductor 114, and the hydrogen can be removed as HO (dehydration). As a result, the hydrogen remaining in the semiconductor 114 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0213] Alternatively, oxygenation treatment can be performed by microwave treatment in an oxygen-containing atmosphere. In this case, the semiconductor 114 is irradiated with microwaves, high-frequency waves such as RF, oxygen plasma, oxygen radicals, or the like. For the microwave treatment, a microwave treatment device having a power source for generating high-density plasma using microwaves is preferably used. The microwave treatment device may also have a power source for applying RF to the substrate side. High-density plasma can be generated by high-density oxygen radicals. Applying RF to the substrate (not shown) can efficiently guide oxygen ions generated by high-density plasma into the opening 131. The microwave treatment is preferably performed under reduced pressure, with a pressure of 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, and even more preferably 400 Pa or higher. The oxygen flow ratio O2 / (O2+Ar) is preferably 50% or lower, and more preferably 10% to 30%. The treatment temperature is preferably 750°C or lower, preferably 500°C or lower, for example, approximately 400°C. Furthermore, after the oxygen plasma treatment, a heat treatment may be carried out successively without exposure to the outside air.

[0214] The V contained in the semiconductor 114 is O H can be split off and hydrogen H can be removed from the semiconductor 114. O H→H+V O )" and "V O +O→null” reaction occurs, and the hydrogen concentration in the semiconductor 114 can be reduced. O H can be reduced to lower the carrier concentration.

[0215] After the semiconductor 114 is formed, the conductor 115 is formed. In this embodiment, the conductor 115 is formed using tungsten.

[0216] Next, a portion of the conductor 115 in the opening 131 is etched. The conductor 115 is etched except for the portion that overlaps with the semiconductor 114 when viewed from the Z direction (see FIG. 19A). This exposes the semiconductor 114 and the conductor 115 in the opening 131. After the semiconductor 114 and the conductor 115 are exposed, an oxygen-adding process may be performed.

[0217] Next, the insulator 116 is formed along the side surface of the opening 131 (see FIG. 19B). The surfaces of the semiconductor 114 and the conductor 115 exposed in the opening 131 are covered with the insulator 116. When an oxide semiconductor is used for the semiconductor 114, for example, silicon oxide, silicon oxynitride, or the like may be used as the insulator 116 as appropriate. By providing an insulator containing oxygen in contact with the semiconductor 114, oxygen vacancies in the semiconductor 114 can be reduced and the reliability of the transistor can be improved. The insulator 116 may be made of a material similar to that of the insulator 113. The insulator 116 may have a stacked structure of multiple insulators.

[0218] In particular, when an oxide semiconductor is used for the semiconductor 114 and the semiconductor 117, the insulator 116 is preferably an insulator having a region containing oxygen that is released by heating. The insulator 116 may have a stacked structure of multiple insulators. For example, when an oxide semiconductor is used for the semiconductor 114 and the semiconductor 117, the insulator 116 may have a three-layer structure of silicon oxide or silicon oxynitride, hafnium oxide or aluminum oxide, and silicon oxide or silicon oxynitride. That is, the insulator 116 may have a structure in which one layer of hafnium oxide or aluminum oxide is sandwiched between two layers of silicon oxide or silicon oxynitride. Note that the insulator 116 may have a two-layer structure or a four-layer or more layer structure.

[0219] After the formation of the insulator 116, an oxygen-adding treatment may be performed (see FIG. 20A).

[0220] Next, the semiconductor 117 is formed along the side surface of the opening 131 (see FIG. 20B). The surface of the insulator 116 exposed in the opening 131 is covered with the semiconductor 117. When an oxide semiconductor is used for the semiconductor 117, oxygen addition treatment may be performed as in the case of using an oxide semiconductor for the semiconductor 114.

[0221] Next, the insulator 118 is formed along the side surface of the opening 131 (see FIG. 21A). The surface of the semiconductor 117 exposed in the opening 131 is covered with the insulator 118. When an oxide semiconductor is used for the semiconductor 117, for example, silicon oxide, silicon oxynitride, or the like can be used as the insulator 118 as appropriate. By providing an insulator containing oxygen in contact with the semiconductor 117, oxygen vacancies in the semiconductor 117 can be reduced and the reliability of the transistor can be improved. The insulator 118 may be made of a material similar to that of the insulator 113 or the insulator 116.

[0222] The insulator 118 may have a stacked-layer structure of multiple insulators. When an oxide semiconductor is used for the semiconductor 117, the insulator in contact with the semiconductor 117, among the multiple insulators included in the insulator 118, preferably has a region containing oxygen that is released by heating. The insulator in contact with the conductor 119 preferably has a function of suppressing oxygen transmission. For example, silicon oxide or silicon oxynitride may be used as the insulator in contact with the semiconductor 117 among the multiple insulators included in the insulator 118. Furthermore, hafnium oxide or aluminum oxide may be used as the insulator in contact with the conductor 119 among the multiple insulators included in the insulator 118.

[0223] Alternatively, for example, the insulator 118 may be a stack of silicon oxide or silicon oxynitride, aluminum oxide, and silicon nitride. When silicon nitride is used for the insulator 118, it is preferable to use silicon nitride with a low hydrogen content.

[0224] Next, after the formation of the insulator 118, the conductor 119 is formed (see FIG. 21B). In this embodiment, tungsten is used as the conductor 119. Note that the conductor 119 may have a stacked structure of multiple conductors. Of the multiple conductors that make up the conductor 119, it is preferable to use a conductive material that is resistant to oxidation for the conductor that is in contact with the insulator 118. For example, titanium nitride may be used for the conductor that is in contact with the insulator 118 of the conductor 119. For example, the conductor 119 may be a stacked structure of titanium nitride and tungsten.

[0225] In this way, the structure 130 is formed in the opening 131. Next, a part of the stacked body 140 is removed in a region that does not overlap with the structure 130 when viewed from the Z direction to form a region 132 (see FIG. 22A). The region 132 can be formed in the same manner as the opening 131. In the region 132, the side surfaces of the insulator 101, the conductor 102, and the conductor 103 are exposed.

[0226] Next, an insulator 121 is formed to cover the exposed side surfaces of the insulator 101, the conductor 102, and the conductor 103 (see FIG. 22B). The insulator 121 is preferably made of an insulating material that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, aluminum oxide or the like can be used for the insulator 121.

[0227] The insulator 121 may have a stacked structure of multiple insulators. For example, the insulator 121 may be a stacked structure of hafnium oxide and silicon oxynitride. Of the multiple insulators that make up the insulator 121, an insulator that has a function of suppressing oxygen permeation is preferably used as the insulator in contact with the conductor 102 and the conductor 103.

[0228] In this manner, the memory cell 100 can be fabricated.

[0229] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0230] (Embodiment 2) In this embodiment, an example of a circuit configuration and an example of an operation method of a semiconductor device 300 including a plurality of memory strings 200 will be described with reference to the drawings.

[0231] <Circuit configuration example> The circuit configuration of the semiconductor device 300 will be described with reference to Fig. 23. The semiconductor device 300 has m memory strings 200. In this embodiment and the like, the first memory string 200 is referred to as memory string 200[1], the mth memory string 200 is referred to as memory string 200[m] (m is an integer equal to or greater than 1), and the jth memory string 200 is referred to as memory string 200[j] (j is an integer equal to or greater than 1 and equal to or less than m).

[0232] As described in the above embodiment, the memory string 200 has n memory cells 100. In Fig. 23, the memory cell 100 has the circuit configuration shown in Fig. 4A, but the memory cell 100 may have the circuit configuration shown in Figs. 4B, 4C, 5A, and 5B. In the present embodiment and the like, the kth (k is an integer between 1 and n) memory cell 100 included in the jth memory string 200 is referred to as memory cell 100[k,j].

[0233] 23 has n wirings WWL, n wirings RWL, m wirings WBL, m wirings RBL, and m wirings BGL. In this embodiment and the like, the kth wirings WWL and RWL are respectively indicated as wiring WWL[k] and wiring RWL[k]. Furthermore, the jth wirings WBL, RBL, and BGL are respectively indicated as wiring WBL[j], wiring RBL[j], and wiring BGL[j].

[0234] The wiring WWL[1] is electrically connected to the gates (conductors 103) of the transistors WTr included in each of the memory cells 100[1,1] to 100[1,m]. The wiring WWL[k] is electrically connected to the gates (conductors 103) of the transistors WTr included in each of the memory cells 100[k,1] to 100[k,m]. The wiring WWL[n] is electrically connected to the gates (conductors 103) of the transistors WTr included in each of the memory cells 100[n,1] to 100[n,m].

[0235] The wiring RWL[1] is electrically connected to the capacitor Cs included in each of the memory cells 100[1,1] to 100[1,m]. The wiring RWL[k] is electrically connected to the capacitor Cs included in each of the memory cells 100[k,1] to 100[k,m]. The wiring RWL[n] is electrically connected to the capacitor Cs included in each of the memory cells 100[n,1] to 100[n,m]. The wiring RWL is electrically connected to the gate (conductor 115) of the transistor RTr through the capacitor Cs.

[0236] The wiring WBL[1] is electrically connected to one of the source or drain (semiconductor 114) of the transistor WTr included in the memory cell 100[n,1]. The wiring WBL[j] is electrically connected to one of the source or drain (semiconductor 114) of the transistor WTr included in the memory cell 100[n,j]. The wiring WBL[m] is electrically connected to one of the source or drain (semiconductor 114) of the transistor WTr included in the memory cell 100[n,m].

[0237] The wiring RBL[1] is electrically connected to one of the source and drain (semiconductor 117) of the transistor RTr included in the memory cell 100[1,1]. The wiring RBL[j] is electrically connected to one of the source and drain (semiconductor 117) of the transistor RTr included in the memory cell 100[1,j]. The wiring RBL[m] is electrically connected to one of the source and drain (semiconductor 117) of the transistor RTr included in the memory cell 100[1,m].

[0238] The wiring BGL[1] is electrically connected to the back gates (conductors 119) of the transistors RTr included in each of the memory cells 100[1,1] to 100[n,1]. The wiring BGL[j] is electrically connected to the back gates (conductors 119) of the transistors RTr included in each of the memory cells 100[1,j] to 100[n,j]. The wiring BGL[m] is electrically connected to the back gates (conductors 119) of the transistors RTr included in each of the memory cells 100[1,m] to 100[n,m].

[0239] The wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0240] 23, the region electrically connected to the other of the source or drain of the transistor RTr included in the memory cell 100[1,1] is denoted as node N1[1], and the region electrically connected to one of the source or drain of the transistor RTr included in the memory cell 100[n,1] is denoted as node N2[1]. Similarly, the nodes N1 and N2 of the memory string 200[j] are denoted as node N1[j] and node N2[j], respectively. The nodes N1 and N2 of the memory string 200[m] are denoted as node N1[m] and node N2[m], respectively.

[0241] <Example of operation> Next, an example of an operation method of the semiconductor device 300 shown in Fig. 23 will be described. In this embodiment, an example of an operation to write data to the memory cells 100 included in the memory string 200[1] and an example of an operation to read data will be described.

[0242] Note that the low-level potential (Low) and high-level potential (High) used in the following description do not mean specific potentials, and the specific potentials may differ depending on the wiring. For example, the low-level potential and high-level potential applied to the wiring WWL may be different from the low-level potential and high-level potential applied to the wiring RWL.

[0243] In this example of the operation method, it is assumed that a potential within a range in which the transistors RTr and WTr operate normally is applied to the wiring BGL in advance.

[0244] 25A is a timing chart illustrating an example of an operation for writing data to the memory string 200[1], and FIG. 25B is a timing chart illustrating an example of an operation for reading data from the memory string 200[1]. The timing chart illustrated in FIG. 25 shows changes in the magnitude of the potentials of the wiring WWL[1], the wiring WWL[2], the wiring WWL[n-1], the wiring WWL[n], the wiring RWL[1], the wiring RWL[2], the wiring RWL[n-1], the wiring RWL[n], the node N1[1], and the node N2[1]. The wiring WBL[1] indicates data supplied to the wiring WBL[1].

[0245] 25A shows an example in which data D[1] to data D[n] are written to memory cells 100[1,1] to 100[n,1], respectively. Note that data D[1] to data D[n] can be binary or multi-valued. Data D[1] to data D[n] are supplied from wiring WBL[1].

[0246] Data is written to the memory string 200[1] sequentially from memory cell 100[n,1] to memory cell 100[1,1]. If data is written to memory cell 100[1,1] and then data is written to memory cell 100[2,1], the data stored in memory cell 100[1,1] will be lost when the data is written to memory cell 100[2,1]. Therefore, it is necessary to first read the data written to memory cell 100[1,1] and save it elsewhere.

[0247] In the circuit configuration of the memory string 200, when data is written to the memory cell 100[k,1], in order to prevent the data stored in the memory cells 100[n,1] to 100[k+1,1] from being rewritten, a low-level potential is supplied to the wirings WWL[n] to WWL[k+1] to turn off the transistors WTr included in the memory cells 100[n,1] to 100[k+1,1]. This makes it possible to protect the data stored in the memory cells 100[n,1] to 100[k+1,1].

[0248] When writing data to the memory cell 100[k,1], the data is supplied from the wiring WBL[1], so a high-level potential is supplied to the wirings WWL[1] to WWL[k] to turn on the transistors WTr included in each of the memory cells 100[1,1] to 100[k,1]. This allows the data to be held in the storage node of the memory cell 100[k,1].

[0249] When writing data to the memory cells 100[1,1] to 100[n,1], the wiring RBL[1] can be independently controlled and does not need to be set to a specific potential. For example, the potential of the wiring RBL[1] may be set to a low-level potential. The potentials of the nodes N1[1] and N2[1] may be set to a low-level potential.

[0250] Based on the above, an example of a method for operating the semiconductor device 300 will be described.

[0251] <<Charge injection operation>> An example of a charge injection operation will be described using the timing chart of Fig. 24. First, an example of an operation in which charge is injected into the functional body 112 to increase the threshold voltage of the transistor WTr will be described. In this embodiment, an operation in which charge is injected into the functional body 112 of the transistor WTr in the memory cell 100[k,j] will be described.

[0252] In a period T1, a program potential (Prog) is supplied to the wiring WBL[j]. The program potential is higher than the high-level potential.

[0253] During period T2, a program potential is supplied to the wires WWL other than the wire WWL[k]. A low-level potential is supplied to the wire WWL[k]. Then, charges are injected from the wire WWL[k] to the function body 112 via the insulator 111.

[0254] In the period T3, a low-level potential is supplied to the wirings WWL and WBL. The wirings RWL[1] to RWL[n] may have any potential during the charge injection operation, but in this embodiment, a low-level potential is supplied to them.

[0255] In this way, charge can be injected into the functional body 112 from the wiring WWL side. The charge injection operation may be performed at the initial startup of the semiconductor device 300. The charge injection operation may be performed every time the semiconductor device 300 is started up, or may be performed at regular intervals. By injecting charge into the functional body 112 to increase the threshold voltage of the transistor WTr, the transistor WTr can be made into a normally-off transistor. For example, by making the transistor RTr a normally-on transistor, it is possible to form normally-off transistors and normally-on transistors separately within the memory cell 100.

[0256] <<Write operation>> An example of a write operation will be described with reference to the timing chart of Fig. 25A. In a period T10, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL[1], the node N1[1], and the node N2[1] are all low-level potentials.

[0257] In the period T11, a high-level potential is supplied to the wirings WWL[1] to WWL[n]. As a result, the transistors WTr included in each of the memory cells 100[1,1] to 100[n,1] are fully turned on. Then, data D[n] is supplied to the wiring WBL[1]. Because the transistors WTr included in each of the memory cells 100[1,1] to 100[n,1] are fully turned on, the data D[n] is supplied to the storage node of the memory cell 100[n,1].

[0258] During the period T12, a low-level potential is supplied to the wiring WWL[n], and a high-level potential is continuously supplied to the wirings WWL[n-1] to WWL[1]. As a result, the transistor WTr included in the memory cell 100[n,1] is turned off, and the transistors WTr included in each of the memory cells 100[n-1,1] to 100[1,1] are maintained in an on state. Data D[n-1] is supplied to the wiring WBL[1]. Because the transistors WTr included in each of the memory cells 100[n-1,1] to 100[1,1] are fully on, the data D[n-1] is supplied to the storage node of the memory cell 100[n-1,1]. Because the transistor WTr of the memory cell 100[n,1] is off, the data D[n] written to the memory cell 100[n,1] during the period T11 is retained.

[0259] In the period T13, similarly to the periods T11 and T12, data D[n-2] to data D[2] are sequentially written to the memory cells 100[n-2,1] to 100[2,1], respectively.

[0260] Specifically, the transistors WTr in the memory cells 100[n,1] to 100[k+1,1] to which data has already been written are turned off, and the transistors WTr in the memory cells 100[k,1] to 100[1,1] to which data has not yet been written are turned on. Data D[k] is then supplied from the wiring WBL and written to the memory node of the memory cell 100[k,1]. After writing of the data D[k] to the memory cell 100[k,1] is completed, the transistor WTr in the memory cell 100[k,1] is turned off. Next, data D[k-1] is supplied from the wiring WBL[1] and written to the memory node of the memory cell 100[k-1,1].

[0261] Note that the write operation when k is 1 will be described in the period T14. During the period T14, a low-level potential is supplied to the wirings WWL[n] to WWL[2], and a high-level potential is continuously supplied to the wiring WWL[1]. As a result, the transistors WTr included in the memory cells 100[n,1] to 100[2,1] are turned off, and the transistor WTr included in the memory cell 100[1,1] remains on. Then, data D[1] is supplied to the wiring WBL[1]. Because the transistor WTr included in the memory cell 100[1,1] is fully on, the data D[1] reaches the storage node of the memory cell 100[1,1] and is written therein. Furthermore, since the transistors WTr of the memory cells 100[n,1] to 100[2,1] are in the off state, the data D[n] to D[2] stored in the memory cells 100[n,1] to 100[2,1], respectively, are retained.

[0262] In this manner, data can be written to the memory cells 100[1,1] to 100[n,1].

[0263] In this embodiment, the write operation has been described with a focus on the memory string 200[1], but in the circuit configuration of the semiconductor device 300, when a high-level potential is supplied to the wiring WWL[k], all of the transistors WTr electrically connected to the wiring WWL[k] are turned on. Therefore, data is written not only to the memory string 200[1], but also to the memory strings 200[2] to 200[m] at the same time.

[0264] The memory cell 100 described in this embodiment is an OS memory. Therefore, the semiconductor device 300 including the memory cell 100 does not require an erase operation before rewriting data, and can achieve a high-speed write operation.

[0265] Furthermore, when writing (rewriting) data to a memory cell 100 close to the wiring WBL, the operation of writing data to a memory cell 100 farther from the wiring WBL can be omitted. For example, when writing (rewriting) data to the memory cell 100[1,1], the operation of writing data to the memory cells 100[2,1] to 100[n,1] can be omitted. When writing data to the memory cell 100[2,1], the operation of writing data to the memory cells 100[3,1] to 100[n,1] can be omitted.

[0266] By storing data that is frequently rewritten in the memory cells 100 close to the wiring WBL, the time required to write (rewrite) the data can be shortened, that is, the data writing (rewriting) speed can be increased.

[0267] By operating in this way, OS NAND type (including 3D OS NAND type) storage devices can be made to operate like RAM.

[0268] <<Read operation>> 25B shows an example in which data D[1] to data D[n] are read from the memory cells 100[1,1] to 100[n,1], respectively. Note that at this time, the transistors WTr are required to be in an off state in order to maintain the data held in each memory cell 100. Therefore, during the operation of reading data from the memory cells 100[1,1] to 100[n,1], the potentials of the wirings WWL[1] to WWL[n] are set to low-level potentials.

[0269] 23, when reading data from a specific memory cell 100, the transistor RTr of the memory cell 100 to be read is operated in a saturated region after the transistors RTr of the other memory cells 100 are fully turned on. In other words, the magnitude of the current flowing between the source and drain of the transistor RTr of the memory cell 100 to be read is determined depending on the voltage between the source and drain and the data stored in the memory cell 100 to be read.

[0270] For example, consider the case where data stored in the memory cell 100[k,1] is read. In the read operation, a high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] in order to turn on the transistors RTr included in the memory cells 100[1,1] to 100[n,1] excluding the memory cell 100[k,1].

[0271] On the other hand, since the transistor RTr in the memory cell 100[k,1] switches between an on state and an off state depending on the data stored in the memory cell 100[k,1], the potential of the wiring RWL[k] needs to be the same as when the data was written to the memory cell 100[k,1]. Note that the potential of the wiring RWL[k] during the write operation and the read operation is considered to be a low-level potential.

[0272] For example, a potential of +3 V is applied to the node N1[1], and a potential of 0 V is applied to the node N2[1]. Then, the node N2[1] is set to a floating state, and the potential of the node N2[1] is measured thereafter. When the potentials of the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] are set to a high-level potential, the transistors RTr included in each of the memory cells 100[1,1] to 100[n,1] excluding the memory cell 100[k,1] are fully turned on.

[0273] On the other hand, since the voltage between the source and drain of transistor RTr in memory cell 100[k,1] is determined by the potential of the gate of transistor RTr and the potential of node N1[1], the potential of node N2[1] is determined according to the data stored in the memory node of memory cell 100[k,1].

[0274] In this way, the data stored in the memory cell 100[k,1] can be read.

[0275] Based on the above, an example of a read operation will be described using the timing chart in Figure 25B. During the period T20, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1[1], and the node N2[1] are all low. In particular, the node N2[1] is in a floating state. Data D[1] to D[n] are stored in the storage nodes of the memory cells 100[1,1] to 100[n,1], respectively.

[0276] During the period T21, a low-level potential is supplied to the wiring RWL[1], and a high-level potential is supplied to the wirings RWL[2] to RWL[n]. As a result, the transistors RTr in the memory cells 100[2,1] to 100[n,1] are fully turned on. The on / off state of the transistor RTr in the memory cell 100[1,1] is determined according to the data D[1] stored in the storage node of the memory cell 100[1,1].

[0277] In addition, a potential VR is supplied to the wiring RBL[1]. As a result, the potential of the node N1[1] becomes VR, and the potential of the node N2[1] is determined according to the potential VR of the node N1[1] and the data stored in the memory node of the memory cell 100[1,1]. Here, the potential of the node N2[1] is VD[1]. Then, by measuring the potential VD[1] of the node N2[1], the data D[1] stored in the memory node of the memory cell 100[1,1] can be read.

[0278] In the period T22, a low-level potential is supplied to the wirings RWL[1] to RWL[n]. A low-level potential is supplied to the node N2[1], and then the node N2[1] is set to a floating state. That is, in the period T22, the potentials of the wirings RWL[1] to RWL[n] and the node N2[1] are the same as those in the period T20. The potential VR may continue to be supplied to the wiring RBL[1], or a low-level potential may be supplied. In this operation example, the potential VR is continuously supplied to the wiring RBL[1] after the period T21. Therefore, the potential VR is continuously supplied to the node N1[1].

[0279] During the period T23, a low-level potential is supplied to the wiring RWL[2], and a high-level potential is supplied to the wiring RWL[1] and the wirings RWL[3] to RWL[n]. This causes the transistors RTr in the memory cell 100[1,1] and the memory cells 100[3,1] to 100[n,1] to be fully turned on. The on / off state of the transistor RTr in the memory cell 100[2,1] is determined based on the data D[2] stored in the memory cell 100[2,1]. A potential VR is supplied to the wiring RBL[1]. The potential of the node N2[1] is determined based on the potential VR of the node N1[1] and the data stored in the memory cell 100[2,1]. Here, the potential of the node N2[1] is VD[2]. Then, by measuring the potential VD[2] of the node N2[1], the data D[2] stored in the storage node of the memory cell 100[2,1] can be read.

[0280] In the period T24, similar to the read operations in the periods T22 and T23, data D[3] to D[n-1] are sequentially read from the memory cells 100[3,1] to 100[n-1,1], respectively.

[0281] Specifically, when data D[k] is read from memory cell 100[k,1], the potential of node N2[1] is set to a low-level potential and node N2[1] is set to a floating state, and then a high-level potential is supplied to wirings RWL[1] to RWL[n] except for wiring RWL[k], thereby turning on the transistors RTr included in memory cells 100[1,1] to 100[n,1] except for memory cell 100[k,1], and turning on the transistor RTr included in memory cell 100[k,1] according to the data D[k]. Next, by setting the potential of node N1[1] to VR, the potential of node N2[1] becomes a potential according to the data D[k], and by measuring this potential, the data D[k] can be read. After the data D[k] stored in the memory cell 100[k,1] has been read, in preparation for the next read operation, a low-level potential is supplied to the wirings RWL[1] to RWL[n], a low-level potential is supplied to the node N2[1], and then the node N2[1] is set to a floating state.

[0282] During the period T25, a low-level potential is supplied to the wirings RWL[1] to RWL[n]. A low-level potential is supplied to the node N2[1], and then the node N2[1] is set to a floating state. That is, during the period T25, the potentials of the wirings RWL[1] to RWL[n] and the node N2[1] are the same as those during the period T20.

[0283] During the period T26, a low-level potential is supplied to the wiring RWL[n], and a high-level potential is supplied to the wirings RWL[1] to RWL[n-1]. This causes the transistors RTr in the memory cells 100[1,1] to 100[n-1,1] to be fully turned on. The transistor RTr in the memory cell 100[n,1] is turned on according to the data D[n] stored in the memory cell 100[n,1]. The potential VR is continuously supplied to the wiring RBL[1]. This causes the potential of the node N2[1] to depend on the potential VR of the node N1[1] and the data stored in the memory cell 100[n,1]. Here, the potential of the node N2[1] is VD[n]. By measuring the potential VD[n] of the node N2[1], the data D[n] stored in the memory cell 100[n,1] can be read.

[0284] In this manner, the data stored in the memory cells 100[1,1] to 100[n,1] can be read out.

[0285] In this embodiment, the read operation has been described focusing on memory string 200[1]. However, the circuit configuration of the semiconductor device 300 allows data to be read not only from memory string 200[1], but also from memory strings 200[2] to 200[m] simultaneously. Furthermore, by turning off the transistor WTr, data held in the storage nodes is not corrupted during a data read operation. Therefore, only the data contained in any memory string 200 can be read.

[0286] <Example of semiconductor device structure> Next, an example of the structure of the semiconductor device 300 will be described.

[0287] 26A to 26C are exemplary schematic diagrams showing a portion of semiconductor device 300. Fig. 26A shows a perspective view of the portion of the semiconductor device, and Fig. 26B shows a top view of the portion of the semiconductor device. Furthermore, Fig. 26C shows a cross-sectional view corresponding to the dashed dotted line Z1-Z2 in Fig. 26B.

[0288] The semiconductor device has a structure in which a wiring WL (wiring WWL or wiring RWL) and an insulator (a region not hatched in FIGS. 26A to 26C) are stacked.

[0289] An opening is formed in the structure so as to penetrate the insulator and the wiring WL together, and a structure 130 is formed in the opening to provide a memory cell 100 in a region AR penetrated by the wiring WL.

[0290] 26A, the structures 130 inside the structure are indicated by dashed lines. The region in which the structures 130 are formed is indicated as region SA. The memory strings 200 are formed along the structures 130, and therefore, are formed in region SA.

[0291] The region TM where the wiring WL is exposed functions as a connection terminal for applying a potential to the wiring WL. That is, by electrically connecting the wiring WL to the wiring in the region TM, a potential can be applied to the gate of the transistor included in the memory cell 100. The wiring WL corresponds to the conductor 103 or the conductor 102.

[0292] 26A to 26C. The semiconductor device 300 according to one aspect of the present invention may have a configuration in which an insulator is formed on the region TM, an opening is provided in the insulator, and a conductor PG is formed to fill the opening, as shown in FIGS.

[0293] Fig. 27A shows a perspective view of a portion of the semiconductor device, and Fig. 27B shows a top view of a portion of the semiconductor device. Furthermore, Fig. 27C shows a cross-sectional view corresponding to the dashed-dotted line Z1-Z2 in Fig. 27B. Note that wiring ER is formed on the conductor PG, thereby electrically connecting the wiring ER and wiring WL. In Fig. 27A, the conductor PG provided inside the structure is shown by a dashed line.

[0294] <Example of connection to peripheral circuits> The semiconductor device 300 according to one embodiment of the present invention may have peripheral circuits for a memory cell array, such as a read circuit and a precharge circuit, formed below it. In this case, Si transistors may be formed on a silicon substrate or the like to form the peripheral circuits, and then the semiconductor device 300 according to one embodiment of the present invention may be formed on the peripheral circuits. Fig. 28A is a cross-sectional view of a peripheral circuit formed of planar Si transistors, with the semiconductor device 300 according to one embodiment of the present invention formed above it. Fig. 29A is a cross-sectional view of a peripheral circuit formed of FIN Si transistors, with the semiconductor device 300 according to one embodiment of the present invention formed above it.

[0295] 28A and 29A, Si transistors constituting the peripheral circuit are formed on a substrate 1700. Element isolation layers 1701 are formed between multiple Si transistors. Conductors 1712 are formed as the sources and drains of the Si transistors. Conductors 1730 are formed to extend in the channel width direction and are connected to other Si transistors or the conductors 1712 (not shown).

[0296] The substrate described in the above embodiment can be used as the substrate 1700. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

[0297] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Alternatively, a semiconductor element may be formed using a substrate and then transferred to another substrate. Figures 28A and 29A show an example in which a single crystal silicon wafer is used as the substrate 1700.

[0298] 28A and 29A show a conductor 1221, a conductor 1222, a conductor 1223, and an insulator 1202 provided on the memory string 200 in the region SA. The conductor 1221 is electrically connected to the source or drain of the transistor RTr located at the end of the memory string 200.

[0299] The insulator 1202 is provided to cover the conductor 1221. The conductor 1222 is provided so as to be embedded in the insulator 1202 in a region overlapping with the conductor 119. The conductor 1223 is provided above the insulator 1202 and is electrically connected to the conductor 119 via the conductor 1222.

[0300] 28A and 29A, an insulator 1203 is formed to cover the conductor 1223, the insulator 1202, the memory string 200, and the like. It is preferable to use an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 1203. By using an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 1203, it is possible to suppress the diffusion of impurities from the outside (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.)) into the memory string 200.

[0301] Here, the Si transistor will be described in detail. The planar Si transistor shown in FIG. 28A is a cross-sectional view taken along the channel length direction, and the planar Si transistor shown in FIG. 28B is a cross-sectional view taken along the channel width direction. The Si transistor includes a channel formation region 1793 provided in a well 1792, a low-concentration impurity region 1794, and a high-concentration impurity region 1795 (collectively referred to as impurity regions), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surfaces of the gate electrode 1790. The conductive region 1796 may be made of a metal silicide or the like.

[0302] The fin-type Si transistor shown in FIG. 29A is a cross-sectional view taken along the channel length direction, and the fin-type Si transistor shown in FIG. 29B is a cross-sectional view taken along the channel width direction. The Si transistor shown in FIGS. 29A and 29B has a channel formation region 1793 that has a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along its side and upper surfaces. While this embodiment shows a case in which a convex portion is formed by processing a portion of a semiconductor substrate, a semiconductor layer having a convex shape may also be formed by processing an SOI substrate. The reference symbols shown in FIGS. 29A and 29B are the same as those shown in FIGS. 28A and 28B.

[0303] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0304] (Embodiment 3) In this embodiment, a semiconductor device 400 including a memory device or a semiconductor device according to one embodiment of the present invention will be described.

[0305] Fig. 30 is a block diagram showing a configuration example of a semiconductor device 400. The semiconductor device 400 shown in Fig. 30 has a drive circuit 410 and a memory array 420. The memory array 420 has one or more memory strings 200. Fig. 30 shows an example in which the memory array 420 has a plurality of memory strings 200 arranged in a matrix.

[0306] The drive circuit 410 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411 (row decoder), a control circuit 412, and a voltage generation circuit 428.

[0307] In the semiconductor device 400, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0308] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by control circuit 412.

[0309] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates a control signal for the peripheral circuit 411 so that this operation mode is executed.

[0310] The voltage generating circuit 428 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 428. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 428 generates a negative voltage.

[0311] The peripheral circuit 411 is a circuit for writing and reading data to and from the memory string 200. The peripheral circuit 411 includes a row decoder 441, a column decoder 442, a row driver 423, a column driver 424, an input circuit 425, an output circuit 426, and a sense amplifier 427.

[0312] The row decoder 441 and the column decoder 442 have the function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying a row to be accessed, and the column decoder 442 is a circuit for specifying a column to be accessed. The row driver 423 has the function of selecting the wiring WL specified by the row decoder 441. The column driver 424 has the function of writing data to the memory string 200, reading data from the memory string 200, and holding the read data.

[0313] The input circuit 425 has a function of holding a signal WDA. The data held by the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is data (Din) to be written to the memory string 200. The data (Dout) read from the memory string 200 by the column driver 424 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. In addition, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is a signal RDA.

[0314] The PSW241 has a function of controlling the supply of VDD to the peripheral circuit 415. The PSW242 has a function of controlling the supply of VHM to the row driver 423. In this example, the high power supply voltage of the semiconductor device 400 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW241 is controlled by a signal PON1, and the on / off of the PSW242 is controlled by a signal PON2. In FIG. 30, the number of power domains to which VDD is supplied in the peripheral circuit 415 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0315] The drive circuit 410 and memory array 420 of the semiconductor device 400 may be provided on the same plane. Alternatively, as shown in Fig. 31, the drive circuit 410 and memory array 420 may be provided overlapping each other. By providing the drive circuit 410 and memory array 420 overlapping each other, the signal propagation distance can be shortened. Fig. 31 also includes an enlarged perspective view of a portion of the semiconductor device 400.

[0316] Furthermore, the semiconductor device 400 may use an arithmetic processing device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) as the control circuit 412 of the drive circuit 410. By using a CPU and / or a GPU, the semiconductor device 400 can be realized with an arithmetic processing function.

[0317] As described above, the memory string 200 can function as a RAM. Therefore, a part of the memory array 420 can function as a main memory or a cache memory. Also, as described above, the memory string 200 can function as a flash memory. Therefore, a part of the memory array 420 can function as a flash memory. The semiconductor device 400 according to one aspect of the present invention can function as a universal memory.

[0318] Furthermore, according to one aspect of the present invention, the functions of a CPU, a NAND flash memory, and a cache memory can be fabricated on the same chip.

[0319] 31 includes a driver circuit 410 including a CPU and a 3D OS NAND storage device according to one embodiment of the present invention in a memory array 420. The 3D OS NAND storage device according to one embodiment of the present invention functions as a cache memory and a flash memory.

[0320] 32 shows how a host 450 manages a plurality of semiconductor devices 400. Each semiconductor device 400 has an arithmetic processing function and can perform parallel writing and reading to a flash memory and a cache memory. By having the host 450 manage a plurality of semiconductor devices 400, an information processing system that realizes non-von Neumann computing can be constructed.

[0321] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0322] (Fourth embodiment) In this embodiment mode, an example of a processing unit that can include a semiconductor device such as the memory device described in the above embodiment mode will be described.

[0323] 33 is a block diagram of the central processing unit 1100. In FIG. 33, an example of the configuration of a CPU is shown as an example of the configuration that can be used for the central processing unit 1100.

[0324] The central processing unit 1100 shown in FIG. 33 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189 on a substrate 1190. The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may also be provided on separate chips.

[0325] The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding that data.

[0326] The central processing unit 1100 shown in Figure 33 is merely one example of a simplified configuration, and actual central processing units 1100 have a wide variety of configurations depending on their applications. For example, the central processing unit 1100 shown in Figure 33 or a configuration including an arithmetic circuit may be used as one core, and a configuration may include multiple such cores, each operating in parallel, i.e., a GPU-like configuration. Furthermore, the number of bits that the central processing unit 1100 can handle in its internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0327] An instruction input to the central processing unit 1100 via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

[0328] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Furthermore, the interrupt controller 1194 processes interrupt requests from external input / output devices and peripheral circuits based on their priority and mask status while the central processing unit 1100 is executing a program. The register controller 1197 generates addresses for the register 1196 and reads and writes data from and to the register 1196 depending on the state of the central processing unit 1100.

[0329] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0330] 33, a memory device is provided in the register 1196 and the cache 1199. As the memory device, for example, the memory devices described in the above embodiments can be used.

[0331] In the central processing unit 1100 shown in FIG. 33, the register controller 1197 selects the holding operation of the register 1196 in accordance with an instruction from the ALU 1191. That is, it selects whether the memory cells in the register 1196 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 1196. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 1196 can be stopped.

[0332] The semiconductor device 400 and the central processing unit 1100 shown in the above embodiment can be provided overlapping each other. Figs. 34A and 34B show perspective views of a semiconductor device 1150A. The semiconductor device 1150A has a semiconductor device 400 that functions as a memory device on the central processing unit 1100. The central processing unit 1100 and the semiconductor device 400 have overlapping regions. To make the configuration of the semiconductor device 1150A easier to understand, the central processing unit 1100 and the semiconductor device 400 are shown separately in Fig. 34B.

[0333] By stacking the semiconductor device 400 and the central processing unit 1100, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0334] As described in the above embodiment, by using an OS NAND type memory device for the semiconductor device 400, some or all of the memory strings 200 included in the semiconductor device 400 can function as RAM. Therefore, the semiconductor device 400 can function as a main memory. The semiconductor device 400 functioning as the main memory is connected to a cache 1199 via a cache interface 1189.

[0335] Whether the semiconductor device 400 functions as a main memory (RAM) or as storage is controlled by a control circuit 412 shown in Fig. 30. The control circuit 412 can cause some or all of the multiple memory strings 200 included in the semiconductor device 400 to function as RAM based on a signal supplied from the central processing unit 1100.

[0336] The semiconductor device 400 can cause some of the multiple memory strings 200 to function as RAM and the other memory strings 200 to function as storage. By using an OS NAND type storage device for the semiconductor device 400, it can function as a cache, a main memory, and a storage. The semiconductor device 400 according to one aspect of the present invention can function as, for example, a universal memory.

[0337] Furthermore, when the semiconductor device 400 is used as a main memory, its storage capacity can be increased or decreased as needed. When the semiconductor device 400 is used as a cache, its storage capacity can be increased or decreased as needed.

[0338] 30 may have a function of performing error detection and correction (also referred to as ECC: Error Check and Correct) when data is moved or copied between an area functioning as a storage and an area functioning as a main memory of the semiconductor device 400. The control circuit 412 may also have a function of performing ECC when data is moved or copied between an area functioning as a main memory of the semiconductor device 400 and the cache 1199.

[0339] Furthermore, multiple semiconductor devices 400 may be provided overlapping the central processing unit 1100. Perspective views of a semiconductor device 1150B are shown in FIGS. 35A and 35B. The semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the central processing unit 1100. The central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. To make the configuration of the semiconductor device 1150B easier to understand, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately in FIG. 35B.

[0340] The semiconductor device 400a and the semiconductor device 400b function as memory devices. For example, a NOR type memory device may be used as the semiconductor device 400a. Also, a NAND type memory device may be used as the semiconductor device 400b. Both the semiconductor device 400a and the semiconductor device 400b may be NAND type memory devices. Since a NOR type memory device can operate faster than a NAND type memory device, for example, a part of the semiconductor device 400a may be used as a main memory and / or a cache 1199. Note that the stacking order of the semiconductor device 400a and the semiconductor device 400b may be reversed.

[0341] 36A and 36B show perspective views of semiconductor device 1150C. Semiconductor device 1150C has a configuration in which central processing unit 1100 is sandwiched between semiconductor device 400a and semiconductor device 400b. Therefore, central processing unit 1100, semiconductor device 400a, and semiconductor device 400b have overlapping regions. To make the configuration of semiconductor device 1150C easier to understand, central processing unit 1100, semiconductor device 400a, and semiconductor device 400b are shown separately in FIG. 36B.

[0342] The configuration of the semiconductor device 1150C can increase the communication speed between the semiconductor device 400a and the central processing unit 1100, and the communication speed between the semiconductor device 400b and the central processing unit 1100. In addition, the power consumption can be reduced compared to the semiconductor device 1150B.

[0343] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0344] (Embodiment 5) In this embodiment mode, an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed and an electronic component in which the semiconductor device is incorporated will be described.

[0345] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 37A.

[0346] 37A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of wafer 4801. On the upper surface of wafer 4801, a portion where circuit portions 4802 are not present is spacing 4803, which is a region for dicing.

[0347] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0348] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0349] By performing a dicing process, chips 4800a as shown in FIG. 37B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0350] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 37A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0351] <Electronic components> 37C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 37C includes a chip 4800a in a mold 4711. A memory device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0352] 37C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0353] 37D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0354] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, or a high bandwidth memory (HBM). The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0355] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0356] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0357] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0358] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0359] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0360] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0361] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. FIG. 37D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0362] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0363] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0364] (Embodiment 6) In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0365] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 38A shows various memory devices used in semiconductor devices by layer. The higher the layer, the faster the operating speed required for the memory device, while the lower the layer, the larger the memory capacity and recording density required for the memory device. Figure 38A shows, from the top layer, memories embedded as registers in arithmetic processing units such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0366] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0367] SRAM is used, for example, in caches. Caches have the function of duplicating and storing a portion of the data stored in main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased. The storage capacity required for caches is smaller than that of main memory, but they are required to operate at a faster speed than main memory. In addition, data rewritten in the cache is duplicated and supplied to main memory.

[0368] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 Gbit / mm 2 ~0.3Gbit / mm 2 is.

[0369] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that needs to be stored for a long period of time, as well as various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 Gbit / mm 2 ~6.0Gbit / mm 2 is.

[0370] A storage device according to one embodiment of the present invention has a high operating speed and is capable of long-term data retention. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0371] Furthermore, a storage device according to an embodiment of the present invention can be suitably used in both the tier where the main memory is located and the tier where the storage is located. Also, a storage device according to an embodiment of the present invention can be suitably used in the tier where the cache is located. Figure 38B shows various tiers of storage devices different from those shown in Figure 38A.

[0372] 38B shows, from the top layer, a memory integrated as a register in a processing unit such as a CPU, an SRAM used as a cache, and a 3D OS NAND memory. A storage device according to one embodiment of the present invention can be used for the cache, main memory, and storage. Note that when a high-speed memory of 1 GHz or higher is required as a cache, the cache is integrated into a processing unit such as a CPU.

[0373] A storage device according to one embodiment of the present invention can be applied to, for example, storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0374] 39A to 39J and 40A to 40E illustrate examples of electronic devices including a memory device according to one embodiment of the present invention, each of which includes an electronic component 4700 or an electronic component 4730 including the memory device.

[0375] [mobile phone] 39A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0376] By applying a storage device according to one embodiment of the present invention, the information terminal 5500 can store temporary files (such as caches when using a web browser) generated when an application is executed.

[0377] [Wearable devices] 39B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0378] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0379] [Information terminal] 39C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0380] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0381] 39A to 39C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0382] [electric appliances] 39D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0383] A storage device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the storage device.

[0384] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0385] [Game consoles] 39E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0386] FIG. 39F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 39F, the controller 7522 can include a display unit that displays game images, and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 39F, and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0387] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0388] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0389] Furthermore, by applying the storage device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files necessary for calculations that occur during game execution can be stored.

[0390] As an example of a game machine, a portable game machine is shown in FIG. 39E. Also, a home-use stationary game machine is shown in FIG. 39F. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0391] [Moving object] The storage device described in the above embodiment can be applied to a vehicle, which is a moving object, and to the vicinity of the driver's seat of the vehicle.

[0392] FIG. 39G illustrates an automobile 5700 as an example of a moving object.

[0393] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0394] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0395] The storage device described in the above embodiment can temporarily store information, and therefore, for example, the storage device can be used to store necessary temporary information in an automatic driving system for the automobile 5700, a system that provides road guidance, hazard prediction, or the like. The display device may be configured to display temporary information such as road guidance and hazard prediction. The display device may also be configured to store video images from a driving recorder installed in the automobile 5700.

[0396] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0397] [camera] The storage device described in the above embodiment can be applied to a camera.

[0398] 39H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, here, the digital camera 6240 is configured so that the lens 6246 can be detached from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured so that a strobe device, a viewfinder, etc. can be separately attached.

[0399] A low-power digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0400] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0401] 39I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0402] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the storage device described above, the video camera 6300 can store temporary files generated during encoding.

[0403] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0404] 39J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least battery 5401, electronic components 4700, a regulator, a control circuit, antenna 5404, wire 5402 to the right atrium, and wire 5403 to the right ventricle.

[0405] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0406] The ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (such as in the case of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0407] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, and so on.

[0408] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0409] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0410] [PC expansion device] The storage devices described in the above embodiments can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0411] Figure 40A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Figure 40A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0412] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the storage devices and the like described in the above embodiments. For example, the board 6104 is equipped with an electronic component 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0413] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0414] FIG. 40B is a schematic diagram of the external appearance of an SD card, and FIG. 40C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, and the like provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0415] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0416] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0417] FIG. 40D is a schematic diagram of the external appearance of an SSD, and FIG. 40E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the circuit board 5153 is equipped with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0418] [Calculator] 41A is an example of a large-scale computer. The computer 5600 has a rack 5610 storing a plurality of rack-mounted computers 5620.

[0419] Computer 5620 can have the configuration shown in the perspective view in Fig. 41B, for example. In Fig. 41B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0420] PC card 5621 shown in FIG. 41C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 41C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0421] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0422] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0423] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0424] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0425] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device. The electronic component 4700 can be used as the semiconductor device 5628.

[0426] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0427] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0428] Next, a configuration example of a computer system applicable to the calculator 5600 will be described. Fig. 42 is a diagram illustrating a configuration example of a computer system 700. The computer system 700 is configured to include software and hardware. Note that the hardware included in a computer system may be referred to as an information processing device.

[0429] The software that makes up the computer system 700 includes an operating system including device drivers, middleware, various development environments, AI-related application programs (AI applications), and application programs unrelated to AI.

[0430] The device driver includes an application program for controlling an auxiliary storage device, a display device, a printer, and other externally connected devices.

[0431] The hardware that constitutes the computer system 700 includes a first processor, a second processor, a first storage device, etc. The second processor also includes a second storage device.

[0432] The first processing unit may be, for example, a central processing unit such as a Noff OS CPU. The Noff OS CPU has a storage means (e.g., nonvolatile memory) using OS transistors, and has a function of storing necessary information in the storage means and stopping the power supply to the central processing unit when operation is not required. Using a Noff OS CPU as the first processing unit can reduce the power consumption of the computer system 700.

[0433] The second arithmetic processing device can be, for example, a GPU or an FPGA. It is preferable to use an AI OS Accelerator as the second arithmetic processing device. The AI ​​OS Accelerator is configured using OS transistors and has arithmetic means such as a product-sum operation circuit. The AI ​​OS Accelerator consumes less power than a general GPU. Using the AI ​​OS Accelerator as the second arithmetic processing device can reduce the power consumption of the computer system 700.

[0434] It is preferable to use a storage device according to an embodiment of the present invention as the first storage device and the second storage device. For example, it is preferable to use a 3D OS NAND type storage device. The 3D OS NAND type storage device can function as a cache, a main memory, and a storage. Furthermore, using a 3D OS NAND type storage device makes it easier to realize a non-von Neumann type computer system.

[0435] A 3D OS NAND type storage device consumes less power than a 3D NAND type storage device that uses Si transistors. Using a 3D OS NAND type storage device as a storage device can reduce the power consumption of the computer system 700. In addition, because a 3D OS NAND type storage device can function as a universal memory, the number of parts required to configure the computer system 700 can be reduced.

[0436] By configuring the semiconductor device constituting the hardware with a semiconductor device including an OS transistor, it becomes easy to monolithically integrate the hardware including the central processing unit, the processing unit, and the storage device. Monolithic integration of the hardware not only makes it possible to reduce the size, weight, and thickness of the hardware, but also facilitates further reduction in power consumption.

[0437] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0438] (Embodiment 7) A normally-off CPU (also referred to as an "Noff-CPU") can be realized by using the OS memory described in this specification. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an "off state") even when the gate voltage is 0 V.

[0439] The Noff-CPU can stop the power supply to circuits within the Noff-CPU that are not in operation, putting those circuits into a standby state. When the power supply is stopped and the circuit is in a standby state, no power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, it is possible to quickly return from the standby state. In this way, the Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0440] The Noff-CPU can be suitably used in small-scale systems such as IoT terminal devices (also called "endpoint microcomputers") 803 in the field of IoT (Internet of Things).

[0441] Figure 43 shows the hierarchical structure of an IoT network and trends in required specifications. In Figure 43, power consumption 804 and processing performance 805 are shown as required specifications. The hierarchical structure of an IoT network is broadly divided into an upper-level cloud field 801 and a lower-level embedded field 802. The cloud field 801 includes, for example, servers. The embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, and home appliances.

[0442] The higher the layer, the more important it is for high processing performance rather than low power consumption. Therefore, in the cloud field 801, high-performance CPUs, high-performance GPUs, large-scale SoCs (System on a Chip), and the like are used. Furthermore, the lower the layer, the more important it is for low power consumption rather than high processing performance, and the number of devices increases explosively. A semiconductor device according to one embodiment of the present invention can be suitably used for a communication device of an IoT terminal device that requires low power consumption.

[0443] The term "endpoint" refers to the terminal area of ​​the embedded field 802. Devices used as endpoints include, for example, microcomputers used in factories, home appliances, infrastructure, agriculture, and the like.

[0444] FIG. 44 illustrates an image of factory automation as an application example of an endpoint microcontroller. A factory 884 is connected to a cloud (server) 883 via an Internet line. The cloud 883 is connected to a home 881 and an office 882 via the Internet line. The Internet line may be a wired communication system or a wireless communication system. For example, in the case of a wireless communication system, a semiconductor device according to one embodiment of the present invention may be used in a communication device to perform wireless communication in accordance with a communication standard such as a fourth-generation mobile communication system (4G) or a fifth-generation mobile communication system (5G). The factory 884 may be connected to factories 885 and 886 via the Internet line.

[0445] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to a cloud 883 and transmitting and receiving information. The master device 831 is also connected to a plurality of industrial robots 842 included in an IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet ("Ethernet" is a registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0446] A factory manager can connect to a factory 884 via a cloud 883 from a home 881 or office 882 to know the operating status, etc. He can also check for incorrect or missing items, give instructions on where to put them, measure takt time, etc.

[0447] In recent years, the introduction of IoT into factories has been progressing worldwide, labeling them as "smart factories." In smart factory cases, there have been reported cases where endpoint microcomputers are used not only for simple inspection and auditing, but also for fault detection and anomaly prediction.

[0448] In small-scale systems such as endpoint microcontrollers, the overall system power consumption during operation is often low, so the CPU tends to account for a large proportion of power consumption. For this reason, the power reduction effect of Noff-CPUs during standby operation is significant in small-scale systems such as endpoint microcontrollers. On the other hand, in the embedded field of IoT, quick response is sometimes required, and the use of Noff-CPUs makes it possible to achieve fast recovery from standby operation.

[0449] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes. [Example]

[0450] The rewrite endurance of a NAND memory string using an OS memory according to one embodiment of the present invention was evaluated using device simulation software. In this example, the evaluation results are described. The rewrite endurance was evaluated using device simulation software TCAD Sentaurus manufactured by Synopsys.

[0451] FIG. 45A shows a perspective conceptual diagram of a semiconductor device including a plurality of NAND memory strings using OS memory (also referred to as "3D OS NAND strings"). The semiconductor device shown in FIG. 45A is the 3D OS NAND memory device described in the above embodiment. FIG. 45A shows the NAND memory strings, control gates CG, writing gates WG, etc.

[0452] The structure of the memory cells (OS memories) constituting the memory string is assumed to be the structure of memory cell 100A (see FIG. 12A) described in the above embodiment. FIG. 45B shows an equivalent circuit diagram of the memory cell. The memory cell shown in FIG. 45B is a 2T-1C type memory cell having two transistors (transistor WTr and transistor RTr) and one capacitance element Cs. Note that FIG. 45B is equivalent to the circuit diagram shown in FIG. 5A described in the above embodiment.

[0453] 45B are OS transistors. In addition, the transistor WTr is a transistor having a floating gate (FG). In this example, the FG is assumed to be polycrystalline silicon containing boron.

[0454] The gate of the transistor WTr is electrically connected to the write gate WG, and one of the source or drain is electrically connected to the write bit line WBL. The other of the source or drain of the transistor WTr is electrically connected to one electrode of the capacitance element Cs and the gate of the transistor RTr. The node electrically connecting the other of the source or drain of the transistor WTr, one electrode of the capacitance element Cs, and the gate of the transistor RTr functions as a retention node SN. The retention node SN is also electrically connected to a wiring BWBL. The other electrode of the capacitance element Cs is electrically connected to the control gate CG. One of the source or drain of the transistor RTr is electrically connected to the read bit line RBL and the back gate of the transistor WTr. The back gate of the transistor RTr is electrically connected to a back gate line BG. The other of the source or drain of the transistor RTr is electrically connected to a wiring BRBL.

[0455] Figure 46 shows a timing chart for write and read operations of a 3D OS NAND string. Figure 46 shows a case where four memory cells are connected as a 3D OS NAND string. During a write operation, the potential of the read bit line RBL is written to all cells located on the drain terminal (read bit line RBL) side of the memory cell to be written to. Therefore, the write operation must be performed in order, starting with the cell farthest from the read bit line RBL. The read operation can follow the read operation of NAND flash memory.

[0456] Table 2 shows the setting parameters of the oxide semiconductor used in the simulation.

[0457] [Table 2]

[0458] Table 3 shows the power supply voltages used in the simulations of write and read operations.

[0459] [Table 3]

[0460] To adjust the threshold voltage of the transistor WTr, charge is injected into the FG only once at 15 V, but the power supply voltage used for other operations is 4 V. In other words, a high power supply voltage like that used in NAND flash memory is not used during write operations.

[0461] Figure 47A shows the Id-Vwg characteristics of transistor WTr. Figure 47A shows the Id-Vwg characteristics for each voltage (Vpre: pre-charge voltage) when injecting charge into the FG of transistor WTr. Figure 47B shows the relationship between the threshold voltage (Vth) of transistor WTr and Vpre. It can be seen that as Vpre increases, Vth shifts to the positive side.

[0462] Retention characteristics are important in memory devices. The retention characteristics of 3D OS NAND memory devices are determined by the Vth of the transistor WTr and the magnitude of the current (off-current) that flows between the source and drain when a voltage lower than Vth is applied to the gate. OS transistors have extremely low off-current, making them suitable for use as WTr transistors.

[0463] The simulation for this example was performed assuming a 3D OS NAND memory string in which eight memory cells are connected in series. Figure 48 shows the retention characteristics of the 3D OS NAND memory string. Figure 48 shows the retention characteristics of six memory cells, excluding the two in the center, out of the eight memory cells connected in series. Figure 48A shows the retention characteristics when Vpre = 12.5V, and Figure 48B shows the retention characteristics when Vpre = 15V. Two types of data patterns were used for evaluating the retention characteristics: a checkered pattern (writing "1" to odd-numbered memory cells and "0" to even-numbered memory cells) and an inverted checkered pattern (writing "0" to odd-numbered memory cells and "1" to even-numbered memory cells).

[0464] 48A and 48B, the horizontal axis represents the elapsed time (Time), and the vertical axis represents the voltage Vsn of the retention node SN. As can be seen from FIGS. 48A and 48B, the device structure used in the simulation had a retention time of 10 years (3.2×10 8 In order to achieve the retention of voltage s), it is necessary to set Vpre to 15 V and Vth of the transistor WTr to about 2 V. In the following, in this example, a simulation result when Vpre is set to 15 V will be described.

[0465] Figures 49A and 49B show the simulation results of the memory cell retention characteristics when a checkered pattern and an inverted checkered pattern are written alternately to a memory string. Here, "writing a checkered pattern and an inverted checkered pattern alternately to a memory string" means repeatedly writing a "1" to one memory cell and then writing a "0" to the same memory cell after a certain period of time has passed. At this time, different data is always written to adjacent memory cells.

[0466] It is expected that the farther a memory cell is from the write bit line WBL, the longer it will take to write data to that memory cell. Therefore, by examining the retention characteristics of memory cells close to the wiring BWBL, the worst case of the retention characteristics can be predicted.

[0467] In Figures 49A and 49B, the horizontal axis represents elapsed time (Time), and the vertical axis represents the voltage Vsn of the retention node SN. Figure 49A shows the retention characteristics of the retention node SN (retention node SN[1]) of the memory cell closest to the wiring BWBL. Figure 49B shows the retention characteristics of the retention node SN (retention node SN[2]) of the memory cell second closest to the wiring BWBL.

[0468] 49A and 49B show the change in the voltage Vsn of node SN when a "0" is written 10 μs after a "1" is written, and the change in the voltage Vsn of node SN when a "1" is written 10 μs after a "0" is written. It can be seen that the potential difference between "1" and "0" is smaller at retention node SN[1] than at retention node SN[2].

[0469] 50 shows the simulation results of the read current Irbl (the magnitude of the current flowing through the read bit line RBL during a read operation) when the retention nodes SN[1] to SN[8] retain "0" and the read current Irbl when they retain "1." Note that the retention node SN[8] is the retention node SN included in the memory cell closest to the write bit line WBL in this embodiment.

[0470] 50, it can be seen that almost the same read current Irbl is obtained in each memory cell including the retention nodes SN[2] to SN[8]. On the other hand, in the memory cell including the retention node SN[1], although there is a difference in the read current Irbl between "1" and "0", it can be seen that the value of the read current Irbl is significantly different from that of the other memory cells. Therefore, it is preferable not to use the memory cell closest to the wiring BWBL for actual operation and to treat it as a dummy cell.

[0471] Table 4 shows a comparison table of common DRAM and NAND flash memory with 3D OS NAND type storage devices.

[0472] [Table 4]

[0473] Simulation results show that 3D OS NAND memory devices can be expected to reduce power supply voltage while maintaining 10-year retention. Furthermore, because 3D OS NAND memory devices store data in retention nodes via transistors, their rewrite endurance is expected to be comparable to that of DRAM. In this way, 3D OS NAND memory devices combine the advantages of both NAND flash memory and DRAM. Therefore, 3D OS NAND memory devices can be used as universal memory. [Explanation of symbols]

[0474] 100: memory cell, 101: insulator, 102: conductor, 103: conductor, 108: central axis, 111: insulator, 112: functional body, 113: insulator, 114: semiconductor, 115: conductor, 116: insulator, 117: semiconductor, 118: insulator, 119: conductor, 120: cavity, 121: insulator, 130: structure, 131: opening, 132: region, 140: stack, 200: memory string

Claims

[Claim 1] a structure extending in a first direction; a first conductor extending in a second direction; a second conductor extending in the second direction, The structure is a third conductor extending in the first direction; a first insulator adjacent to the third conductor; a first semiconductor adjacent to the first insulator; a second insulator adjacent to the first semiconductor; and At a first intersection where the structure and the first conductor intersect, The structure is a second semiconductor adjacent to the second insulator; a third insulator adjacent to the second semiconductor; a functional body adjacent to the third insulator; a fourth insulator adjacent to the functional body; and At a second intersection where the structure and the second conductor intersect, The structure is a fourth conductor adjacent to the second insulator; the second semiconductor adjacent to the fourth conductor; the third insulator adjacent to the second semiconductor; and At the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor, the third insulator, the functional body, and the fourth insulator are concentrically provided outside the third conductor when viewed from the first direction, At the second intersection, The semiconductor device in which the first insulator, the first semiconductor, the second insulator, the fourth conductor, the second semiconductor, and the third insulator are concentrically arranged outside the third conductor when viewed from the first direction.

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