Manufacturing method of semiconductor device

Abstract

To propose a technique for suppressing disconnection of a metal layer formed by a sputtering method.SOLUTION: A manufacturing method of a semiconductor device includes: a step of preparing a semiconductor wafer including a semiconductor substrate having a plurality of trenches provided on an upper surface thereof, a gate insulating film provided in each trench, a gate electrode, and an interlayer insulating film covering the upper surface of the gate electrode, in which an inter-trench portion located between the plurality of trenches of the semiconductor wafer protrudes upward from an upper surface of the interlayer insulating film; and a step of forming a metal layer covering a range spanning a surface of an inter-trench portion and a surface of the interlayer insulating film by a sputtering method in which a component in a longitudinal direction of a trench is larger than a component in a width direction of the trench in an emission angle distribution of sputtered particles. In this semiconductor manufacturing method, the metal layer appropriately grows in a portion of the step between the inter-trench portion and the interlayer insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method for depositing a metal layer on a substrate by sputtering. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special table 2017-520683 publication Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing process of trench-gate semiconductor devices, a metal layer that covers the interlayer insulating film provided in the trench and the surface of the semiconductor wafer may be formed by sputtering. If the surface of the semiconductor wafer (i.e., the portion between the trenches) protrudes above the upper surface of the interlayer insulating film, the metal layer may not grow properly at the stepped portion. This specification proposes a technology to suppress step discontinuities in the metal layer formed by the sputtering method. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to aspect 1 disclosed in the present specification includes the steps of: preparing a semiconductor wafer including a semiconductor substrate having a plurality of trenches formed on an upper surface thereof; a gate insulating film formed in each of the trenches; a gate electrode formed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; and an interlayer insulating film formed in each of the trenches and covering an upper surface of the gate electrode, wherein inter-trench portions of the semiconductor wafer located between the plurality of trenches protrude above an upper surface of the interlayer insulating film; and forming a metal layer that covers an area spanning the surface of the inter-trench portions and a surface of the interlayer insulating film by a sputtering method in which the emission angle distribution of sputtered particles has a greater component in the longitudinal direction of the trench than in the width direction of the trench.

[0006] In the semiconductor manufacturing method, the step of forming the metal layer is performed by a sputtering method in which the component in the longitudinal direction of the trench is greater than the component in the width direction of the trench in the emission angle distribution of sputtered particles, so that the metal layer grows appropriately in the step portion between the trenches and the interlayer insulating film. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram of a semiconductor device. [Figure 2] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] 1 is a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] FIG. 2 is a plan view of a collimator. [Figure 15] FIG. 2 is a plan view of a collimator.

[0008] The semiconductor device 100 shown in FIG. 1 is a MOSFET (metal-oxide-semiconductor field-effect transistor). The semiconductor device 100 has a semiconductor substrate 12. The semiconductor substrate 12 is a SiC substrate. A plurality of trenches 14 are provided in an upper surface 12a of the semiconductor substrate 12. A gate insulating film 16, a gate electrode 18, and an interlayer insulating film 20 are provided in each trench 14. The gate insulating film 16 covers the inner surface of the trench 14. The gate electrode 18 is provided inside the gate insulating film 16. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The interlayer insulating film 20 covers the upper surface of the gate electrode 18.

[0009] The semiconductor substrate 12 is provided with an n-type source layer 42, a p-type body layer 44, an n-type drift layer 46, and an n-type drain layer 48. The source layer 42 is disposed in an area including the upper surface 12a of the semiconductor substrate 12. The source layer 42 is in contact with the gate insulating film 16 on the side surface of the trench 14. The source layer 42 is an n-type layer with a high concentration of n-type impurities.

[0010] The body layer 44 is in contact with the lower surface of the source layer 42. The body layer 44 is also in contact with the gate insulating film 16 on the side surface of the trench 14 below the source layer 42.

[0011] The drift layer 46 is in contact with the lower surface of the body layer 44. The drift layer 46 is in contact with the gate insulating film 16 on the side surface of the trench 14 below the body layer 44 and on the bottom surface of the trench 14. The n-type impurity concentration of the drift layer 46 is lower than the n-type impurity concentration of the source layer 42.

[0012] The drain layer 48 is in contact with the lower surface of the drift layer 46. The drain layer 48 is disposed in a range that includes the lower surface of the semiconductor substrate 12. The n-type impurity concentration of the drain layer 48 is higher than the n-type impurity concentration of the drift layer 46.

[0013] The semiconductor device 100 has a source electrode 25. The source electrode 25 covers the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating film 20. The source electrode 25 is in ohmic contact with the source layer 42. The source electrode 25 is also in ohmic contact with the body layer 44 at a position not shown. The source electrode 25 has a silicide layer 22, a barrier metal layer 23, and a surface electrode layer 24.

[0014] The silicide layer 22 is made of silicide (e.g., nickel silicide). The silicide layer 22 covers the upper surface 12a of the semiconductor substrate 12, which is a portion between the plurality of trenches 14. The upper surface 12a of the semiconductor substrate 12 is located higher than the upper surface of the interlayer insulating film 20. The upper surface 12a of the semiconductor substrate 12 is slightly curved upwardly between adjacent trenches 14. Therefore, the silicide layer 22 is curved upwardly along the upper surface 12a. The silicide layer 22 is in ohmic contact with the source layer 42.

[0015] The barrier metal layer 23 is made of Ti, TiN, a titanium alloy, or the like. The barrier metal layer 23 is disposed on the semiconductor substrate 12 and is distributed over an area spanning the plurality of trenches 14. The barrier metal layer 23 contacts the upper surface of the silicide layer 22 in the area between the plurality of trenches 14, and also contacts the upper surface of the interlayer insulating film 20 within the trenches 14.

[0016] The surface electrode layer 24 is made of a metal such as aluminum. The surface electrode layer 24 is disposed on the barrier metal layer 23 and is distributed over an area spanning the plurality of trenches 14. The surface electrode layer 24 covers the upper surface of the barrier metal layer 23. The surface electrode layer 24 is separated from the silicide layer 22 by the barrier metal layer 23. The barrier metal layer 23 suppresses mutual diffusion of elements between the surface electrode layer 24 and the semiconductor substrate 12.

[0017] The semiconductor device 100 has a drain electrode 52. The drain electrode 52 is in contact with the lower surface of the semiconductor substrate 12. The drain electrode 52 is in ohmic contact with the drain layer 48.

[0018] Example 1 Next, a manufacturing method of the semiconductor device 100 of Example 1 will be described. Fig. 2 shows the semiconductor substrate 12 before electrodes are formed. The semiconductor substrate 12 shown in Fig. 2 has the above-mentioned source layer 42, body layer 44, drift layer 46, and drain layer 48. Note that, hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, and a direction parallel to the upper surface 12a of the semiconductor substrate 12 and perpendicular to the x direction is referred to as the y direction.

[0019] First, as shown in FIG. 3, the upper surface 12a of the semiconductor substrate 12 is selectively etched to form multiple trenches 14 in the upper surface 12a. Here, the trenches 14 are formed linearly in the y direction in the upper surface 12a. The trenches 14 are formed at intervals in the x direction. The trenches 14 are formed so as to extend from the upper surface 12a through the body layer 44 and reach the drift layer 46. Furthermore, because the pitch of the trenches 14 is narrow, the upper surface 12a has an upwardly convex curved shape between the trenches 14. Next, a gate insulating film 16 is formed on the upper surface 12a and the inner surfaces of the trenches 14 by thermal oxidation or CVD. After the gate insulating film 16 is formed, a gate electrode 18 is formed in the trench 14. Here, the gate electrode 18 is formed so that the upper surface of the gate electrode 18 is located lower than the upper surface 12a of the semiconductor substrate 12 (i.e., the portion located between the trenches 14).

[0020] Next, as shown in FIG. 4, an insulating film 26 is grown over the surface of the gate insulating film 16 and the upper surface of the gate electrode 18 by, for example, CVD.

[0021] Next, as shown in FIG. 5, the insulating film 26 is etched back. At this time, the upper surface 12a located between the trenches 14 is exposed from the insulating film 26, and the insulating film 26 is left inside the trenches 14 (i.e., above the gate electrodes 18). The insulating film 26 remaining inside the trenches 14 becomes the interlayer insulating film 20. Here, the interlayer insulating film 20 is formed so that the upper surface of the interlayer insulating film 20 is located lower than the upper surface 12a of the semiconductor substrate 12 (more specifically, the portion located between the trenches 14). Note that, as shown in FIG. 6, the insulating film 26 is left outside the region where the trenches 14 are formed. The remaining insulating film 26 becomes the protective insulating film 26 that protects the outer periphery. At the end of the trench 14 in the y direction, a step S1 exists where the upper surface 12a is located higher than the upper surface of the gate electrodes 18. The step S1 is covered with the protective insulating film 26.

[0022] Next, as shown in FIG. 7, a nickel layer 30 is formed across the upper surface 12a and the upper surface of the interlayer insulating film 20. Next, an annealing process is performed at a predetermined temperature to react the semiconductor substrate 12 and the nickel layer 30 at their interface. As a result, a silicide layer 22 (i.e., a nickel silicide layer) covering the upper surface 12a is formed, as shown in FIG. 8. The silicide layer 22 is curved along the upper surface 12a. An end 22a of the silicide layer 22 tends to grow in the x direction. The silicide layer 22 makes ohmic contact with the semiconductor substrate 12.

[0023] Next, the unreacted nickel layer 30 is removed by etching. As a result, the silicide layer 22 and the interlayer insulating film 20 are exposed as shown in FIG. 9. At this time, the upper surface of the silicide layer 22 protrudes above the interlayer insulating film 20. That is, in the semiconductor wafer shown in FIG. 9, the portions between the trenches 14 protrude above the interlayer insulating film 20.

[0024] Next, a barrier metal layer 23 is formed by a sputtering method using a sputtering target 60 shown in FIG. 10 . The sputtering target 60 is placed above the semiconductor wafer. The sputtering target 60 is placed so that a normal 90 to the surface of the sputtering target 60 is inclined at an angle θ with respect to the z direction. Here, the normal 90 is inclined along the y direction with respect to the z direction (i.e., in the yz plane). The sputtering target 60 emits sputter particles radially from the normal 90. The sputtering target 60 emits the sputter particles toward the semiconductor wafer. The emitted sputter particles adhere to and deposit on the surface of the semiconductor wafer, thereby forming a barrier metal layer 23 across the surface of the interlayer insulating film 20 and the surface of the silicide layer 22, as shown in FIGS. 10 and 11 . Therefore, the barrier metal layer 23 is in contact with the interlayer insulating film 20 and the silicide layer 22.

[0025] Generally, a sputtered layer does not grow easily near a step, such as the end 22a of the silicide layer 22. Therefore, if the sputtering method is inappropriate, the barrier metal layer 23 may not grow properly near the end 22a, resulting in a step 92, as shown in FIG. 12 . The formation of the step 92 significantly reduces the barrier performance of the barrier metal layer 23. In contrast, as described above, in the step of forming the barrier metal layer 23 in Example 1, the sputtered particles are emitted radially from a perpendicular line 90 inclined along the y direction. Therefore, in the emission angle distribution of the sputtered particles, the y-direction component (the component in the longitudinal direction of the trench 14) is greater than the x-direction component. Therefore, the sputtered particles grow uniformly on the upper surface of the interlayer insulating film 20, as shown in FIG. 11 . This prevents the formation of the step 92.

[0026] 1, a surface electrode layer 24 is formed so as to cover the upper surface of the barrier metal layer 23 in an area spanning the plurality of trenches 14. Because the barrier metal layer 23 does not have a discontinuity 92, the barrier metal layer 23 can prevent interdiffusion of elements between the surface electrode layer 24 and the semiconductor substrate 12. Thereafter, a drain electrode 52 is formed on the lower surface of the semiconductor substrate 12, thereby completing the semiconductor device 100.

[0027] As described above, according to the first embodiment, the barrier metal layer 23 can be prevented from being broken, and therefore the semiconductor device 100 with good performance can be manufactured.

[0028] Example 2 A method for manufacturing a semiconductor device 100 according to a second embodiment will be described. In the second embodiment, a semiconductor wafer is processed to the state shown in FIG. 9, as in the first embodiment. Next, a barrier metal layer 23 is formed by a sputtering method using a collimator 62 shown in FIG. 13. In FIG. 13, parts common to those in FIG. 10 are given the same reference numerals. As shown in FIG. 13, the collimator 62 is disposed between the sputtering target 60 and the semiconductor wafer. In addition, the sputtering target 60 is disposed so that a normal to its surface is parallel to the z direction.

[0029] As shown in FIG. 14, the collimator 62 is a plate-shaped member and has a plurality of openings 64. Each opening 64 penetrates the collimator 62 in the z direction. The openings 64 have the same shape. The openings 64 have a rectangular shape that is long in the y direction. That is, the length Y1 of the openings 64 along the y direction is longer than the length X1 of the openings 64 along the x direction. Note that each opening 64 of the collimator 62 may have a hexagonal shape that is long in the y direction, as shown in FIG. 15.

[0030] In the process of forming the barrier metal layer 23 of Example 2, as shown in FIG. 13 , a sputtering target 60 emits sputter particles. The sputtering target 60 emits sputter particles radially from the z direction. The sputtering target 60 emits sputter particles with a substantially uniform angular distribution in the x and y directions. The sputter particles emitted from the sputtering target 60 adhere to the surface of the semiconductor wafer via a collimator 62. The sputter particles that pass through the collimator 62 adhere to and deposit on the surface of the semiconductor wafer, thereby forming a barrier metal layer 23 across the surface of the interlayer insulating film 20 and the surface of the portion between the trenches 14, as shown in FIG. 11 . Furthermore, when passing through the collimator 62, sputter particles whose movement direction is inclined with respect to the z direction are cut off. Because the length of the opening 64 of the collimator 62 along the y direction is longer than the length along the x direction, sputter particles having an angular component along the x direction are cut off at a higher rate than sputter particles having an angular component along the y direction. Therefore, at the position after passing through the collimator 62, the y-direction component (the component in the longitudinal direction of the trench 14) is greater than the x-direction component in the emission angle distribution of the sputtered particles. By cutting the x-direction component, the growth rate of the barrier metal layer 23 on the surface of the end 22a is slowed. Therefore, as shown in FIG. 11, the barrier metal layer 23 grows uniformly on the surface of the interlayer insulating film 20. This prevents the formation of a discontinuity 92.

[0031] Next, the surface electrode layer 24 is formed in the same manner as in Example 1. Since the barrier metal layer 23 does not have a discontinuity 92, the barrier metal layer 23 can prevent interdiffusion of elements between the surface electrode layer 24 and the semiconductor substrate 12. Thereafter, the drain electrode 52 is formed on the lower surface of the semiconductor substrate 12, thereby completing the semiconductor device 100.

[0032] In the above-described embodiment, the semiconductor substrate 12 is a SiC substrate. However, the semiconductor substrate 12 may be made of other semiconductor materials containing silicon (for example, single crystal silicon).

[0033] In the above-described embodiment, the upper surface 12a of the semiconductor substrate 12 is slightly curved in an upwardly convex direction between adjacent trenches 14. However, the upper surface 12a does not have to be curved between adjacent trenches 14. Also, the silicide layer 22 is curved along the upper surface 12a. However, the silicide layer 22 does not have to be curved.

[0034] In the above-described embodiment, the metal layer is grown by sputtering on the surfaces of the interlayer insulating film 20 and the silicide layer 22. However, the sputtering method disclosed in this specification may be used when growing the metal layer by sputtering on the surfaces of the interlayer insulating film 20 and the semiconductor substrate 12 (i.e., the surfaces where the semiconductor layer is exposed).

[0035] In the above-described embodiment, the barrier metal layer 23 is made of Ti, TiN, a titanium alloy, etc. However, the barrier metal layer 23 may be made of a plurality of metal layers.

[0036] In the above-described embodiment, the barrier metal layer 23 is provided in the semiconductor device 100. However, other metal layers other than the barrier metal layer may be provided.

[0037] In the above-described embodiment, the opening 64 of the collimator 62 is rectangular or hexagonal, but the shape of the opening 64 may be polygonal or circular.

[0038] An embodiment of the method for manufacturing a semiconductor device disclosed in this specification will be described below. (Aspect 1) a gate insulating film provided in each of the trenches; a gate electrode provided in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; and an interlayer insulating film provided in each of the trenches and covering an upper surface of the gate electrode, wherein inter-trench portions of the semiconductor wafer located between the plurality of trenches protrude above an upper surface of the interlayer insulating film; and a method for manufacturing a semiconductor device, the method comprising the steps of: preparing a semiconductor wafer; (Aspect 2) A method for manufacturing a semiconductor device, the method comprising the steps of: preparing a semiconductor wafer comprising: a semiconductor substrate having a plurality of trenches formed on an upper surface thereof; a gate insulating film formed in each of the trenches; gate electrodes formed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; and an interlayer insulating film formed in each of the trenches and covering upper surfaces of the gate electrodes, wherein inter-trench portions of the semiconductor wafer located between the plurality of trenches protrude above an upper surface of the interlayer insulating film; and forming a metal layer covering an area spanning the surface of the inter-trench portions and a surface of the interlayer insulating film by a sputtering method in which a normal to a sputtering target is inclined along the longitudinal direction of the trenches with respect to the thickness direction of the semiconductor wafer. (Aspect 3) a metal layer covering an area spanning the surface of the inter-trench portion and the surface of the inter-layer insulating film by a sputtering method using a collimator having an opening whose dimension in the longitudinal direction of the trench is longer than the width direction of the trench, the metal layer forming ... (Aspect 4) 4. The manufacturing method of any one of aspects 1 to 3, wherein the step of preparing the semiconductor wafer includes the step of forming an insulating film on the upper surface of the gate electrode and the upper surface of the semiconductor substrate, and then etching back the insulating film while leaving the insulating film in the trench, thereby forming the interlayer insulating film. (Aspect 5) The manufacturing method according to any one of aspects 1 to 4, wherein the step of preparing the semiconductor wafer includes preparing the semiconductor wafer in such a way that a step is provided at an end of the trench in the longitudinal direction, whereby the upper surface of the semiconductor substrate is positioned higher than the upper surface of the gate electrode, and the step is covered with a protective insulating film. (Aspect 6) Aspect 6. The manufacturing method according to any one of Aspects 1 to 5, wherein in the step of preparing the semiconductor wafer, the semiconductor wafer is prepared having a silicide layer provided on an upper surface of the inter-trench portion. (Aspect 7) 7. The method according to any one of aspects 1 to 6, wherein the metal layer is a barrier metal layer.

[0039] According to the second aspect, the metal layer can be effectively formed on the step portion.

[0040] According to the third aspect, the metal layer can be effectively formed on the step portion.

[0041] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0042] 12: Semiconductor substrate 14: Trench 16: Gate insulating film 18: Gate electrode 20: Interlayer insulating film 22: Silicide layer 23: Barrier metal layer 60: Sputtering target 62: Collimator 64: Opening 90: Perpendicular 92: Step break 100: Semiconductor device

Claims

1. A method for manufacturing a semiconductor device (100), comprising: a semiconductor substrate (12) having a plurality of trenches (14) formed on an upper surface (12a); a gate insulating film (16) provided in each of the trenches; a gate electrode (18) provided in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; an interlayer insulating film (20) provided in each of the trenches and covering the upper surface of the gate electrode; preparing a semiconductor wafer comprising: a step of: providing the semiconductor wafer, wherein inter-trench portions located between a plurality of the trenches of the semiconductor wafer protrude above an upper surface of the interlayer insulating film; forming a metal layer covering an area spanning the surface of the inter-trench portion and the surface of the interlayer insulating film by a sputtering method in which the component in the longitudinal direction of the trench is greater than the component in the width direction of the trench in the emission angle distribution of sputtered particles; A manufacturing method comprising the steps of:

2. A method for manufacturing a semiconductor device (100), comprising: a semiconductor substrate (12) having a plurality of trenches (14) formed on an upper surface (12a); a gate insulating film (16) provided in each of the trenches; a gate electrode (18) provided in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; an interlayer insulating film (20) provided in each of the trenches and covering the upper surface of the gate electrode; preparing a semiconductor wafer comprising: a step of: providing the semiconductor wafer, wherein inter-trench portions located between a plurality of the trenches of the semiconductor wafer protrude above an upper surface of the interlayer insulating film; a step of forming a metal layer covering an area spanning the surface of the inter-trenches and the surface of the interlayer insulating film by a sputtering method in which a normal to a sputtering target (60) is inclined along the longitudinal direction of the trench with respect to the thickness direction of the semiconductor wafer; A manufacturing method comprising the steps of:

3. A method for manufacturing a semiconductor device (100), comprising: a semiconductor substrate (12) having a plurality of trenches (14) formed on an upper surface (12a); a gate insulating film (16) provided in each of the trenches; a gate electrode (18) provided in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; an interlayer insulating film (20) provided in each of the trenches and covering the upper surface of the gate electrode; preparing a semiconductor wafer comprising: a step of: providing the semiconductor wafer, wherein inter-trench portions located between a plurality of the trenches of the semiconductor wafer protrude above an upper surface of the interlayer insulating film; a step of forming a metal layer covering an area spanning the surface of the inter-trenches and the surface of the interlayer insulating film by a sputtering method in which a collimator (62) having an opening (64) whose dimension in the longitudinal direction of the trench is longer than the width direction of the trench is disposed between the sputtering target (60) and the semiconductor wafer; A manufacturing method comprising the steps of:

4. 4. The manufacturing method according to claim 1, wherein the step of preparing the semiconductor wafer includes a step of forming an insulating film (26) on the upper surface of the gate electrode and the upper surface of the semiconductor substrate, and then etching back the insulating film while leaving the insulating film in the trench, thereby forming the interlayer insulating film.

5. 4. The manufacturing method according to claim 1, wherein the step of preparing the semiconductor wafer includes providing a step (S1) at an end of the trench in the longitudinal direction, where the upper surface of the semiconductor substrate is positioned higher than the upper surface of the gate electrode, and the step is covered with a protective insulating film (26).

6. 4. The manufacturing method according to claim 1, wherein in the step of preparing the semiconductor wafer, the semiconductor wafer is prepared having a silicide layer (22) provided on an upper surface of the portion between the trenches.

7. The manufacturing method according to any one of claims 1 to 3, wherein the metal layer is a barrier metal layer (23).

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