Semiconductor package

Abstract

To reduce the size.SOLUTION: A resistance chip 10 includes a first element surface 11 where a plurality of electrodes 40 including a first electrode 41 and a second electrode 42 are provided, and a second element surface 12 on the opposite side of the first element surface 11. The resistance chip 10 is mounted on a mount surface 111 of a mount member 110. Sealing resin 160 seals the resistance chip 10 mounted on the mount surface 111. The resistance chip 10 includes a chip substrate 21, an insulator 22, and a resistance layer 30. The chip substrate 21 includes a first substrate surface 21S, and a second substrate surface 21R existing on the opposite side of the first substrate surface 21S and forming the second element surface 12. The insulator 22 is provided on the first substrate surface 21S. The resistance layer 30 is provided in the insulator 22. The resistance layer 30 is connected between the first electrode 41 and the second electrode 42. The resistance chip 10 is mounted on the mount surface 111 with the first element surface 11 and the mount surface 111 facing each other in a thickness direction of the resistance chip 10.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor packages. [Background technology]

[0002] Conventionally, semiconductor devices that detect high voltages using resistive voltage division have been known. For example, Patent Document 1 discloses a semiconductor device that includes a resistive element mounted on a high-voltage die pad and a semiconductor element mounted on a low-voltage die pad. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 176963

[0004] [overview] There is a demand for miniaturization of the above-mentioned semiconductor devices.

[0005] A semiconductor package according to one embodiment of the present disclosure includes a resistor chip having a first element surface on which a plurality of electrodes including a first electrode and a second electrode are provided, and a second element surface opposite the first element surface, a mounting member having a mounting surface on which the resistor chip is mounted, a sealing resin that seals the resistor chip when mounted on the mounting surface, and a first external terminal and a second external terminal, wherein the resistor chip includes a chip substrate having a first substrate surface and a second substrate surface opposite the first substrate surface and constituting the second element surface, an insulator provided on the first substrate surface, and a resistive layer provided within the insulator, the resistive layer being connected between the first electrode and the second electrode, and the resistor chip is mounted on the mounting surface with the first element surface and the mounting surface facing each other in the thickness direction of the resistor chip. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing an example of a semiconductor package according to the first embodiment. [Figure 2] FIG. 2 is a schematic rear view showing an example of the semiconductor package of FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 5] FIG. 5 is a circuit diagram showing an example of the electrical configuration of the semiconductor package of FIG. [Figure 6] FIG. 6 is a schematic plan view showing an example of the resistor chip of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the resistor chip of FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a semiconductor package according to a modified example. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a semiconductor package according to a modified example. [Figure 10] FIG. 10 is a schematic plan view showing an example of a semiconductor package according to the second embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 13] FIG. 13 is a schematic plan view showing an example of a semiconductor package according to the third embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 15] FIG. 15 is a schematic plan view showing an example of a semiconductor package according to the fourth embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 17] FIG. 17 is a schematic plan view showing an example of a semiconductor package according to the fifth embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 19]FIG. 19 is a schematic plan view showing an example of a semiconductor package according to the sixth embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view of the semiconductor package of FIG. [Figure 21] FIG. 21 is a schematic plan view showing the amplifier chip and the connection member of FIG. [Figure 22] FIG. 22 is a schematic plan view showing the resistor chip and the connection member of FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a semiconductor package according to a modified example. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a semiconductor package according to a modified example. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a modified resistor chip. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a modified resistor chip. [Figure 27] FIG. 27 is a schematic cross-sectional view showing a modified resistor chip. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a modified resistor chip. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a modified resistor chip. [Figure 30] FIG. 30 is a schematic cross-sectional view showing a modified resistor chip.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor package of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] (First embodiment) A semiconductor package 100 according to a first embodiment will be described with reference to FIGS. FIG. 1 shows an example of a planar structure of a semiconductor package 100 according to the first embodiment. FIG. 2 shows an example of the semiconductor package of FIG. 1. In FIG. 2, the resistor chip 10, the amplifier chip 60, and the mounting member 110 are shown through a sealing resin 160. FIG. 3 shows an example of a cross-sectional structure of the semiconductor package 100 of FIG. 2, illustrating the resistor chip 10 and the mounting member 110. In FIG. 3, the resistive layer 30 is shown as a single member connected between the first electrode 41 and the third electrode 43. FIG. 4 shows an example of a cross-sectional structure of the semiconductor package 100 of FIG. 2, illustrating the connection between the resistor chip 10 and the amplifier chip 60. In FIG. 4, the resistive layer 30 is shown as a single member connected between the first electrode 41 and the second electrode 42. The term "planar view" used in this disclosure refers to viewing the semiconductor package 100 in the Z-axis direction of the XYZ axes shown in FIG. 1.

[0011] (Schematic structure of semiconductor package) As shown in FIG. 1, the semiconductor package 100 is connected to a battery 800. The semiconductor package 100 is used as a high-voltage monitor having a high withstand voltage. The battery 800 is the object to be monitored and may be, for example, a battery for an electric vehicle or a hybrid vehicle. The rated voltage of the semiconductor package 100 may be, for example, 1200V.

[0012] 1 to 4, the semiconductor package 100 includes a resistor chip 10, an amplifier chip 60, a mounting member 110, and a sealing resin 160. The resistor chip 10 and the amplifier chip 60 are mounted on the mounting member 110. The sealing resin 160 seals the resistor chip 10, the amplifier chip 60, and a portion of the mounting member 110.

[0013] The sealing resin 160 has, for example, a rectangular flat plate shape with its thickness direction in the Z-axis direction. The sealing resin 160 includes a first surface 161 and a second surface 162 opposite to the first surface 161. The sealing resin 160 includes a plurality of sealing side surfaces 163, 164, 165, and 166 that connect the first surface 161 and the second surface 162.

[0014] The sealing resin 160 is made of an electrically insulating material. The sealing resin 160 may be made of an epoxy resin. The material that makes up the sealing resin 160 may be colored, for example, black.

[0015] 4 and 5, the mounting member 110 includes a mounting surface 111. The resistor chip 10 and the amplifier chip 60 are mounted on the mounting surface 111 of the mounting member 110. (Resistor chip overview) 1 to 4, the resistor chip 10 has a generally rectangular shape in a plan view. The resistor chip 10 includes a first element surface 11 and a second element surface 12 opposite the first element surface 11. The resistor chip 10 includes a plurality of element side surfaces 13, 14, 15, and 16 connecting the first element surface 11 and the second element surface 12. The resistor chip 10 has a rectangular shape in a plan view with its short side direction aligned in the X-axis direction and its long side direction aligned in the Y-axis direction. That is, the resistor chip 10 includes element side surfaces 13 and 14 extending along the X-axis direction and element side surfaces 15 and 16 extending along the Y-axis direction.

[0016] 2, the resistor chip 10 includes a plurality of electrodes 40 provided on the first element surface 11. In one example, the plurality of electrodes 40 include a first electrode 41, a second electrode 42, and a third electrode 43. In one example, the first electrode 41 and the second electrode 42 are arranged in the central portion of the resistor chip 10 in the X-axis direction. In one example, the first electrode 41 and the second electrode 42 are arranged spaced apart in the Y-axis direction.

[0017] The resistor chip 10 includes a plurality of third electrodes 43. The plurality of third electrodes 43 include a reference electrode 43B, a first detection electrode 43A, and a second detection electrode 43C. In one example, the reference electrode 43B, the first detection electrode 43A, and the second detection electrode 43C are arranged in a central region of the resistor chip 10 in the Y-axis direction, closer to the element side surface 16. In one example, the first detection electrode 43A and the second detection electrode 43C are arranged on either side of the reference electrode 43B in the Y-axis direction. The reference electrode 43B, the first detection electrode 43A, and the second detection electrode 43C are arranged along the element side surface 16 of the resistor chip 10.

[0018] (Overview of amplifier chip) 1 to 4, the amplifier chip 60 has a generally rectangular shape in a plan view. The amplifier chip 60 includes a first element surface 61 and a second element surface 62 opposite to the first element surface 61. The amplifier chip 60 includes a plurality of element side surfaces 63 to 66 connecting the first element surface 61 and the second element surface 62.

[0019] The amplifier chip 60 includes a semiconductor substrate. In one example, the semiconductor substrate is a substrate made of a material containing Si. The semiconductor substrate may be an epitaxial substrate including a Si substrate and an epitaxial layer stacked on the Si substrate. Functional devices that constitute the circuit of the amplifier chip 60 shown in FIG. 5 are formed on the semiconductor substrate. The functional devices may include passive elements such as resistors, active elements such as transistors, a circuit network made up of multiple elements, etc.

[0020] 2, the amplifier chip 60 includes a plurality of electrodes 70 provided on the first element surface 61. In one example, the plurality of electrodes 70 may include a first electrode 71 and a second electrode 72.

[0021] The first electrode 71 may be an electrode for connecting the amplifier chip 60 to the resistor chip 10. The first electrode 71 is provided corresponding to the third electrode 43 of the resistor chip 10. The amplifier chip 60 may include a plurality of first electrodes 71. The plurality of first electrodes 71 may include a reference electrode 71B, a first input electrode 71A, and a second input electrode 71C. In one example, the plurality of first electrodes 71 are arranged closer to the element side surface 65. In one example, the first input electrode 71A and the second input electrode 71C are arranged with the reference electrode 71B sandwiched between them.

[0022] The second electrode 72 may be an electrode for connecting the amplifier chip 60 to an external device. The amplifier chip 60 may include a plurality of second electrodes 72. In one example, the plurality of second electrodes 72 may be arranged closer to the element side surface 66. The arrangement positions of the plurality of second electrodes 72 may be changed as appropriate. The plurality of second electrodes 72 may be arranged along the element side surface 63 or the element side surface 64. The plurality of second electrodes 72 may be arranged separately along the plurality of element side surfaces.

[0023] The multiple second electrodes 72 may include a first power supply electrode 72A and a second power supply electrode 72B for supplying a drive voltage (power supply voltage) to the amplifier chip 60. The multiple second electrodes 72 may also include multiple output electrodes 72C. The multiple output electrodes 72C may include electrodes for outputting to the outside an output voltage corresponding to a divided voltage generated in the resistor chip 10 connected to the amplifier chip 60. The multiple output electrodes 72C may include electrodes for supplying a signal or the like to the amplifier chip 60.

[0024] 3, the amplifier chip 60 includes an insulating film 73 that covers the first element surface 61 and the multiple electrodes 70. The insulating film 73 includes openings 73X that expose portions of the electrodes 70. The amplifier chip 60 includes connection members 80 connected to the multiple electrodes 70.

[0025] (mounting components) 1 and 2, the mounting member 110 includes a plurality of leads 120. The upper surfaces of the plurality of leads 120 form a mounting surface 111. The resistor chip 10 is mounted on the mounting surface 111 of the plurality of leads 120. In addition, the amplifier chip 60 is mounted on the mounting surface 111 of the plurality of leads 120.

[0026] (1st lead, 2nd lead) The plurality of leads 120 includes a first lead 121 and a second lead 122. In one example, the first lead 121 is connected to the positive terminal of the battery 800, and the second lead 122 is connected to the negative terminal of the battery 800.

[0027] The first lead 121 and the second lead 122 are arranged to protrude from a third sealing side surface 165 of the sealing resin 160. In detail, the first lead 121 is arranged to protrude from a portion of the third sealing side surface 165 closer to the first sealing side surface 163, and the second lead 122 is arranged to protrude from a portion of the third sealing side surface 165 closer to the second sealing side surface 164.

[0028] The first lead 121 and the second lead 122 include an internal lead 123 embedded in the sealing resin 160 and an external lead 124 protruding from a third sealing side surface 165 of the sealing resin 160. The external lead 124 constitutes an external terminal with which the semiconductor package 100 is mounted on a mounting substrate. The external lead 124 of the first lead 121 corresponds to the "first external terminal." The external lead 124 of the second lead 122 corresponds to the "second external terminal."

[0029] 3 and 4, the external lead 124 may be bent and include a first portion 124A, a second portion 124B, and a third portion 124C. The first portion 124A protrudes laterally from the third sealing side surface 165 of the sealing resin 160. The second portion 124B extends from the tip of the first portion 124A in the Z-axis direction toward the second surface 162 of the sealing resin 160 and gradually moves away from the third sealing side surface 165. The third portion 124C extends from the tip of the second portion 124B in the direction in which the first portion 124A protrudes.

[0030] (Intermediate lead) The multiple leads 120 may include multiple intermediate leads 125. The multiple intermediate leads 125 connect the resistor chip 10 and the amplifier chip 60. The multiple intermediate leads 125 may be provided in accordance with the third electrode 43 of the resistor chip 10. The reference electrode 43B of the resistor chip 10 is connected to the reference electrode 71B of the amplifier chip 60 by the intermediate lead 125B. The first detection electrode 43A of the resistor chip 10 is connected to the first input electrode 71A of the amplifier chip 60 by the intermediate lead 125A. The second detection electrode 43C of the resistor chip 10 is connected to the second input electrode 71C of the amplifier chip 60 by the intermediate lead 125C.

[0031] (3rd lead) The multiple leads 120 may include multiple third leads 126. The multiple third leads 126 are arranged so as to protrude from a fourth sealing side surface 166 of the sealing resin 160. The multiple third leads 126 are arranged spaced apart from one another in the Y-axis direction. The multiple third leads 126 are arranged on the fourth sealing side surface 166 from a portion closer to the first sealing side surface 163 to a portion closer to the second sealing side surface 164.

[0032] The multiple third leads 126 include internal leads 127 embedded in the sealing resin 160 and external leads 128 protruding from a fourth sealing side surface 166 of the sealing resin 160. The external leads 128 constitute external terminals that mount the semiconductor package 100 on a mounting substrate. The external leads 128 of the multiple third leads 126 correspond to "third external terminals."

[0033] 3, the external lead 128 may be bent and include a first portion 128A, a second portion 128B, and a third portion 128C. The first portion 128A protrudes laterally from the fourth sealing side surface 166 of the sealing resin 160. The second portion 128B extends from the tip of the first portion 128A in the Z-axis direction toward the second surface 162 of the sealing resin 160 and gradually moves away from the fourth sealing side surface 166. The third portion 128C extends from the tip of the second portion 128B in the direction in which the first portion 128A protrudes.

[0034] As shown in FIGS. 3 and 4 , the first lead 121, the second lead 122, the intermediate lead 125, and the third lead 126 may have the same thickness. The first lead 121, the second lead 122, the intermediate lead 125, and the third lead 126 may be formed, for example, by partially removing a plate-like member by etching. The partially removed member may be called a lead frame. The plate-like member may be made of the same material as the first lead 121, the second lead 122, the intermediate lead 125, and the third lead 126. This makes it easy to form a mounting member 110 including multiple leads 120, i.e., a mounting member 110 including the first lead 121, the second lead 122, the intermediate lead 125, and the third lead 126.

[0035] (Resistor chip mounting format) The resistor chip 10 is mounted on a mounting member 110. More specifically, the resistor chip 10 is mounted on a first lead 121, a second lead 122, and an intermediate lead 125.

[0036] The resistor chip 10 includes a plurality of electrodes 40 provided on the first element surface 11. The plurality of electrodes 40 are connected to any of the first lead 121, the second lead 122, and the intermediate lead 125. In other words, the resistor chip 10 is mounted with the first element surface 11 facing the mounting surface 111 of the mounting member 110. It can be said that the resistor chip 10 is mounted with the first element surface 11 provided with the plurality of electrodes 40 facing the mounting member 110. It can be said that the resistor chip 10 is flip-chip mounted on the mounting member 110.

[0037] The resistor chip 10 includes a plurality of connection members 50. The plurality of electrodes 40 of the resistor chip 10 are electrically connected to a plurality of leads 120 of the mounting member 110 by the plurality of connection members 50. The plurality of connection members 50 include a first connection member 51, a second connection member 52, and a third connection member 53 corresponding to the first electrode 41, the second electrode 42, and the third electrode 43.

[0038] The first electrode 41 is electrically connected to the first lead 121 by a first connecting member 51. The second electrode 42 is electrically connected to the second lead 122 by a second connecting member 52. The third electrode 43 is electrically connected to the intermediate lead 125 by a third connecting member 53.

[0039] As shown in Figures 3, 4, and 7, the connection member 50 includes a terminal portion 50A and a joint portion 50B. The terminal portion 50A is electrically connected to each electrode 40. The terminal portion 50A protrudes in the Z-axis direction from the first element surface 11. The terminal portion 50A has a pillar shape. In one example, the terminal portion 50A may have a cylindrical shape. In one example, the terminal portion 50A is made of a material containing Cu. The terminal portion 50A may be called a pillar portion. The terminal portion 50A made of a material containing Cu may be called a Cu pillar.

[0040] The joint portion 50B is disposed between the terminal portion 50A and the mounting member 110. The joint portion 50B is used to join the mounting member together. In one example, the joint portion 50B is made of a material containing SnAg. The joint portion 50B may be called a solder layer. The joint portion 50B may have a layered structure including a first layer made of a material containing Ni and Fe and a second layer made of a material containing SnAg.

[0041] (Amplifier chip implementation) The amplifier chip 60 is mounted on the mounting member 110. More specifically, the amplifier chip 60 is mounted on the intermediate lead 125 and the third lead 126.

[0042] The amplifier chip 60 includes a plurality of electrodes 70 provided on a first element surface 61. The plurality of electrodes 70 are connected to any of a plurality of intermediate leads 125 and a plurality of third leads 126. In other words, the amplifier chip 60 is mounted with the first element surface 61 facing the mounting surface 111 of the mounting member 110. It can be said that the amplifier chip 60 is mounted with the first element surface 61, on which the plurality of electrodes 70 are provided, facing the mounting member 110. It can be said that the amplifier chip 60 is flip-chip mounted on the mounting member 110.

[0043] The amplifier chip 60 includes a plurality of connection members 80. The plurality of electrodes 70 of the amplifier chip 60 are electrically connected to a plurality of leads 120 of the mounting member 110 by the plurality of connection members 80. The plurality of connection members 80 include a first connection member 81 and a second connection member 82 corresponding to the first electrode 71 and the second electrode 72. The first electrode 71 is electrically connected to the intermediate lead 125 by the first connection member 81. The second electrode 72 is electrically connected to the third lead 126 by the second connection member 82. The second connection member 82 corresponds to the "third connection member."

[0044] As shown in FIGS. 3 and 4 , the connection member 80 includes a terminal portion 80A and a joint portion 80B. The terminal portion 80A is electrically connected to each electrode 70. The terminal portion 80A protrudes in the Z-axis direction from the first element surface 61. The terminal portion 80A has a pillar shape. In one example, the terminal portion 80A may have a cylindrical shape. In one example, the terminal portion 80A is made of a material containing Cu. The terminal portion 80A may be called a pillar portion. The terminal portion 80A made of a material containing Cu may be called a Cu pillar.

[0045] The joint portion 80B is disposed between the terminal portion 80A and the mounting member 110. The joint portion 80B is used to join the mounting member together. In one example, the joint portion 80B is made of a material containing SnAg. The joint portion 80B may be called a solder layer. The joint portion 80B may have a layered structure including a first layer made of a material containing Ni and Fe and a second layer made of a material containing SnAg.

[0046] (Circuit configuration of semiconductor package) FIG. 5 shows an example of the electrical configuration of the semiconductor package of FIG. The semiconductor package 100 includes a resistor chip 10 and an amplifier chip 60 connected to the resistor chip 10 .

[0047] The resistor chip 10 includes a resistive layer 30 connected between a first electrode 41 and a second electrode 42. The resistive layer 30 includes a first resistive layer 31, a second resistive layer 32, a third resistive layer 33, and a fourth resistive layer 34. The first to fourth resistive layers 31 to 34 form a voltage dividing circuit that divides the voltage between the first electrode 41 and the second electrode 42.

[0048] The first resistive layer 31 is connected to a first electrode 41. The fourth resistive layer 34 is connected to a second electrode 42. The second resistive layer 32 and the third resistive layer 33 connect the first resistive layer 31 and the second resistive layer 32 together.

[0049] The connection point between the first resistive layer 31 and the second resistive layer 32 is connected to a first detection electrode 43A. The connection point between the second resistive layer 32 and the third resistive layer 33 is connected to a reference electrode 43B. The connection point between the third resistive layer 33 and the fourth resistive layer 34 is connected to a second detection electrode 43C. The connection points between the first to fourth resistive layers 31 to 34 can be said to be connected to the third electrode 43.

[0050] In one example, the first resistive layer 31 and the fourth resistive layer 34 have the same resistance value. In one example, the second resistive layer 32 and the third resistive layer 33 have the same resistance value. In one example, the resistance value of the second resistive layer 32 is smaller than the resistance value of the first resistive layer 31. The resistance value RB of the second resistive layer 32 may be 1 / 100 or less of the resistance value RA of the first resistive layer 31. In one example, the ratio of the resistance value RB of the second resistive layer 32 to the resistance value RA of the first resistive layer 31 (RB / RA) is 1 / 999. In one example, the resistance value RC of the third resistive layer 33 is smaller than the resistance value RD of the fourth resistive layer 34. The resistance value RC of the third resistive layer 33 may be 1 / 100 or less of the resistance value RD of the fourth resistive layer 34. In one example, the ratio of the resistance value RC of the third resistive layer 33 to the resistance value RD of the fourth resistive layer 34 (RC / RD) is 1 / 999. The resistive layer 30 generates a voltage by dividing the voltage between the first electrode 41 and the second electrode 42 in accordance with the ratio of the resistance values ​​RA to RD of the first to fourth resistive layers 31 to 34. The resistance values ​​of the first to fourth resistive layers 31 to 34 included in the resistive layer 30 may be set in accordance with the input voltage applied between the first electrode 41 and the second electrode 42 and the input voltage of the amplifier chip 60. The resistance value of the resistive layer 30 may be, for example, 20 MΩ or more.

[0051] A power supply voltage VCC is supplied to a first power supply electrode 72A of the amplifier chip 60, and a second power supply electrode 72B of the amplifier chip 60 is connected to a reference potential terminal (for example, a ground terminal). The amplifier chip 60 includes a first voltage follower circuit 91, a second voltage follower circuit 92, and a differential amplifier circuit 93. The input terminal of the first voltage follower circuit 91 is connected to the first detection electrode 43A, and the input terminal of the second voltage follower circuit 92 is connected to the second detection electrode 43C. The output terminals of the first voltage follower circuit 91 and the second voltage follower circuit 92 are connected to two input terminals of a differential amplifier circuit 93. The output terminal of the first voltage follower circuit 91 is connected to the output electrode 72C1, and the output terminal of the second voltage follower circuit 92 is connected to the output electrode 72C2. The output terminal of the differential amplifier circuit 93 is connected to the output electrode 72C3. The amplifier chip 60 also includes a voltage adjustment circuit 94. The voltage adjustment circuit 94 is connected to the reference electrode 71B. The voltage adjustment circuit 94 generates a reference voltage Vr. The reference voltage Vr may be, for example, half the power supply voltage VCC.

[0052] The amplifier chip 60 outputs an output voltage Vout corresponding to the difference between the voltage of the first detection electrode 43A and the voltage of the second detection electrode 43C. The amplifier chip 60 outputs the output voltage of the first voltage follower circuit 91 as a first monitor voltage Vpm, and outputs the output voltage of the second voltage follower circuit 92 as a second monitor voltage Vnm. The amplifier chip 60 outputs the reference voltage Vr as a monitor voltage Vm.

[0053] (Resistor chip configuration) Fig. 6 is a schematic plan view showing an example of the resistor chip of Fig. 1. Fig. 7 shows an outline of the cross-sectional structure of the resistor chip of Fig. 6. In Fig. 7, the resistive layer 30 is shown as a single member connected between the first electrode 41 and the second electrode 42.

[0054] 6 and 7, the resistor chip 10 includes a first electrode 41, a second electrode 42, and a third electrode 43 (a first detection electrode 43A, a reference electrode 43B, and a second detection electrode 43C). The resistor chip 10 includes connection members 51 to 53 connected to the electrodes 41 to 43, respectively.

[0055] The resistor chip 10 includes an annular conductor 46. The annular conductor 46 has an annular shape extending along each of the element side surfaces 13 to 16 of the resistor chip 10. The annular conductor 46 is arranged inside the resistor chip 10 relative to each of the element side surfaces 13 to 16. The multiple electrodes 40 (41 to 43) and the resistive layer 30 are arranged inside the annular conductor 46. The annular conductor 46, for example, prevents moisture from penetrating the insulator 22 on which the resistive layer 30 and the multiple electrodes 40 (41 to 43) are arranged, and prevents cracks from penetrating due to dicing. The annular conductor 46 may be omitted.

[0056] Resistive layer 30 includes a plurality of thin-film resistive layers 30A. The plurality of thin-film resistive layers 30A may extend linearly. The plurality of thin-film resistive layers 30A extend in the Y-axis direction. The plurality of thin-film resistive layers 30A are arranged at intervals in the X-axis direction. The plurality of thin-film resistive layers 30A are connected in series between first electrode 41 and second electrode 42 by via conductors and connecting conductors. First to fourth resistive layers 31 to 34 may include thin-film resistive layers 30A in numbers corresponding to their respective resistance values.

[0057] 7, the resistor chip 10 includes a chip substrate 21. The chip substrate 21 has a rectangular flat plate shape with its thickness direction in the Z-axis direction. The chip substrate 21 includes a first substrate surface 21S and a second substrate surface 21R opposite to the first substrate surface 21S. The second substrate surface 21R of the chip substrate 21 forms the second element surface 12 of the resistor chip 10.

[0058] The chip substrate 21 is, for example, a glass substrate. The chip substrate 21 may be a sapphire substrate or a semiconductor substrate made of a material containing Si (silicon). The chip substrate 21 may also be a substrate using a wide band gap semiconductor made of SiC (silicon nitride) or a compound semiconductor such as AlN (aluminum nitride).

[0059] The resistor chip 10 may include an insulator 22 disposed on a first substrate surface 21S of the chip substrate 21. The insulator 22 includes a first surface 22S and a second surface 22R opposite to the first surface 22S. The second surface 22R of the insulator 22 contacts the first substrate surface 21S of the chip substrate 21. The first surface 22S of the insulator 22 forms the first element surface 11 of the resistor chip 10.

[0060] The insulator 22 may include first to fifth insulating layers 23 to 27. The first to fifth insulating layers 23 to 27 are stacked in the Z-axis direction from the first substrate surface 21S of the chip substrate 21. In the resistor chip 10, the Z-axis direction can be said to be the thickness direction of the insulator 22, or the stacking direction of the first to fifth insulating layers 23 to 27.

[0061] The first insulating layer 23 is provided on the chip substrate 21. The first insulating layer 23 is in contact with the first substrate surface 21S of the chip substrate 21. The first insulating layer 23 may be an insulating layer that covers the first substrate surface 21S of the chip substrate 21. The first insulating layer 23 forms the second surface 22R of the insulator 22. The fifth insulating layer 27 forms the first surface 22S of the insulator 22.

[0062] The first to fifth insulating layers 23 to 27 are made of a material containing Si. The first to fifth insulating layers 23 to 27 may be made of a material containing SiO2, SiN, SiC, SiCN, etc. In one example, the first to fifth insulating layers 23 to 27 are made of a material containing SiO2. The first to fifth insulating layers 23 to 27 may be made of different materials. The first to fifth insulating layers 23 to 27 may be oxide films formed by different methods.

[0063] The resistor chip 10 includes a resistive layer 30. The resistive layer 30 is provided in an insulator 22. It can be said that the resistor chip 10 includes a resistive layer 30 provided in an insulator 22. As shown in FIG. 6, the resistive layer 30 includes a plurality of thin-film resistive layers 30A. The plurality of thin-film resistive layers 30A are provided in an insulator 22 shown in FIG. 7. It can be said that the resistor chip 10 includes a plurality of thin-film resistive layers 30A provided in an insulator 22.

[0064] The resistive layer 30 is disposed on the third insulating layer 25. The resistive layer 30 is in contact with the upper surface of the third insulating layer 25. The resistive layer 30 is covered with the fourth insulating layer . The resistive layer 30 is made of a resistive material having a desired resistivity. For example, the resistive layer 30 may be made of a resistive material having a resistivity higher than that of polysilicon. The resistive layer 30 is made of a material containing Cr (chromium) and Si. The resistive layer 30 may be made of a material containing one of CrSi, CrSiC, and CrSiN. The resistive layer 30 may also be made of a material other than a material containing Cr and Si. For example, the resistive layer 30 may be made of a material containing at least one of TaN and TiN.

[0065] The first electrode 41 and the second electrode 42 are disposed on the fifth insulating layer 27. The first electrode 41 and the second electrode 42 are in contact with the first surface 22S of the insulator 22, which is formed by the upper surface of the fifth insulating layer 27. It can be said that the first electrode 41 and the second electrode 42 are disposed on the insulator 22. It can be said that the first electrode 41 and the second electrode 42 are disposed on the first surface 22S of the insulator 22. Note that the first detection electrode 43A, the reference electrode 43B, and the second detection electrode 43C shown in FIG. 6 are disposed on the fifth insulating layer 27, similar to the first electrode 41 and the second electrode 42.

[0066] The first electrode 41 and the second electrode 42 may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W. In one example, the first electrode 41 and the second electrode 42 are made of a material containing Al and Cu. The first electrode 41 and the second electrode 42 may be made of multiple metal layers.

[0067] The resistor chip 10 includes a resistor connection portion 45 that connects the first electrode 41 and the second electrode 42 to the resistor layer 30. The resistor connection portion 45 is disposed within the insulator 22. The resistor connection portion 45 includes a connection wiring 45A and connection vias 45B and 45C.

[0068] The connection wiring 45A is disposed on the first insulating layer 23. The connection wiring 45A is in contact with the upper surface of the first insulating layer 23. The connection wiring 45A is covered with the second insulating layer 24. The connection wiring 45A may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W. The connection wiring 45A may be made of multiple metal layers.

[0069] The connection between the first electrode 41 and the resistance layer 30 by the resistance connection portion 45 will be described. A first end 45A1 of the connection wiring 45A is disposed so as to overlap the first electrode 41 in a plan view. The first connection via 45B penetrates the second to fifth insulating layers 24 to 27 between the first electrode 41 and the connection wiring 45A. The first end 45A1 of the connection wiring 45A is electrically connected to the first electrode 41 by the first connection via 45B. A second end 45A2 of the connection wiring 45A is disposed so as to overlap the resistive layer 30 in a plan view. The second connection via 45C penetrates the second insulating layer 24 and the third insulating layer 25 between the resistive layer 30 and the connection wiring 45A. The second end 45A2 of the connection wiring 45A is electrically connected to the resistive layer 30 by the second connection via 45C. The first connection via 45B and the second connection via 45C may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W.

[0070] Similar to the first electrode 41 , the second electrode 42 is electrically connected to the resistance layer 30 by a resistance connection portion 45 . 7 shows resistive layer 30. Resistive layer 30 includes a plurality of thin-film resistive layers 30A, as shown in FIG. 6. The plurality of thin-film resistive layers 30A are connected in series between first electrode 41 and second electrode 42 by resistive connectors 45. Furthermore, predetermined thin-film resistive layers 30A among the plurality of thin-film resistive layers 30A are electrically connected by resistive connectors 45 to first detection electrode 43A, reference electrode 43B, and second detection electrode 43C shown in FIG. 6.

[0071] The annular conductor 46 may include a peripheral wiring 46A, a peripheral via conductor 46B, and a peripheral resistive film 46C. The peripheral wiring 46A is disposed on the first insulating layer 23. The peripheral wiring 46A is in contact with the upper surface of the first insulating layer 23. The peripheral wiring 46A is covered with the second insulating layer 24. The peripheral wiring 46A may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W. The peripheral wiring 46A may be made of multiple metal layers. The peripheral wiring 46A may be made of the same material as the connection wiring 45A, or may be made of a different material.

[0072] The peripheral resistive film 46C is disposed on the third insulating layer 25. The peripheral resistive film 46C is in contact with the upper surface of the third insulating layer 25. The peripheral resistive film 46C is disposed at a position overlapping the peripheral wiring 46A in plan view. The peripheral resistive film 46C may have a continuous annular shape or an intermittent annular shape in plan view. The peripheral resistive film 46C is covered by the fourth insulating layer 26. The peripheral resistive film 46C may be made of a material containing at least one of CrSi, CrSiC, CrSiN, TaN, and TiN. The peripheral resistive film 46C may be made of the same material as the resistive layer 30, or may be made of a different material.

[0073] The peripheral via conductor 46B is provided between the peripheral wiring 46A and the peripheral resistive film 46C. The peripheral via conductor 46B penetrates the second insulating layer 24 and the third insulating layer 25. The peripheral via conductor 46B electrically connects the peripheral wiring 46A and the peripheral resistive film 46C. The peripheral via conductor 46B may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W. The peripheral via conductor 46B may be made of the same material as the connection vias 45B and 45C, or may be made of a different material.

[0074] The resistor chip 10 may include a passivation film 28 disposed on the fifth insulating layer 27. The passivation film 28 includes a plurality of openings 28X. The plurality of openings 28X includes openings that expose portions of the first electrode 41 and the second electrode 42. The plurality of openings 28X also includes openings that expose portions of the first detection electrode 43A, the reference electrode 43B, and the second detection electrode 43C shown in FIG. 6 .

[0075] The passivation film 28 may include a first passivation film 28A and a second passivation film 28B. The first passivation film 28A is disposed on the fifth insulating layer 27, and the second passivation film 28B is disposed on the first passivation film 28A.

[0076] The first passivation film 28A and the second passivation film 28B may be made of a material containing Si. For example, the first passivation film 28A is made of a material containing SiO2. For example, the second passivation film 28B is made of a material containing SiN.

[0077] The resistor chip 10 may include a resin film 29 disposed on the passivation film 28. The resin film 29 is made of a material containing, for example, polyimide (PI). The resin film 29 includes a plurality of openings 29X. The plurality of openings 29X includes openings that expose parts of the first electrode 41 and the second electrode 42 and a part of the passivation film 28. The plurality of openings 29X also includes openings that expose parts of the first detection electrode 43A, the reference electrode 43B, and the second detection electrode 43C shown in FIG. 6 and a part of the passivation film 28.

[0078] (Function of the semiconductor package of the first embodiment) The semiconductor package 100 includes a resistor chip 10, a mounting member 110, a sealing resin 160, a first lead 121, and a second lead 122. The resistor chip 10 includes a first element surface 11 on which a plurality of electrodes 40 including a first electrode 41 and a second electrode 42 are provided, and a second element surface 12 opposite the first element surface 11. The resistor chip 10 is mounted on the mounting surface 111 of the mounting member 110. The sealing resin 160 seals the resistor chip 10 mounted on the mounting surface 111. The resistor chip 10 includes a chip substrate 21, an insulator 22, and a resistive layer 30. The chip substrate 21 includes a first substrate surface 21S and a second substrate surface 21R opposite the first substrate surface 21S and constituting the second element surface 12. The insulator 22 is provided on the first substrate surface 21S. The resistive layer 30 is provided within the insulator 22. The resistive layer 30 is connected between the first electrode 41 and the second electrode 42. The resistive chip 10 is mounted on the mounting surface 111 with the first element surface 11 and the mounting surface 111 facing each other in the thickness direction of the resistive chip 10.

[0079] Therefore, the mounting member 110 does not require a die pad or the like for mounting the resistor chip 10. This eliminates the need to provide a die pad or to provide other members at a distance from the die pad, increasing the degree of freedom in arrangement within the semiconductor package 100. As a result, the semiconductor package 100 can be made smaller.

[0080] For example, in a case where the chip substrate 21 is mounted on a die pad or the like, it is necessary to increase the distance between the resistive layer 30 and the chip substrate 21 depending on the rating of the resistor chip 10, i.e., the rating of the semiconductor package 100. On the other hand, in the semiconductor package of the first embodiment, the resistor chip 10 is mounted on the mounting surface 111 with the first element surface 11 and the mounting surface 111 facing each other in the thickness direction of the resistor chip 10. In other words, the chip substrate 21 is in a floating state. This makes it possible to prevent the distance between the resistive layer 30 and the chip substrate 21 from affecting the rating of the resistor chip 10 and the rating of the semiconductor package 100.

[0081] The resistor chip 10 is mounted on the mounting surface 111 with the first element surface 11 and the mounting surface 111 facing each other in the thickness direction of the resistor chip 10. Therefore, the sealing resin 160 does not require space for wires or the like for connecting the resistor chip 10 to the mounting member 110, and the semiconductor package 100 can be made smaller.

[0082] The mounting member 110 includes a first lead 121 and a second lead 122 to which the resistor chip 10 is connected, and a third lead 126 to which the amplifier chip 60 is connected. The first lead 121, the second lead 122, and the third lead 126 are formed as a metal plate made of the material of each lead 121, 122, and 126, for example, as a lead frame. The semiconductor package 100 is mounted on a circuit board or the like by each lead 121, 122, and 126. In this way, the semiconductor package 100 can be easily mounted.

[0083] The semiconductor package 100 includes an amplifier chip 60 connected to the resistor chip 10. Therefore, there is no need to separately mount the amplifier chip 60, and the number of steps required for mounting and the area required on the circuit board or the like can be reduced.

[0084] Similar to the resistor chip 10, the amplifier chip 60 is mounted with the electrodes 70 of the amplifier chip 60 facing the mounting member 110. Therefore, the semiconductor package 100 including the amplifier chip 60 can be made smaller.

[0085] (Effects of the first embodiment) As described above, the semiconductor package 100 of the first embodiment provides the following advantages.

[0086] (1-1) The semiconductor package 100 includes a resistor chip 10, a mounting member 110, a sealing resin 160, a first lead 121, and a second lead 122. The resistor chip 10 includes a first element surface 11 on which a plurality of electrodes 40 including a first electrode 41 and a second electrode 42 are provided, and a second element surface 12 opposite the first element surface 11. The resistor chip 10 is mounted on the mounting surface 111 of the mounting member 110. The sealing resin 160 seals the resistor chip 10 mounted on the mounting surface 111. The resistor chip 10 includes a chip substrate 21, an insulator 22, and a resistive layer 30. The chip substrate 21 includes a first substrate surface 21S and a second substrate surface 21R opposite the first substrate surface 21S and constituting the second element surface 12. The insulator 22 is provided on the first substrate surface 21S. The resistive layer 30 is provided within the insulator 22. The resistive layer 30 is connected between a first electrode 41 and a second electrode 42. The resistive chip 10 is mounted on the mounting surface 111 with the first element surface 11 and the mounting surface 111 facing each other in the thickness direction of the resistive chip 10.

[0087] Therefore, the mounting member 110 does not require a die pad or the like for mounting the resistor chip 10. This eliminates the need to provide a die pad or to provide other members at a distance from the die pad, increasing the degree of freedom in arrangement within the semiconductor package 100. As a result, the semiconductor package 100 can be made smaller.

[0088] (1-2) In the semiconductor package, the resistor chip 10 is mounted on the mounting surface 111 with the first element surface 11 and the mounting surface 111 facing each other in the thickness direction of the resistor chip 10. In other words, the chip substrate 21 is in a floating state. This makes it possible to prevent the distance between the resistive layer 30 and the chip substrate 21 from affecting the rating of the resistor chip 10 and the rating of the semiconductor package 100.

[0089] (1-3) The resistor chip 10 is mounted on the mounting surface 111 with the first element surface 11 and the mounting surface 111 facing each other in the thickness direction of the resistor chip 10. Therefore, the sealing resin 160 does not require space for wires or the like for connecting the resistor chip 10 to the mounting member 110, and the semiconductor package 100 can be made smaller.

[0090] (1-4) The mounting member 110 includes a first lead 121 and a second lead 122 to which the resistor chip 10 is connected, and a third lead 126 to which the amplifier chip 60 is connected. The first lead 121, the second lead 122, and the third lead 126 are formed as, for example, a lead frame, as a metal plate made of the material of each lead 121, 122, and 126. The semiconductor package 100 is mounted on a circuit board or the like by each lead 121, 122, and 126. In this way, the semiconductor package 100 can be easily mounted.

[0091] (1-5) The semiconductor package 100 includes an amplifier chip 60 connected to the resistor chip 10. This eliminates the need to separately mount the amplifier chip 60, reducing the number of steps required for mounting and the area required on the circuit board, etc.

[0092] (1-6) Like the resistor chip 10, the amplifier chip 60 is mounted with the electrodes 70 of the amplifier chip 60 facing the mounting member 110. Therefore, the semiconductor package 100 including the amplifier chip 60 can be made smaller.

[0093] (Modification of the first embodiment) The first embodiment can be modified, for example, as follows: The first embodiment can be combined with the following modifications as long as no technical contradiction occurs. In the following modifications, parts common to the first embodiment will be assigned the same reference numerals as in the first embodiment, and their description will be omitted.

[0094] FIG. 8 shows a semiconductor package 100A of a modified example. FIG. 8 shows a schematic cross-sectional structure corresponding to FIG. 3 showing the semiconductor package 100 of the first embodiment. A mounting member 110A of the semiconductor package 100A includes a plurality of leads 130. The plurality of leads 130 include a first lead 131, a second lead 132, a third lead 133, and an intermediate lead 134. Note that in FIG. 8, the second lead 132 is shown in parentheses together with the first lead 131. The second lead 132 has the same configuration as the first lead 131. The first lead 131, the second lead 132, and the third lead 133 of the modified example do not protrude from the sealing resin 160.

[0095] The first lead 131 and the third lead 133 may include a wiring portion 135 and a terminal portion 136. The wiring portion 135 of the first lead 131 extends from a portion overlapping with the resistor chip 10 to a third sealing side surface 165 in a plan view. The wiring portion 135 of the third lead 133 extends from a portion overlapping with the amplifier chip 60 to a fourth sealing side surface 166 in a plan view.

[0096] The terminal portion 136 extends from the wiring portion 135 to the second surface 162 of the sealing resin 160. The terminal portion 136 is exposed on the second surface 162 and the sealing side surface 166 of the sealing resin 160. The wiring portion 135 and the terminal portion 136 may be an integrally formed unit.

[0097] The resistor chip 10 is mounted on the wiring portion 135 of the first lead 131. The amplifier chip 60 is mounted on the wiring portion 135 of the third lead 133. The resistor chip 10 and the amplifier chip 60 are mounted on the intermediate lead 134. The intermediate lead 134 electrically connects the resistor chip 10 and the amplifier chip 60. In the Z-axis direction, the thickness of the wiring portion 135 may be thinner than the thickness of the terminal portion 136. The intermediate lead 134 may have the same thickness as the wiring portion 135.

[0098] The first lead 131, the third lead 133, and the intermediate lead 134 may be formed, for example, by partially removing, for example, by etching, a plate-like member made of the material of the first lead 131, the third lead 133, and the intermediate lead 134. This makes it possible to easily form the mounting member 110A including the first lead 131, the third lead 133, and the intermediate lead 134.

[0099] Furthermore, the semiconductor package 100A of the modified example may include an external conductive film 140 that covers the surfaces of the leads 130 exposed from the sealing resin 160. In the modified example shown in FIG. 8, the external conductive film 140 covers the surfaces of the first lead 131 and the third lead 133. The external conductive film 140 may cover the surfaces of the wiring portion 135 and the terminal portion 136 exposed from the sealing resin 160. The external conductive film 140 may be composed of, for example, a metal layer. The metal layer may be composed of, for example, at least one of a Ni layer, a Pd layer, and an Au layer.

[0100] The first lead 131 is exposed on the second surface 162 and the sealing side surface 165 of the sealing resin 160. The third lead 133 is exposed on the second surface 162 and the sealing side surface 166 of the sealing resin 160. The surfaces exposed on the second surface 162 and the sealing side surfaces 165, 166 are surfaces to which a joining material such as solder is attached for mounting the semiconductor package 100A of this modified example to a mounting substrate. This allows the semiconductor package 100A to be firmly mounted to the mounting substrate. In the semiconductor package 100A of this modified example, the first lead 131 and the third lead 133 do not protrude from the sealing side surfaces 165, 166 of the sealing resin 160, thereby allowing the semiconductor package 100A to be made smaller. Furthermore, the area occupied by the semiconductor package 100A on the mounting substrate is small.

[0101] Fig. 9 shows a semiconductor package 100B according to a modified example, and shows a schematic cross-sectional structure corresponding to Fig. 3 showing the semiconductor package 100 according to the first embodiment. The semiconductor package 100B of the modified example shown in Fig. 9 differs from the semiconductor package 100A of the modified example shown in Fig. 8 in the position of the terminal portion 136. The terminal portion 136 is arranged from sealing side surfaces 165, 166 of the sealing resin 160 toward the inside of the semiconductor package 100B and spaced apart from the sealing side surfaces 165, 166. In the semiconductor package 100B of the modified example shown in Fig. 9, the terminal portion 136 is not exposed from the sealing side surfaces 165, 166. The semiconductor package 100B of this modified example also achieves the same effects as the semiconductor package 100A of the modified example shown in Fig. 8.

[0102] (Second embodiment) A semiconductor package 200 according to the second embodiment will be described with reference to Figures 10 to 12. Below, the second embodiment will be described, focusing on the differences from the semiconductor package 100 according to the first embodiment, and components common to the first embodiment will be assigned the same reference numerals and detailed description thereof will be omitted.

[0103] Fig. 10 shows an example of a semiconductor package according to the second embodiment. Fig. 11 shows an example of a cross-sectional structure of the semiconductor package 200 of Fig. 10, illustrating the resistor chip 10 and the mounting member 210. Fig. 12 shows an example of a cross-sectional structure of the semiconductor package 200 of Fig. 10, illustrating the connection between the resistor chip 10 and the amplifier chip 60.

[0104] The semiconductor package 200 of the second embodiment differs from the semiconductor package 100 of the first embodiment in the configuration of the mounting member 210. The semiconductor package 200 includes a mounting member 210 and a sealing resin 260 disposed on the mounting member 210 .

[0105] (insulating substrate) The mounting member 210 includes an insulating substrate 220 . The insulating substrate 220 is formed of, for example, an insulating material. The insulating material may be, for example, a material containing epoxy resin. The insulating substrate 220 may be formed of a resin material containing filler. For example, the insulating substrate 220 may be formed of a glass epoxy resin. The insulating material may also be formed of, for example, a material containing ceramic. Examples of materials containing ceramic include aluminum nitride (AlN) and alumina (Al2O3). The insulating substrate 220 may also be formed of a plurality of materials. The insulating substrate 220 may also be formed of a laminated plate including a metal plate such as Cu as a core and an insulating material such as resin covering the metal plate.

[0106] Insulating substrate 220 includes mounting surface 221 and back surface 222 opposite mounting surface 221. Insulating substrate 220 includes substrate side surfaces 223, 224, 225, and 226 connecting mounting surface 221 and back surface 222.

[0107] (wiring components) The mounting member 210 includes a plurality of wiring members 230 . The plurality of wiring members 230 include a first wiring member 231 and a second wiring member 232.

[0108] (First wiring member, second wiring member) The first wiring member 231 and the second wiring member 232 may include a wiring portion 233, a through wiring portion 234, and a back surface electrode 235. The wiring portion 233 corresponds to the first wiring portion. The back surface electrode 235 corresponds to the second wiring portion. The back surface electrode 235 of the first wiring member 231 corresponds to the "first external terminal." The back surface electrode 235 of the second wiring member 232 corresponds to the "second external terminal."

[0109] The wiring portion 233 is provided on the insulating substrate 220. The wiring portion 233 includes a connection surface 233A and a bottom surface 233B opposite to the connection surface 233A. The bottom surface 233B of the wiring portion 233 is in contact with the mounting surface 221 of the insulating substrate 220. In one example, the wiring portion 233 extends in the Y-axis direction from a position overlapping with the resistor chip 10 in a plan view to a position not overlapping with the resistor chip 10. The wiring portion 233 is made of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0110] The through wiring portion 234 penetrates the insulating substrate 220. The insulating substrate 220 includes a through hole 227 that penetrates the insulating substrate 220 from the mounting surface 221 to the back surface 222. The through hole 227 may be called a via hole. The through wiring portion 234 is disposed in the through hole 227 of the insulating substrate 220. The through wiring portion 234 extends within the insulating substrate 220 from the mounting surface 221 of the insulating substrate 220 to the back surface 222 of the insulating substrate 220. The through wiring portion 234 may be formed of a metal member filled in the through hole 227. The through wiring portion 234 may be formed of a cylindrical metal member that covers the inner surface of the through hole 227. In the case of a cylindrical metal member, the inside may be filled with a resin or the like.

[0111] In one example, the through wiring portion 234 is arranged at a position that overlaps with the wiring portion 233 but does not overlap with the resistor chip 10 in a planar view. The through wiring portion 234 may be arranged at a position that overlaps with the resistor chip 10 in a planar view. The through wiring portion 234 is electrically connected to the wiring portion 233. The through wiring portion 234 is made of a material containing at least one of Cu, Al, Ag, Au, Ni, and Ti.

[0112] The back surface electrode 235 is provided on the back surface 222 of the insulating substrate 220. The back surface electrode 235 is disposed at a position overlapping the through wiring portion 234 in a plan view. The back surface electrode 235 is electrically connected to the through wiring portion 234. The back surface electrode 235 is made of a material containing at least one of Cu, Al, Ag, Au, Ni, and Ti.

[0113] (Intermediate wiring) The plurality of wiring members 230 may include a plurality of intermediate wirings 236 . The intermediate wiring 236 is provided on the insulating substrate 220. The intermediate wiring 236 is in contact with the mounting surface 221 of the insulating substrate 220. The intermediate wiring 236 includes a connection surface 236A and a side surface 236B that intersects with the connection surface 236A. The connection surface 236A and the side surface 236B of the intermediate wiring 236 are covered with a sealing resin 260. In one example, the intermediate wiring 236 extends, in a plan view, from a position overlapping with the resistor chip 10 along the X-axis direction to a position overlapping with the amplifier chip 60. The intermediate wiring 236 is made of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0114] (Third wiring member) The plurality of wiring members 230 may include a third wiring member 237. The third wiring member 237 may include a wiring portion 238 , a through wiring portion 239 , and a back surface electrode 240 .

[0115] The wiring portion 238 is provided on the insulating substrate 220. The wiring portion 238 includes a connection surface 238A and a bottom surface 238B opposite to the connection surface 238A. The bottom surface 238B of the wiring portion 238 is in contact with the mounting surface 221 of the insulating substrate 220. In one example, the wiring portion 238 extends in the Y-axis direction from a position overlapping with the amplifier chip 60 in a plan view to a position not overlapping with the amplifier chip 60. The wiring portion 238 is made of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0116] The through wiring portion 239 penetrates the insulating substrate 220. The through wiring portion 239 is disposed in a through hole 227 of the insulating substrate 220. The through wiring portion 239 extends within the insulating substrate 220 from the mounting surface 221 of the insulating substrate 220 to the back surface 222 of the insulating substrate 220. The through wiring portion 239 may be made of a metal member filled in the through hole 227. The through wiring portion 239 may be made of a cylindrical metal member that covers the inner surface of the through hole 227. In the case of a cylindrical metal member, the inside may be filled with a resin or the like.

[0117] In one example, the through wiring portion 239 is arranged at a position that overlaps with the wiring portion 238 in a plan view but does not overlap with the amplifier chip 60. The through wiring portion 239 may be arranged at a position that overlaps with the amplifier chip 60 in a plan view. The through wiring portion 239 is electrically connected to the wiring portion 238. The through wiring portion 239 is made of a material that includes at least one of Cu, Al, Ag, Au, Ni, and Ti.

[0118] The back surface electrode 240 is provided on the back surface 222 of the insulating substrate 220. The back surface electrode 240 is arranged at a position overlapping the through wiring portion 239 in a plan view. The back surface electrode 240 is electrically connected to the through wiring portion 239. The back surface electrode 240 is made of a material containing at least one of Cu, Al, Ag, Au, Ni, and Ti. The back surface electrode 240 corresponds to a "third external electrode."

[0119] (Resistor chip mounting format) The resistor chip 10 is mounted on a mounting member 210. More specifically, the resistor chip 10 is mounted on a first wiring member 231, a second wiring member 232, and an intermediate wiring 236. It can be said that the resistor chip 10 is flip-chip mounted on the mounting member 210. A first electrode 41 of the resistor chip 10 is electrically connected to the first wiring member 231 by a connection member 50 (51). A second electrode 42 of the resistor chip 10 is electrically connected to the second wiring member 232 by a connection member 50 (52). A third electrode 43 of the resistor chip 10 is electrically connected to the intermediate wiring 236 by a connection member 50 (53).

[0120] (Amplifier chip implementation) The amplifier chip 60 is mounted on a mounting member 210. More specifically, the amplifier chip 60 is mounted on an intermediate wiring 236 and a third wiring member 237. It can be said that the amplifier chip 60 is flip-chip mounted on the mounting member 210. A first electrode 71 of the amplifier chip 60 is electrically connected to the intermediate wiring 236 by a connection member 80 (81). A second electrode 72 of the amplifier chip 60 is electrically connected to the third wiring member 237 by a connection member 80 (82).

[0121] (Sealing resin) The sealing resin 260 is provided on the insulating substrate 220. The sealing resin 260 covers the mounting surface 221 of the insulating substrate 220.

[0122] The sealing resin 260 includes a first sealing surface 261 and a second sealing surface 262 opposite to the first sealing surface 261. The first sealing surface 261 of the sealing resin 260 contacts the mounting surface 221 of the insulating substrate 220. The sealing resin 260 includes sealing side surfaces 263 to 266 that connect the first sealing surface 261 and the second sealing surface 262.

[0123] In one example, the sealing resin 260 has the same size as the insulating substrate 220 in a plan view. First to fourth sealing side surfaces 263 to 266 of the sealing resin 260 may be flush with the first to fourth substrate side surfaces 223 to 226 of the insulating substrate 220, respectively.

[0124] (jointing material) The semiconductor package 200 may include a bonding member 242 connected to the back electrodes 235, 240. In one example, the bonding member 242 has a spherical shape. The bonding member 242 may be made of a material containing SnAg. The spherical bonding member 242 may be called a solder ball. The bonding member 242 may include a spherical core and a solder layer covering the surface of the core. The core may be made of a conductive metal material, an insulating resin material, or the like. The bonding member 242 connected to the back electrode 235 of the first wiring member 231 corresponds to the "first bonding member." The bonding member 242 connected to the back electrode 235 of the second wiring member 232 corresponds to the "second bonding member." The bonding member 242 connected to the back electrode 240 of the third wiring member 237 corresponds to the "third bonding member."

[0125] (Effects of the second embodiment) As described above, the semiconductor package 200 of the second embodiment provides the following advantages.

[0126] (2-1) The same effects as those of the semiconductor package 100 of the first embodiment are achieved. (2-2) The mounting member 210 includes an insulating substrate 220. This insulating substrate 220 allows the semiconductor package 200 to be easily mounted.

[0127] (2-3) In plan view, the insulating substrate 220 and the sealing resin 260 have the same size. Therefore, the area required for mounting the semiconductor package 200 can be reduced. (Third embodiment) A semiconductor package 300 according to the third embodiment will be described with reference to Figures 13 and 14. The following description of the second embodiment will focus on the differences from the first and second embodiments, and components common to the first and second embodiments will be denoted by the same reference numerals and detailed description thereof will be omitted.

[0128] Fig. 13 shows an example of a semiconductor package according to the third embodiment. Fig. 14 shows an example of a cross-sectional structure of the semiconductor package 300 of Fig. 13, illustrating the connection between the resistor chip 10 and the amplifier chip 60.

[0129] The semiconductor package 300 of the third embodiment differs from the semiconductor package 200 of the second embodiment in the configuration of the mounting member 310. The semiconductor package 300 includes a mounting member 310 and a sealing resin 260 disposed on the mounting member 310 .

[0130] (insulating substrate) The mounting member 310 includes an insulating substrate 320 . Insulating substrate 320 includes mounting surface 321 and back surface 322 opposite mounting surface 321. Insulating substrate 320 includes substrate side surfaces 323, 324, 325, and 326 connecting mounting surface 321 and back surface 322.

[0131] The insulating substrate 320 is formed of, for example, an insulating material. The insulating material may be, for example, a material containing epoxy resin. The insulating substrate 320 may be formed of a resin material containing a filler. The filler may be, for example, SiO2. The insulating substrate 320 may be colored, for example, black. Cutting marks may be formed on the surfaces of the insulating substrate 320, i.e., the mounting surface 321, the back surface 322, and the substrate side surfaces 323 to 326. The filler may be exposed on the surfaces of the insulating substrate 320, i.e., the mounting surface 321, the back surface 322, and the substrate side surfaces 323 to 326.

[0132] (wiring components) The mounting member 310 includes a plurality of wiring members 330. The plurality of wiring members 330 includes a first wiring member 331 and a second wiring member 332. The plurality of wiring members 330 corresponds to "a plurality of wiring layers."

[0133] (First wiring member, second wiring member) The first wiring member 331 and the second wiring member 332 may include a wiring layer 333 and a through wiring 334. The wiring layer 333 of the first wiring member 331 corresponds to the "first wiring layer." The wiring layer 333 of the second wiring member 332 corresponds to the "second wiring layer."

[0134] The wiring layer 333 is provided on the insulating substrate 320. The wiring layer 333 includes a connection surface 333A and a bottom surface 333B opposite to the connection surface 333A. The bottom surface 333B of the wiring layer 333 is in contact with the mounting surface 321 of the insulating substrate 320. The wiring layer 333 includes a side surface 333C connecting the connection surface 333A and the bottom surface 333B. The side surface 333C of the wiring layer 333 is in contact with the sealing resin 260.

[0135] In one example, the wiring layer 333 extends in the Y-axis direction from a position overlapping the resistor chip 10 in a plan view to a position not overlapping the resistor chip 10. The wiring layer 333 is made of a material containing at least one of Cu and Ti, for example. The wiring layer 333 may be made of multiple metal layers. In one example, the wiring layer 333 may be made of a first metal layer disposed on the mounting surface 321 of the insulating substrate 320 and a second metal layer disposed on the first metal layer. The first metal layer may be made of a first layer made of a material mainly containing Ti, for example, and a second layer made mainly of Cu. The second metal layer may be made of a material mainly containing Cu.

[0136] The through wiring 334 penetrates the insulating substrate 320. The through wiring 334 extends within the insulating substrate 320 from the mounting surface 321 of the insulating substrate 320 to the back surface 322 of the insulating substrate 320. The insulating substrate 320 includes a through hole 327 that penetrates the insulating substrate 320 from the mounting surface 321 to the back surface 322. The through wiring 334 is arranged in the through hole 327. In one example, the through wiring 334 is arranged at a position that overlaps the wiring layer 333 but does not overlap the resistor chip 10 in a plan view. The through wiring 334 includes an upper surface 334A and a lower surface 334B. The through wiring 334 includes a side surface 334C that connects the upper surface 334A and the lower surface 334B. The side surface 334C of the through wiring 334 is in contact with the inner wall surface of the through hole 327. An upper surface 334A of the through wiring 334 is electrically connected to the wiring layer 333. A lower surface 334B of the through wiring 334 is exposed from the rear surface 322 of the insulating substrate 320. The through wiring 334 of the first wiring member 331 corresponds to a "first external terminal." The through wiring 334 of the second wiring member 332 corresponds to a "second external terminal." The lower surface 334B of the through wiring 334 corresponds to an "exposed surface." The through wiring 334 may be made of a material containing Cu.

[0137] (Intermediate wiring) The plurality of wiring members 330 may include a plurality of intermediate wirings 336 . The intermediate wiring 336 is provided on the insulating substrate 320. The intermediate wiring 336 is in contact with the mounting surface 321 of the insulating substrate 320. The intermediate wiring 336 includes a connection surface 336A and a side surface 336B intersecting with the connection surface 336A. The connection surface 336A and the side surface 336B of the intermediate wiring 336 are covered with a sealing resin 260. In one example, the intermediate wiring 336 extends, in a plan view, from a position overlapping with the resistor chip 10 along the X-axis direction to a position overlapping with the amplifier chip 60. The intermediate wiring 336 is made of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0138] (Third wiring member) The plurality of wiring members 330 may include a third wiring member 337. The third wiring member 337 may include a wiring layer 338 and a through-wire 339. The wiring layer 338 of the third wiring member 337 corresponds to the "third wiring layer."

[0139] The wiring layer 338 is provided on the insulating substrate 320. The wiring layer 338 includes a connection surface 338A and a bottom surface 338B opposite to the connection surface 338A. The bottom surface 338B of the wiring layer 338 contacts the mounting surface 321 of the insulating substrate 320. The wiring layer 338 includes a side surface 338C connecting the connection surface 338A and the bottom surface 338B. The side surface 338C of the wiring layer 338 contacts the sealing resin 260.

[0140] In one example, the wiring layer 338 extends in the Y-axis direction from a position overlapping with the amplifier chip 60 in a plan view to a position not overlapping with the amplifier chip 60. The wiring layer 338 is made of a material containing at least one of Cu and Ti, for example. The wiring layer 338 may be made of multiple metal layers. In one example, the wiring layer 338 may be made of a first metal layer disposed on the mounting surface 321 of the insulating substrate 320 and a second metal layer disposed on the first metal layer. The first metal layer may be made of a first layer made of a material mainly containing Ti, for example, and a second layer mainly containing Cu. The second metal layer may be made of a material mainly containing Cu.

[0141] The through wiring 339 penetrates the insulating substrate 320. The through wiring 339 extends within the insulating substrate 320 from the mounting surface 321 of the insulating substrate 320 to the back surface 322 of the insulating substrate 320. The insulating substrate 320 includes a through hole 327 that penetrates the insulating substrate 320 from the mounting surface 321 to the back surface 322. The through wiring 339 is arranged in the through hole 327. In one example, the through wiring 339 is arranged at a position that overlaps the wiring layer 338 but does not overlap the resistor chip 10 in a plan view. The through wiring 339 includes an upper surface 339A and a lower surface 339B. The through wiring 339 includes a side surface 339C that connects the upper surface 339A and the lower surface 339B. The side surface 339C of the through wiring 339 contacts the inner wall surface of the through hole 327. An upper surface 339A of the through wiring 339 is electrically connected to the wiring layer 338. A lower surface 339B of the through wiring 339 is exposed from the rear surface 322 of the insulating substrate 320. The through wiring 339 may be made of a material containing Cu. The through wiring 339 of the third wiring member 337 corresponds to a "third external terminal." The lower surface 339B of the through wiring 339 corresponds to an "exposed surface."

[0142] (Resistor chip mounting format) The resistor chip 10 is mounted on a mounting member 310. More specifically, the resistor chip 10 is mounted on a first wiring member 331, a second wiring member 332, and an intermediate wiring 336. It can be said that the resistor chip 10 is flip-chip mounted on the mounting member 310. A first electrode 41 of the resistor chip 10 is electrically connected to the first wiring member 331 by a connection member 50 (51). A second electrode 42 of the resistor chip 10 is electrically connected to the second wiring member 332 by a connection member 50 (52). A third electrode 43 of the resistor chip 10 is electrically connected to the intermediate wiring 336 by a connection member 50 (53).

[0143] (Amplifier chip implementation) The amplifier chip 60 is mounted on a mounting member 310. More specifically, the amplifier chip 60 is mounted on an intermediate wiring 336 and a third wiring member 337. It can be said that the amplifier chip 60 is flip-chip mounted on the mounting member 310. A first electrode 71 of the amplifier chip 60 is electrically connected to the intermediate wiring 336 by a connection member 80 (81). A second electrode 72 of the amplifier chip 60 is electrically connected to the third wiring member 337 by a connection member 80 (82).

[0144] (Sealing resin) The sealing resin 260 is provided on the insulating substrate 320. The sealing resin 260 covers the mounting surface 321 of the insulating substrate 320.

[0145] The sealing resin 260 includes a first sealing surface 261 and a second sealing surface 262 opposite to the first sealing surface 261. The first sealing surface 261 of the sealing resin 260 contacts the mounting surface 321 of the insulating substrate 320. The sealing resin 260 includes sealing side surfaces 263, 264, 265, and 266 that connect the first sealing surface 261 and the second sealing surface 262.

[0146] In one example, the sealing resin 260 has the same size as the insulating substrate 320 in a plan view. First to fourth sealing side surfaces 263 to 266 of the sealing resin 260 may be flush with the first to fourth substrate side surfaces 323 to 326 of the insulating substrate 320, respectively.

[0147] (jointing material) The semiconductor package 300 may include bonding members 342 connected to the lower surfaces 334B, 339B of the through wirings 334, 339. In one example, the bonding members 342 have a spherical shape. The bonding members 342 may be made of a material containing SnAg. The spherical bonding members 342 may be referred to as solder balls. The bonding members 342 may include a spherical core and a solder layer covering the surface of the core. The core may be made of a conductive metal material, an insulating resin material, or the like. The bonding members 342 connected to the through wirings 334 of the first wiring member 331 correspond to the "first bonding member." The bonding members 342 connected to the through wirings 334 of the second wiring member 332 correspond to the "second bonding member." The bonding members 342 connected to the through wirings 339 of the third wiring member 337 correspond to the "third bonding member."

[0148] (Effects of the third embodiment) As described above, the semiconductor package 300 of the third embodiment provides the same effects as the second embodiment.

[0149] (Fourth embodiment) A semiconductor package 400 according to the fourth embodiment will be described with reference to Figures 15 and 16. Below, the second embodiment will be described, focusing on the differences from the first to third embodiments, and components common to the first to third embodiments will be assigned the same reference numerals and detailed description thereof will be omitted.

[0150] Fig. 15 shows an example of a semiconductor package according to the fourth embodiment. Fig. 16 shows an example of a cross-sectional structure of the semiconductor package 400 of Fig. 15, illustrating the connection between the resistor chip 10 and the amplifier chip 60.

[0151] The semiconductor package 400 of the fourth embodiment differs from the semiconductor package 200 of the second embodiment in the configuration of the mounting member 410. The semiconductor package 400 includes a mounting member 410 and a sealing resin 260 disposed on the mounting member 410 .

[0152] (insulating substrate) The mounting member 410 includes an insulating substrate 420 . Insulating substrate 420 includes mounting surface 421 and back surface 422 opposite mounting surface 421. Insulating substrate 420 includes substrate side surfaces 423, 424, 425, and 426 connecting mounting surface 421 and back surface 422.

[0153] Insulating substrate 420 is formed of, for example, an insulating material. The insulating material may be, for example, a material containing epoxy resin. Insulating substrate 420 may be formed of a resin material containing a filler. The filler may be, for example, SiO2. Insulating substrate 420 may be colored, for example, black. Cutting marks may be formed on mounting surface 421, back surface 422, and substrate side surfaces 423 to 426, which are the surfaces of insulating substrate 420. Filler may be exposed on mounting surface 421, back surface 422, and substrate side surfaces 423 to 426, which are the surfaces of insulating substrate 420.

[0154] (wiring components) The mounting member 410 includes a plurality of wiring members 430 . The plurality of wiring members 430 include a first wiring member 431 and a second wiring member 432.

[0155] (First wiring member, second wiring member) The first wiring member 431 and the second wiring member 432 may include a wiring layer 433 and a through-wire 434 .

[0156] The wiring layer 433 is provided on the insulating substrate 420. The wiring layer 433 includes a connection surface 433A and a bottom surface 433B opposite to the connection surface 433A. The bottom surface 433B of the wiring layer 433 contacts the mounting surface 421 of the insulating substrate 420. The wiring layer 433 includes side surfaces 433C and 433D that connect the connection surface 433A and the bottom surface 433B. The side surface 433C of the wiring layer 433 contacts the sealing resin 260. The side surface 433D of the wiring layer 433 is exposed from the sealing resin 260.

[0157] The first wiring member 431 extends from the resistor chip 10 to the first sealing side surface 263 of the sealing resin 260. A side surface 433D of the wiring layer 433 of the first wiring member 431 is exposed from the first sealing side surface 263 of the sealing resin 260. The side surface 433D of the first wiring member 431 can be said to be an exposed side surface exposed from the sealing resin 260. The second wiring member 432 extends from the resistor chip 10 to the second sealing side surface 264 of the sealing resin 260. A side surface 433D of the wiring layer 433 of the second wiring member 432 is exposed from the second sealing side surface 264 of the sealing resin 260. The side surface 433D of the second wiring member 432 can be said to be an exposed side surface exposed from the sealing resin 260.

[0158] In one example, the wiring layer 433 extends in the Y-axis direction from a position overlapping the resistor chip 10 in a plan view to a position not overlapping the resistor chip 10. The wiring layer 433 is made of a material containing at least one of Cu and Ti, for example. The wiring layer 433 may be made of multiple metal layers. In one example, the wiring layer 433 may be made of a first metal layer disposed on the mounting surface 421 of the insulating substrate 420 and a second metal layer disposed on the first metal layer. The first metal layer may be made of a first layer made of a material mainly containing Ti, for example, and a second layer made mainly of Cu. The second metal layer may be made of a material mainly containing Cu.

[0159] The through wiring 434 penetrates the insulating substrate 420. The through wiring 434 extends within the insulating substrate 420 from the mounting surface 421 of the insulating substrate 420 to the back surface 422 of the insulating substrate 420. The insulating substrate 420 includes a through hole 427 that penetrates the insulating substrate 420 from the mounting surface 421 to the back surface 422. The through wiring 434 is arranged in the through hole 427. In one example, the through wiring 434 is arranged at a position that overlaps the wiring layer 433 but does not overlap the resistor chip 10 in a plan view. The through wiring 434 includes an upper surface 434A and a lower surface 434B. The through wiring 434 includes side surfaces 434C and 434D that connect the upper surface 434A and the lower surface 434B. The upper surface 434A of the through wiring 434 is electrically connected to the wiring layer 433. The lower surface 434 B of the through wiring 434 is exposed from the rear surface 422 of the insulating substrate 420 .

[0160] A side surface 434C of the through wiring 434 contacts the inner wall surface of the through hole 427. A side surface 434D of the through wiring 434 is exposed from the sealing resin 260. The through wiring 434 of the first wiring member 431 extends to the second sealing side surface 264 of the sealing resin 260. The side surface 434D of the through wiring 434 of the first wiring member 431 is exposed from the first sealing side surface 263 of the sealing resin 260. The side surface 434D of the through wiring 434 of the first wiring member 431 can be said to be an exposed side surface exposed from the sealing resin 260. The through wiring 434 of the second wiring member 432 extends from the resistor chip 10 to the second sealing side surface 264 of the sealing resin 260. The side surface 434D of the through wiring 434 of the second wiring member 432 is exposed from the second sealing side surface 264 of the sealing resin 260. The side surface 434D of the through wiring 434 of the second wiring member 432 can be said to be an exposed side surface exposed from the sealing resin 260. The through wiring 434 may be made of a material containing Cu.

[0161] (Intermediate wiring) The plurality of wiring members 430 may include a plurality of intermediate wirings 436 . The intermediate wiring 436 is provided on the insulating substrate 420. The intermediate wiring 436 is in contact with the mounting surface 421 of the insulating substrate 420. The intermediate wiring 436 includes a connection surface 436A and a side surface 436B that intersects with the connection surface 436A. The connection surface 436A and the side surface 436B of the intermediate wiring 436 are covered with the sealing resin 260. In one example, the intermediate wiring 436 extends in the X-axis direction from a position overlapping with the resistor chip 10 to a position overlapping with the amplifier chip 60 in a plan view. The intermediate wiring 436 is made of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0162] (Third wiring member) The plurality of wiring members 430 may include a third wiring member 437. The third wiring member 437 may include a wiring layer 438 and a through wiring 439 .

[0163] The wiring layer 438 is provided on the insulating substrate 420. The wiring layer 438 includes a connection surface 438A and a bottom surface 438B opposite to the connection surface 438A. The bottom surface 438B of the wiring layer 438 contacts the mounting surface 421 of the insulating substrate 420. The wiring layer 438 includes side surfaces 438C and 438D that connect the connection surface 438A and the bottom surface 438B. The side surface 438C of the wiring layer 438 contacts the sealing resin 260.

[0164] A side surface 438D of the wiring layer 438 of the third wiring member 437 is exposed from the sealing resin 260. In one example, the wiring layer 438 of the third wiring member 437 extends to either the first sealing side surface 263 or the second sealing side surface 264 of the sealing resin 260. The side surface 438D of the wiring layer 438 is exposed from either the first sealing side surface 263 or the second sealing side surface 264 of the sealing resin 260. It can be said that the semiconductor package 400 includes the third wiring member 437 exposed from the first sealing side surface 263 and the third wiring member 437 exposed from the second sealing side surface 264. The side surface 438D of the wiring layer 438 can be said to be an exposed surface exposed from the sealing resin 260.

[0165] In one example, the wiring layer 438 extends in the Y-axis direction from a position overlapping with the amplifier chip 60 in a plan view to a position not overlapping with the amplifier chip 60. The wiring layer 438 is made of a material containing at least one of Cu and Ti, for example. The wiring layer 438 may be made of multiple metal layers. In one example, the wiring layer 438 may be made of a first metal layer disposed on the mounting surface 421 of the insulating substrate 420 and a second metal layer disposed on the first metal layer. The first metal layer may be made of a first layer made of a material mainly containing Ti, for example, and a second layer mainly containing Cu. The second metal layer may be made of a material mainly containing Cu.

[0166] The through wiring 439 penetrates the insulating substrate 420. The through wiring 439 extends within the insulating substrate 420 from the mounting surface 421 of the insulating substrate 420 to the back surface 422 of the insulating substrate 420. The insulating substrate 420 includes a through hole 427 that penetrates the insulating substrate 420 from the mounting surface 421 to the back surface 422. The through wiring 439 is arranged in the through hole 427. In one example, the through wiring 439 is arranged at a position that overlaps with the wiring layer 438 but does not overlap with the resistor chip 10 in a plan view. The through wiring 439 may be made of a material containing Cu.

[0167] The through wiring 439 includes an upper surface 439A and a lower surface 439B. The through wiring 439 includes side surfaces 439C and 439D connecting the upper surface 439A and the lower surface 439B. The upper surface 439A of the through wiring 439 is electrically connected to the wiring layer 438. The lower surface 439B of the through wiring 439 is exposed from the rear surface 422 of the insulating substrate 420. The side surface 439C of the through wiring 439 is in contact with the inner wall surface of the through hole 427. The side surface 439D of the through wiring 439 is exposed from the sealing resin 260. The through wiring 439 may be made of a material containing Cu.

[0168] A side surface 439D of the through wiring 439 is exposed from the sealing resin 260. In one example, the through wiring 439 extends to either the first sealing side surface 263 or the second sealing side surface 264 of the sealing resin 260. The side surface 439D of the through wiring 439 is exposed at either the first sealing side surface 263 or the second sealing side surface 264 of the sealing resin 260. The side surface 439D of the through wiring 439 can be said to be an exposed surface exposed from the sealing resin 260.

[0169] (Resistor chip mounting format) The resistor chip 10 is mounted on a mounting member 410. More specifically, the resistor chip 10 is mounted on a first wiring member 431, a second wiring member 432, and an intermediate wiring 436. It can be said that the resistor chip 10 is flip-chip mounted on the mounting member 410. The first electrode 41 of the resistor chip 10 is electrically connected to the first wiring member 431 by a connection member 50 (51). The second electrode 42 of the resistor chip 10 is electrically connected to the second wiring member 432 by a connection member 50 (52). The third electrode 43 of the resistor chip 10 is electrically connected to the intermediate wiring 436 by a connection member 50 (53).

[0170] (Amplifier chip implementation) The amplifier chip 60 is mounted on a mounting member 410. More specifically, the amplifier chip 60 is mounted on an intermediate wiring 436 and a third wiring member 437. It can be said that the amplifier chip 60 is flip-chip mounted on the mounting member 410. A first electrode 71 of the amplifier chip 60 is electrically connected to the intermediate wiring 436 by a connection member 80 (81). A second electrode 72 of the amplifier chip 60 is electrically connected to the third wiring member 437 by a connection member 80 (82).

[0171] (Sealing resin) The sealing resin 260 is provided on the insulating substrate 420. The sealing resin 260 covers the mounting surface 421 of the insulating substrate 420.

[0172] In one example, the sealing resin 260 has the same size as the insulating substrate 420 in a plan view. The first to fourth sealing side surfaces 263 to 266 of the sealing resin 260 may be flush with the first to fourth substrate side surfaces 423 to 426 of the insulating substrate 420, respectively.

[0173] (external conductive film) The semiconductor package 400 may include an external conductive film 442. The external conductive film 442 covers the mounting member 410 exposed from the insulating substrate 420 and the sealing resin 260. In one example, the external conductive film 442 covers the side surfaces 433D and 438D of the wiring layers 433 and 438 and the lower surfaces 434B and 439B and side surfaces 434D and 439D of the through-wires 434 and 439. The external conductive film 442 may be composed of, for example, a metal layer. The metal layer may be composed of, for example, at least one of a Ni layer, a Pd layer, and an Au layer.

[0174] (Effects of the fourth embodiment) As described above, the semiconductor package 400 of the fourth embodiment provides the same effects as the second and third embodiments.

[0175] (Fifth embodiment) A semiconductor package 500 according to the fifth embodiment will be described with reference to Figures 17 and 18. Below, the second embodiment will be described, focusing on the differences from the first to fourth embodiments, and components common to the first to fourth embodiments will be assigned the same reference numerals and detailed description thereof will be omitted.

[0176] Fig. 17 shows an example of a semiconductor package according to the fifth embodiment. Fig. 18 shows an example of a cross-sectional structure of the semiconductor package 500 of Fig. 17, illustrating the connection between the resistor chip 10 and the amplifier chip 60.

[0177] The semiconductor package 500 of the fifth embodiment differs from the semiconductor package 400 of the fourth embodiment in the configuration of the mounting member 510. The semiconductor package 500 includes a mounting member 510 and a sealing resin 560 disposed on the mounting member 510 .

[0178] (insulating substrate) The mounting member 510 includes an insulating substrate 520 . The insulating substrate 520 has a plate shape and does not include a through-hole.

[0179] Insulating substrate 520 includes mounting surface 521 and back surface 522 opposite mounting surface 521. Insulating substrate 520 includes substrate side surfaces 523, 524, 525, and 526 connecting mounting surface 521 and back surface 522.

[0180] The insulating substrate 520 is formed of, for example, an insulating material. The insulating material may be, for example, a material containing epoxy resin. The insulating substrate 520 may be made of a resin material containing a filler. The filler may be, for example, SiO2. The insulating substrate 520 may be colored, for example, black. The insulating substrate 520 may be made of ceramics, glass, or the like. The insulating substrate 520 may also be composed of a base material made of a semiconductor material such as Si, and an insulating layer covering the base material. The insulating layer may be, for example, an oxide film such as SiO2, or a resin film such as polyimide resin. The insulating layer forms the mounting surface of the insulating substrate 520.

[0181] (Sealing resin) The sealing resin 560 is provided on the insulating substrate 520. The sealing resin 560 covers the mounting surface 521 of the insulating substrate 520.

[0182] The sealing resin 560 includes a first sealing surface 561 and a second sealing surface 562 opposite to the first sealing surface 561. The first sealing surface 561 of the sealing resin 560 contacts the mounting surface 521 of the insulating substrate 520. The sealing resin 560 includes sealing side surfaces 563, 564, 565, and 566 that connect the first sealing surface 561 and the second sealing surface 562.

[0183] In one example, the sealing resin 560 has the same size as the insulating substrate 520 in a plan view. First to fourth sealing side surfaces 563 to 566 of the sealing resin 560 may be flush with the first to fourth substrate side surfaces 523 to 526 of the insulating substrate 520, respectively. The sealing resin 560 includes a plurality of through holes 567 that penetrate the sealing resin 560 from the first sealing surface 561 to the second sealing surface 562. The shape of the through holes 567 may be, for example, rectangular in a plan view. The shape of the through holes 567 may be any shape, such as circular or polygonal, in a plan view.

[0184] (wiring components) The mounting member 510 includes a plurality of wiring members 530. The plurality of wiring members 530 includes a first wiring member 531 and a second wiring member 532. The plurality of wiring members 530 corresponds to "a plurality of wiring layers."

[0185] (First wiring member, second wiring member) The first wiring member 531 and the second wiring member 532 may include a wiring layer 533 and a through wiring 534. The wiring layer 533 of the first wiring member 531 corresponds to the "first wiring layer." The wiring layer 533 of the second wiring member 532 corresponds to the "second wiring layer."

[0186] The wiring layer 533 is provided on the insulating substrate 520. The wiring layer 533 includes a connection surface 533A and a bottom surface 533B opposite to the connection surface 533A. The bottom surface 533B of the wiring layer 533 is in contact with the mounting surface 521 of the insulating substrate 520. The wiring layer 533 includes a side surface 533C connecting the connection surface 533A and the bottom surface 533B. The side surface 533C of the wiring layer 533 is in contact with the sealing resin 560.

[0187] The first wiring member 531 extends from the resistor chip 10 toward a first sealing side surface 563 of the sealing resin 560. The second wiring member 532 extends from the resistor chip 10 toward a second sealing side surface 564 of the sealing resin 560.

[0188] In one example, the wiring layer 533 extends in the Y-axis direction from a position overlapping the resistor chip 10 in a plan view to a position not overlapping the resistor chip 10. The wiring layer 533 is made of a material containing at least one of Cu and Ti, for example. The wiring layer 533 may be made of multiple metal layers. In one example, the wiring layer 533 may be made of a first metal layer disposed on the mounting surface 521 of the insulating substrate 520 and a second metal layer disposed on the first metal layer. The first metal layer may be made of a first layer made of a material mainly containing Ti, for example, and a second layer made mainly of Cu. The second metal layer may be made of a material mainly containing Cu.

[0189] The through wiring 534 is disposed in a through hole 567 of the sealing resin 560. It can be said that the through wiring 534 penetrates the sealing resin 560. The through wiring 534 extends from the connection surface 533A of the wiring layer 533 to the second sealing surface 562 of the sealing resin 560 within the insulating substrate 520. In one example, the through wiring 534 is disposed at a position that overlaps the wiring layer 533 but does not overlap the resistor chip 10 in a plan view. The through wiring 534 includes an upper surface 534A and a lower surface 534B. The through wiring 534 includes a side surface 534C that connects the upper surface 534A and the lower surface 534B. The upper surface 534A of the through wiring 534 is exposed from the second sealing surface 562 of the sealing resin 560. The lower surface 534B of the through wiring 534 is electrically connected to the wiring layer 533. A side surface 534C of the through wiring 534 contacts the inner wall surface of the through hole 567. The through wiring 534 may be made of a material containing Cu. The through wiring 534 of the first wiring member 531 corresponds to a "first external terminal." The through wiring 534 of the second wiring member 532 corresponds to a "second external terminal."

[0190] (Intermediate wiring) The plurality of wiring members 530 may include a plurality of intermediate wirings 536 . The intermediate wiring 536 is provided on the insulating substrate 520. The intermediate wiring 536 is in contact with the mounting surface 521 of the insulating substrate 520. The intermediate wiring 536 includes a connection surface 536A and a side surface 536B intersecting with the connection surface 536A. The connection surface 536A and the side surface 536B of the intermediate wiring 536 are covered with a sealing resin 560. In one example, the intermediate wiring 536 extends, in a plan view, from a position overlapping with the resistor chip 10 along the X-axis direction to a position overlapping with the amplifier chip 60. The intermediate wiring 536 is made of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0191] (Third wiring member) The plurality of wiring members 530 may include a third wiring member 537. The third wiring member 537 may include a wiring layer 538 and a through-wire 539. The wiring layer 538 of the third wiring member 537 corresponds to the "third wiring layer."

[0192] Wiring layer 538 is provided on insulating substrate 520. Wiring layer 538 includes a connection surface 538A and a bottom surface 538B opposite to connection surface 538A. Bottom surface 538B of wiring layer 538 contacts mounting surface 521 of insulating substrate 520. Wiring layer 538 includes a side surface 538C connecting connection surface 538A and bottom surface 538B. Side surface 538C of wiring layer 538 contacts sealing resin 560.

[0193] In one example, the wiring layer 538 extends in the Y-axis direction from a position overlapping with the amplifier chip 60 in a plan view to a position not overlapping with the amplifier chip 60. The wiring layer 538 is made of a material containing at least one of Cu and Ti, for example. The wiring layer 538 may be made of multiple metal layers. In one example, the wiring layer 538 may be made of a first metal layer disposed on the mounting surface 521 of the insulating substrate 520 and a second metal layer disposed on the first metal layer. The first metal layer may be made of a first layer made of a material mainly containing Ti, for example, and a second layer made mainly of Cu. The second metal layer may be made of a material mainly containing Cu.

[0194] The through wiring 539 is disposed in a through hole 567 of the sealing resin 560. It can be said that the through wiring 539 penetrates the sealing resin 560. The through wiring 539 extends from a connection surface 538A of the wiring layer 538 to a second sealing surface 562 of the sealing resin 560 within the insulating substrate 520. In one example, the through wiring 539 is disposed at a position that overlaps the wiring layer 538 but does not overlap the amplifier chip 60 in a plan view. The through wiring 539 includes an upper surface 539A and a lower surface 539B. The through wiring 539 includes a side surface 539C that connects the upper surface 539A and the lower surface 539B. The upper surface 539A of the through wiring 539 is exposed from the second sealing surface 562 of the sealing resin 560. The lower surface 539B of the through wiring 539 is electrically connected to the wiring layer 538. A side surface 539C of the through wiring 539 contacts the inner wall surface of the through hole 567. The through wiring 539 may be made of a material containing Cu. The through wiring 539 of the third wiring member 537 corresponds to the "third external terminal." An upper surface 539A of the through wiring 539 corresponds to the "exposed surface."

[0195] (Resistor chip mounting format) The resistor chip 10 is mounted on a mounting member 510. More specifically, the resistor chip 10 is mounted on a first wiring member 531, a second wiring member 532, and an intermediate wiring 536. It can be said that the resistor chip 10 is flip-chip mounted on the mounting member 510. A first electrode 41 of the resistor chip 10 is electrically connected to the first wiring member 531 by a connection member 50 (51). A second electrode 42 of the resistor chip 10 is electrically connected to the second wiring member 532 by a connection member 50 (52). A third electrode 43 of the resistor chip 10 is electrically connected to the intermediate wiring 536 by a connection member 50 (53).

[0196] (Amplifier chip implementation) The amplifier chip 60 is mounted on a mounting member 510. More specifically, the amplifier chip 60 is mounted on an intermediate wiring 536 and a third wiring member 537. It can be said that the amplifier chip 60 is flip-chip mounted on the mounting member 510. A first electrode 71 of the amplifier chip 60 is electrically connected to the intermediate wiring 536 by a connection member 80 (81). A second electrode 72 of the amplifier chip 60 is electrically connected to the third wiring member 537 by a connection member 80 (82).

[0197] (jointing material) The semiconductor package 500 may include a bonding member 542 connected to the through wiring 539. The bonding member 542 may be made of a material containing SnAg. The bonding member 542 may be called a solder bump. The bonding member 542 connected to the through wiring 539 of the first wiring member 531 corresponds to the "first bonding member." The bonding member 542 connected to the through wiring 539 of the second wiring member 532 corresponds to the "second bonding member." The bonding member 542 connected to the through wiring 539 of the third wiring member 537 corresponds to the "third bonding member."

[0198] (Effects of the fifth embodiment) As described above, the semiconductor package 500 of the fifth embodiment provides the same effects as the second to fourth embodiments.

[0199] (Sixth embodiment) A semiconductor package 600 according to the sixth embodiment will be described with reference to Figures 19 to 22. Below, the second embodiment will be described, focusing on the differences from the first to fifth embodiments, and components common to the first to fifth embodiments will be assigned the same reference numerals and detailed description thereof will be omitted.

[0200] Fig. 19 is a schematic plan view showing an example of a semiconductor package according to a sixth embodiment. Fig. 20 is a schematic cross-sectional view of the semiconductor package of Fig. 19. Fig. 21 is a schematic plan view showing the amplifier chip and connecting member of Fig. 10. Fig. 22 is a schematic plan view showing the resistor chip and connecting member of Fig. 10. Fig. 23 is a schematic cross-sectional view showing a semiconductor package of a modified example. Fig. 24 is a schematic cross-sectional view showing a semiconductor package of a modified example.

[0201] The semiconductor package 600 includes an amplifier chip 60 that is arranged to overlap the resistor chip 10 in a plan view. In one example, the amplifier chip 60 is arranged on top of the resistor chip 10.

[0202] The semiconductor package 600 includes a mounting member 610 . (insulating substrate) The mounting member 610 includes an insulating substrate 620. The insulating substrate 620 includes a mounting surface 621 and a back surface 622 opposite the mounting surface 621. The insulating substrate 620 includes a substrate side surface 623 connecting the mounting surface 621 and the back surface 622. The insulating substrate 620 is made of, for example, an electrically insulating material. The insulating substrate 620 may be made of, for example, a material containing epoxy resin. The insulating substrate 620 may be made of a resin material containing a filler. The filler may be made of, for example, SiO2. The insulating substrate 620 may be colored, for example, black. Cutting marks may be formed on the mounting surface 621, the back surface 622, and the substrate side surface 623, which are the surfaces of the insulating substrate 620. The filler may be exposed on the mounting surface 621, the back surface 622, and the substrate side surface 623, which are the surfaces of the insulating substrate 620.

[0203] (Sealing resin) The sealing resin 660 is provided on the insulating substrate 620. The sealing resin 660 covers the mounting surface 621 of the insulating substrate 620. The sealing resin 660 includes a first sealing surface 661 and a second sealing surface 662 opposite to the first sealing surface 661. The first sealing surface 661 is in contact with the mounting surface 621.

[0204] The sealing resin 660 includes a first resin portion 663 and a second resin portion 666. The first resin portion 663 is provided on the insulating substrate 620. The first resin portion 663 includes a first surface 664 and a second surface 665 opposite the first surface 664. The first surface 664 of the first resin portion 663 is in contact with the mounting surface 621 of the insulating substrate 620. The second resin portion 666 is provided on the first resin portion 663. The second resin portion 666 includes a first surface 667 and a second surface 668 opposite the first surface 667. The first surface 667 of the second resin portion 666 is in contact with the second surface 665 of the first resin portion 663. It can be said that the first resin portion 663 and the second resin portion 666 are layered on the insulating substrate 620.

[0205] First resin portion 663 and second resin portion 666 are made of, for example, an electrically insulating material. First resin portion 663 and second resin portion 666 may be made of a material containing epoxy resin. First resin portion 663 and second resin portion 666 may be colored, for example, black. The material and shape of first resin portion 663 and second resin portion 666 are not limited. Furthermore, the material of first resin portion 663 and the material of the second resin portion may be different from each other.

[0206] (First wiring member, second wiring member) The semiconductor package 600 includes a plurality of wiring members 630. The plurality of wiring members 630 includes a first wiring member 631 and a second wiring member 632. The plurality of wiring members 630 corresponds to "a plurality of wiring layers."

[0207] The first wiring member 631 and the second wiring member 632 may include a wiring layer 633 and a through wiring 634. The wiring layer 633 of the first wiring member 631 corresponds to the "first wiring layer." The wiring layer 633 of the second wiring member 632 corresponds to the "second wiring layer."

[0208] The wiring layer 633 is provided on the insulating substrate 620. The wiring layer 633 includes a connection surface 633A and a bottom surface 633B opposite to the connection surface 633A. The bottom surface 633B of the wiring layer 633 contacts the mounting surface 621 of the insulating substrate 620. The wiring layer 633 includes a side surface 633C connecting the connection surface 633A and the bottom surface 633B. The side surface 633C of the wiring layer 633 contacts the sealing resin 660. In one example, the wiring layer 633 extends in a plan view from a position overlapping the resistor chip 10 along the Y-axis direction to a position not overlapping the resistor chip 10. The wiring layer 633 is made of a material including at least one of Cu, Al, Ag, Au, Ni, and Ti, for example.

[0209] The through wiring 634 penetrates the insulating substrate 620. The insulating substrate 620 includes a through hole 627 that penetrates the insulating substrate 620 from the mounting surface 621 to the back surface 622. The through hole 627 may be called a via hole. The through wiring 634 is disposed in the through hole 627 of the insulating substrate 620. The through wiring 634 extends within the insulating substrate 620 from the mounting surface 621 of the insulating substrate 620 to the back surface 622 of the insulating substrate 620. The through wiring 634 may be formed of a metal member filled in the through hole 627. The through wiring 634 may be formed of a cylindrical metal member that covers the inner surface of the through hole 627. In the case of a cylindrical metal member, the inside may be filled with resin or the like.

[0210] In one example, the through wiring 634 is arranged at a position that overlaps with the wiring layer 633 but does not overlap with the resistor chip 10 in a planar view. The through wiring 634 may be arranged at a position that overlaps with the resistor chip 10 in a planar view. The through wiring 634 is electrically connected to the wiring layer 633. The through wiring 634 is made of a material containing at least one of Cu, Al, Ag, Au, Ni, and Ti. The through wiring 634 of the first wiring member 631 corresponds to a "first external terminal." The through wiring 634 of the second wiring member 632 corresponds to a "second external terminal."

[0211] (resistor chip) The resistor chip 10 is mounted on a mounting member 610. The resistor chip 10 includes a first element surface 11 and a second element surface 12. The resistor chip 10 is arranged with the first element surface 11 facing the mounting member 610. More specifically, the resistor chip 10 is mounted on a first wiring member 631, a second wiring member 632, and an intermediate wiring 640. It can be said that the resistor chip 10 is flip-chip mounted on the mounting member 610. A first electrode 41 of the resistor chip 10 is electrically connected to the first wiring member 631 by a connecting member 50 (51). A second electrode 42 of the resistor chip 10 is electrically connected to the second wiring member 632 by the connecting member 50 (51).

[0212] The resistor chip 10 is sealed by a first resin portion 663 of the sealing resin 660. The second element surface 12 of the resistor chip 10 is exposed from a second surface 665 of the first resin portion 663. In one example, the second element surface 12 of the resistor chip 10 may be flush with the second surface 665 of the first resin portion 663. The second resin portion 666 is in contact with the second surface 665 of the first resin portion 663. Therefore, the second element surface 12 of the resistor chip 10 is covered by the second resin portion 666. The second resin portion 666 is in contact with the second element surface 12 of the resistor chip 10.

[0213] (amplifier chip) The semiconductor package 600 includes a conductive layer 635 disposed on the resistor chip 10. The semiconductor package 600 includes a plurality of conductive layers 635. The amplifier chip 60 is mounted on the conductive layer 635. The connection member 80 (82) electrically connects the electrodes 72 of the amplifier chip 60 to the conductive layer 635. The amplifier chip 60 is sealed by a second resin portion 666 of the sealing resin 660. The second resin portion 666 covers the surface of the amplifier chip 60.

[0214] The conductive layer 635 is electrically connected to through-wires 638 provided in the insulating substrate 620. More specifically, the semiconductor package 600 includes a third wiring layer 637 provided on the mounting surface of the insulating substrate 620. The third wiring layer 637 is electrically connected to through-wires 638 that penetrate the insulating substrate 620. The semiconductor package 600 includes through-wires 636 electrically connected to the third wiring layer 637. The through-wires 636 penetrate the first resin portion 663. The through-wires 636 are electrically connected to the conductive layer 635 provided on the second surface 665 of the first resin portion 663. The amplifier chip 60 is electrically connected to the through-wires 638 via the conductive layer 635, the through-wires 636, and the third wiring layer 637. The through-wires 638 electrically connected to the amplifier chip 60 correspond to the "third external terminals."

[0215] (Intermediate wiring) The semiconductor package 600 includes intermediate wiring 640 that electrically connects the resistor chip 10 and the amplifier chip 60 .

[0216] The intermediate wiring 640 includes a first intermediate wiring 641, a second intermediate wiring 642, and an intermediate through wiring 643. The first intermediate wiring 641 is disposed on the mounting surface 621 of the insulating substrate 620. The first intermediate wiring 641 is covered with a first resin portion 663. The first intermediate wiring 641 is electrically connected to the third electrode 43 of the resistor chip 10. The second intermediate wiring 642 is disposed on the first resin portion 663. The second intermediate wiring 642 is covered with a second resin portion 666. The second intermediate wiring 642 is electrically connected to the amplifier chip 60. The intermediate through wiring 643 penetrates the first resin portion 663. The intermediate through wiring 643 electrically connects the first intermediate wiring 641 and the second intermediate wiring 642.

[0217] (jointing material) The semiconductor package 600 may include a bonding member 646 connected to the through wiring 634, 638. The bonding member 646 may be made of a material containing SnAg. The bonding member 646 may be called a solder bump. The bonding member 646 connected to the through wiring 634 of the first wiring member 631 corresponds to the "first bonding member." The bonding member 646 connected to the through wiring 634 of the second wiring member 632 corresponds to the "second bonding member." The bonding member 646 connected to the through wiring 638 corresponds to the "third bonding member."

[0218] (Effects of the sixth embodiment) As described above, the semiconductor package 600 of the sixth embodiment provides the following advantages.

[0219] (6-1) The same effects as those of the first to fifth embodiments are achieved. (6-2) The semiconductor package 600 includes, in a plan view, an amplifier chip 60 that is arranged to overlap the resistor chip 10. Therefore, the semiconductor package 600 can be made smaller in size in a plan view.

[0220] (6-3) The semiconductor package 600 includes an amplifier chip 60 that is arranged to overlap the resistor chip 10 in a plan view. Therefore, the area of ​​a circuit board or the like on which the semiconductor package 600 is mounted can be further reduced.

[0221] (Modification of the sixth embodiment) The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0222] 23, in a semiconductor package 600A of the modified example, the second element surface 12 of the resistor chip 10 may be covered with a first resin portion 663 of a sealing resin 660. A second resin portion 666 arranged on the first resin portion 663 is spaced apart from the second element surface 12 of the resistor chip 10. The semiconductor package 600A of this modified example has the same effects as the semiconductor package 600 described above.

[0223] 24 , in a semiconductor package 600B of the modified example, the resistor chip 10 may be disposed on the amplifier chip 60. The first resin portion 663 is provided on the insulating substrate 620 and seals the amplifier chip 60. The second resin portion 666 is provided on the first resin portion 663 and seals the resistor chip 10. The second resin portion 666 may be spaced apart from the second element surface 62 of the amplifier chip 60. The first resin portion 663 may cover the second element surface 62 of the amplifier chip 60.

[0224] The mounting member 610B may include an insulating substrate 620, a first resin part 663 including a second surface 665 that constitutes the mounting surface, and multiple wiring layers 670 arranged on the second surface 665 of the first resin part 663. The insulating substrate 620 includes a mounting surface 621 and a back surface 622 opposite the mounting surface 621. The multiple wiring layers 670 include a first wiring layer 671 and a second wiring layer 672. The first electrode 41 and the second electrode 42 of the resistor chip 10 are electrically connected to the first wiring layer 671 and the second wiring layer 672.

[0225] A third wiring layer 673 and a fourth wiring layer 674 are provided on the insulating substrate 620. The third wiring layer 673 and the fourth wiring layer 674 are electrically connected to through-wires 675 and 676 that penetrate the insulating substrate 620. The third wiring layer 673 is electrically connected to the first wiring layer 671 by a first through-wire 677 that penetrates the first resin portion 663. The fourth wiring layer 674 is electrically connected to the second wiring layer 672 by a second through-wire 678 that penetrates the first resin portion 663. The first electrode 41 of the resistor chip 10 is electrically connected to the through-wire 675 through the first wiring layer 671, the first through-wire 677, and the third wiring layer 673. The second electrode 42 of the resistor chip 10 is electrically connected to the through-wire 676 through the second wiring layer 672, the second through-wire 678, and the fourth wiring layer 674.

[0226] A fifth wiring layer 681 is disposed on the mounting surface 621 of the insulating substrate 620. A plurality of fifth wiring layers 681 are provided. The fifth wiring layer 681 is electrically connected to through wirings 682 that penetrate the insulating substrate 620. The through wirings 682 are exposed from the back surface 622 of the insulating substrate 620. The amplifier chip 60 is electrically connected to the fifth wiring layer 681.

[0227] 24, the semiconductor package 600 includes intermediate wiring 640 arranged in the same manner as the above-described semiconductor package 500. The intermediate wiring 640 includes first intermediate wiring 641, second intermediate wiring 642, and intermediate through wiring 643. The amplifier chip 60 is electrically connected to the first intermediate wiring 641, and the resistor chip 10 is electrically connected to the second intermediate wiring 642.

[0228] (Example of change) The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0229] The configuration of the resistor chip 10 may be changed as appropriate. As shown in FIG. 25, a resistor chip 10A of the modified example may include an insulating member 700 disposed between the chip substrate 21 and the insulator 22.

[0230] The insulating member 700 is composed of a plurality of insulating films 710. For example, the insulating member 700 may include insulating films 711 to 716. The number of insulating films 710 constituting the insulating member 700 may be changed as appropriate. The lowest insulating film 711 may be an insulating film that covers the first substrate surface 21S of the chip substrate 21.

[0231] The insulating film 710 may be composed of a first insulating film 710A and a second insulating film 710B disposed on the first insulating film 710A. The first insulating film 710A may be thinner than the second insulating film 710B. The first insulating film 710A may be composed of a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. In one example, the first insulating film 710A is composed of a material containing SiN. The second insulating film 710B may be thicker than the first insulating film 710A. The second insulating film 710B may be composed of a material containing SiO2 (silicon oxide). The lowest insulating film 716 may be composed of a material containing SiO2. The lowest insulating film 711 may be composed only of the second insulating film 710B. The first insulating layer 23 of the insulator 22 may be omitted. The connection wiring 45A of the resistor connection section 45 may be disposed on the second insulating film 710B of the uppermost insulating film 716.

[0232] 26, a resistor chip 10B of a modified example may include an insulating member 720. The insulating member 720 may be composed of one first insulating film 721 and second insulating films 722 and 723 that sandwich the first insulating film 721. The first insulating layer 23 of the insulator 22 (see FIG. 6) may be omitted. The connection wiring 45A of the resistor connection portion 45 may be disposed on the second insulating film 723 that covers the first insulating film 721.

[0233] As shown in FIG. 27, a resistor chip 10C of a modified example may include an insulating member 730. The insulating member 730 may be made of a resin material. The insulating member 730 may be made of a resin material having insulating properties, such as mold resin or polyimide resin. The first insulating layer 23 of the insulator 22 (see FIG. 7) may be omitted. The connection wiring 45A of the resistor connection portion 45 may be disposed on the insulating member 730.

[0234] As shown in FIG. 28, a resistor chip 10D of a modified example may include an insulating member 740. The insulating member 740 may include a first insulating layer 741, a second substrate 742, and a second insulating layer 743. The second substrate 742 is, for example, a Si substrate. The second substrate 742 may be a glass substrate, a sapphire substrate, or the like. The second substrate 742 may also be a substrate using a wide bandgap semiconductor such as SiC (silicon nitride) or a compound semiconductor such as AlN (aluminum nitride). The second substrate 742 may be made of the same material as the chip substrate 21, or may be made of a different material from the chip substrate 21.

[0235] First insulating layer 741 and second insulating layer 743 may be made of an insulating resin material such as mold resin, polyimide resin, etc. First insulating layer 741 and second insulating layer 743 may be made of the same material or different materials.

[0236] 29, the first insulating layer 741 and the second insulating layer 743 may be composed of a plurality of insulating layers 744. The plurality of insulating layers 744 may be composed of a material including SiO, SiN, SiC, SiCN, etc. The first insulating layer 741 and the second insulating layer 743 may be composed of the same material or different materials.

[0237] The first insulating layer 741 may be made of an insulating resin material such as mold resin or polyimide resin, and the second insulating layer 743 may be made of a material containing SiO2, SiN, SiC, SiCN, etc. The first insulating layer 741 may be made of a material containing SiO2, SiN, SiC, SiCN, etc., and the second insulating layer 743 may be made of an insulating resin material such as mold resin or polyimide resin.

[0238] As shown in FIG. 30, a resistor chip 10F of the modified example may include solder bumps 750 connected to a plurality of electrodes 40 as connecting members. As used in this disclosure, the term "on" includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0239] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0240] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0241] (Appendix 1) a resistor chip (10) including a first element surface (11) provided with a plurality of electrodes (40) including a first electrode (41) and a second electrode (42), and a second element surface (12) opposite to the first element surface (11); a mounting member (110) including a mounting surface (111) on which the resistor chip (10) is mounted; a sealing resin (160) that seals the resistor chip (10) mounted on the mounting surface (111); a first external terminal (121) and a second external terminal (122); Including, The resistor chip (10) is a chip substrate (21) including a first substrate surface (21S) and a second substrate surface (21R) opposite to the first substrate surface (21S) and constituting the second element surface (12); an insulator (22) provided on the first substrate surface (21S); a resistive layer (30) provided within the insulator (22); Including, the resistive layer (30) is connected between the first electrode (41) and the second electrode (42); The resistor chip (10) is mounted on the mounting surface (111) in a state where the first element surface (11) and the mounting surface (111) face each other in the thickness direction of the resistor chip (10). Semiconductor package.

[0242] (Appendix 2) a first connection member (51) provided between the first element surface (11) and the mounting surface (111) and used to electrically connect the first electrode (41) and the first external terminal (121); a second connection member (52) provided between the first element surface (11) and the mounting surface and used to electrically connect the second electrode (42) and the second external terminal (122); Including, 1. A semiconductor package as defined in claim 1.

[0243] (Appendix 3) The plurality of electrodes (40) includes a third electrode (43), an amplifier chip (60) electrically connected to the third electrode (43); The amplifier chip (60) is sealed in the sealing resin (160). 1. A semiconductor package as defined in claim 2.

[0244] (Appendix 4) The amplifier chip (60) includes a first element surface (61) and a second element surface (62) opposite to the first element surface (61), The amplifier chip (60) is mounted on the mounting surface in a state where the first element surface (61) of the amplifier chip (60) and the mounting surface face each other in a thickness direction of the amplifier chip (60). 1. The semiconductor package of claim 3.

[0245] (Appendix 5) The mounting member includes a plurality of leads (120); the plurality of leads include a first lead (121) and a second lead (122); the first connection member (51) electrically connects the first lead (121) and the first electrode (41); The second connection member (52) electrically connects the second lead (122) and the second electrode (42). 1. A semiconductor package according to claim 3 or 4.

[0246] (Appendix 6) The first lead (121) is a first internal lead (123) that is embedded in the sealing resin (160) and faces the first electrode (41); a first external lead (124) that projects laterally from a side surface of the sealing resin and constitutes the first external terminal; Including, The second lead (122) is a second internal lead (123) that is embedded in the sealing resin (160) and faces the second electrode (42); a second external lead (124) that projects laterally from the side surface of the sealing resin and constitutes the second external terminal; Including, 6. The semiconductor package of claim 5.

[0247] (Appendix 7) The plurality of leads includes an intermediate lead (125) connected between the third electrode and the amplifier chip (60). 10. A semiconductor package according to claim 5 or 6.

[0248] (Appendix 8) a third external terminal (126); a third connecting member (82) used to electrically connect the third external terminal (126) and an electrode (70) of the amplifier chip (60); 8. The semiconductor package of claim 5.

[0249] (Appendix 9) the plurality of leads includes a third lead (126); The third connection member (82) electrically connects the third lead and the electrode (70) of the amplifier chip (60). 9. The semiconductor package of claim 8.

[0250] (Appendix 10) The third lead (126) is a third internal lead (127) that is embedded in the sealing resin (160) and faces the second electrode (42); a third external lead (128) that projects laterally from the side surface of the sealing resin (160) and constitutes the third external terminal; Including, 10. The semiconductor package of claim 9.

[0251] (Appendix 11) The mounting member (210) is an insulating substrate (220) including the mounting surface and a back surface opposite the mounting surface; a plurality of wiring members (230) provided on the insulating substrate; Including, The plurality of wiring members include: a first wiring member (231) electrically connected to the first connection member; a second wiring member (232) electrically connected to the second connection member; Including, the first wiring member includes the first external terminal provided on the back surface of the insulating substrate, the second wiring member includes the second external terminal provided on the back surface of the insulating substrate; 1. A semiconductor package according to claim 3 or 4.

[0252] (Appendix 12) The first wiring member and the second wiring member are a first wiring portion (233) provided on the mounting surface; a second wiring portion (235) provided on the rear surface; a through wiring portion (234) that electrically connects the first wiring portion and the second wiring portion; Including, The second wiring portion (235) of the first wiring member (231) constitutes the first external terminal, the second wiring portion (235) of the second wiring member (232) constitutes the second external terminal, 12. The semiconductor package of claim 11.

[0253] (Appendix 13) a first connecting member (242) connected to the first external terminal; a second connecting member (242) connected to the second external terminal; Including, 13. The semiconductor package of claim 11 or 12.

[0254] (Appendix 14) The plurality of wiring members include an intermediate wiring (236) connected between the third electrode and the amplifier chip (60). 14. The semiconductor package of claim 11.

[0255] (Appendix 15) the plurality of wiring members includes a third wiring member (237) electrically connected to the amplifier chip (60); The third wiring member includes a third external terminal (240) provided on the back surface of the insulating substrate. 15. The semiconductor package of claim 11.

[0256] (Appendix 16) a third connecting member (242) connected to the third external terminal; 16. The semiconductor package of claim 15.

[0257] (Appendix 17) The mounting member (310) is an insulating substrate (320) including the mounting surface (321) and a back surface (322) opposite to the mounting surface; A plurality of wiring layers (330) arranged on the mounting surface, including a first wiring layer (333 / 331) and a second wiring layer (333 / 332); Including, the first connection member electrically connects the first electrode (41) and the first wiring layer (333 / 331); the second connection member electrically connects the second electrode (42) and the second wiring layer (333 / 332); the first external terminal (334 / 331) is electrically connected to the first wiring layer and is exposed from the back surface; the second external terminal (334 / 332) is electrically connected to the second wiring layer and exposed from the back surface; 1. A semiconductor package according to claim 3 or 4.

[0258] (Appendix 18) the insulating substrate includes a plurality of through holes (327) that penetrate from the mounting surface to the back surface, the first external terminal and the second external terminal are disposed in the plurality of through holes; 18. The semiconductor package of claim 17.

[0259] (Appendix 19) a first connecting member (342) connected to the exposed surface of the first external terminal (334 / 331); a second connecting member (342) connected to the exposed surface of the second external terminal; Including, 19. The semiconductor package of claim 17 or 18.

[0260] (Appendix 20) the plurality of wiring layers are arranged on the mounting surface and include an intermediate wiring connected between the third electrode and the amplifier chip (60); 19. The semiconductor package of claim 17.

[0261] (Appendix 21) the plurality of wiring layers includes a third wiring layer (338 / 337) electrically connected to the amplifier chip (60); a third external terminal (339 / 337) electrically connected to the third wiring layer and penetrating the insulating substrate and exposed from the rear surface; 21. The semiconductor package of claim 17.

[0262] (Appendix 22) a third bonding member (342) provided on the third external terminal exposed from the rear surface, 22. The semiconductor package of claim 21.

[0263] (Appendix 23) The sealing resin (560) a first sealing surface (561) in contact with the mounting surface; a second sealing surface (562) opposite the first sealing surface; Including, The mounting member (510) is an insulating substrate (520) that constitutes the mounting surface; A plurality of wiring layers (530) arranged on the mounting surface, including a first wiring layer (533 / 531) and a second wiring layer (533 / 532); Including, the first connection member electrically connects the first electrode (41) and the first wiring layer; the second connection member electrically connects the second electrode (42) and the second wiring layer; the first external terminal (534 / 531) is electrically connected to the first wiring layer and penetrates the sealing resin to be exposed from the second sealing surface; The second external terminals (534 / 532) are electrically connected to the second wiring layer and penetrate the sealing resin to be exposed from the second sealing surface. 1. A semiconductor package according to claim 3 or 4.

[0264] (Appendix 24) the sealing resin includes a plurality of through holes (567) that penetrate from the first sealing surface to the second sealing surface, the first external terminal and the second external terminal are disposed in the plurality of through holes; 24. The semiconductor package of claim 23.

[0265] (Appendix 25) a first bonding member (542) provided on the first external terminal exposed from the second sealing surface; a second bonding member (542) provided on the second external terminal exposed from the second sealing surface; Including, 25. The semiconductor package of claim 23 or 24.

[0266] (Appendix 26) the plurality of wiring layers include an intermediate wiring (536) disposed on the mounting surface and connected between the third electrode and the amplifier chip (60); 26. The semiconductor package of claim 23.

[0267] (Appendix 27) the plurality of wiring layers includes a third wiring layer (538) electrically connected to the amplifier chip (60); a third external terminal (539) electrically connected to the third wiring layer and penetrating the sealing resin to be exposed from the second sealing surface; 27. The semiconductor package of claim 23.

[0268] (Appendix 28) a third bonding member (542) provided on the third external terminal exposed from the second sealing surface; 28. The semiconductor package of claim 27.

[0269] (Appendix 29) The amplifier chip (60) is arranged to overlap the resistor chip (10) when viewed in the thickness direction of the resistor chip (10). 1. The semiconductor package of claim 3.

[0270] (Appendix 30) The mounting member (610) an insulating substrate (620) including the mounting surface and a back surface opposite the mounting surface; A plurality of wiring layers (630) arranged on the mounting surface, including a first wiring layer (633 / 631) and a second wiring layer (633 / 632); Including, the first connection member electrically connects the first electrode (41) and the first wiring layer; the second connection member electrically connects the second electrode (42) and the second wiring layer; the first external terminal (634 / 631) is electrically connected to the first wiring layer and is exposed from the back surface; the second external terminals (634 / 632) are electrically connected to the second wiring layer and exposed from the back surface; 20. The semiconductor package of claim 29.

[0271] (Appendix 31) the insulating substrate includes a plurality of through holes (627) that penetrate from the mounting surface to the back surface, the first external terminal and the second external terminal are disposed in the plurality of through holes; 31. The semiconductor package of claim 30.

[0272] (Appendix 32) a first joining member (646) connected to the exposed surface of the first external terminal; a second joining member (646) connected to the exposed surface of the second external terminal; Including, 32. The semiconductor package of claim 30 or 31.

[0273] (Appendix 33) The sealing resin (660) a first resin portion (663) provided on the insulating substrate and sealing the resistor chip (10); a second resin portion (666) provided on the first resin portion and sealing the amplifier chip (60); Including, 33. The semiconductor package of claim 32.

[0274] (Appendix 34) the second element surface (12) of the resistor chip (10) is exposed from the first resin portion (663), The second resin portion (666) is in contact with the second element surface (12) of the resistor chip (10). 34. The semiconductor package of claim 33.

[0275] (Appendix 35) the first resin portion (663) covers the second element surface (12) of the resistor chip (10); The second resin portion (666) is spaced apart from the second element surface (12) of the resistor chip (10). 34. The semiconductor package of claim 33.

[0276] (Appendix 36) a conductive layer (635) disposed on the second element surface (12) of the resistor chip (10); The amplifier chip (60) is mounted on the conductive layer (635). 36. The semiconductor package of claim 34 or 35.

[0277] (Appendix 37) a third external terminal (638) electrically connected to the conductive layer and penetrating the insulating substrate and exposed from the rear surface; 37. The semiconductor package of claim 36.

[0278] (Appendix 38) a third wiring layer (637) provided on the mounting surface of the insulating substrate and electrically connected to the third external terminal; a through-wire (636) that penetrates the first resin portion and electrically connects the conductive layer and the third wiring layer; Including, 38. The semiconductor package of claim 37.

[0279] (Appendix 39) and an intermediate wiring (640) connected between the third electrode of the resistor chip (10) and the amplifier chip (60). 39. The semiconductor package of any one of appendices 34 to 38.

[0280] (Appendix 40) The intermediate wiring is a first intermediate wiring (641) disposed on the mounting surface of the insulating substrate and electrically connected to the third electrode of the resistor chip (10); a second intermediate wiring (642) disposed on the first resin portion and electrically connected to the amplifier chip (60); an intermediate through wiring (643) that penetrates the first resin portion and electrically connects the first intermediate wiring and the second intermediate wiring; Including, 39. The semiconductor package of claim 39.

[0281] (Appendix 41) an insulating substrate (620) including a front surface and a back surface opposite the front surface; The sealing resin (660) a first resin portion (663) provided on the insulating substrate and sealing the amplifier chip (60); a second resin portion (666) provided on the first resin portion and sealing the resistor chip (10); Including, 20. The semiconductor package of claim 29.

[0282] (Appendix 42) The mounting member is the insulating substrate; The first resin portion (663) that configures the mounting surface (665); A plurality of wiring layers (670) arranged on the mounting surface and including a first wiring layer (671) and a second wiring layer (672); Including, the first connection member electrically connects the first electrode (41) and the first wiring layer (671); the second connection member electrically connects the second electrode (42) and the second wiring layer (672); the first external terminal (675) is electrically connected to the first wiring layer and is exposed from the back surface of the insulating substrate; the second external terminal (676) is electrically connected to the second wiring layer and is exposed from the back surface of the insulating substrate; 42. The semiconductor package of claim 41.

[0283] (Appendix 43) the insulating substrate includes a plurality of through holes that penetrate from the mounting surface to the back surface, the first external terminal and the second external terminal are disposed in the plurality of through holes; 43. The semiconductor package of claim 42.

[0284] (Appendix 44) a third wiring layer (673) provided on the mounting surface of the insulating substrate and electrically connected to the first external terminal; a fourth wiring layer (674) provided on the mounting surface of the insulating substrate and electrically connected to the second external terminal; a first through wiring (677) that penetrates the first resin portion and electrically connects the first wiring layer and the third wiring layer; a second through-wire (678) that penetrates the first resin portion and electrically connects the second wiring layer and the fourth wiring layer; Including, 44. The semiconductor package of claim 42 or 43.

[0285] (Appendix 45) a first joining member (646) connected to the exposed surface of the first external terminal; a second joining member (646) connected to the exposed surface of the second external terminal; Including, 45. The semiconductor package of any one of appendices 41 to 44.

[0286] (Appendix 46) the second element surface (62) of the amplifier chip (60) is exposed from the first resin portion (663), the second resin portion (666) is in contact with the second element surface (62) of the amplifier chip (60); 46. ​​The semiconductor package of any one of appendices 41 to 45.

[0287] (Appendix 47) the first resin portion (663) covers the second element surface (62) of the amplifier chip (60); The second resin portion (666) is spaced apart from the second element surface (62) of the amplifier chip (60). 46. ​​The semiconductor package of any one of appendices 41 to 45.

[0288] (Appendix 48) a plurality of fifth wiring layers (681) provided on the surface of the insulating substrate; The amplifier chip (60) is electrically connected to the plurality of fifth wiring layers. 48. The semiconductor package of any one of appendices 41 to 47.

[0289] (Appendix 49) a third external terminal (646) electrically connected to the plurality of fifth wiring layers and penetrating the insulating substrate and exposed from the rear surface; 49. The semiconductor package of claim 48.

[0290] (Appendix 50) and an intermediate wiring (640) connected between the third electrode of the resistor chip (10) and the amplifier chip (60). 49. The semiconductor package of claim 41.

[0291] (Appendix 51) The intermediate wiring (640) a first intermediate wiring (641) disposed on the mounting surface of the insulating substrate and electrically connected to the amplifier chip (60); a second intermediate wiring (642) disposed on the first resin portion and electrically connected to the third electrode of the resistor chip (10); an intermediate through wiring (643) that penetrates the first resin portion and electrically connects the first intermediate wiring and the second intermediate wiring; Including, 51. The semiconductor package of claim 50.

[0292] (Appendix 52) The resistor chip (10) includes an insulating member (700, 720, 730, 740) disposed between the chip substrate and the insulator. 52. The semiconductor package of claim 1.

[0293] (Appendix 53) The resistor chip (10) includes a plurality of resistor layers connected in series between the first electrode (41) and the second electrode (42). 53. The semiconductor package of any one of Supplementary Notes 1 to 52.

[0294] (Appendix 54) the resistive layer is made of a material containing CrSi; 54. The semiconductor package of any one of Supplementary Notes 1 to 53.

[0295] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0296] 100, 200, 300, 400, 500, 600 semiconductor packages 10,10A~10F resistor chip 11 First element surface 12 Second element surface 21 Chip substrate 21S 1st board surface 21R Second board surface 22 Insulators 30 resistance layer 40 electrodes 41 1st electrode 42 2nd electrode 60 Amplifier Chip 61 First element surface 62 Second element surface 70 electrodes 71 1st electrode 72 2nd electrode 110 Mounting materials 121 First Lead 122 Second Lead 125 Intermediate Lead 126 Third Lead 210 Mounting materials 220 Insulating substrate 230 Wiring materials 231 first wiring member 232 second wiring member 236 Intermediate wiring 237 Third wiring member 310 Mounting materials 320 Insulating substrate 330 Wiring materials 331 First wiring member 332 Second wiring member 336 Intermediate wiring 410 Mounting materials 420 Insulating substrate 430 Wiring materials 431 First wiring member 432 Second wiring member 436 Intermediate wiring 437 Third wiring member 510 Mounting materials 520 Insulating substrate 530 Wiring materials 531 First wiring member 532 Second wiring member 536 Intermediate wiring 537 Third wiring member 560 Sealing resin 610 Mounting materials 620 Insulating substrate 631 First wiring member 632 Second wiring member 637 3rd wiring layer 640 Intermediate wiring 660 Sealing resin

Claims

1. a resistor chip including a first element surface on which a plurality of electrodes including a first electrode and a second electrode are provided, and a second element surface opposite to the first element surface; a mounting member including a mounting surface on which the resistor chip is mounted; a sealing resin that seals the resistor chip mounted on the mounting surface; a first external terminal and a second external terminal; Including, The resistor chip is a chip substrate including a first substrate surface and a second substrate surface opposite the first substrate surface and constituting the second element surface; an insulator provided on the first substrate surface; a resistive layer disposed within the insulator; Including, the resistive layer is connected between the first electrode and the second electrode; the resistor chip is mounted on the mounting surface in a state where the first element surface and the mounting surface face each other in a thickness direction of the resistor chip; Semiconductor package.

2. a first connection member provided between the first element surface and the mounting surface and used to electrically connect the first electrode and the first external terminal; a second connection member provided between the first element surface and the mounting surface and used to electrically connect the second electrode and the second external terminal; Including, The semiconductor package of claim 1 .

3. the plurality of electrodes includes a third electrode; an amplifier chip electrically connected to the third electrode; the amplifier chip is sealed in the sealing resin; The semiconductor package according to claim 2 .

4. the amplifier chip includes a first element surface and a second element surface opposite to the first element surface, the amplifier chip is mounted on the mounting surface in a state in which the first element surface and the mounting surface of the amplifier chip face each other in a thickness direction of the amplifier chip; The semiconductor package according to claim 3 .

5. the mounting member includes a plurality of leads; the plurality of leads includes a first lead and a second lead; the first connection member electrically connects the first lead and the first electrode; the second connection member electrically connects the second lead and the second electrode; The semiconductor package according to claim 3 .

6. The first lead is a first internal lead that is embedded in the sealing resin and faces the first electrode; a first external lead that projects laterally from a side surface of the sealing resin and constitutes the first external terminal; Including, The second lead is a second internal lead that is embedded in the sealing resin and faces the second electrode; a second external lead that projects laterally from a side surface of the sealing resin and constitutes the second external terminal; Including, The semiconductor package according to claim 5 .

7. the plurality of leads includes an intermediate lead connected between the third electrode and the amplifier chip; The semiconductor package according to claim 5 .

8. The mounting member is an insulating substrate including the mounting surface and a back surface opposite to the mounting surface; a plurality of wiring members provided on the insulating substrate; Including, The plurality of wiring members include: a first wiring member electrically connected to the first connection member; a second wiring member electrically connected to the second connection member; Including, the first wiring member includes the first external terminal provided on the back surface of the insulating substrate, the second wiring member includes the second external terminal provided on the back surface of the insulating substrate; The semiconductor package according to claim 3 .

9. The first wiring member and the second wiring member are a first wiring portion provided on the mounting surface; a second wiring portion provided on the rear surface; a through wiring portion that electrically connects the first wiring portion and the second wiring portion; Including, the second wiring portion of the first wiring member constitutes the first external terminal, the second wiring portion of the second wiring member constitutes the second external terminal, The semiconductor package according to claim 8 .

10. a first joint member connected to the first external terminal; a second joining member connected to the second external terminal; Including, The semiconductor package according to claim 8 .

11. The mounting member is an insulating substrate including the mounting surface and a back surface opposite to the mounting surface; a plurality of wiring layers disposed on the mounting surface, the wiring layers including a first wiring layer and a second wiring layer; Including, the first connection member electrically connects the first electrode and the first wiring layer; the second connection member electrically connects the second electrode and the second wiring layer; the first external terminal is electrically connected to the first wiring layer and is exposed from the back surface; the second external terminal is electrically connected to the second wiring layer and is exposed from the back surface; The semiconductor package according to claim 3 .

12. the insulating substrate includes a plurality of through holes that penetrate from the mounting surface to the back surface, the first external terminal and the second external terminal are disposed in the plurality of through holes; The semiconductor package of claim 11.

13. a first bonding member connected to an exposed surface of the first external terminal; a second bonding member connected to an exposed surface of the second external terminal; Including, The semiconductor package of claim 11.

14. The sealing resin is a first sealing surface in contact with the mounting surface; a second sealing surface opposite the first sealing surface; Including, The mounting member is an insulating substrate that forms the mounting surface; a plurality of wiring layers disposed on the mounting surface, the wiring layers including a first wiring layer and a second wiring layer; Including, the first connection member electrically connects the first electrode and the first wiring layer; the second connection member electrically connects the second electrode and the second wiring layer; the first external terminal is electrically connected to the first wiring layer and penetrates the sealing resin to be exposed from the second sealing surface; the second external terminal is electrically connected to the second wiring layer and penetrates the sealing resin to be exposed from the second sealing surface; The semiconductor package according to claim 3 .

15. the sealing resin includes a plurality of through holes that penetrate from the first sealing surface to the second sealing surface, the first external terminal and the second external terminal are disposed in the plurality of through holes; The semiconductor package of claim 14.

16. a first bonding member provided on the first external terminal exposed from the second sealing surface; a second bonding member provided on the second external terminal exposed from the second sealing surface; Including, The semiconductor package of claim 14.

17. the amplifier chip is disposed so as to overlap the resistor chip when viewed in the thickness direction of the resistor chip; The semiconductor package according to claim 3 .

18. The mounting member is an insulating substrate including the mounting surface and a back surface opposite to the mounting surface; a plurality of wiring layers disposed on the mounting surface, the wiring layers including a first wiring layer and a second wiring layer; Including, the first connection member electrically connects the first electrode and the first wiring layer; the second connection member electrically connects the second electrode and the second wiring layer; the first external terminal is electrically connected to the first wiring layer and is exposed from the back surface; the second external terminal is electrically connected to the second wiring layer and is exposed from the back surface; 18. The semiconductor package of claim 17.

19. the insulating substrate includes a plurality of through holes that penetrate from the mounting surface to the back surface, the first external terminal and the second external terminal are disposed in the plurality of through holes; 20. The semiconductor package of claim 18.

20. a first bonding member connected to an exposed surface of the first external terminal; a second bonding member connected to an exposed surface of the second external terminal; Including, 20. The semiconductor package of claim 18.

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