Motor driver

Abstract

To stop a motor on the basis of the detection of an abnormal condition even when a WDT function built in a CPU or a FW falls into the abnormal condition.SOLUTION: A motor driver of an embodiment of the present invention includes: monitor means for monitoring a motor control signal for controlling a motor; timekeeping means for measuring time when the PWM duty of the motor control signal monitored by the monitor means does not change; reset means for resetting the time measured by the timekeeping means when the PWM duty of the motor control signal monitored by the monitor means changes; determination means for determining whether or not the measured time is larger than a prescribed threshold time; and first output means for outputting a stop signal for stopping the motor based on the determination result of the determination means.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a motor driver, and more particularly to a motor driver that stops a motor by monitoring the PWM duty of a motor control signal even if a WDT (watchdog timer) built into a CPU or firmware (FW) enters an abnormal state. [Background technology]

[0002] Conventionally, in preparation for when the CPU or FW goes into an abnormal state, a WDT built into the system, such as the controller CPU or FW, is activated. In Patent Document 1, a counter built into the controller measures the time during which PWM data is not updated, and if the measured time is equal to or less than the WDT setting value in the register, it is determined to be normal, and if the measured time exceeds the WDT setting value, it is determined to be abnormal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-111915 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with the method disclosed in Patent Document 1, if the WDT function built into the system that controls the motor driver goes into an abnormal state, the WDT function may not function properly and the motor may continue to rotate.

[0005] In view of the above problems, the present disclosure aims to detect an abnormal state and stop a motor even when a WDT function built into a CPU or FW goes into an abnormal state. [Means for solving the problem]

[0006] One embodiment of the present invention is a motor driver characterized by having: a monitoring means for monitoring a motor control signal for controlling a motor; a timing means for measuring time when the PWM duty of the motor control signal monitored by the monitoring means does not change; a reset means for resetting the measured time measured by the timing means when the PWM duty of the motor control signal monitored by the monitoring means changes; a judgment means for judging whether the measured time is greater than a predetermined time threshold; and a first output means for outputting a stop signal to stop the motor based on the judgment result of the judgment means. [Effects of the Invention]

[0007] According to the present disclosure, even if the WDT function built into the CPU or firmware goes into an abnormal state, it is possible to detect the abnormal state and stop the motor, thereby improving safety. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a printer unit in a first embodiment. [Figure 2] Block diagram of a motor control circuit in the first embodiment [Figure 3] 1 is a block diagram of a first H-bridge control unit according to a first embodiment; [Figure 4] 1 is a flowchart of a process executed by a first H-bridge control unit in the first embodiment; [Figure 5] Timing chart of the first H-bridge control unit in the first embodiment [Figure 6] 1 is a block diagram of a first H-bridge control unit according to a second embodiment; [Figure 7] 10 is a flowchart of a process executed by a first H-bridge control unit in the second embodiment. [Figure 8] Timing chart of the first H-bridge control unit in the second embodiment [Figure 9] Block diagram of a first H-bridge control unit in the third embodiment. [Figure 10]10 is a flowchart of a process executed by a first H-bridge control unit in the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, various embodiments in which the technology according to the present disclosure is applied to a multifunction inkjet printer will be described.

[0010] [First embodiment] <Printer unit configuration> 1A and 1B are diagrams showing the configuration of a printer unit, in which Fig. 1A is a perspective view showing the internal configuration of the printer unit, and Fig. 1B is a perspective view showing the overall configuration of the printer unit.

[0011] 1(a), the printer unit includes a transport mechanism 101 that transports recording media, an LF motor 102 that drives the transport mechanism, a cleaning mechanism 103 that cleans the nozzles of the print head, and a carriage 104 that transports the print head. The printer unit also includes a CR motor 105 that drives the carriage 104, and an automatic transport mechanism 106 that picks up only the topmost recording medium from multiple recording media and feeds it into the printer unit. The printer unit also includes an APP motor 107 that drives the cleaning mechanism 103 and automatic transport mechanism 106, an AC adapter 108, and a control board 109 that controls the entire printer in this embodiment, including a motor control circuit 200 (see FIG. 2).

[0012] Fig. 1(b) shows a state in which an image reading unit 110 and a panel unit 111 are incorporated into the printer unit shown in Fig. 1(a). The image reading unit 110 has an image reading sensor 112, an FB motor 113 that drives the image reading sensor 112, and a platen glass 114 on which a document is placed.

[0013] <Motor control circuit configuration> 2 is a block diagram showing a detailed configuration of the motor control circuit 200. The motor control circuit 200 includes a ROM 201, a CPU 202, and a motor driver 203.

[0014] The motor driver 203 has an H-bridge control unit 204. The H-bridge control unit 204 has a first H-bridge control unit 204A, a second H-bridge control unit 204B, a third H-bridge control unit 204C, and a fourth H-bridge control unit 204D. The first H-bridge control unit 204A has a stop time setting register 205A, and similarly, the second H-bridge control unit 204B to the fourth H-bridge control unit 204D have stop time setting registers 205B to 205D.

[0015] The motor driver 203 also has a first H-bridge circuit 210, a second H-bridge circuit 211, a third H-bridge circuit 212, and a fourth H-bridge circuit 213. The first H-bridge circuit 210 controls the LF motor 102, the second H-bridge circuit 211 controls the CR motor 105, the third H-bridge circuit 212 controls the APP motor 107, and the fourth H-bridge circuit 213 controls the FB motor 113.

[0016] The CPU 202 transmits motor control signals ENx and PHx (where x is any one of the letters A, B, C, or D; details will be described later) to the H-bridge control unit 204 based on the FW stored in the ROM 201. Note that EN indicates an Enable signal, and PH indicates a Phase signal.

[0017] Furthermore, before driving the motor, the CPU 202 performs three-wire serial interface communication with the H-bridge control unit 204 using the operation mode switching signal MODE and some of the motor control signals (e.g., ENA, PHA, PHB). This three-wire serial interface communication writes setting information to the stop time setting registers 205A to 205D. When the operation mode switching signal MODE is at low level, ENA, PHA, and PHB function as STRB, PHA as CLK, and PHB as DATA. Here, STRB is a latch signal that determines the register level, CLK is a signal that determines the transfer rate of serial communication, and DATA is a data signal for serial communication.

[0018] On the other hand, when the operation mode switching signal MODE is at a high level, the motor control signal functions as the signal shown below.

[0019] The motor control signal ENx is a binary signal that indicates whether or not the motor x is energized, with a low level indicating that it is not energized and a high level indicating that it is energized. As mentioned above, x can be A, B, C, or D, where motor A corresponds to the LF motor 102, motor B corresponds to the CR motor 105, motor C corresponds to the APP motor 107, and motor D corresponds to the FB motor 113.

[0020] The motor control signal PHx is a PWM signal that determines the rotation of the motor; the signal level determines the direction of current flow to motor x, and the PWM duty (the ratio of high level to one cycle) determines the amount of current flowing to motor x. For example, consider the case where the current flow direction is CW (clockwise) when the signal level is low, and CCW (counterclockwise) when the signal level is high. In this case, when the PWM duty is 40%, the average current flowing to motor x is 20% in the CW direction ((50 - 40) / 50 x 100 = 20). When the PWM duty is 50%, the average current flowing to motor x is zero. When the PWM duty is 80%, the average current flowing to motor x is 60% in the CCW direction ((80 - 50) / 50 x 100 = 60).

[0021] The H-bridge control unit 204 controls the energization of the LF motor 102 via a first H-bridge circuit 210 based on the motor control signals ENA and PHA received from the CPU 202. The H-bridge control unit 204 controls the energization of the CR motor 105 via a second H-bridge circuit 211 based on the motor control signals ENB and PHB received from the CPU 202. The H-bridge control unit 204 controls the energization of the APP motor 107 via a third H-bridge circuit 212 based on the motor control signals ENC and PHC received from the CPU 202. The H-bridge control unit 204 controls the energization of the FB motor 113 via a fourth H-bridge circuit 213 based on the motor control signals END and PHD received from the CPU 202.

[0022] <Configuration of the first H-bridge control unit> FIG. 3 is a block diagram showing the configuration of the first H-bridge control unit 204A in this embodiment.

[0023] First, the operation mode switching signal MODE is set to low level, and the first H-bridge control unit 204A sets a stop time in the stop time setting register 205A using ENA (STRB), PHA (CLK), and PHB (DATA). (That is, setting information is written to the stop time setting register.) Specific stop times can be set to, for example, 60 seconds or 120 seconds. Next, the operation mode switching signal MODE is set to high level, and the first H-bridge control unit 204A controls the LF motor 102 based on the motor control signals ENA and PHA received from the CPU 202.

[0024] The terminal monitoring means 301 monitors the PWM duty of the PHA. When this PWM duty does not change, the timer count value of the timing means 302 is counted up, and when the PWM duty changes, the timing reset means 303 resets the timer count value of the timing means 302 to zero. Furthermore, when ENA is at a low level or when the PWM duty is 50%, the timing reset means 303 resets the timer count value of the timing means 302 to zero. This is because when ENA is at a low level, the LF motor 102 is in a non-energized state and therefore is stopped, and also because the average amount of current when the PWM duty is 50% is zero and therefore the LF motor 102 is stopped.

[0025] The stop determination means 304 is connected to a stop signal input terminal of the H-bridge control unit core 305, which will be described later. When the timer count value of the timing means 302 exceeds the stop time set in the stop time setting register 205A, the stop determination means 304 determines that an abnormal state has occurred in which the CPU 202 or FW cannot update the PWM duty. After making this determination, the stop determination means 304 outputs a stop signal SS at a high level to the stop signal input terminal of the H-bridge control unit core 305. When the received stop signal SS is at a high level, the H-bridge control unit core 305 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0026] Thereafter, the H-bridge control unit core 305 outputs a reset signal RST to the CPU 202. Upon receiving the reset signal RST, the CPU 202 returns the internal circuitry to the initial settings.

[0027] <Processing performed by the first H-bridge control unit> FIG. 4 is a flowchart of the process executed by the first H-bridge control unit 204A.

[0028] In step S401, the first H-bridge control unit 204A sets the timer count value of the clock means 302 to zero. More specifically, the first H-bridge control unit 204A sets the operation mode switching signal MODE to low level, and uses ENA (STRB), PHA (CLK), and PHB (DATA) to enable a clock enable setting register (not shown) that sets whether the function of the clock means 302 is enabled or disabled. This sets the timer count value of the clock means 302 to zero. Note that hereinafter, "step S~" will be abbreviated to "S~".

[0029] In S402, the terminal monitoring means 301 performs an Enable monitoring process to monitor the Enable signal. Specifically, the terminal monitoring means 301 determines whether ENA is at a High level. If the determination result in this step is true, the process proceeds to S403. On the other hand, if the determination result in this step is false, the process proceeds to S405.

[0030] In S403, the terminal monitoring means 301 performs PWM duty monitoring processing. Specifically, the terminal monitoring means 301 determines whether the PWM duty is the same (i.e., the PWM duty does not change). If the determination result in this step is true, the process proceeds to S404. On the other hand, if the determination result in this step is false (i.e., the PWM duty has changed), the process proceeds to S405.

[0031] In S404, the terminal monitoring means 301 performs a PWM duty 50% determination process. Specifically, the terminal monitoring means 301 determines whether the PWM duty is 50%. If the determination result in this step is true, the process proceeds to S405. On the other hand, if the determination result in this step is false, the process proceeds to S406.

[0032] In S405, the time count reset means 303 resets the timer count value of the time count means 302 to zero, and then the process returns to the Enable monitoring process (S402).

[0033] In S406, the CPU 202 counts up the time count value of the timer 302.

[0034] In S407, the stop determination means 304 compares the timer count value of the timing means 302 with the stop time set in the stop time setting register 205A, and determines whether the timer count value is greater than the stop time. If the determination result in this step is true, the process proceeds to S408. On the other hand, if the determination result in this step is false, the process returns to S402. The stop time used in the determination process in this step is also called a "time threshold value."

[0035] In S408, the stop determination means 304 determines that the CPU 202 or FW is in an abnormal state where it cannot update the PWM duty, and sets the stop signal SS to High level. As a result of this step, the H-bridge control unit core 305 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0036] In S409 , the H-bridge control unit core 305 outputs a reset signal RST to the CPU 202 .

[0037] <Timing Chart of the First H-Bridge Control Unit 204A> 5 shows a timing chart of the first H-bridge control unit 204A. From time T0 to time T1, ENA is at low level, so the timer reset means 303 resets the timer count value of the timer means 302 to zero. From time T2 to time T3, the PWM duty of the PHA remains unchanged at 20%, so the timer count value of the timer means 302 counts up. From time T3 to time T4, the PWM duty of the PHA is 50%, so the timer reset means 303 resets the timer count value of the timer means 302 to zero.

[0038] From time T4 onwards, the PWM duty of the PHA is 70%, so the timer count value of the timing means 302 is counted up. Then, at time T5, when the timer count value exceeds the stop time set in the stop time setting register 205A, the stop determination means 304 determines that the CPU 202 or FW is in an abnormal state where it cannot update the PWM duty. Having made this determination, the stop determination means 304 outputs a stop signal SS at a high level to the H-bridge control unit core 305. As a result, the H-bridge control unit core 305 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0039] Terminal monitoring means 301 monitors the PWM duty of the PHASE signal (phase signal) among the motor control signals, and if the PWM duty does not change, counts up the timer count value of timing means 302. If this timer count value exceeds the stop time set in stop time setting register 205A, stop determination means 304 outputs a stop signal SS at a high level to H-bridge control unit core 305. At this time, H-bridge control unit core 305 stops the LF motor 102 by turning off the power supply to the LF motor 102. This makes it possible to stop the motor even in an abnormal state where the CPU 202 or FW cannot update the PWM duty, thereby increasing safety.

[0040] As described above, the operation of the first H-bridge control unit 204A relative to the first H-bridge circuit 210 has been described here, but the operation of the other H-bridge control units is similar. The operation of the second H-bridge control unit 204B to the fourth H-bridge control unit 204D relative to the second H-bridge circuit 211 to the fourth H-bridge circuit 213 is the same as that of the first H-bridge control unit 204A, so a description thereof will be omitted.

[0041] [Second embodiment] In the first embodiment, a case where the technology of the present disclosure is applied to a method of controlling the amount of current supplied to a DC motor by the PWM duty of a PHASE signal (phase signal) among motor control signals, that is, a so-called PHASE chopping method, is shown. In contrast, in this embodiment, a case where the technology of the present disclosure is applied to a method of controlling the amount of current supplied to a DC motor by the PWM duty of a motor control signal ENA, that is, a so-called ENABLE chopping method is shown.

[0042] 6 is a block diagram showing the configuration of the first H-bridge control unit 204A' in this embodiment. Here, the first H-bridge control unit 204A' is an ENABLE chopping-compatible version of the first H-bridge control unit 204A in the first embodiment. In the first H-bridge control unit 204A described above, the terminal monitoring means 301 monitors the PWM duty of the motor control signal PHA. In contrast, in the first H-bridge control unit 204A' of this embodiment, the terminal monitoring means 601 monitors the PWM duty of the motor control signal ENA.

[0043] Like the first H-bridge control unit 204A described above, the first H-bridge control unit 204A′ sets a stop time in the stop time setting register 205A and controls the LF motor 102 via the first H-bridge circuit 210 based on the motor control signals ENA and PHA received from the CPU 202.

[0044] Terminal monitoring means 601 monitors the PWM duty of ENA. When this PWM duty does not change, the timer count value of timing means 602 is counted up, and when the PWM duty changes, timing reset means 603 resets the timer count value of timing means 602 to zero. Furthermore, when the PWM duty is 0%, the timing reset means 603 resets the timer count value of timing means 602 to zero. This is because when the PWM duty is 0%, the LF motor 102 is in a non-energized state and therefore in a stopped state.

[0045] The stop determination means 604 is connected to a stop signal input terminal of an H-bridge control unit core 605, which will be described later. When the timer count value of the timing means 602 exceeds the stop time set in the stop time setting register 205A, the stop determination means 604 determines that an abnormal state has occurred in which the CPU 202 or FW cannot update the PWM duty. After making this determination, the stop determination means 604 outputs a stop signal SS at a high level to the stop signal input terminal of the H-bridge control unit core 605. When the received stop signal SS is at a high level, the H-bridge control unit core 605 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0046] Thereafter, the H-bridge control unit core 605 outputs a reset signal RST to the CPU 202. Upon receiving the reset signal RST, the CPU 202 returns the internal circuitry to the initial settings.

[0047] <Processing performed by the first H-bridge control unit> FIG. 7 is a flowchart of the process executed by the first H-bridge control unit 204A'.

[0048] In S701, the first H-bridge control unit 204A' sets the timer count value of the clock means 602 to zero. More specifically, the first H-bridge control unit 204A' sets the operation mode switching signal MODE to low level. Then, the first H-bridge control unit 204A' uses ENA (STRB), PHA (CLK), and PHB (DATA) to enable a clock enable setting register (not shown) that sets whether the function of the clock means 602 is enabled or disabled. This sets the timer count value of the clock means 602 to zero.

[0049] In S702, the terminal monitoring means 601 performs PWM duty monitoring processing. Specifically, the terminal monitoring means 601 determines whether the PWM duty is the same (i.e., the PWM duty does not change). If the determination result in this step is true, the process proceeds to S703. On the other hand, if the determination result in this step is false (i.e., the PWM duty has changed), the process proceeds to S704.

[0050] In S703, the terminal monitoring means 601 performs a PWM duty 0% determination process. Specifically, the terminal monitoring means 601 determines whether the PWM duty is 0%. If the determination result in this step is true, the process proceeds to S704. On the other hand, if the determination result in this step is false, the process proceeds to S705.

[0051] In S704, the time count reset means 603 resets the timer count value of the time count means 602 to zero, and then the process returns to the PWM duty monitoring process (S702).

[0052] In S705, the CPU 202 counts up the time count value of the timer 602.

[0053] In S706, the stop determination means 604 compares the timer count value of the timing means 602 with the stop time set in the stop time setting register 205A, and determines whether the timer count value is greater than the stop time. If the determination result in this step is true, the process proceeds to S707. On the other hand, if the determination result in this step is false, the process returns to S702.

[0054] In S707, the stop determination means 604 determines that the CPU 202 or FW is in an abnormal state where it cannot update the PWM duty, and sets the stop signal SS to High level. As a result of this step, the H-bridge control unit core 605 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0055] In S708, the H-bridge control unit core 605 outputs a reset signal RST to the CPU 202.

[0056] <Timing Chart of First H-Bridge Control Unit 204A'> 8 shows a timing chart of the first H-bridge control unit 204A'. From time T6 to time T7, the PWM duty of ENA remains unchanged at 20%, so the timer count value of the timing means 602 is counted up. From time T7 to time T8, the PWM duty of ENA is 0%, so the timing reset means 603 resets the timer count value of the timing means 602 to zero.

[0057] From time T8 onwards, the PWM duty of ENA is 70%, so the timer count value of the timing means 602 is counted up. Then, at time T9 when the timer count value exceeds the stop time set in the stop time setting register 205A, the stop determination means 604 determines that the CPU 202 or FW is in an abnormal state where it cannot update the PWM duty. Having made this determination, the stop determination means 604 then outputs a stop signal SS at a high level to the H-bridge control unit core 605. As a result, the H-bridge control unit core 605 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0058] As described above, the operation of the first H-bridge control unit 204A' with respect to the first H-bridge circuit 210 in the Enable chopping method has been described here, but the operation of the other H-bridge control units is similar. The operation of the H-bridge control units (not shown) with respect to the second H-bridge circuit 211 to the fourth H-bridge circuit 213 is also similar, so description thereof will be omitted.

[0059] [Third embodiment] In this embodiment, a configuration will be described in which the H-bridge control unit has two different stop time setting registers. This configuration can be applied to both the PHASE chopping method and the ENABLE chopping method shown in the first and second embodiments. Here, a case where it is applied to the PHASE chopping method will be described as a representative example.

[0060] FIG. 9 is a block diagram showing the configuration of the first H-bridge control unit 204A'' in this embodiment, specifically, the first H-bridge control unit 204A'' having two different stop time setting registers.

[0061] First, the operation mode switching signal MODE is set to low level, and the first H-bridge control unit 204A'' sets stop times in two different stop time setting registers using ENA (STRB), PHA (CLK), and PHB (DATA). (In other words, setting information is written to these stop time setting registers.) In this embodiment, the two different stop time setting registers are referred to as a first stop time setting register 901 and a second stop time setting register 902. Specific stop times set in the stop time setting registers can be, for example, 120 seconds in the first stop time setting register 901 and 60 seconds in the second stop time setting register 902. Next, the operation mode switching signal MODE is set to high level, and the first H-bridge control unit 204A'' controls the LF motor 102 based on the motor control signals ENA and PHA received from the CPU 202.

[0062] Terminal monitoring means 903 monitors the PWM duty of PHA. When this PWM duty does not change, the timer count value of timing means 904 is counted up, and when the PWM duty changes, timing reset means 905 resets the timer count value of timing means 904 to zero. Furthermore, when ENA is at low level or when the PWM duty is 50%, timing reset means 905 resets the timer count value of timing means 904 to zero. This is because when ENA is at low level, the LF motor 102 is in a non-conductive state and therefore is stopped, and also because the average amount of current when the PWM duty is 50% is zero and therefore the LF motor 102 is stopped.

[0063] The stop time setting means 906 can apply either the stop time set in the first stop time setting register 901 or the second stop time setting register 902 depending on the PWM duty of the PHA monitored by the terminal monitoring means 903. For example, when the PWM duty of the PHA monitored by the terminal monitoring means 903 is 30% to 49% or 51% to 70%, the stop time setting means 906 applies the stop time of 120 seconds set in the first stop time setting register 901. Also, when the PWM duty of the PHA monitored by the terminal monitoring means 903 is 0% to 29% or 71% to 100%, the stop time setting means 906 applies the stop time of 60 seconds set in the second stop time setting register 902. As a result, when the average amount of current flowing to the LF motor 102 is large, it is possible to determine that the situation is more dangerous and shorten the stop time.

[0064] The stop determination means 907 is connected to a stop signal input terminal of an H-bridge control unit core 908, which will be described later. Here, consider a case where the timer count value of the timing means 904 exceeds the stop time set in either the first stop time setting register 901 or the second stop time setting register 902, which is applied by the stop time setting means 906. In this case, the stop determination means 907 determines that an abnormal state has occurred in which the CPU 202 or FW cannot update the PWM duty, and outputs a stop signal SS at a high level to the stop signal input terminal of the H-bridge control unit core 908. When the received stop signal SS is at a high level, the H-bridge control unit core 908 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0065] Thereafter, the H-bridge control unit core 908 outputs a reset signal RST to the CPU 202. Upon receiving the reset signal RST, the CPU 202 returns the internal circuitry to the initial settings.

[0066] As described above, the H-bridge control unit has two different stop time setting registers, but may have three or more different stop time setting registers.

[0067] <Processing Executed by First H-Bridge Control Unit A''> FIG. 10 is a flowchart of the process executed by the first H-bridge control unit 204A''.

[0068] In S1001, the first H-bridge control unit 204A'' sets the timer count value of the clock means 904 to zero. More specifically, the first H-bridge control unit 204A'' sets the operation mode switching signal MODE to low level. Then, the first H-bridge control unit 204A'' uses ENA (STRB), PHA (CLK), and PHB (DATA) to enable a clock enable setting register (not shown) that sets whether the function of the clock means 904 is enabled or disabled. This sets the timer count value of the clock means 904 to zero.

[0069] In S1002, the terminal monitoring means 903 performs an Enable monitoring process to monitor the Enable signal. Specifically, the terminal monitoring means 903 determines whether ENA is at a High level. If the determination result in this step is true, the process proceeds to S1003. On the other hand, if the determination result in this step is false, the process proceeds to S1005.

[0070] In S1003, the terminal monitoring means 903 performs PWM duty monitoring processing. Specifically, the terminal monitoring means 903 determines whether the PWM duty is the same (i.e., the PWM duty does not change). If the determination result in this step is true, the process proceeds to S1004. On the other hand, if the determination result in this step is false (i.e., the PWM duty has changed), the process proceeds to S1005.

[0071] In S1004, the terminal monitoring means 903 performs a PWM duty 50% determination process. Specifically, the terminal monitoring means 903 determines whether the PWM duty is 50%. If the determination result in this step is true, the process proceeds to S1005. On the other hand, if the determination result in this step is false, the process proceeds to S1006.

[0072] In S1005, the timer reset means 905 resets the timer count value of the timer means 904 to zero, and then the process returns to the Enable monitoring process (S1002).

[0073] In S1006, the CPU 202 counts up the time count value of the timer 904.

[0074] In S1007, the stop time setting means 906 performs PWM duty determination processing. Specifically, it determines whether the PWM duty of the PHA monitored by the terminal monitoring means 903 is within a predetermined range. Here, the predetermined range is, for example, 30 to 49%, or 51 to 70%, etc. If the determination result in this step is true, the process proceeds to S1008. On the other hand, if the determination result in this step is false, the process proceeds to S1009.

[0075] In S1008, the stop time setting means 906 executes a process of applying the stop time set in the first stop time setting register 901 (this process is referred to as a first stop time setting process).

[0076] In S1009, the stop time setting means 906 executes a process (hereinafter referred to as a second stop time setting process) to apply the stop time set in the second stop time setting register 902. Note that the second stop time is shorter than the first stop time.

[0077] In S1010, the stop determination means 907 compares the timer count value of the timing means 904 with the stop time set in the first stop time setting register 901 or the second stop time setting register 902, and determines whether the timer count value is greater than the stop time. If the determination result in this step is true, the process proceeds to S1011. On the other hand, if the determination result in this step is false, the process returns to S1002.

[0078] In S1011, the stop determination means 907 determines that the CPU 202 or FW is in an abnormal state where it cannot update the PWM duty, and sets the stop signal SS to High level. As a result of this step, the H-bridge control unit core 908 stops the LF motor 102 by turning off the power supply to the LF motor 102 via the first H-bridge circuit 210.

[0079] In S1012, the H-bridge control unit core 908 outputs a reset signal RST to the CPU 202.

[0080] As described above, the stop time setting means 906 performs a PWM duty determination process to determine whether the PWM duty of the PHA monitored by the terminal monitoring means 903 is within a predetermined range. If it is within the predetermined range, the stop time setting means 906 applies the first stop time, and if it is outside the predetermined range, the stop time setting means 906 applies the second stop time. This makes it possible to determine that an increase in the average amount of current flowing to the motor in accordance with the PWM duty is dangerous and shorten the stop time. This improves safety.

[0081] As described above, the operation of the first H-bridge control unit 204A'' with respect to the first H-bridge circuit 210 has been described here, but the operation of the other H-bridge control units is similar. The operation of the H-bridge control units (not shown) with respect to the second H-bridge circuit 211 to the fourth H-bridge circuit 213 is similar to that of the first H-bridge control unit 204A'', and therefore description thereof will be omitted.

[0082] [Other embodiments] The present disclosure can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0083] [Technical Features of the Present Disclosure] The present disclosure includes the following configurations.

[0084] <Configuration 1> A motor driver comprising: monitoring means for monitoring a motor control signal for controlling a motor; timing means for measuring time when the PWM duty of the motor control signal monitored by said monitoring means does not change; resetting means for resetting the time measured by said timing means when the PWM duty of the motor control signal monitored by said monitoring means changes; determination means for determining whether the time measured is greater than a predetermined time threshold; and first output means for outputting a stop signal for stopping the motor based on the determination result of said determination means. <Configuration 2> The motor driver according to configuration 1, wherein the predetermined time threshold is a stop time set in a register. <Configuration 3> The motor driver according to configuration 1 or 2, further comprising second output means for outputting a reset signal to a CPU after the stop signal is output by the first output means. <Configuration 4> A motor driver according to any one of configurations 1 to 3, characterized in that when the determination means determines that the measured time is greater than a predetermined time threshold, the first output means outputs the stop signal. <Configuration 5> A motor driver according to any one of configurations 1 to 4, characterized in that even when the PWM duty of the motor control signal monitored by the monitoring means does not change, the resetting means resets the counting time in accordance with the PWM duty. <Configuration 6> The motor driver according to any one of configurations 1 to 5, wherein the monitoring means monitors a PWM duty of a phase signal among the motor control signals and an enable signal among the motor control signals, and when the enable signal monitored by the monitoring means is at a low level, the resetting means resets the counting time, and when the enable signal monitored by the monitoring means is at a high level and the PWM duty of the motor control signal monitored by the monitoring means is 50%, the resetting means resets the counting time. <Configuration 7> The motor driver according to any one of configurations 1 to 6, wherein the monitoring means monitors the PWM duty of a phase signal among the motor control signals, and when the PWM duty of the motor control signal monitored by the monitoring means is 0%, the resetting means resets the counting time. <Configuration 8> A motor driver according to any one of configurations 1 to 7, further comprising: a first register in which a first stop time is set as the stop time; a second register in which a second stop time is set as the stop time; and stop time setting means for applying either the first stop time or the second stop time as the predetermined time threshold in accordance with the PWM duty of the motor control signal monitored by the monitoring means. <Configuration 9> A motor driver according to any one of configurations 1 to 8, characterized in that when the PWM duty of the motor control signal monitored by the monitoring means is within a predetermined range, the stop time setting means applies the first stop time as the predetermined time threshold, and when the PWM duty of the motor control signal monitored by the monitoring means is not within the predetermined range, the stop time setting means applies the second stop time as the predetermined time threshold. <Configuration 10> The motor driver according to any one of configurations 1 to 9, wherein the first stop time is longer than the second stop time.

Claims

1. a monitoring means for monitoring a motor control signal for controlling the motor; a timer that measures time when the PWM duty of the motor control signal monitored by the monitor does not change; a reset means for resetting the time measured by the timer means when the PWM duty of the motor control signal monitored by the monitor means changes; a determination means for determining whether the measured time is greater than a predetermined time threshold; a first output means for outputting a stop signal for stopping the motor based on the determination result of the determination means; A motor driver comprising:

2. the predetermined time threshold is a stop time set in a register; 2. The motor driver according to claim 1.

3. The control device further includes a second output means for outputting a reset signal to a CPU after the first output means has output the stop signal.

3. The motor driver according to claim 2.

4. When the determination means determines that the measured time is greater than a predetermined time threshold, the first output means outputs the stop signal.

4. The motor driver according to claim 3.

5. Even if the PWM duty of the motor control signal monitored by the monitoring means does not change, the resetting means resets the count time in accordance with the PWM duty.

5. The motor driver according to claim 4.

6. the monitoring means monitors a PWM duty of a phase signal among the motor control signals and an enable signal among the motor control signals; When the enable signal monitored by the monitoring means is at a low level, the resetting means resets the time count; When the enable signal monitored by the monitoring means is at a high level and the PWM duty of the motor control signal monitored by the monitoring means is 50%, the resetting means resets the count time.

6. The motor driver according to claim 5.

7. the monitoring means monitors the PWM duty of a phase signal of the motor control signal, When the PWM duty of the motor control signal monitored by the monitoring means is 0%, the resetting means resets the time measurement.

6. The motor driver according to claim 5.

8. a first register in which a first stop time is set as the stop time; a second register in which a second stop time is set as the stop time; a stop time setting means for applying either the first stop time or the second stop time as the predetermined time threshold in accordance with the PWM duty of the motor control signal monitored by the monitoring means; Further comprising:

8. The motor driver according to claim 6 or 7.

9. When the PWM duty of the motor control signal monitored by the monitoring means is within a predetermined range, the stop time setting means applies the first stop time as the predetermined time threshold; When the PWM duty of the motor control signal monitored by the monitoring means is not within a predetermined range, the stop time setting means applies the second stop time as the predetermined time threshold.

9. The motor driver according to claim 8.

10. The first stop time is longer than the second stop time.

10. The motor driver according to claim 9.

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