Semiconductor integrated circuit

What is AI technical title?
AI technical title is built by Patsnap AI team. It summarizes the technical point description of the patent document.
The semiconductor integrated circuit design reduces pin usage for test mode by using a first and second signal input to terminals, enabling efficient and cost-effective testing without high-voltage circuits.

JP2025161278APending Publication Date: 2025-10-24NISSHINBO MICRO DEVICES INC

View PDF 3 Cites 0 Cited by

Patent Information

Application Number: JP2024064330
Authority / Receiving Office: JP · JP
Patent Type: Applications
Current Assignee / Owner
Filing Date: 2024-04-12
Publication Date: 2025-10-24

AI Technical Summary

Technical Problem

Existing semiconductor integrated circuits require a large number of pins for test mode settings, which is impractical, especially for analog ICs, and methods involving high-voltage circuits are costly and inefficient.

Method used

A semiconductor integrated circuit design that transitions to test mode using a first and second signal input to terminals, with a third signal terminating the test mode, reducing the need for dedicated pins by incorporating an enable circuit and test mode block.

Benefits of technology

The design reduces the number of pins required for test mode switching, lowers testing costs, and allows efficient testing without high-voltage circuits, maintaining low power consumption.

✦ Generated by Eureka AI based on patent content.

Smart Images

Figure 2025161278000001_ABST

Patent Text Reader

Abstract

To provide a semiconductor integrated circuit capable of reducing the number of pins for setting a test mode when setting a normal operation mode to the test mode in a semiconductor integrated circuit having a test mode circuit.SOLUTION: By inputting a first signal to a first terminal and inputting a second signal to a second terminal of a semiconductor integrated circuit, the semiconductor integrated circuit is shifted to a test mode selection mode capable of receiving a test mode selection signal. The semiconductor integrated circuit is temporarily set to a predetermined test mode by applying the test mode selection signal from a terminal other than the first and second terminals of the semiconductor integrated circuit. The semiconductor integrated circuit is configured to have means for ending the test mode selection mode and actually setting the predetermined test mode by inputting a third signal different from the first signal to the first terminal.SELECTED DRAWING: Figure 1

Need to check novelty before this filing date? Find Prior Art

Description

[Technical Field]

[0001] The present invention relates to a semiconductor integrated circuit, and more particularly to one that has a built-in test mode circuit and can be switched from a normal operation mode to a test mode. [Background technology]

[0002] When testing semiconductor integrated circuits, it is necessary to check not only whether they are operating properly, but also whether their performance meets the required specifications. Without any ingenuity, not only would high-performance measuring equipment be required for testing, but the testing time would increase, resulting in higher testing costs. Therefore, technology that embeds test circuits within semiconductor integrated circuit chips, i.e., DFT (Design For Testability) technology, represented by BIST (Built-In Self Test), shortens the testing process, which is prone to become a bottleneck, and improves throughput.

[0003] To use the above-mentioned DFT technology, it is necessary to provide pins or pads dedicated to testing on semiconductor integrated circuits. Therefore, as disclosed in Patent Documents 1 to 3, attempts have been made to reduce the number of pins used for testing by enabling semiconductor integrated circuits to switch between normal operation mode and test mode and inputting a predetermined signal into a pin for setting the test mode to switch to test mode. Specifically, Patent Document 1 discloses a method for enabling test mode even with a relatively small number of pins, since accessing many pins is practically difficult. Patent Document 2 discloses a method for avoiding the creation of new pins dedicated to test mode in order to maintain compatibility. Patent Document 3 discloses a method for easily setting test mode by applying a voltage higher than the normal value to an input pin. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4255953 [Patent Document 2] Patent No. 3917817 [Patent Document 3] Patent No. 2639319 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the methods of Patent Documents 1 and 2, for example, in a semiconductor integrated circuit with approximately 10 pins, the pins dedicated to test mode setting still account for a large proportion of the total, and even with these methods, many pins are still used for test mode. In particular, with analog ICs, it can be difficult to perform various settings and operations during power-on reset, making these methods impractical solutions. Furthermore, methods requiring high-voltage circuits, such as those in Patent Document 3, have problems such as high test equipment costs due to the need for circuits to apply high voltages, and large circuit size due to the need to increase the internal voltage resistance of the integrated circuit and prevent erroneous inputs caused by surges. Therefore, one of the objectives of the present invention is to provide a test circuit that can switch a semiconductor integrated circuit into test mode with a small number of pins. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor integrated circuit configured to include means for transitioning the semiconductor integrated circuit to a test mode selection mode capable of accepting a test mode selection signal by inputting a first signal to a first terminal of the semiconductor integrated circuit and a second signal to a second terminal thereof, for provisionally setting the semiconductor integrated circuit to a predetermined test mode by applying the test mode selection signal from a terminal other than the first and second terminals of the semiconductor integrated circuit, and for terminating the test mode selection mode and determining the predetermined test mode by inputting a third signal different from the first signal to the first terminal of the semiconductor integrated circuit. [Effects of the Invention]

[0007] According to one aspect of the present invention, there is provided a semiconductor integrated circuit having a test mode circuit, which can reduce the number of pins for test mode setting when switching from a normal operation mode to a test mode. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram illustrating a semiconductor integrated circuit according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of an enable circuit according to the first embodiment. [Figure 3] FIG. 10 is a diagram illustrating a semiconductor integrated circuit according to a second embodiment. [Figure 4] FIG. 10 is a diagram illustrating a semiconductor integrated circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0010] (First embodiment) A first embodiment will be described with reference to FIG. 1. A plurality of signal input / output terminals 23, an enable terminal 21, and a current detection terminal 22 are pins (external terminals) exposed from the molding resin of a semiconductor integrated circuit chip, and are electrically connectable to a test mode block 3. A signal from the test mode block 3 is output to a test mode signal output terminal 24, which is an output terminal inside the semiconductor integrated circuit. The enable circuit 1 and the test mode block 3 are built into the semiconductor integrated circuit and do not operate in the normal operation mode of the semiconductor integrated circuit, but only when testing the semiconductor integrated circuit. These terminals and built-in circuits together constitute a test mode circuit. Each component of the test mode circuit in this embodiment will be described in detail below, followed by a detailed description of the circuit operation. Note that when expressing high and low voltages, a high level may be written as H and a low level as L.

[0011] <Input terminal> The enable terminal 21 is the first input terminal in the test mode, and the current detection terminal 22 is the second input terminal in the test mode. The test mode is started, maintained, changed, and ended by applying voltages to these two terminals. What is generally called an enable terminal is used to enable or disable the output of an IC, and in normal operating mode, a high-level voltage is applied to enable the output of the semiconductor integrated circuit. Conversely, applying a low-level voltage disables (stops) the output. This can be used to achieve low power consumption, so it is sometimes called a control terminal. To change the voltage level applied to the enable terminal 21, for example, a configuration can be adopted in which a divided voltage of the power supply is applied to the enable terminal 21 via dividing resistors, and one of the dividing resistors is switched to another resistor of a different value using a switch.

[0012] On the other hand, the second input terminal, current detection terminal 22, is a terminal connected to, for example, an external shunt resistor, and receives a signal with little change in potential during normal operation. The voltage level applied to current detection terminal 22 can be changed by connecting a series circuit of a current source and resistor that can apply high or low level voltage to current detection terminal 22 via a switch. Whether the applicable voltage is high or low level can be selected arbitrarily by setting the shunt resistor to either ground potential or power supply voltage, but in Figure 1, the applicable voltage is set to high level.

[0013] <Enable circuit> The enable circuit 1 outputs a low signal when the voltage input from the enable terminal 21 exceeds Vth1 and a high signal when the voltage is below Vth1. The output of the enable circuit 1 also goes high when the voltage falls below Vth2, which is lower than Vth1 and higher than ground potential. These thresholds Vth1 and Vth2 may have hysteresis. The enable circuit 1 can be implemented using a UVLO circuit that detects drops in the power supply voltage. For example, the circuit configuration shown in Figure 2 can be used. An example configuration of the enable circuit 1 is described below with reference to Figure 2. The voltage applied to the enable terminal 21 is input to the non-inverting input terminal of the comparator 11 via voltage-dividing resistors 13 and 14 and compared with a reference potential 15 connected to the inverting input terminal of the comparator. If the divided voltage level is higher than the reference potential, the comparator 11 outputs a high signal; if it is lower, the comparator 11 outputs a low signal. The inverter 12 inverts the output of the comparator 11 and outputs it to terminal 17. The bias for the comparator 11 and the inverter 12 is supplied from the enable terminal 21, and the connection node between the output of the inverter 12 and the terminal 17 is connected to the ground potential via the resistor 16. With this configuration, the operation of the enable circuit 1 described above can be realized by setting the reference potential 15 to Vth1 and the minimum bias value at which the operation of the inverter 12 can be maintained to Vth2.

[0014] <Test mode block> The test mode block 3 comprises a bus line 31, an AND circuit 32, a power-on reset circuit 34, an SR latch 35, an inverter 36, a decoder circuit 37, a switch 38, and a D flip-flop 39. Here, the signal input / output terminals 23 and the decoder circuit 37 can exchange data via the bus lines 31. However, because each bus line 31 has a switch 38 inserted therein, data cannot be transferred unless the switch 38 is turned on. Furthermore, the D flip-flop 39 is a type that captures data with a rising edge trigger, and data is not transferred to the decoder circuit 37 via the bus line 31 unless this trigger input is received. Therefore, when the semiconductor integrated circuit is placed in the normal operation mode, the switch 38 is turned off, preventing a trigger input to the D flip-flop 39. When the semiconductor integrated circuit is placed in the test mode, the switch 38 is turned on, allowing a trigger input to the D flip-flop 39. In this embodiment, before a complete transition to the test mode occurs, the system transitions to the test mode selection mode, and in this mode, the switch 38 is turned on, but no trigger input is made to the D flip-flop 39. The power-on reset circuit 34 is used as a tool for mode transition, but it does not need to be provided as a dedicated test circuit; a circuit already built into the semiconductor integrated circuit may be used. Next, the circuit operation will be described in detail for each mode.

[0015] <Normal operation mode> Needless to say, the semiconductor integrated circuit of this embodiment is in normal operation mode by default. Normal operation mode refers to a normal operating state in which the semiconductor integrated circuit produces a predetermined output in response to an input. In this embodiment, if no operation is performed after power-on, the semiconductor integrated circuit will be in normal operation mode. The process from power-on to normal operation mode will be described below. First, upon power-on, the voltage applied to the enable terminal 21 rises to a high level exceeding Vth1. During this time, a low-level voltage is applied to the current detection terminal 22, so the output of the AND circuit 32 is low, which is applied to the set input of the SR latch 35. The output of the power-on reset circuit 34 is high when the power supply voltage is low, and the output signal changes from high to low a predetermined time after power-on. Therefore, immediately after power-on, a high level is applied to the reset input of the SR latch 35, initializing the Q output to low. The Q output is applied to the reset terminals of all D flip-flops 39, resetting the D flip-flops 39 and forcibly changing their outputs to low. Meanwhile, the output of the enable circuit 1 is inverted by the inverter 36, and a high level is applied to the clock input of the D flip-flops 39, but the outputs of the D flip-flops 39 remain low. Furthermore, the switch 38, whose gate is connected to the Q output of the SR latch 35, is turned off. In this way, after power is turned on, the switch 38 is in the off state and the D flip-flop 39 remains in the reset state, so that the normal operating mode is entered in which signals applied to the multiple signal input / output terminals 23 are not transmitted to the decoder circuit 37.

[0016] <Test mode selection mode> Next, the transition to the test mode selection mode, that is, the start of the test mode, will be described. The start of the test mode is performed by changing the voltages applied to the enable terminal 21 and the current detection terminal 22, as described above. First, a High-level voltage is applied to current detection terminal 22, and then the voltage applied to enable terminal 21 is reduced to between Vth2 and Vth1. As a result, the output of the enable circuit goes High, causing the output of AND circuit 32 to also go High, which is applied to the set input of SR latch 35, causing the Q output to go High, releasing the reset of D flip-flop 39 and switching switch 38 to the ON state. Meanwhile, the output of the enable circuit is inverted by inverter 36 and Low is applied to the clock input of D flip-flop 39, but the output of D flip-flop 39 remains unchanged and remains Low.

[0017] As a result of the above, the multiple input / output terminals 23 and the multiple bus lines 31 are connected via the switches 38. However, even if a signal is input to each of the multiple input / output terminals 23, the D flip-flop 39 does not take in the data, so no significant signal is input to the decoder circuit 37. This state is the test mode selection mode, and any signal can be applied to each of the multiple input / output terminals 23 without affecting subsequent stages. First, to select a test mode, a test mode selection signal is applied. This may be a combination of H or L signals. In this case, the test mode selection signal is binary, so if there are k input / output terminals 23, for example, 2 to the power of k test mode selection signals can be prepared. In this embodiment, a TMode terminal 25 is provided as shown in Fig. 1. This TMode terminal 25 is connected to the Q output of the SR latch 35, so when the mode is changed to the test mode selection mode, H is output to this terminal. This signal can be used to stop the output terminal of the IC via a selector switch (not shown). Therefore, the output terminal of the IC can also be used to input the test mode selection signal. As described above, in normal operation mode, all input terminals, including those that serve as output terminals of the IC, can be used to temporarily set the test mode.

[0018] <Test mode> After the application of the test mode selection signal has finished, the voltage applied to the enable terminal 21 is reduced below Vth2, causing the output of the enable circuit 1 to go low, the output of the inverter 36 to go high, and the clock input of the D flip-flop 39 to go high. This confirms the test mode as provisionally set. The decoder circuit 37 shown in the figure is composed of a combinational logic circuit, and generates a test mode signal according to the test mode selection signal and transfers the test mode signal to the subsequent circuit block via 2k test mode signal output terminals 24. The test mode signal is output in such a way that the potential of one test mode signal output terminal 24 is high and the potential of the other test mode signal output terminals 24 is low.

[0019] A test mode signal is applied to a predetermined node of each circuit block in the semiconductor integrated circuit, activating only one circuit block as the target of the test. All k input / output terminals can be used to input the test signal during the test. A node (not shown) can be provided between each switch 38 and each D flip-flop 39, connectable to the input or output of each circuit block. After the test mode is established, the input / output or output of the activated circuit block can be connected to the node via a response switch (not shown), electrically connecting the input / output terminal 23 to the activated circuit block. This allows various test signals to be input through several input / output terminals 23, and corresponding outputs can be output to other input / output terminals 23. The input / output terminals 23 to which the test signal is output can be determined appropriately in association with a test mode selection signal. In other words, in response to a specific test mode selection signal, an internal signal of the semiconductor integrated circuit can be output to a specific one of the other terminals via the response switch. The response switch can be a MOS transistor or a bipolar transistor, the control electrode of which receives a signal linked to the test mode selection signal.

[0020] In test mode, the Q output of the SR latch 35 is fixed at H and the reset of the D flip-flop 39 is released, so the D flip-flop 39 does not acquire data unless a trigger input is received. Therefore, it is possible to apply another test mode selection signal immediately after lowering the voltage applied to the enable terminal 21 below Vth2. To change to another test mode, after applying another test mode selection signal to the input / output terminal 23, return the voltage applied to the enable terminal 21 to a range between Vth2 and Vth1, and then lower the voltage applied to the enable terminal 21 below Vth2. This input triggers the D flip-flop 39, allowing it to acquire data and change to another test mode. Note that, as long as a trigger input is received after the application of another test mode selection signal, the application of another test mode selection signal and the return of the voltage applied to the enable terminal 21 from a range between Vth2 and Vth1 may occur in any order.

[0021] In this embodiment, the Q output of SR latch 35 does not change unless there is a trigger input from power-on reset circuit 34, and is therefore fixed to the H level regardless of the voltage level applied to current detection terminal 22. Therefore, after transitioning to test mode, current detection terminal 22 can also be used to input a test signal and output a signal corresponding to the test signal.

[0022] <Exiting test mode> After the test is completed, the test mode can be exited by turning off the power. Turning off the power returns the power-on reset circuit 34 to its initial state, so turning the power back on will return the device to normal operation mode. To return to test mode, the device can be re-entered by applying the predetermined potential to the enable terminal 21 and the current detection terminal 22, as described above.

[0023] (Second embodiment) The second embodiment will be described with reference to FIG. 3. In this figure, the same reference numerals as in FIGS. 1 and 2 indicate the same or corresponding components. This embodiment includes a regulator 33 as an internal power supply. This regulator 33 does not need to be prepared as a circuit dedicated to the test circuit, and a regulator already built into the semiconductor integrated circuit may be used. Circuit operation will be described in detail below by mode.

[0024] <Normal operation mode> First, when power is turned on, the voltage applied to enable terminal 21 rises to a high level exceeding Vth1, and H is applied to the first input of regulator 33 via terminal 18 (FIG. 2) of enable circuit 1, causing regulator 33 to start up and begin supplying power to power-on reset circuit 34 and other circuits in test mode block 3. The signal from terminal 18 is connected to the control electrode of a first normally-off switch (not shown) in regulator 33, and regulator 33 continues to operate as long as the signal is H. During this time, the voltage applied to current detection terminal 22 is low, and the output of AND circuit 32 also becomes L, which is applied to the set input of SR latch 35. The output of power-on reset circuit 34 outputs H when the voltage supplied from regulator 33 is low, and the output signal changes from H to L after a predetermined time has passed since power was turned on and the output level of regulator 33 reaches a predetermined value. Therefore, SR latch 35, which receives the output of power-on reset circuit 34 at its reset input, is initialized immediately after power is turned on, and its Q output is applied to the reset terminals of all D flip-flops 39, resetting D flip-flops 39 and forcibly setting their outputs to L. Meanwhile, the output of enable circuit 1 is inverted by inverter 36, and H is applied to the clock input of D flip-flop 39, but the output of D flip-flop 39 remains L. Also, switch 38, whose gate is connected to the Q output of SR latch 35, is turned off. In this way, normal operation mode is achieved after power is turned on.

[0025] <Test mode selection mode> As in the first embodiment, the test mode is initiated by changing the voltages applied to the enable terminal 21 and the current detection terminal 22. First, a High-level voltage is applied to current detection terminal 22, and then the voltage applied to enable terminal 21 is reduced to between Vth2 and Vth1. As a result, the output of the enable circuit goes High, causing the output of AND circuit 32 to also go High, which is applied to the set input of SR latch 35, causing the Q output to go High, releasing the reset of D flip-flop 39 and switching switch 38 to the ON state. Meanwhile, the output of the enable circuit is inverted by inverter 36 and Low is applied to the clock input of D flip-flop 39, but the output of D flip-flop 39 remains unchanged and remains Low.

[0026] As a result of the above, the test mode selection mode is entered, and it becomes possible to apply a High or Low signal to each of the plurality of input / output terminals 23 as appropriate without affecting subsequent stages. Then, when the application of the test mode selection signal is completed, a state in which an H or L signal is applied to each of the plurality of input / output terminals 23 is achieved, similar to the first embodiment. The nature of the test mode selection signal is also similar to the first embodiment.

[0027] This embodiment differs from the first embodiment in that power is supplied by a regulator 33 to the circuits that make up the test mode block 3. The regulator can supply precise power with little fluctuation to the circuits, thereby achieving low power consumption. 3, it is possible to maintain the operating state of regulator 33 by adding OR circuit 4, connecting its input to current detection terminal 22 and the Q output of SR latch 35, and connecting its output to the second input of regulator 33. Note that the signal from OR circuit 4 is connected to the control electrode of a second normally-off switch (not shown) in regulator 33, and since this switch is connected in parallel with the first normally-off switch, regulator 33 continues to operate as long as the output of OR circuit 4 is H.

[0028] <Test mode> As in the first embodiment, when application of the test mode selection signal has finished, the voltage applied to the enable terminal 21 is reduced below Vth2 to perform a trigger input to the D flip-flop 39, a signal is transferred to the decoder 37 in accordance with the test mode selection signal, and a test signal is input to each circuit block via the test mode signal output terminal 24. The function of the decoder circuit 37, details of the test signal, and changes in test mode are also the same as in the first embodiment. The difference from the first embodiment is that the Q output of the SR latch 35 is fixed to H and the output of the OR circuit 4 is maintained at H, so that the regulator 33 maintains an operating state regardless of the input to the current detection terminal. As described in the first embodiment, all of the external terminals of the semiconductor integrated circuit except for the enable terminal 21 can be used for signal input and output.

[0029] <Exiting test mode> The test mode can be exited by turning off the power supply, as in the first embodiment. Turning off the power cuts off the power supply to the regulator 33, and the power-on reset circuit 34 returns to its initial state. When the power is turned on again, the normal operation mode is restored. To return to the test mode, the voltage of the predetermined level is applied to the enable terminal 21 and the current detection terminal 22, as in the first embodiment.

[0030] (Third embodiment) A third embodiment will be described with reference to FIG. 4. In this figure, the same reference numerals as in FIGS. 1 to 3 indicate the same or corresponding components. In this embodiment, a decoder 37 is provided with a control terminal 310, and further includes an inverter 311 that inverts the output of the control terminal 310, and an AND circuit 312 that receives the outputs of the inverter 311 and the SR latch 35 as inputs, and the output of the AND circuit 312 is connected to one input of the OR circuit 4. In the second embodiment, one input of the OR circuit 4 was connected to the current detection terminal 22, and the other was connected to the Q output of the SR latch 35, but in this embodiment, the output of the AND circuit 312 is connected instead of the Q output of the SR latch 35. As in the second embodiment, this embodiment can achieve low power consumption because power is supplied to the circuits that make up the test mode block 3 by the regulator 33. This embodiment differs from the second embodiment in that the output of the OR circuit 4 can be changed to L by a specific test mode selection signal. Circuit operation will be described in detail below for each mode.

[0031] <Normal operation mode> As in the second embodiment, when the power is turned on, the Q output of the SR latch 35 goes low, and the output of the AND circuit 312 also goes low. Therefore, the output of the OR circuit 4 remains low unless the voltage applied to the current detection terminal 22 goes high, resulting in the same initial state as in the second embodiment. That is, the normal operation mode is entered when the power is turned on. The initial state of the control terminal 310 of the decoder 37 is low, and the output of the inverter 311 that receives this goes high.

[0032] <Test mode selection mode> As in the first and second embodiments, the test mode is initiated by changing the voltages applied to the enable terminal 21 and the current detection terminal 22. First, a High-level voltage is applied to current detection terminal 22, and then the voltage applied to enable terminal 21 is reduced to between Vth2 and Vth1. As a result, the output of the enable circuit goes High, causing the output of AND circuit 32 to also go High, which is applied to the set input of SR latch 35, causing the Q output to go High, releasing the reset of D flip-flop 39 and switching switch 38 to the ON state. Meanwhile, the output of the enable circuit is inverted by inverter 36 and Low is applied to the clock input of D flip-flop 39, but the output of D flip-flop 39 remains unchanged and remains Low.

[0033] As a result, the test mode selection mode is entered, and it becomes possible to apply a High or Low signal to each of the plurality of input / output terminals 23 as appropriate without affecting subsequent stages. Then, when the application of the test mode selection signal is completed, a High or Low signal is applied to each of the plurality of input / output terminals 23, as in the first and second embodiments. The nature of the test mode selection signal is also the same as in the first and second embodiments.

[0034] <Test mode> As in the first and second embodiments, when application of the test mode selection signal has finished, the voltage applied to the enable terminal 21 is reduced below Vth2 to perform a trigger input to the D flip-flop 39, a signal is transferred to the decoder 37 in accordance with the test mode selection signal, and a test signal is input to each circuit block via the test mode signal output terminal 24. The function of the decoder circuit 37, the details of the test signal, and the change of the test mode are also the same as in the first and second embodiments. The difference from the second embodiment is that the Q output of the SR latch 35 is not input directly to the OR circuit 4 but passes through the AND circuit 313. However, as described above, the initial state of the control terminal 310 of the decoder 37 is L and the output of the AND circuit 313 remains H, so the regulator 33 remains in an operating state regardless of the input to the current detection terminal. Also, as in the first and second embodiments, all of the external terminals of the semiconductor integrated circuit except for the enable terminal 21 can be used for signal input and output.

[0035] <Exiting test mode> In the first and second embodiments, exiting test mode was accomplished by turning off the power supply. However, in this embodiment, test mode can be exited without turning off the power supply. As described above, this is because the output of the OR circuit 4 can be changed to L by a specific test mode selection signal, which stops the operation of the regulator 33 and returns the power-on reset to its initial state. In test mode, the Q output of the SR latch 35 is fixed to H, so the output of the OR circuit 4 cannot be changed to L unless the output of the AND circuit 313 is set to L. Therefore, the output of the control terminal 310, which is initially L, must be changed to H. This operation is nothing more than inputting specific test mode selection signals to multiple signal input / output terminals 23. For example, the decoder circuit 37 may be configured so that the output of the control terminal 310 becomes H when H is input to all signal input / output terminals 23. In this case, all inputs to the decoder 37 are H, and the logical AND of all these inputs results in H. This is then output to the control terminal 310.

[0036] Although the preferred embodiments of the present invention have been described in detail above, various modifications and variations of the present invention can be made within the technical scope of the present invention. In the first to third embodiments, an enable terminal is used as the first input terminal and a current detection terminal is used as the second input terminal. However, other terminals can also be used. However, for a terminal that enables or disables a semiconductor integrated circuit, such as an enable terminal, a voltage of either a high or low level is typically applied. Therefore, using the voltage of the level that stops the output as a signal to transition to test mode is convenient because no interference occurs within the circuit. Similarly, for a terminal such as a current detection terminal, which has a current detection resistor connected to it and is connected to ground or a power supply and to which a voltage of either a high or low level is applied during normal operation, using the opposite voltage, either a low or high level, as a signal to transition to test mode is convenient because no interference occurs within the circuit. Furthermore, in the first to third embodiments, a power-on reset circuit is used as the timing element, but this can be replaced with a different circuit, such as a timer, counter, soft start circuit, etc., as appropriate, depending on the circuit scale and the purpose of the test. However, semiconductor integrated circuits with large circuit scales generally have a built-in power-on reset circuit, and using this circuit will provide cost benefits. Although a decoder circuit is used in the first to third embodiments, a parallel-input, serial-output shift register may be used to perform a predetermined test based on the read data. However, a decoder circuit using a combinational logic circuit can be used without increasing the circuit size. Furthermore, logic circuits such as logic gates such as NOT, OR, and AND, and flip-flops are used, but these can be replaced with other logic circuits. [Explanation of symbols]

[0037] 1: Enable circuit, 21: Enable terminal, 22: Current detection terminal, 23: Signal input / output terminal, 24: Test mode signal output terminal, 25: TMode terminal, 3: Test mode block, 31: Bus line, 32, 312: AND circuit, 33: Regulator, 34: Power-on reset circuit, 35: SR latch, 36, 311: Inverter, 37: Decoder circuit, 38: Switch, 39: D flip-flop, 4: OR circuit,

Claims

1. A semiconductor integrated circuit having a test mode circuit that transitions from a normal operation mode to a test mode, The test mode circuit inputting a first signal to a first terminal of the semiconductor integrated circuit and a second signal to a second terminal thereof, thereby transitioning the semiconductor integrated circuit to a test mode selection mode in which the semiconductor integrated circuit can receive a test mode selection signal; a means for ending the test mode selection mode and determining a predetermined test mode when the test mode selection signal is applied from a terminal other than the first and second terminals of the semiconductor integrated circuit and a third signal different from the first signal is input to the first terminal of the semiconductor integrated circuit.

2. the first terminal is an enable terminal, the first signal input to the first terminal is a voltage equal to or lower than a first threshold value for switching an output of the semiconductor integrated circuit from on to off, and equal to or higher than a second threshold value that is not a ground potential; the third signal is a voltage lower than the second threshold value; 2. The semiconductor integrated circuit according to claim 1.

3. the second terminal is a terminal to which a voltage signal with a small difference in level is input in a normal operation mode, the second signal input to the second terminal is either a voltage higher than the voltage signal and lower than a power supply voltage, or a voltage lower than the voltage signal.