Storing data in memory system

Abstract

To provide a method capable of correcting data errors.SOLUTION: A method for operating a memory system comprises: receiving a first write command to write first user data to a memory device; generating first parity data corresponding to the first user data based on a first encoding algorithm; storing the first user data and the first parity data in a memory block of the memory device of the memory system; receiving a second write command to write second user data to the memory device; generating second parity data corresponding to the second user data based on a second encoding algorithm, the second encoding algorithm being different from the first encoding algorithm; and storing the second user data and the second parity data in the same memory block as the first user data and the first parity data.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to memory devices and systems for storing data. [Background technology]

[0002] A memory system can include one or more memory devices and a memory controller that manages data stored in the one or more memory devices and communicates with a host. The memory system can be a non-volatile memory (e.g., NAND flash memory) that stores data in memory pages and erases data in memory blocks containing multiple memory pages. In some cases, errors in the stored data can result in read failures and affect the reliability of the memory system. The memory system can detect and correct errors in the stored data by using an error correcting code (ECC). Summary of the Invention

[0003] The present disclosure relates to storing data in a memory system. In one embodiment, a method of operating a memory system includes receiving a first write command to write first user data to a memory device. The method further includes generating first parity data corresponding to the first user data based on a first encoding algorithm. The method further includes storing the first user data and the first parity data in a memory block of a memory device of the memory system. The method further includes receiving a second write command to write second user data to the memory device. The method further includes generating second parity data corresponding to the second user data based on a second encoding algorithm, the second encoding algorithm being different from the first encoding algorithm. The method further includes storing the second user data and the second parity data in the same memory block as the first user data and the first parity data.

[0004] The method can include one or more of the following features.

[0005] In some implementations, the second user data and the second parity data are stored in the same memory block as the first user data and the first parity data.

[0006] In some implementations, the first parity data and the second parity data include low-density parity-check (LDPC) parity data, the first encoding algorithm includes a first LDPC matrix, and the second encoding algorithm includes a second LDPC matrix.

[0007] In some implementations, the method further includes storing a first identifier of the first user data in a memory controller of the memory system and a second identifier of the second user data in the memory controller, the first identifier corresponding to the first encoding algorithm, and the second identifier corresponding to the second encoding algorithm.

[0008] In some implementations, the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table.

[0009] In some implementations, the logical address of the first user data is mapped to a first identifier in the P2L mapping table, and the logical address of the second user data is mapped to a second identifier in the P2L mapping table.

[0010] In some implementations, the method further includes identifying a first LDPC matrix based on the first identifier, and decoding the first parity data based on the first LDPC matrix.

[0011] In some implementations, the first user data is contained in logical blocks of a first format and the second user data is contained in logical blocks of a second format.

[0012] Certain aspects of the subject matter described herein can be implemented as a memory system. The memory system can include one or more memory devices and a memory controller coupled to the one or more memory devices. The memory system is configured to perform operations including receiving a first write command to write first user data to the one or more memory devices. The operation further includes generating first parity data corresponding to the first user data based on a first encoding algorithm. The operation further includes storing the first user data and the first parity data in memory blocks of the memory devices of the memory system. The operation further includes receiving a second write command to write second user data to the one or more memory devices. The operation further includes generating second parity data corresponding to the second user data based on a second encoding algorithm, the second encoding algorithm being different from the first encoding algorithm. The operation further includes storing the second user data and the second parity data in the same memory blocks as the first user data and the first parity data.

[0013] The memory system may include one or more of the following features.

[0014] In some implementations, the second user data and the second parity data are stored in the same memory block as the first user data and the first parity data.

[0015] In some implementations, the first parity data and the second parity data include low-density parity-check (LDPC) parity data, the first encoding algorithm includes a first LDPC matrix, and the second encoding algorithm includes a second LDPC matrix.

[0016] In some implementations, the operations further include storing a first identifier of the first user data in a memory controller of the memory system and a second identifier of the second user data in the memory controller, the first identifier corresponding to the first encoding algorithm, and the second identifier corresponding to the second encoding algorithm.

[0017] In some implementations, the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table, where a logical address of the first user data is mapped to the first identifier in the P2L mapping table and a logical address of the second user data is mapped to the second identifier in the P2L mapping table.

[0018] In some implementations, the first user data is contained in logical blocks of a first format and the second user data is contained in logical blocks of a second format.

[0019] Certain aspects of the subject matter described herein can be implemented as a memory controller. The memory controller can include a first interface, a second interface, and an encoder. The first interface can be configured to receive a first write command including first user data and a second write command including second user data. The encoder can be configured to generate first parity data corresponding to the first user data based on a first encoding algorithm and generate second parity data corresponding to the second user data based on a second encoding algorithm. The second encoding algorithm is different from the first encoding algorithm. The second interface can be configured to send a third write command to write the first user data and the first parity data to a memory block of the memory device and send a fourth write command to write the second user data and the second parity data to the memory block.

[0020] The memory system may include one or more of the following features.

[0021] In some implementations, the memory controller is configured to control the memory device to store the second user data and the second parity data in the same memory block as the first user data and the first parity data.

[0022] In some implementations, the memory controller can further include a decoder. The second interface can be further configured to receive first user data and first parity data from the memory blocks and second user data and second parity data from the memory blocks. The decoder can be configured to decode the first parity data based on a first encoding algorithm and to decode the second parity data based on a second encoding algorithm.

[0023] In some implementations, the memory controller is further configured to store a first identifier of the first user data in the memory controller and a second identifier of the second user data in the memory controller, the first identifier corresponding to the first encoding algorithm and the second identifier corresponding to the second encoding algorithm.

[0024] In some implementations, the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table, where a logical address of the first user data is mapped to the first identifier in the P2L mapping table and a logical address of the second user data is mapped to the second identifier in the P2L mapping table.

[0025] In some implementations, the first parity data and the second parity data include low-density parity-check (LDPC) parity data, the first encoding algorithm includes a first LDPC matrix, and the second encoding algorithm includes a second LDPC matrix.

[0026] While generally described as computer-implemented software embodied on a tangible medium that processes and transforms respective data, some or all of the present aspects may be computer-implemented methods for performing the functions described herein, or may further be included in respective systems or other devices. These and other aspects and implementation details of the present disclosure are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the present disclosure will be apparent from the specification and drawings, and from the claims. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a block diagram of an example system having a memory device in accordance with some aspects of the present disclosure. [Figure 2A] FIG. 1 illustrates an example storage product in accordance with some aspects of the present disclosure. [Figure 2B] FIG. 1 illustrates an example storage product in accordance with some aspects of the present disclosure. [Figure 3] FIG. 1 illustrates an example of a schematic diagram of a memory device including peripheral circuitry, in accordance with some aspects of the present disclosure. [Figure 4] FIG. 1 illustrates some example peripheral circuits according to some aspects of the present disclosure. [Figure 5A] FIG. 1 is a block diagram of an example system including a memory device, a memory controller, and a host, in accordance with some aspects of the present disclosure. [Figure 5B] FIG. 1 is a block diagram of an example system including a memory device, a memory controller, and a host, in accordance with some aspects of the present disclosure. [Figure 6A] FIG. 2 illustrates an example data structure in an LBA format, according to some aspects of the present disclosure. [Figure 6B] FIG. 10 illustrates another example data structure in LBA format, according to some aspects of the present disclosure. [Figure 7]FIG. 1 illustrates an example physical-to-logical (P2L) mapping table in accordance with some aspects of the present disclosure. [Figure 8] FIG. 1 illustrates an example data structure of a write command in accordance with some aspects of the present disclosure. [Figure 9] FIG. 1 illustrates an example method for writing data to a memory system in accordance with some aspects of the present disclosure. [Figure 10] FIG. 1 illustrates an example method for reading data from a memory system in accordance with some aspects of the present disclosure. [Figure 11] 1 is a flow diagram of an example method for storing data in a memory system in accordance with some aspects of the present disclosure.

[0028] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0029] To ensure data integrity and system reliability, error correction is performed in memory systems. Various factors, such as physical defects in memory cells, electrical noise, thermal fluctuations, and natural aging of memory systems, can cause errors in data stored in memory systems. Such errors, specifically, erroneous bits in data, can lead to read failures or data loss. Memory systems can maintain data accuracy by detecting and correcting errors using error-correcting codes (ECCs). For example, memory systems can process data using low-density parity check (LDPC) codes for error correction. When receiving user data from a host, the memory system can encode the user data by generating parity data using an LDPC matrix. Both the user data and the corresponding parity data are stored in a memory device of the memory system. During a read operation, the memory system can retrieve the user data and the corresponding parity data from the memory device. The memory system can also detect and correct erroneous bits in the data using the LDPC matrix.

[0030] In some implementations, a memory system can be configured to receive user data in different logical block addressing (LBA) formats. For example, the memory space of the memory system can be logically divided into multiple namespaces. Each namespace can have a corresponding LBA format. That is, the formats of logical blocks in different namespaces can be different. The memory system can encode user data in different LBA formats using different encoding algorithms (e.g., different LDPC matrices).

[0031] In some implementations, memory blocks in a memory device store user data and corresponding parity data in the same LBA format. If the LBA format receives user data that differs from previous user data, a different memory block can be used to store the user data and the corresponding parity data. Thus, a memory system may contain an excessive number of free memory blocks (i.e., memory blocks that are partially filled with data but still have space to store additional data), which may increase demands on hold-up capacitors in the memory controller of the memory system that retain data in the event of a power failure. An excessive number of free memory blocks may also increase demands on redundant array of independent disks (RAID) resources, resulting in higher hardware costs for the memory system.

[0032] In some implementations, memory blocks within a memory device can store user data and corresponding parity data in various LBA formats. In response to receiving user data whose LBA format differs from previous user data, the memory device can store the user data and corresponding parity data in the same memory block as the previous user data without opening a separate memory block. The memory system can record an identifier indicating an encoding algorithm for encoding the user data in each LBA format. Therefore, optimizing the allocation of free memory blocks within the memory device can further improve the cost and power efficiency of memory system operation.

[0033] These and several other aspects of the disclosure are described in more detail below.

[0034] FIG. 1 illustrates a block diagram of an example system 100 having a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As seen in FIG. 1 , the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may include one or more processors of the electronic device. The processor may be a central processing unit (CPU) or a system-on-chip (SoC) such as an application processor (AP). The host 108 may be configured to send and receive data and commands to and from the memory system 102.

[0035] The memory device 104 can be any memory device disclosed in this disclosure, such as a NAND flash memory device. Note that NAND flash is merely one example of a memory device for illustrative purposes. This can include any suitable solid-state non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), spin-transfer torque magnetic random access memory (STT-RAM), or resistive random access memory (RRAM). In some implementations, the memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0036] The memory controller 106 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gate logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform various functions described in more detail below.

[0037] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low-duty-cycle environments, such as with Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in high-duty-cycle environments, such as with solid-state drives (SSDs) or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, and laptop computers, and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, logical-to-physical mapping management, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correcting codes (ECC) on data read from or written to memory device 104. Other suitable functions, such as formatting memory device 104, may be performed by memory controller 106 as well.

[0038] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with an external device through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc. The memory controller 106 is configured to receive and send commands to and from the host 108 and to perform or execute several functions and operations provided in this disclosure, as described below.

[0039] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices. For example, the memory controller 106 and one or more memory devices 104 can be packaged into a Universal Flash Storage (UFS) package or an eMMC package. In the embodiment shown in FIG. 2A , the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA: Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, etc. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 of FIG. 1 ). 2B , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 of FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0040] FIG. 3 illustrates an example of a schematic diagram of a memory device 300 including peripheral circuitry according to some aspects of the present disclosure. The memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically on a substrate (not shown in FIG. 3 ). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped in the storage layer of the memory cell 306. The logic state (i.e., data) of each memory cell 306 in a memory block 304 is determined by the threshold voltage V of the memory cell 306. th Each memory cell 306 may be a floating gate memory cell including a floating gate transistor, or a charge trapping memory cell including a charge trapping transistor.

[0041] In some implementations, each memory cell 306 is a single-level cell (SLC) with two possible memory states capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing two or more bits of data in three or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to support a range of possible nominal storage values. In one embodiment, if each MLC stores two bits of data, the MLC can be programmed from the erased state to one of three possible programming levels by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0042] 3 , each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate a selected NAND memory string 308 (a column of the array) during read and program operations. In some implementations, the sources of NAND memory strings 308 within the same memory block 304 are coupled through the same source line (SL) 314, e.g., a common SL. That is, according to some implementations, NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some implementations, the DSG 312 of each NAND memory string 308 is coupled to a respective bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor comprising DSG 312) or a deselect voltage (e.g., 0V) to the respective DSG 312 through one or more DSG lines 313, and / or by applying a select voltage (e.g., above the threshold voltage of the transistor comprising SSG 310) or a deselect voltage (e.g., 0V) to the respective SSG 310 through one or more SSG lines 315.

[0043] As shown in FIG. 3 , the NAND memory strings 308 can be organized into multiple memory blocks 304, and each memory block can have a common SL 314 coupled to an ACS. In some implementations, each memory block 304 can serve as a basic data unit for an erase operation, such that memory cells 306 in the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, the SLs 314 coupled to the selected memory block 304 and deselected memory blocks in the same plane can be biased with an erase voltage. For example, the erase voltage can be a high positive voltage (e.g., 20 V or greater). In some implementations, the erase operation can be performed at a half-block level, a quarter-block level, or any suitable number or fraction of memory blocks.

[0044] Memory cells 306 of adjacent NAND memory strings 308 can be coupled through word lines 318. The word lines 318 can select a row of memory cells 306 to be affected by read and program operations. Each word line 318 can include a gate line that couples to multiple control gates (gate electrodes) of multiple memory cells 306. The example word lines shown in FIG. 3 are between one or more DSG lines 313 and one or more SSG lines 315.

[0045] 4 illustrates some example peripheral circuits 302 according to some embodiments of the present disclosure. The peripheral circuits 302 can be coupled to the memory cell array 301 through bit lines 316, word lines 318, SL lines 314, SSG lines 315, and DSG lines 313. The peripheral circuits 302 can include any suitable analog, digital, and mixed-signal circuitry for supporting operation of the memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 through the bit lines 316, word lines 318, SL lines 314, SSG lines 315, and DSG lines 313. The peripheral circuits 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. The example peripheral circuits 302 include a page buffer / sense amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage source 410, control logic 412, registers 414, an interface 416, and a data bus. In some embodiments, additional peripheral circuits not shown in FIG. 4 may also be included.

[0046] The page buffer / sense amplifier 404 can be configured to read and program (write) data to and from the memory cell array 301 according to control signals from the control logic 412. In one embodiment, the page buffer / sense amplifier 404 can store a page of program data (write data) to be programmed into a page 320 of the memory cell array 301. In another embodiment, the page buffer / sense amplifier 404 can perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to a selected word line 418. In yet another embodiment, the page buffer / sense amplifier 404 can also sense low-power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify this small voltage swing to a discernible logic level during a read operation. The column decoder / bit line driver 406 can be configured, controlled by the control logic 412, to select one or more NAND memory strings 308 by applying bit line voltages generated from a voltage source 410.

[0047] The row decoder / word line driver 408 is controlled by control logic 412 and can be configured to select / deselect memory blocks 304 of the memory cell array 301 and further to select / deselect word lines 418 of the memory blocks 304. The row decoder / word line driver 408 can be further configured to drive the word lines 418 using word line voltages generated from a voltage source 410. In some implementations, the row decoder / word line driver 408 can also select / deselect and drive an SSG line 415 and a DSG line 413. As described in more detail below, the row decoder / word line driver 408 is configured to apply a program voltage to a selected word line 418 during a program operation of a memory cell 306 coupled to the selected word line 418.

[0048] The voltage source 410 can be controlled by the control logic 412 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0049] The control logic 412 is coupled to each of the peripheral circuits described above and can be configured to control the operation of each peripheral circuit. The registers 414 are coupled to the control logic 412 and can include status registers, command registers, and address registers for storing status information, command operation codes (opcodes), and command addresses for controlling the operation of each peripheral circuit.

[0050] Interface 416 is coupled to control logic 412 and can function as a control buffer that buffers and relays control commands received by control logic 412 from a host (not shown) and status information received from control logic 412 to the host. Interface 416 is further coupled to column decoder / bit line drivers 406 via a data bus and can function as a data input / output (I / O) interface and data buffer that buffers and relays data to and from memory cell array 301.

[0051] 5A illustrates a block diagram of an example system 500 including a memory device 104a, a memory controller 106a, and a host 108 according to some aspects of the present disclosure. In some implementations, the memory device 104a is a NAND flash memory device. The host 108 can send user data 520 (also known as host data) to be stored in the memory device 104a. The host 108 can be configured to send commands (e.g., write (program) commands, read commands, and erase commands) to the memory controller 106a, thereby enabling the memory device 104a to perform corresponding operations under the control of the memory controller 106a.

[0052] 5A, the memory controller 106a can include a controller processor 504, such as a memory chip controller (MCC) or memory controller unit (MCU). The controller processor 504 is configured to control modules that execute commands or instructions to perform the functions described in this disclosure. The controller processor 504 can also be configured to control operations of the memory device 104a by generating and sending various control signals, such as program instructions for program operations and read instructions for read operations. In some implementations, the memory controller 106a can include one or more controller processors. The one or more processors can include a primary processor and one or more secondary processors.

[0053] The memory controller 106a may further include a storage medium 506. The storage medium 506 may be volatile or nonvolatile memory. In some implementations, the memory controller 106a may include a volatile controller and nonvolatile memory. The storage medium 506 in the form of volatile memory may include registers or cache memory to enable faster access and processing speeds for reading, programming, or erasing data stored therein, but may not retain stored information when power is off. In some implementations, the storage medium 506 includes either dynamic random access memory (DRAM) or static random access memory (SRAM). The storage medium 506 in the form of nonvolatile memory may retain stored information even when power is off. In some implementations, the storage medium 506 may not be included with the memory controller 106a. For example, the storage medium 506 may be coupled to or located outside the memory controller 106a.

[0054] In some implementations, the memory controller 106a may include a first interface 502 configured to receive and send commands or instructions to and from the host 108. In some implementations, the first interface 502 is coupled to a controller processor 504 and configured to receive and send commands or instructions to the controller processor 504 that cause the controller processor 504 to perform the functions disclosed in this disclosure. Additionally, the memory controller 106a may include a second interface 510 configured to receive and send data or commands to and from the memory device 104a. In some implementations, the second interface 510 is coupled to the controller processor 504 and configured to send commands from the controller processor 504 to the memory device 104a.

[0055] In some implementations, the memory controller 106a may include an encoder 532 that includes one or more encoding circuits. When the first interface 502 receives user data 520 to be stored in the memory device 104a, the encoder 532 may encode the user data 520 by generating parity data for the user data 520. The parity data may be used for error correction when programming and reading data from the memory device 104a. In some cases, when storing the user data 520 in the memory device 104a, some bits of the user data 520 may flip (e.g., become “0”) from their originally set values ​​(e.g., “1”) due to electronic drift, data retention issues, or other phenomena. Such erroneous bits may cause read errors and affect the reliability of the memory device 104a. Using the parity data to detect and correct erroneous bits may ensure that data read from the memory device 104a is accurate and reliable.

[0056] In some implementations, the generated parity data is appended to the user data 520 to form a code word 522. For example, the code word 522 may include a user data portion containing the user data 520 received from the host and a parity data portion following the user data portion containing the generated parity data. The second interface 510 may transmit the code word 522 to the memory device 104a for storage.

[0057] In some implementations, the encoder 532 can generate parity data based on an error-correcting code (ECC), such as an LDPC code. LDPC codes are a type of linear block error-correcting code that includes a sparse parity-check matrix, enabling efficient error detection and correction for high-density memory devices, such as NAND memory devices. LDPC codes are based on a set of parity-check equations that transmitted or stored data must satisfy. During a read operation, the decoder 534 can employ an iterative algorithm to identify and correct errors by analyzing discrepancies in the parity-check equations. Specifically, the encoder 532 can generate parity data for the user data 520 based on an LDPC matrix that represents the set of parity-check equations. An LDPC matrix is ​​a sparse binary matrix that may be dominated by 0s and have a small percentage of 1s. In some implementations, the rows of the LDPC matrix represent the parity-check equations, and the columns of the LDPC matrix correspond to the bits of the codeword 522. The presence of a "1" in a particular row and column indicates that the corresponding bit of codeword 522 is included in the associated parity check equation. During a read operation, decoder 534 can use the LDPC matrix to identify erroneous bits through an iterative process of checks and balances. By iteratively adjusting the values ​​of bits that violate the parity check constraints, decoder 534 can converge toward the correct data, thereby correcting errors made during a program or read operation.

[0058] In some implementations, memory controller 106a can receive user data 520 in various LBA formats. For example, system 500 may support various namespaces, allowing different data to be logically separated. This allows different users or applications to store data separately on the same physical memory device without interfering with each other. Various namespaces may support various LBA formats. In some implementations, when writing or reading data having various LBA formats, the minimum operable data size (e.g., logical block size, such as 512 bytes or 4K bytes) may differ. In some cases, metadata associated with each logical block (e.g., address and identifier) ​​may differ depending on the LBA format.

[0059] For example, the system 500 may support multiple namespaces, including a first namespace and a second namespace. The user data 530 in the first namespace may be in a first LBA format, and the user data 540 in the second namespace may be in a second LBA format. In some implementations, the encoder 532 may generate parity data corresponding to the user data 530, 540 in the various LBA formats using various encoding algorithms (i.e., various LDPC matrices if the memory system employs an LDPC code as the ECC code). As shown in FIGS. 6A and 6B, the user data 530 may be in the first LBA format, and the user data 540 may be in the second LBA format. In some cases, the user data 530, 540 may differ in size due to differences in the minimum operable data size dictated by the various LBA formats. When the user data 530, 540 are stored in the memory device 104a, they are stored as fixed-size allocation units 600, 605. The allocation unit may be a page, a half page, a quarter page, or a stripe of a RAID structure. For example, each allocation unit in a memory device has a fixed size of 4K bytes. As seen in FIGS. 6A and 6B , user data 530 occupies a portion of an allocation unit 600, and the remaining space of the allocation unit 600 can be used to store parity data 612 corresponding to the user data 530. The encoder 532 may generate the parity data 612 using LDPC matrix O1. The user data 530 and the corresponding parity data 612 can be included in a codeword 614. In comparison, the user data 540 may occupy a smaller portion of the allocation unit 605, and the allocation unit 605 may have a larger remaining space for storing parity data 622 corresponding to the user data 540. The encoder 532 may generate the parity data 622 using a different LDPC matrix, for example, LDPC matrix O2.Thus, allocation unit 605 may have a higher coding rate (i.e., ratio of parity data bits / user data bits) and therefore higher error correction performance than allocation unit 600. User data 540 and corresponding parity data 622 may be included in codeword 624. In some implementations, parity data 612 and parity data 622 may have the same length but may differ in other aspects, such as data structure (e.g., whether they include a regular or irregular LDPC code), parity check density (e.g., density of the parity check matrix required to decode the parity data), etc.

[0060] Returning to FIG. 5A , in some implementations, the encoder 532 can generate parity data based on other ECC codes, such as Reed-Solomon codes, other Bose-Chaudhuri-Ockengem (BCH) codes, and Hamming codes. For example, a typical BCH code applied to a 512-byte (4096-bit) sector of data can correct up to four erroneous bits if at least 60 bits are used for parity data. Reed-Solomon codes are a subset of BCH codes and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four erroneous bits in a 512-byte sector of data if approximately 72 bits are used for parity data.

[0061] The memory controller 106a may include a decoder 534 including one or more decoding circuits. During a read operation, the decoder may detect and correct erroneous bits in the data. For example, if an LDPC code is used as the ECC code, the decoder 534 may employ an iterative algorithm that identifies and corrects errors by analyzing inconsistencies in a parity check equation represented by an LDPC matrix. In some implementations, a memory block may store codewords 614, 624 corresponding to user data in various LBA formats. For example, a codeword 614 including user data 530 and parity data 612 and a codeword 624 including user data 540 and parity data 622 may be stored in the same memory block of the memory device 104a. The decoder 534 may decode the codeword 614 using a corresponding LDPC matrix (e.g., LDPC matrix 01) and decode the codeword 624 using a corresponding LDPC matrix (e.g., LDPC matrix 02). Additionally, the decoder 534 can identify the LDPC matrix that corresponds to a given codeword based on an identifier recorded by the memory controller 106a when encoding the data.

[0062] In some implementations, the decoder 534 can operate based on an LDPC hard decoding strategy and an LDPC soft decoding strategy. The LDPC hard decoding strategy uses the hard value (i.e., 0 or 1) of each received bit. The LDPC soft decoding strategy uses both the hard value of each received bit and a log-likelihood ratio (LRR) that represents the likelihood that the bit is 0 or 1. For example, for a given bit, the LRR is

number

[0063] When the memory controller receives user data 520 from the host 108, a flash translation layer (FTL) (not shown in FIG. 5A ) of the memory controller 106a can determine a physical address in the memory device 104a to store the data and can further translate the logical address of the user data 520 into a physical address. After the encoder 532 generates the code word 522 (i.e., after adding parity data to the user data 520), the code word is stored in the memory space indicated by the physical address. Furthermore, the FTL can generate one or more mapping tables that indicate a mapping relationship between the logical address of the data and the physical address where the data is stored. In some implementations, the one or more mapping tables can include a logical-to-physical (L2P) mapping table and a physical-to-logical (P2L) mapping table. The L2P mapping table can map logical addresses to physical addresses. When new data is stored in a physical address, the memory controller 106a can update the entries in the L2P mapping table. For example, the memory controller 106a can unmap the physical address from the logical address of the replaced data and associate the physical address with the logical address of the new data. A P2L mapping table can map the physical address to the logical address. When new data is stored at a physical address, the memory controller 106a can add a new entry to the P2L mapping table to map the logical and physical addresses of the new data without deleting or modifying the previous entry that mapped the physical address to the logical address of the replaced data.

[0064] In some implementations, the L2P mapping table and the P2L mapping table are stored in the storage medium 506 of the memory controller 106a. In some implementations, the memory controller 106a can periodically transmit the P2L mapping table and a portion of the L2P mapping table (e.g., a second-level table of a multi-level L2P mapping table) to the memory device 104a, thereby allowing the mapping tables to be restored if the power is accidentally turned off.

[0065] The second interface 510 can transmit code words 522 (e.g., code words 614 and 624 in FIG. 6A and FIG. 6B ) containing user data 520 and corresponding parity data to the memory device 104a for storage. In some implementations, as shown in FIG. 5A , for example, the encoding algorithms generating the code words 614 and 624 for user data 530 and 540 having different LBA formats are different, so the code words 614 and 624 are stored in different memory blocks (e.g., memory block 304 in FIG. 3 ) of the memory device 104a. That is, data in the first namespace and data in the second namespace are stored in different memory blocks of the memory device. For example, the code word 614 containing user data 530 in the first LBA format can be stored in memory block A 512 of the memory device, and the code word 624 containing user data 540 in the second LBA format can be stored in memory block B 514 of the memory device. Therefore, in a certain memory block, the parity data of various allocation units are generated based on the same encoding algorithm (i.e., the same LDPC matrix when the memory system adopts an LDPC code as an ECC code), but this may result in an excessive number of free memory blocks in the memory device 104a.

[0066] FIG. 5B illustrates a block diagram of an example system 501 including a memory device 104b, a memory controller 106b, and a host 108 according to some aspects of the present disclosure. The memory device 104b and the memory controller 106b may be the same as or similar to the memory device 104a and the memory controller 106a in the system 501, except that the memory controller 106b can control the memory device 104b to store code words 614, 624 corresponding to user data 530, 540 having different LBA formats in the same memory block. That is, data in a first namespace and data in a second namespace may be stored in the same memory block. For example, as shown in FIG. 5B, the user data 530 in the first LBA format contained in the code word 614 may be stored in memory block A 512. The user data 540 contained in the code word 624 may also be stored in memory block A 512. Additionally, the memory controller 106b can record an identifier that indicates the encoding algorithm used to encode each user data 530, 540. Thus, the number of free memory blocks in the memory device 104b can be optimized.

[0067] In some implementations, the memory controller 106b can record an identifier in the P2L mapping table that indicates the encoding algorithm implemented to encode each user data. For example, as seen in FIG. 7 , the P2L mapping table 700 can have a first column 710 that records an identifier that indicates the encoding algorithm. For example, the binary numbers 00, 01, 10, and 11 in the first column 710 can represent four different LDPC matrices used to encode data in four different LBA formats, respectively. The P2L mapping table 700 can further include a second column 720 that records a logical address of the data and a third column (not shown in FIG. 7 ) that records a physical address where the data is stored. In the P2L mapping table 700 shown in FIG. 7 , the physical address can be represented by a row number of each entry. For example, data associated with a logical address in the first row of the P2L mapping table can be stored in a first allocation unit of a memory block, and data associated with a logical address in the second row can be stored in a second allocation unit of the memory block. In response to a write command, when mapping the logical address of the data to the physical address where the data is stored, the P2L mapping table 700 may also map an identifier of the LDPC matrix that the encoder 532 implements to encode the data. In other implementations, the memory controller 106b may record the identifier indicating the encoding algorithm in another mapping table or by other suitable means.

[0068] FIG. 8 illustrates an example data structure 800 for a write command according to some aspects of the present disclosure. The data structure 800 may be 16 bytes divided into four DWORDS, each of which is 4 bytes. The data structure 800 includes information that instructs the memory system to perform a write operation. For example, the data structure 800 may include a command identifier 802, which is a command ID that tracks the progress and response of each command. An operation code (opcode) 804 may indicate the operation to be performed, such as a write command in this case. A namespace identifier 806 may identify the namespace in which the data is stored. In some implementations, the namespace identifier may correspond to the LBA format of the data to be stored.

[0069] Additionally, data structure 800 may further include the following elements: metadata pointer 808 may point to the location of the metadata for the write operation; physical region page (PRP) entry 1810 may point to the first memory block or page where the data is stored; if the data is stored across multiple memory blocks or a single memory page, PRP entry 2812 may point to the second memory block or page; starting LBA 814 may indicate the starting logical address where to begin writing the data, and number of logical addresses 816 may indicate the length of the data. Data structure 800 may further include reserved bits 820 for future or command-specific use.

[0070] FIG. 9 illustrates an example method 900 for writing data to a memory system according to some aspects of the present disclosure.

[0071] At 902, the host may send a write command (the write command of data structure 800 of FIG. 8 ) to a memory controller coupled to the memory device. The write command may include a namespace identifier that indicates a namespace in which user data associated with the write command is stored. In some implementations, the data associated with the write command is in an LBA format that corresponds to the namespace.

[0072] The host sends user data associated with the write command to the memory controller at 904. In some implementations, the host sends the user data after receiving a RTT (Ready to Transfer) signal from the memory controller.

[0073] At 906, the memory controller may determine an encoding algorithm corresponding to the LBA format that the user data is in. For example, if an LDPC code is implemented as a parity code in the encoding scheme, the encoding algorithm may be an LDPC matrix corresponding to the LBA format that the user data is in. In some implementations, the LDPC matrices used to encode user data in various LBA formats are different.

[0074] At 908, the memory controller may record the identifier of the encoding algorithm in a P2L mapping table (e.g., P2L mapping table 700 of FIG. 7). For example, the memory controller may map the identifier of the encoding algorithm (e.g., a binary identifier of an LDPC matrix) to a logical address of the user data, and map the logical address of the user data to a physical address of the memory device where the user data is stored. It should be noted that operation 906 may be performed before, after, or simultaneously with operation 908.

[0075] At 910, the memory controller may encode the user data based on the identified encoding algorithm (e.g., LDPC matrix), thereby generating a codeword of the user data (e.g., codeword 614 of FIG. 6A or codeword 624 of FIG. 6B). In some implementations, the encoder (e.g., encoder 532 of FIG. 5A or 5B) may generate a codeword that may include a user data portion and a parity data portion appended to the end of the user data portion. The parity data portion may include parity data generated based on the user data using the identified LDPC matrix.

[0076] At 912, the memory controller transmits the generated codeword to a memory device for storage. For example, the codeword may be stored in an allocation unit within the memory device (e.g., allocation unit 600 in FIG. 6A, allocation unit 605 in FIG. 6B).

[0077] The memory device stores the code words of the user data in the different LBA formats in the same memory block at 914. For example, referring to Figures 5 and 6, the code word 614 corresponding to the user data 530 in the first LBA format and the code word 624 corresponding to the user data 540 in the second LBA format may be stored in allocation units 600, 605 within the same memory block of the memory device.

[0078] FIG. 10 illustrates an example method 1000 for reading data from a memory system according to some aspects of the present disclosure.

[0079] At 1002, the host sends a read command to the memory controller. The read command may include a logical address (e.g., a starting LBA and a length of 620 LBAs) of data to be read from the memory device. In response to receiving the read command, the memory controller may identify a physical address of the data to be read. For example, the memory controller may use an L2P mapping table to identify the physical address based on the logical address.

[0080] At 1004, the memory controller sends a read command and the identified physical address to the memory device. The read command can instruct the memory device to read data from the identified physical address. In some implementations, a codeword containing the data to be read (i.e., user data) and its corresponding parity data are stored at the identified physical address.

[0081] At 1006, the memory device transmits the codeword, including the user data and corresponding parity data, to the memory controller. In some implementations, the memory device can transmit the codeword in response to receiving a read command, in response to receiving a command to perform a garbage collection (GC) operation for purposes of managing and optimizing storage space within the memory device, or in other scenarios where the memory controller needs to read data from the memory device.

[0082] At 1008, the memory controller identifies a logical address corresponding to the codeword. For example, the memory controller can identify the logical address from a read command that includes the logical address of the data to be read. As another example, the memory controller can identify the logical address based on the physical address of the codeword by checking a mapping table, such as an L2P mapping table or a P2L mapping table.

[0083] At 1010, the memory controller may identify an encoding algorithm (e.g., an LDPC matrix) based on the identified logical address. The identified encoding algorithm is used in the write operation to generate a codeword based on the received user data, as shown in method 900. For example, the memory controller may identify the LDPC matrix from a P2L mapping table that records a mapping association between the logical address of the data and an identifier of the LDPC matrix implemented to encode the data.

[0084] At 1012, the memory controller may decode the codeword based on a decoding algorithm associated with the encoding algorithm. In some implementations, the decoding algorithm may use the same LDPC matrix used in encoding the user data. For example, a decoder (e.g., decoder 534 of FIG. 5A or FIG. 5B) may determine whether the received codeword satisfies a parity check equation dictated by the LDPC matrix. If the received codeword does not satisfy the parity check equation, this indicates that there are erroneous bits in the codeword. The decoder may correct the erroneous bits by repeatedly flipping bits in the codeword until the parity check equation is satisfied or until a minimum number of parity checks are not satisfied. After correcting the erroneous bits, the decoder may converge to the correct user data originally received from the host.

[0085] At 1014, the memory controller may send the user data decoded from the codeword to the host. In some implementations, if a read operation is performed in response to a GC operation, method 1000 does not include operation 1014, and the user data may be stored in a storage medium of the memory controller before being rewritten to another memory space in the memory device.

[0086] FIG. 11 is a flow diagram of an example method 1100 for writing data to a memory system according to some aspects of the present disclosure.

[0087] At 1102, a memory controller coupled to a memory device receives a first write command from a host. The first write command instructs writing first user data (e.g., user data 530 of FIG. 6A) to the memory device. The first user data may be in a first LBA format.

[0088] At 1104, the memory controller may generate first parity data (e.g., parity data 612 of FIG. 6A) corresponding to the first user data. The first parity data may be generated based on a first encoding algorithm (e.g., LDPC matrix 01) corresponding to the LBA format of the first user data. In some implementations, the first parity data may be appended to the end of the first user data to form a first code word (e.g., code word 614 of FIG. 6A).

[0089] At 1106, the memory controller may store the first identifier corresponding to the first encoding algorithm in a P2L mapping table (e.g., P2L mapping table 700 of FIG. 7 ). The P2L mapping table may map the first identifier to a logical address of the first user data.

[0090] At 1108, the memory device may store the first user data and the first parity data (e.g., the first code word 614 of FIG. 6A) in a memory block (e.g., the memory block 304 of FIG. 3). For example, the first user data and the first parity data may be stored in a first allocation unit of the memory block (e.g., the allocation unit 605 of FIG. 6B).

[0091] At 1110, the memory controller receives a second write command from the host. The second write command instructs writing second user data (e.g., user data 540 of FIG. 6B) to the memory device. The second user data may be in a second LBA format.

[0092] At 1112, the memory controller may generate second parity data corresponding to the second user data (e.g., parity data 622 of FIG. 6B). The second parity data may be generated based on a second encoding algorithm (e.g., LDPC matrix 02) corresponding to the LBA format of the second user data. In some implementations, the second parity data may be appended to the end of the second user data to form a second code word (e.g., code word 624 of FIG. 6B).

[0093] At 1114, the memory controller may store a second identifier corresponding to the second encoding algorithm in a P2L mapping table (e.g., P2L mapping table 700 of FIG. 7 ). The P2L mapping table may map the second identifier to a logical address of the second user data.

[0094] At 1116, the memory device may store the second user data and the second parity data (e.g., the second code word 624 of FIG. 6B) in the same memory block (e.g., the memory block 304 of FIG. 3) as the first user data and the first parity data. For example, the second user data and the second parity data may be stored in a second allocation unit (e.g., the allocation unit 605 of FIG. 6B) of the memory block 304. When the memory device receives a read command to read the first user data and the second user data, the first user data and the second user data are read from the same memory block of the memory device.

[0095] While this specification contains details of many specific implementations, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations, individually, or in any subcombination. Furthermore, while the features described above may be described as functioning in a particular combination and may initially be claimed as such, in some cases one or more features may be excluded from the claimed combination, and the claimed combination may also be directed to a subcombination or variations of the subcombination.

[0096] As used in this disclosure, the terms "a," "an," or "the" are used to include one or more unless the context clearly dictates otherwise. The term "or" refers to a non-exclusive "or" unless otherwise indicated. The phrase "at least one of A and B" has the same meaning as "A, B, or A and B." Furthermore, any words, phrases, or terms used in this disclosure and not otherwise defined are for descriptive purposes only and are not intended to be limiting. The use of section headings is intended to aid in the reading and comprehension of the document and should not be construed as limiting. For example, information associated with a section heading may be found within or outside of that particular section.

[0097] As used in this disclosure, the terms "about" or "approximately" may allow for a degree of variation in a value or range, for example, within 10%, within 5%, or within 1% of a stated value or of a stated limit of a range.

[0098] As used in this disclosure, the term "substantially" refers to a majority or a large portion, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0099] Values ​​expressed in range format should be interpreted flexibly, including not only the numerical values ​​stated as the limits of the range, but also individual numerical values ​​or subranges within the range, as if each numerical value and subrange were explicitly stated. For example, a range such as "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise indicated, the phrase "X to Y" has the same meaning as "about X to about Y." Similarly, unless otherwise indicated, the phrase "X, Y, or Z" has the same meaning as "about X, about Y, or about Z."

[0100] Specific implementations of the present subject matter have been described above. Other implementations, modifications, and permutations of the described implementations are within the scope of the following claims, as will be apparent to those skilled in the art. Although the figures or claims may depict operations in a particular order, desirable results do not require that such operations be performed in the particular order depicted, or in sequential order, or that all of the depicted operations be performed (some operations may be considered optional). Where deemed appropriate in certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and implemented.

[0101] Furthermore, the separation or integration of the various system modules and components in the above-described embodiments is not required in all implementations, and in general, the described components and systems may be integrated together or packaged into multiple products.

[0102] Accordingly, the foregoing illustrative embodiments do not define or limit the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

[0103] The foregoing description of specific implementations may be readily modified and / or adapted to suit a variety of applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0104] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other implementations are within the scope of the claims.

Claims

1. 1. A method of operating a memory system, comprising: receiving a first write command to store first user data in a memory device of the memory system; generating first parity data corresponding to the first user data based on a first encoding algorithm; storing the first user data and the first parity data in a memory block of the memory device; receiving a second write command to store second user data in the memory device; generating second parity data corresponding to the second user data based on a second encoding algorithm, the second encoding algorithm being different from the first encoding algorithm; storing the second user data and the second parity data in the memory block.

2. 2. The method of claim 1, wherein the second user data and the second parity data are stored in the same memory block as the first user data and the first parity data.

3. 3. The method of claim 1, wherein the first parity data and the second parity data comprise low-density parity check (LDPC) parity data, the first encoding algorithm comprises a first LDPC matrix, and the second encoding algorithm comprises a second LDPC matrix.

4. storing a first identifier of the first user data in a memory controller of the memory system, the first identifier corresponding to the first encoding algorithm; 4. The method of claim 3, further comprising: storing a second identifier of the second user data in the memory controller, the second identifier corresponding to the second encoding algorithm.

5. The method of claim 4 , wherein the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table.

6. 6. The method of claim 5, wherein a logical address of the first user data is mapped to the first identifier in the P2L mapping table, and a logical address of the second user data is mapped to the second identifier in the P2L mapping table.

7. identifying the first LDPC matrix based on the first identifier; and decoding the first parity data based on the first LDPC matrix.

8. 3. A method according to claim 1, wherein the first user data is contained in logical blocks of a first format and the second user data is contained in logical blocks of a second format.

9. 1. A memory system comprising: one or more memory devices; a memory controller coupled to the one or more memory devices, the memory system configured to perform operations, the operations comprising: receiving a first write command to store first user data in the one or more memory devices; generating first parity data corresponding to the first user data based on a first encoding algorithm; storing the first user data and the first parity data in a memory block of the memory device; receiving a second write command to store second user data in the one or more memory devices; generating second parity data corresponding to the second user data based on a second encoding algorithm, the second encoding algorithm being different from the first encoding algorithm; storing the second user data and the second parity data in the memory block.

10. 10. The memory system of claim 9, wherein the second user data and the second parity data are stored in the same memory block as the first user data and the first parity data.

11. 11. The memory system of claim 9, wherein the first parity data and the second parity data comprise low-density parity check (LDPC) parity data, the first encoding algorithm comprises a first LDPC matrix, and the second encoding algorithm comprises a second LDPC matrix.

12. The operation is storing a first identifier of the first user data in the memory controller, the first identifier corresponding to the first encoding algorithm; 11. The memory system of claim 9, further comprising: storing a second identifier of the second user data in the memory controller, the second identifier corresponding to the second encoding algorithm.

13. the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table; 13. The memory system of claim 12, wherein a logical address of the first user data is mapped to the first identifier of the P2L mapping table, and a logical address of the second user data is mapped to the second identifier of the P2L mapping table.

14. 11. The memory system of claim 9, wherein the first user data is contained in logical blocks of a first format, and the second user data is contained in logical blocks of a second format.

15. A memory controller, a first interface, receiving a first write command including first user data; and receiving a second write command including second user data; 1. An encoder comprising: generating first parity data corresponding to the first user data based on a first encoding algorithm; generating second parity data corresponding to the second user data based on a second encoding algorithm, the second encoding algorithm being different from the first encoding algorithm; a second interface, sending a third write command to write the first user data and the first parity data to a memory block of a memory device; and sending a fourth write command to write the second user data and the second parity data to the memory block.

16. 16. The memory controller of claim 15, wherein the memory controller is configured to control the memory device to store the second user data and the second parity data in the same memory block as the first user data and the first parity data.

17. The second interface is receiving the first user data and the first parity data from the memory block; receiving the second user data and the second parity data from the memory block; the memory controller further includes a decoder; The decoder decoding the first parity data based on the first encoding algorithm; and decoding the second parity data based on the second encoding algorithm.

18. storing a first identifier of the first user data, the first identifier corresponding to the first encoding algorithm; 17. The memory controller of claim 15 or 16, further configured to: store a second identifier of the second user data, the second identifier corresponding to the second encoding algorithm.

19. the first identifier and the second identifier are stored in a physical-to-logical (P2L) mapping table; 20. The memory controller of claim 18, wherein a logical address of the first user data is mapped to the first identifier of the P2L mapping table, and a logical address of the second user data is mapped to the second identifier of the P2L mapping table.

20. the first parity data and the second parity data include low-density parity check (LDPC) parity data; 17. The memory controller of claim 15 or 16, wherein the first encoding algorithm includes a first LDPC matrix and the second encoding algorithm includes a second LDPC matrix.

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