Computation processing device and information processing device

Abstract

To suppress an increase in a package area of a computation processing unit comprising a plurality of chiplets, each including a core and an input / output unit.SOLUTION: A computation processing unit 1 includes: a plurality of chiplets 2, each including a core 4 and an input / output unit 5; a plurality of 1-to-2 optical branching units 31, each having two-input / output sides connected to the input / output unit 5; and an n-way (n is an integer of 3 or greater) optical branching unit 30 connected to one-input / output side of the plurality of 1-to-2 optical branching units 31, and that outputs optical signals input from one-input / output side from among a plurality of one-input / output sides to one or more other one-input / output sides from among the plurality of one-input / output sides. The input / output unit 5 transmits optical signals of different wavelengths between the plurality of chiplets 2 to one of the two-input / output sides, and receives optical signals of wavelengths different from the wavelength of the output optical signal from the other of the two-input / output sides.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a processor and an information processor. [Background technology]

[0002] In the development of processors such as CPUs (Central Processing Units), a packaging technique called chipletization is known as one method for improving costs or yields. Chipletization is a technique in which a large-scale circuit integrated on a single chip is divided into multiple small chips (hereinafter sometimes referred to as "chiplets") and multiple chiplets are mounted on a substrate to form a single package. For example, one chiplet may be implemented with a core die containing the processor cores and an IO die containing the input / output (IO) section between the cores. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-164110 Summary of the Invention [Problem to be solved by the invention]

[0004] In the chiplet approach, chiplets (e.g., IO dies) are connected via electrical wiring on the substrate, and communication between the chiplets is carried out via electrical signals. Therefore, as the number of chiplets mounted on a package increases, the distance (communication distance) between the chiplets may become longer due to the arrangement of multiple chiplets. In this case, the number of chiplets that can be mounted on a package may be limited due to factors such as communication delays caused by the longer electrical wiring, increased power consumption due to the implementation of mechanisms to amplify attenuated signal strength, and electromagnetic interference that hinders higher density or broadband.

[0005] To alleviate or eliminate such limitations, it is conceivable to connect chiplets (fully connected) using optical waveguide wiring, which has less impact on long-distance communication than electrical wiring. For example, the transmitter of an IO die is connected one-to-one with the receiver of another IO die by a single optical waveguide, and the receiver of that IO die is connected one-to-one with the transmitter of that other IO die by a single optical waveguide. In other words, two chiplets communicating with each other are connected by two optical waveguides, each of which transmits optical signals in one direction. In this case, the package is equipped with two optical waveguides equal to the number of combinations of chiplets communicating with each other.

[0006] However, when all chiplets are connected with one-to-one optical waveguide wiring, the number of optical waveguide wiring increases as the number of chiplets increases, resulting in an increase in the wiring area. Furthermore, since the number of transmitter-receiver pairs corresponding to the number of core dies (chiplets) that communicate with each other must be implemented on the IO die, the area of ​​the chiplet itself increases. This increases the overall package area, raising concerns about increased manufacturing costs.

[0007] In this way, when relaxing the limit on the number of chiplets in a chiplet-based processor package, it may become difficult to suppress an increase in the area of ​​the processor package.

[0008] In one aspect, an object of the present invention is to suppress an increase in the area of ​​a package of a processing unit that includes a plurality of chiplets each including a core and an input / output unit. [Means for solving the problem]

[0009] In one aspect, the arithmetic processing device may include a plurality of chiplets each including a core and an input / output unit, a plurality of one-to-two optical branching units each having two input / output sides connected to the input / output unit, and an n (n is an integer greater than or equal to 3)-bifurcation optical branching unit. The n-bifurcation optical branching unit may be connected to one input / output side of the plurality of one-to-two optical branching units and output an optical signal input from any one input / output side of the plurality of one input / output sides to one or more other input / output sides of the plurality of one input / output sides. The input / output unit may transmit optical signals of wavelengths different from each other among the plurality of chiplets to one of the two input / output sides and receive an optical signal of a wavelength different from the wavelength of the optical signal to be output from the other of the two input / output sides. [Effects of the Invention]

[0010] In one aspect, it is possible to suppress an increase in the area of ​​a package of a processing unit that includes a plurality of chiplets each including a core and an input / output unit. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a chiplet-based processor according to a comparative example. [Figure 2] 2 is a diagram illustrating an example of connections between chiplets of the processor illustrated in FIG. 1. [Figure 3] FIG. 1 is a block diagram illustrating an example of the configuration of a chiplet-based processor according to an embodiment. [Figure 4] 4 is a diagram illustrating an example of connections between chiplets of the processor illustrated in FIG. 3. [Figure 5] FIG. 1 is a diagram illustrating an example of a 1-to-2 optical splitter. [Figure 6] FIG. 1 is a diagram illustrating an example of the relationship between input and output of a 1:2 optical splitter. [Figure 7] FIG. 1 is a diagram illustrating an example of a three-path optical branching device. [Figure 8] FIG. 2 is a diagram illustrating an example of the relationship between input and output of a three-path optical branching device. [Figure 9] FIG. 1 is a diagram illustrating an example of a four-path optical branching device. [Figure 10]FIG. 2 is a diagram illustrating an example of the input / output relationship of a four-path optical branching device. [Figure 11] FIG. 10 illustrates another example of connections between chiplets of a processor. [Figure 12] FIG. 4 is a block diagram illustrating an example configuration of the IO die shown in FIG. 3. [Figure 13] FIG. 2 is a diagram illustrating an example of the configuration of transmission data. [Figure 14] FIG. 2 is a diagram for explaining an example of the operation of a processor. [Figure 15] FIG. 4 is a block diagram illustrating a modified example of the configuration of the IO die shown in FIG. 3. [Figure 16] 4 is a diagram illustrating a modified example of the connection between chiplets of the processor illustrated in FIG. 3. [Figure 17] FIG. 4 is a block diagram illustrating another example configuration of the IO die shown in FIG. 3. [Figure 18] FIG. 1 is a block diagram illustrating an example of the hardware configuration of a computer including a processor according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications and application of techniques not explicitly stated below. For example, this embodiment can be implemented with various modifications within the scope of its purpose. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[0013] [A] Description of chiplet processor 1 is a block diagram showing an example of the configuration of a chipletized processor 100 according to a comparative example. The processor 100 is an example of a processing device, and includes a plurality of chiplets 200 (four in FIG. 1) and an optical wiring unit 300.

[0014] 1, chiplet 200 illustratively includes a plurality of (four in FIG. 1) core dies 210 and an IO die 220. Core die 210 has a core function (arithmetic processing function) within chiplet 200. IO die 220 is an example of an input / output unit of chiplet 200, and has an input / output function within chiplet 200 and between chiplets 200.

[0015] The core dies 210 in one chiplet 200 are electrically connected to each other so as to be able to communicate with each other via an internal communication unit (not shown) of the IO die 220. As shown in FIG. 1, the IO die 220 includes one or more (two in FIG. 1) OEs (Optical Engines) 230 for communication between the chiplets 200.

[0016] Fig. 2 is a diagram showing an example of connections between chiplets 200 of the processor 100 shown in Fig. 1. In Fig. 2, attention is focused on an OE 230 that is a part of each chiplet 200. As shown in Fig. 2, each of the multiple chiplets 200 is optically connected between the OEs 230 provided in each chiplet 200 by an optical wiring unit 300, so that the chiplets 200 can communicate with each other. Note that in Fig. 2, the OEs 230 of the four chiplets 200 are denoted as OE#0 to OE#3, respectively.

[0017] The OE 230 includes a plurality of pairs of TX (Transmitter) 230a and RX (Receiver) 230b. The TX 230a includes an electrical-to-optical converter that converts an electrical signal output from the IO die 220 into an optical signal. The RX 230b includes an optical-to-electrical converter that converts an optical signal input to the IO die 220 into an electrical signal. Note that in FIG. 2, when each of the plurality of TX 230a and RX 230b in the OE 230 is specifically indicated, they are denoted as TX#0 to TX#2 and RX#0 to RX#2.

[0018] 2, the optical wiring unit 300 connecting the chiplets 200 includes a plurality of optical waveguides 310. To mutually connect two chiplets 200, for example, between OE#0 and OE#2, one optical waveguide 310 is provided between TX#0 of one chiplet 200 and RX#0 of OE#2 of the other chiplet 200, and one optical waveguide 310 is provided between RX#0 of OE#0 and TX#0 of OE#2. Communication between the chiplets 200 or communication between the processors 100 is performed by optical signals via the plurality of optical waveguides 310 connected one-to-one.

[0019] 2, the optical wiring section 300 is provided with a total of two optical waveguides 310, one for transmission and one for reception, for each chiplet 200 that is the communication destination of one chiplet 200. In the example shown in FIG. 2, in order to connect four chiplets 200 together, m C2×2 (m is the number of chiplets 200, and C is the combination), i.e., 12 optical waveguides 310 are used. Similarly, if the number of chiplets 200 in the processor 100 is five, 20 optical waveguides 310 are used, and if the number is six, 30 optical waveguides 310 are used.

[0020] Thus, as the number of chiplets 200 increases, the number of interconnections of the optical waveguides 310 included in the optical interconnection unit 300 also increases, which increases the interconnection area (area of ​​the optical interconnection unit 300), and therefore the overall area of ​​the processor 100. Furthermore, since a pair of TX 230a and RX 230b is provided in the OE 230 for each pair of interconnected chiplets 200, there is a concern that the area of ​​the OE 230, i.e., the chiplets 200, and ultimately the overall processor 100 will increase. Such an increase in the overall area of ​​the processor 100, i.e., an increase in the area of ​​the package, raises concerns about an increase in packaging costs.

[0021] Therefore, in one embodiment, a method for suppressing an increase in the package area of ​​a processing unit that includes a plurality of chiplets each including a core and an input / output unit will be described.

[0022] [B] Example of a processor configuration according to one embodiment FIG. 3 is a block diagram showing an example configuration of a chipletized processor 1 according to an embodiment. The processor 1 is an example of a processing unit and may be an LSI (Large-Scale Integration) package. As shown in FIG. 3, the processor 1 includes, as a hardware configuration, a plurality of chiplets 2 and an optical wiring unit 3. For convenience, four chiplets 2 are shown in FIG. 1, but the number of chiplets 2 is not limited to this, and the number of chiplets 2 may be two or more, including four (three or more in relation to the optical wiring unit 3 described below).

[0023] As shown in FIG. 3 , the chiplet 2 illustratively includes multiple core dies 4 and an IO die 5. The core die 4 has a core function (computing function) within the chiplet 2. The core die 4 may also be referred to as a core or a processor core. The IO die 5 is an example of an input / output unit of the chiplet 2 and has input / output functions within and between the chiplets 2. Since the processor 1 includes multiple chiplets 2 each having multiple core dies 4, the processor 1 can be said to be a multi-core processor. The chiplet 2 may also be referred to as a core set including cores and IOs.

[0024] The core dies 4 in one chiplet 2 may be electrically connected to each other so as to be able to communicate with each other via an internal communication unit (not shown) of the IO die 5. As shown in Fig. 3, the IO die 5 may include one or more OEs 6 (two in Fig. 3) for communication between the chiplets 2. Communication between the chiplets 2 may be performed by optical signals via the OEs 6 and the optical wiring unit 3 included in each chiplet 2.

[0025] Fig. 4 is a diagram showing an example of connections between chiplets 2 of the processor 1 shown in Fig. 3. In Fig. 4, attention is focused on the OE6, which is a part of each chiplet 2. As shown in Fig. 4, each of the multiple chiplets 2 is optically connected between the OE6 provided in each chiplet 2 by the optical wiring unit 3, so that they can communicate with each other. In Fig. 4, the OE6 of the four chiplets 2 are represented as OE#0 to OE#3, respectively.

[0026] The OE 6 includes a TX 7 having an electrical-to-optical converter, which will be described later, and an RX 8 including an optical-to-electrical converter, which will be described later. The TX 7 transmits an optical signal toward the optical wiring unit 3. The RX 8 receives an optical signal from the optical wiring unit 3 side.

[0027] [B-1] Explanation of optical wiring section As illustrated in Figure 4, the optical wiring section 3 connecting the chiplets 2 connects (optically connects) OE#0 to OE#3, i.e., chiplets 2, so that they can communicate with each other via optical wiring that can be considered as one system (one optical waveguide, as an example).

[0028] A processor 1 according to one embodiment uses wavelength division multiplexing (WDM) technology to enable parallel (e.g., simultaneous or nearly simultaneous) communication between multiple chiplets 2 via an optical wiring unit 3, which is an example of a single optical waveguide. For example, each of OEs #0 to #3 transmits optical signals of different wavelengths from among multiple wavelengths to the optical wiring unit 3, thereby enabling parallel communication between multiple chiplets 2.

[0029] 4 includes a plurality of (four in FIG. 4) one-to-two optical branching devices 31 and one or more (two in FIG. 4) three-way branching devices 32. Hereinafter, in the optical wiring unit 3, the optical wiring connecting the OE 6 and the one-to-two optical branching devices 31, connecting the one-to-two optical branching devices 31 and the three-way branching devices 32, and connecting the three-way branching devices 32 may be referred to as an optical waveguide 33 for convenience.

[0030] The optical waveguide 33 may be a multimode optical waveguide, a single-mode optical waveguide, or a few-mode optical waveguide depending on the optical transmission method, and the material of the optical waveguide may be appropriately selected. Furthermore, the optical wiring unit 3 may include an optical amplifier at any position, for example, on the optical waveguide 33 between the three-way optical splitters 32. Furthermore, the optical wiring unit 3 may be implemented in the processor 1 as a chiplet that connects each chiplet 2.

[0031] The multiple 1-to-2 optical splitters 31 are an example of multiple 1-to-2 optical splitters connected to multiple OEs 6 (in other words, multiple IO dies 5). The multiple 1-to-2 optical splitters 31 may be, for example, the same number as the OEs 6 (in other words, the number of chiplets 2 communicably connected to each other), and each may be provided corresponding to an OE 6.

[0032] 5 is a diagram illustrating an example of a 1-to-2 optical splitter 31. The 1-to-2 optical splitter 31 may include a splitter 31a, two optical waveguides 31b, and one optical waveguide 31c. The two optical waveguides 31b connect ports A1 and A2 to the splitter 31a, respectively. The optical waveguide 31c connects port A3 to the splitter 31a. The splitter 31a outputs an optical signal input from port A1 or A2 via the optical waveguide 31b to port A3 (1 input / output side) via the optical waveguide 31c. Furthermore, the splitter 31a outputs an optical signal input from port A3 via the optical waveguide 31c to both ports A1 and A2 (2 input / output side) via the optical waveguide 31b.

[0033] Hereinafter, for convenience, the optical waveguides 31b connected to ports A1 and A2 may be referred to as optical waveguides A1 and A2, and the optical waveguide 31c connected to port A3 may be referred to as optical waveguide A3. At least one of the optical waveguides 31b and 31c may be an example of the optical waveguide 33 shown in FIG. 4, or may be at least a part of the optical waveguide 33.

[0034] Fig. 6 is a diagram showing an example of the input / output relationship of the 1:2 optical splitter 31. Hereinafter, it is assumed that optical signals of wavelengths λ1 to λ3 are input to the splitter 31a from ports A1 to A3, respectively. Note that the optical signals of wavelengths λ1 to λ3 may be referred to as optical signals λ1 to λ3, respectively. IN in Fig. 6 indicates whether or not an optical signal is input to each of ports A1 to A3, with λ1 to λ3 indicating that an input is present and 0 indicating that an input is not present. OUT in Fig. 6 indicates whether or not the optical signals input in the combinations shown in IN are output from the splitter 31a to ports A1 to A3, with λ1 to λ3 indicating that an output is present and 0 indicating that an output is not present.

[0035] 6, when one or both of optical signals λ1 and λ2 are input from one or both of ports A1 and A2 on the two input / output sides, the splitter 31a outputs the optical signal to port A3 on the one input / output side and suppresses output to ports A1 and A2. That is, the splitter 31a outputs the optical signal λ1 or λ2 input from port A1 or A2 to only A3 among ports A1 to A3.

[0036] On the other hand, when an optical signal λ3 is input from port A3 on the input / output side 1, the splitter 31a outputs the optical signal to each of ports A1 and A2 on the input / output side 2. In other words, the splitter 31a splits the optical signal λ3 input from port A3 and outputs it to both A1 and A2 of ports A1 to A3.

[0037] Since the optical signals λ1 to λ3 have different wavelengths, they do not substantially affect optical signals of other wavelengths when transmitted through the optical path. Therefore, when optical signals are input to the splitter 31a simultaneously from two or more ports among ports A1 to A3, the splitter 31a may output each optical signal to a port that complies with the above-mentioned conditions.

[0038] In the following description, "simultaneously" may include, for example, a case where a plurality of optical signals are input to an input target of the optical signals at the same timing, as well as a case where at least a part of the time intervals during which the plurality of optical signals pass through the input target overlap, in other words, "substantially simultaneously." The input target of the optical signal is, for example, an object to which the optical signal is input in the description, such as the optical wiring unit 3, the optical waveguide 33, or the splitter 31a (1-to-2 optical splitter 31) shown in FIG.

[0039] As an example, when an optical signal λ1 is input from port A1 and an optical signal λ3 is input from port A3 simultaneously, the splitter 31a (1:2 optical splitter 31) outputs the optical signal λ1 to port A3 and the optical signal λ3 to both ports A1 and A2. When an optical signal λ2 is input from port A2 and an optical signal λ3 is input from port A3 simultaneously, the splitter 31a outputs the optical signal λ2 to port A3 and the optical signal λ3 to both ports A1 and A2. When optical signals λ1 to λ3 are input to ports A1 to A3 simultaneously, the splitter 31a outputs the optical signals λ1 and λ2 to port A3 and the optical signal λ3 to both ports A1 and A2.

[0040] 6 shows an example in which optical signals of a single wavelength are input from each port to the splitter 31a, but this is not limiting, and two or more optical signals of different wavelengths may be input simultaneously to the splitter 31a from one port. For example, when optical signals λ1 and λ1' are input simultaneously from port A1, the splitter 31a outputs optical signals λ1 and λ1' to port A3, respectively.

[0041] As shown in Fig. 4, the 1-to-2 optical splitter 31 is connected to TX7 and RX8 of the corresponding OE6 via optical waveguides A1 and A2 (optical waveguide 33) on the 2 input / output side, respectively, and is connected to a 3-way optical splitter 32 via optical waveguide A3 (optical waveguide 33) on the 1 input / output side. In this way, the 1-to-2 optical splitter 31 shown in Fig. 5 has, for example, port A1 connected to TX7 of the corresponding OE6, port A2 connected to RX8 of the OE6, and port A3 connected to another OE6 side, for example, the 3-way optical splitter 32, as shown in Fig. 4.

[0042] As a result, the 1:2 optical splitter 31 can output the optical signal of wavelength λ1 (see Figure 6) transmitted from TX7 of the corresponding OE6 and input to port A1 from port A3 to another chiplet 2 via the optical wiring unit 3 and the 1:2 optical splitter 31 corresponding to another OE6.

[0043] On the other hand, the 1:2 optical splitter 31 can output an optical signal with wavelength λ3 (see FIG. 6) transmitted from another OE6 and input to port A3 from ports A1 and A2 to TX7 and RX8 of the OE6.

[0044] 7 is a diagram illustrating an example of a three-way optical splitter 32. The three-way optical splitter 32 is an example of a three-way branching section, and may be realized by various methods. As an example, the three-way optical splitter 32 may be realized by combining three one-to-two optical splitters 31. In the example shown in FIG. 7, the three-way optical splitter 32 may include a connection section 32a, three splitters 32b, and three optical waveguides 32c.

[0045] The connection unit 32a includes three optical waveguides, each of which interconnects the two input / output sides of the three splitters 32b. The three optical waveguides 32c connect ports B1, B2, and B3 to the one input / output side of the splitter 32b, respectively. The splitter 32b may have a configuration similar to that of the splitter 31a. For example, the splitter 32b outputs an optical signal input from port B1, B2, or B3 via the optical waveguide 32c to the other two splitters 32b via the connection unit 32a connected to the two input / output sides. The splitter 32b also outputs an optical signal input from the connection unit 32a connected to the two input / output sides to the optical waveguide 32c connected to the one input / output side.

[0046] Hereinafter, for convenience, the optical waveguides 32c connected to the ports B1 to B3 may be referred to as optical waveguides B1 to B3. At least one of the optical waveguides 32c may be an example of the optical waveguide 33 shown in FIG.

[0047] 7 is formed by connecting the two input / output sides (A1 and A2 sides in FIG. 5) of the three one-to-two optical splitters 31 shown in FIG. 5 to each other via the connectors 32a. Therefore, an optical signal input to the one input / output side of one one-to-two optical splitter 31 in the three-to-two optical splitter 32 is input to the two input / output sides of another one-to-two optical splitter 31 in accordance with the input / output relationship of the one-to-two optical splitter 31 described above, and is output from the one input / output side of the other one-to-two optical splitter 31.

[0048] Fig. 8 is a diagram showing an example of the input / output relationship of the three-path optical splitter 32. Hereinafter, it is assumed that optical signals with wavelengths λ1 to λ3 are input to the splitter 32b from ports B1 to B3, respectively. Note that the optical signals with wavelengths λ1 to λ3 may be referred to as optical signals λ1 to λ3, respectively. IN in Fig. 8 indicates whether or not an optical signal is input to each of ports B1 to B3, with λ1 to λ3 indicating that an input is present and 0 indicating that no input is present. OUT in Fig. 8 indicates whether or not the optical signals input in the combinations shown in IN are output from splitter 32b to ports B1 to B3, with λ1 to λ3 indicating that an output is present and 0 indicating that no output is present.

[0049] 8, when one or more optical signals λ1 to λ3 are input from one or more of the three ports B1 to B3, the three-way optical splitter 32 outputs the optical signals from two ports other than the port to which the optical signals are input. That is, when an optical signal λ1 is input from port B1, the three-way optical splitter 32 splits and outputs the optical signal λ1 to both ports B2 and B3 other than port B1 of the ports B1 to B3.

[0050] When optical signals are input to the three-way optical splitter 32 from two or more ports among ports B1 to B3, the three-way optical splitter 32 may output each optical signal to a port that complies with the above-mentioned conditions. As an example, assume that an optical signal λ1 is input from port B1, an optical signal λ2 is input from port B2, and an optical signal λ3 is input from port B3 simultaneously to the three-way optical splitter 32. In this case, the three-way optical splitter 32 outputs the optical signal λ1 to both ports B2 and B3, outputs the optical signal λ2 to both ports B1 and B3, and outputs the optical signal λ3 to both ports B1 and B2.

[0051] 8 shows an example in which an optical signal of a single wavelength is input from each port to the splitter 32b (three-path optical splitter 32), but this is not limiting, and two or more optical signals of different wavelengths may be input simultaneously to the splitter 32b from one port. For example, when optical signals λ1 and λ1' are input simultaneously from port B1, the three-path optical splitter 32 outputs both of the two optical signals λ1 and λ1' to ports B2 and B3, respectively.

[0052] 4, the three-way optical branch 32 is connected to the optical waveguide A3 of the one-to-two optical branch 31 connected to the two OEs 6 via two optical waveguides 33 (for example, optical waveguides B1 and B2) of the three optical waveguides B1 to B3. The three-way optical branch 32 is connected to the optical waveguide 33 (for example, optical waveguide B3) of the other three-way optical branch 32 via one optical waveguide 33 (for example, optical waveguide B3) of the three optical waveguides B1 to B3.

[0053] Depending on the number of chiplets 2 in the processor 1, the three-way branching optical splitter 32 may be used as follows. For example, all three optical waveguides 32c may be connected to the optical waveguides A3 of the three one-to-two optical splitters 31, respectively. Alternatively, one optical waveguide 32c may be connected to the optical waveguide A3 of the one-to-two optical splitter 31, and two optical waveguides 32c may be connected to the optical waveguides 32c of the other two three-way branching optical splitters 32, respectively. Alternatively, all three optical waveguides 32c may be connected to the optical waveguides 32c of the other three three-way branching optical splitters 32, respectively.

[0054] As described above, the optical wiring unit 3 including the one-to-two optical branching unit 31 and the three-way optical branching unit 32 can connect a plurality of chiplets 2 to each other so that they can communicate with each other as a single optical waveguide. This makes it possible to suppress an increase in the wiring area of ​​the optical wiring unit 3 compared to, for example, the optical wiring unit 300 shown in FIG.

[0055] 4 shows an example in which two three-way optical splitters 32 are used as an example of the optical wiring unit 3 connecting four chiplets 2, but the configuration of the optical wiring unit 3 is not limited to this. When four chiplets 2 are connected to each other, one four-way optical splitter 34 (see FIG. 9) may be used as the optical wiring unit 3.

[0056] FIG. 9 is a diagram showing an example of a four-path optical splitter 34. The four-path optical splitter 34 is an example of a four-path optical splitting section, and may be realized by various methods. As an example, the four-path optical splitter 34 may be composed of four one-to-three optical splitters. In the example shown in FIG. 9, the four-path optical splitter 34 may include a connection section 34a, four splitters 34b, and four optical waveguides 34c.

[0057] The connection unit 34a has six optical waveguides, and each optical waveguide connects the three input / output sides of the four splitters 34b to each other. The four optical waveguides 34c connect ports C1 to C4 to the one input / output sides of the splitters 34b, respectively. The splitters 34b output optical signals input from the one input / output side of ports C1, C2, C3, or C4 via the optical waveguides 34c to the other splitters 34b via the connection unit 34a connected to the three input / output side. The splitters 34b also output optical signals input from the connection unit 34a connected to the three input / output side to the optical waveguides 34c connected to the one input / output side.

[0058] Hereinafter, for convenience, the optical waveguides 34c connected to the ports C1 to C4 may be referred to as optical waveguides C1 to C4. At least one of the optical waveguides 34c may be an example of the optical waveguide 33 shown in FIG.

[0059] 9 is formed by connecting the three output sides of four 1-to-3 optical splitters to each other via connectors 34a. Therefore, an optical signal input to one input / output side of one 1-to-3 optical splitter in the four-to-3 optical splitter 34 is output toward the other three 1-to-3 optical splitters (toward connectors 34a) and output from the one input / output sides of the other three 1-to-3 optical splitters.

[0060] Fig. 10 is a diagram showing an example of the input / output relationship of the four-path optical splitter 34. Hereinafter, it is assumed that optical signals of wavelengths λ1 to λ4 are input to the splitter 34b from ports C1 to C4, respectively. Note that the optical signals of wavelengths λ1 to λ4 may be referred to as optical signals λ1 to λ4, respectively. IN in Fig. 10 indicates whether or not an optical signal is input to each of ports C1 to C4, with λ1 to λ4 indicating that an input is present and 0 indicating that an input is not present. OUT in Fig. 10 indicates whether or not the optical signals input in the combinations shown in IN are output from the splitter 34b to ports C1 to C4, with λ1 to λ4 indicating that an output is present and 0 indicating that an output is not present.

[0061] 10, when one or more optical signals λ1 to λ4 are input from one or more ports of four ports C1 to C4, the four-way optical branching device 34 outputs the optical signals from three ports other than the port that input the optical signals. That is, the four-way optical branching device 34 branches the optical signal λ1 input from port C1 to all of ports C2 to C4 other than C1.

[0062] When optical signals are input to the splitter 34b from two or more ports among ports C1 to C4, the four-way optical splitter 34 may output each optical signal to a port that complies with the above-mentioned conditions. As an example, assume that an optical signal λ1 is input from port C1, an optical signal λ2 is input from port C2, an optical signal λ3 is input from port C3, and an optical signal λ4 is input from port C4 simultaneously to the four-way optical splitter 34. In this case, the four-way optical splitter 34 outputs the optical signal λ1 to all of ports C2 to C4, outputs the optical signal λ2 to all of ports C1, C3, and C4, outputs the optical signal λ3 to all of ports C1, C2, and C4, and outputs the optical signal λ4 to all of ports C1 to C3.

[0063] 10 shows an example in which an optical signal of a single wavelength is input from each port to the branching device 34b (four-path optical branching device 34), but this is not limiting, and two or more optical signals of different wavelengths may be input simultaneously to the branching device 34b from one port. For example, when optical signals λ1 and λ1' are input simultaneously from port C1, the four-path optical branching device 34 outputs both of the two optical signals λ1 and λ1' to each of ports C2 to C4.

[0064] When connecting four chiplets 2, the four-way optical splitter 34 may be connected to the optical waveguides A3 of the one-to-two optical splitters 31 connected to the four OEs 6 via the optical waveguides 33 of, for example, four optical waveguides C1 to C4. This allows the optical wiring unit 3 including one four-way optical splitter 34 to connect (connect) all four chiplets 2 so that they can communicate with each other.

[0065] In this way, two three-way optical splitters 32 (see FIG. 4) and one four-way optical splitter 34 can be said to be equivalent to each other as configurations of the optical wiring unit 3 for connecting four chiplets 2. For example, in the two three-way optical splitters 32 shown in FIG. 4, a total of four optical waveguides 32c for connecting to the one-to-two optical splitter 31 have the same input / output relationship as that shown in FIG. 10. Therefore, the four-way optical splitter 34 may be formed, for example, by four one-to-three optical splitters as shown in FIG. 9, or may be formed by 3×2=6 one-to-two optical splitters 31 as shown in FIGS. 4 and 5.

[0066] From the above, it can be said that a combination of one or both of the three-way optical branch 32 and the four-way optical branch 34 in the optical wiring unit 3 is an example of an n-way optical branch 30 (see FIGS. 3 and 4) (n is an integer equal to or greater than 3) that has n optical waveguides 33. In the following explanation, we will take as an example a case where the number of chiplets 2 is the same as n. When n=4, the n-way optical branch 30 has four (n) optical waveguides 33 for connection to four (n) 1-to-2 optical branch 31 (chiplets 2), respectively, as shown in FIG. 4 or 9.

[0067] The number n of chiplets 2 communicatively connected to each other can be increased by increasing the number of one or both of the three-path optical splitters 32 and the four-path optical splitters 34 included in the optical wiring unit 3 and increasing the value of n in the n-path optical splitter 30. This makes it possible to suppress an increase in the wiring area of ​​the optical wiring unit 3 compared to, for example, increasing the number of chiplets 200 in the processor 100 shown in FIG.

[0068] 11 is a diagram showing another example of connections between chiplets 2 of a processor 1. The optical wiring unit 3 may include an n-branch optical branching unit 30 (n=6) including two three-branch optical branching units 32 and one four-branch optical branching unit 34 interposed between the two three-branch optical branching units 32. This allows six chiplets 2 to be connected to each other so that they can communicate with each other via a single optical wiring system. In the example shown in FIG. 11, the number of chiplets 2 can be further increased by increasing the number of four-branch optical branching units 34 or three-branch optical branching units 32 interposed between the two three-branch optical branching units 32.

[0069] [B-2] Explanation of OE In the above-mentioned processor 1, an optical signal transmitted from one of the multiple chiplets 2 connected to the optical wiring unit 3 is transmitted to all other chiplets 2 other than the chiplet 2 in question via the optical wiring unit 3, in other words, broadcast.

[0070] Each of the chiplets 2 implemented in the processor 1 outputs optical signals of wavelengths different from each other between the chiplets 2 from TX7 of the OE6 provided in the IO die 5 to the 1:2 optical splitter 31. In addition, each chiplet 2 receives an optical signal of a wavelength different from the wavelength of the optical signal output from TX7 from the 1:2 optical splitter 31 at RX8 of the OE6 provided in the IO die 5.

[0071] This allows multiple chiplets 2 in the processor 1 to simultaneously perform broadcast communication using essentially one branched optical wiring unit 3. Therefore, while ensuring communication functionality between the chiplets 2, communication between the chiplets 2 can be achieved using an optical wiring unit 3 that is smaller in area (for example, has a smaller number of optical waveguides) than the optical wiring unit 300 shown in Fig. 2. In other words, the area of ​​the package (processor 1) can be prevented from increasing.

[0072] Furthermore, even when an upper limit is set on the package area, the processor 1 can reduce the area occupied by the optical wiring unit 3 compared to the processor 100 shown in Fig. 1. This allows the area available for mounting the chiplets 2 in the package to be expanded, thereby increasing the number of chiplets 2 that can be mounted in the processor 1.

[0073] Fig. 12 is a block diagram showing an example configuration of the IO die 5 shown in Fig. 3. Fig. 12 shows an example configuration of the IO die 5 focusing on one OE 6 when four chiplets 2 are implemented in the processor 1. In Fig. 12, an internal communication unit for communication between the IO die 5 and the core die 4 is not shown.

[0074] The IO die 5 may include a destination information addition unit 51, a transmission data memory 52, destination information analysis units 53a to 53c, reception data memories 54a to 54c, and a wavelength setting unit 55. Hereinafter, when there is no need to distinguish between the destination information analysis units 53a to 53c, they will simply be referred to as the destination information analysis unit 53. When there is no need to distinguish between the reception data memories 54a to 54c, they will simply be referred to as the reception data memory 54.

[0075] The transmission data memory 52 is a memory that stores transmission data including data to be transmitted and the destination of the data, and may be realized by a relatively high-speed storage device such as an SRAM (Static Random Access Memory) or a register. The transmission data stored in the transmission data memory 52 is sequentially read out from the transmission data memory 52 by the TX 7 in accordance with, for example, FIFO (First-In, First-Out) and transmitted to the optical wiring unit 3.

[0076] 13 is a diagram showing an example of the configuration of transmission data 10. The transmission data 10 includes a destination information section 10a indicating destination information (destination) and a data section 10b indicating data to be transmitted to the destination. The destination information may be, for example, identification information (ID: Identifier) ​​of the destination chiplet 2 (e.g., core die 4), OE6, RX8, or the like, and may also be referred to as a DID (Destination ID).

[0077] The destination information addition unit 51 adds a destination information section 10a (destination information) of the data section 10b (data to be transmitted) input from the core die 4 to the data section 10b, and stores the resulting transmission data 10 in the transmission data memory 52. ​​The destination information section 10a may be input to the destination information addition unit 51 from the core die 4 together with the data section 10b. Note that if the transmission data 10 itself is input to the IO die 5 by the core die 4, the destination information addition unit 51 may be omitted, and the input transmission data 10 may be stored in the transmission data memory 52.

[0078] The TX 7 may include an electro-optical converter 71 that performs electro-optical conversion to convert an electrical signal (transmission data 10) into an optical signal. The electro-optical converter 71 is an example of a transmitter. The electro-optical converter 71 uses the transmission data 10 read from the transmission data memory 52 to modulate the signal light output from the external laser 9, thereby generating an optical signal on which the transmission data 10 is superimposed, and transmits the generated optical signal to one of the two input / output sides of the 1:2 optical splitter 31. This allows the optical signal on which the transmission data 10 is superimposed to be appropriately transmitted from the OE 6 to the optical wiring unit 3. The modulation method may be a digital modulation method or an analog modulation method, such as intensity (amplitude) modulation, phase modulation, or various other modulation methods.

[0079] The external laser 9 is an example of a light source that generates signal light that serves as a carrier wave. The signal light (light, laser) output from the external laser 9 may have a wavelength that differs from one another for each TX 7 (OE 6). The external laser 9 may be, for example, a semiconductor laser (LD: Laser Diode), for example, a wavelength-tunable semiconductor laser. The external laser 9 may be provided outside the chiplet 2 of the processor 1, or may be provided in the IO die 5 or the optical wiring unit 3, or may be provided outside the processor 1.

[0080] The electro-optical converter 71 converts the wavelength emitted by the external laser 9, for example, wavelength λ 2 , into a signal using the transmission data 10, which is an electrical signal. A The carrier wave of wavelength λ A The optical signal is output.

[0081] TX7 transmits an optical signal with a wavelength λ A In the example of Figure 12, the wavelength is λ B ,λ C ,λ DThe blocking filter may be provided in the section from the electro-optical converter 71 to the optical waveguide 33 on the two input / output sides of the 1:2 optical splitter 31, for example, at the optical signal output end of the electro-optical converter 71. With this, of the optical signals incident on both TX7 and RX8 of the OE6 from the two input / output sides of the 1:2 optical splitter 31 via the optical wiring unit 3, the optical signal incident on TX7 is blocked, while the optical signal incident on RX8 of the OE6 with wavelength λ is blocked. A This optical signal can be transmitted to the 1:2 optical splitter 31. Therefore, even when a plurality of chiplets 2 communicate simultaneously via the optical wiring unit 3, it is possible to reduce the possibility that the transmission process of the optical signal from the TX 7 will be hindered, and the transmission process can be executed appropriately.

[0082] The RX 8 may include wavelength-selective filters 81a to 81c and photoelectric converters 82a to 82c. Hereinafter, when there is no need to distinguish between the wavelength-selective filters 81a to 81c, they will simply be referred to as wavelength-selective filters 81. Furthermore, when there is no need to distinguish between the photoelectric converters 82a to 82c, they will simply be referred to as photoelectric converters 82.

[0083] The wavelength selection filter 81 is an example of a wavelength filter that passes an optical signal of a predetermined wavelength. The wavelength selection filter 81 may be, for example, any of various optical filters such as a ring filter, and one example is a wavelength tunable filter that can variably set a predetermined wavelength.

[0084] The photoelectric converter 82 performs photoelectric conversion processing to convert an optical signal into an electrical signal (transmission data 10). The photoelectric converter 82 is an example of a receiving unit that demodulates an optical signal of a predetermined wavelength that has passed through the wavelength selection filter 81, thereby acquiring (receiving) the transmission data 10 superimposed on the optical signal.

[0085] The RX 8 may include one or more (for example, n-1 sets) of wavelength selection filters 81 and photoelectric converters 82. This allows each OE 6 to receive optical signals of n-1 different wavelengths, other than the wavelength transmitted by the TX 7 of its own chiplet 2, among the n optical signals of different wavelengths transmitted by the n chiplets 2. For example, when n=4, there are three wavelengths λ B ,λ C ,λ D In order to be able to receive the optical signals transmitted from the OEs 6, the RX 8 includes three wavelength-selective filters 81a to 81c and three photoelectric converters 82a to 82c corresponding to the wavelength-selective filters 81a to 81c. The three wavelength-selective filters 81a to 81c are set to have different transmission wavelengths (predetermined wavelengths) so that the three wavelength-selective filters 81a to 81c can receive the optical signals transmitted from the OEs 6, for example.

[0086] The destination information analysis unit 53 is an example of a determination unit that determines whether to discard the data portion 10b included in the demodulated transmission data 10 based on the destination included in the demodulated transmission data 10. The destination information analysis unit 53, for example, analyzes the destination information portion 10a of the transmission data 10 that has passed through the wavelength selection filter 81 and been demodulated into an electrical signal by the photoelectric converter 82, and determines whether the destination indicated by the destination information portion 10a matches its own identification information. The own identification information may be, for example, the ID of the chiplet 2 to which it belongs (e.g., the core die 4), OE6, or RX8, etc. If the destination matches its own identification information, the destination information analysis unit 53 stores the transmission data 10 in the received data memory 54. If the destination does not match its own identification information, the destination information analysis unit 53 discards the data portion 10b (transmission data 10). This makes it possible to realize individual communication between two or more chiplets 2 while interconnecting multiple chiplets 2 in a manner that enables broadcast communication.

[0087] The received data memory 54 is a memory for storing the received transmission data 10 (received data) addressed to the core die 4, and may be realized by a relatively high-speed storage device such as an SRAM or a register. The received data stored in the transmission data memory 52 is sequentially read out from the received data memory 54 by the IO die 5, for example, according to FIFO, and transmitted to the core die 4, for example, via an internal communication unit (not shown).

[0088] For example, when n=4, the IO die 5 includes three (n-1) destination information analysis units 53a to 53c corresponding to the photoelectric converters 82a to 82c, and three (n-1) received data memories 54 corresponding to the destination information analysis units 53a to 53c.

[0089] In this way, the IO die 5 has sets (systems) of wavelength selection filters 81, photoelectric converters 82, destination information analyzers 53, and received data memories 54, the number of which is equal to n-1, the number of wavelengths of optical signals received by the OE 6. As a result, even when the chiplet 2 simultaneously receives optical signals from 2 to n-1 chiplets 2, it is possible to perform reception processing in parallel using each set for each wavelength corresponding to the source chiplet 2. This reduces the possibility that the reception processing of optical signals in the RX 8 and the IO die 5 will be hindered or fail, and allows the reception processing to be performed appropriately.

[0090] The wavelength setting unit 55 is an example of a setting unit that sets the wavelength of the optical signal transmitted from the TX 7 and the transmission wavelength (predetermined wavelength) of the wavelength selection filter 81.

[0091] In the example of FIG. 12, as an example of setting the wavelength of the optical signal transmitted from the TX 7, the wavelength setting unit 55 sets the wavelength of the optical signal transmitted from the electro-optical converter 71 to the wavelength λ 1 corresponding to the chiplet 2. A The setting may include, for example, setting the transmission wavelength of the cutoff filter of the TX7. In this case, the external laser 9 may be configured to have, for example, multiple wavelengths (for example, when n=4, wavelength λ A ~λ DAlternatively, if the external laser 9 is wavelength tunable, the wavelength of the optical signal transmitted from the TX 7 may be set by, for example, setting the wavelength of the signal light (laser) emitted by the external laser 9 to a wavelength λ A The above-described settings, such as the settings for the electro-optical converter 71 and / or the external laser 9, can ensure that optical signals of different wavelengths are transmitted from the electro-optical converter 7 for each chiplet 2.

[0092] Furthermore, as an example of setting the transmission wavelength of the wavelength selection filter 81, the wavelength setting unit 55 sets n wavelengths λ for the n−1 wavelength selection filters 81 a to 81 c. A ~λ D Each of the wavelengths λ B ,λ C ,λ D It is possible to set the wavelength to pass only the candidate wavelength λ A ~λ D The wavelength λ of the optical signal transmitted from TX7 of its own OE6 A may be excluded.

[0093] In the example of FIG. 12, the wavelength setting unit 55 sets the wavelength selection filter 81a to the wavelength λ B The wavelength selection filter 81b selects the wavelength λ C The wavelength selection filter 81c is a wavelength λ D The optical signals input to RX8 from the two input / output sides of the 1:2 optical splitter 31 are incident on all of the wavelength selection filters 81a to 81c, and each of the wavelength selection filters 81a to 81c blocks the passage of optical signals with wavelengths other than the set transmission wavelength.

[0094] For example, the wavelength λ input to RX8 B The optical signal of wavelength λ 1 passes only through the wavelength selection filter 81a, without passing through the wavelength selection filters 81b and 81c. BThe optical signal is photoelectrically converted by the photoelectric converter 82a. The transmission data 10 obtained by the photoelectric conversion is analyzed by the destination information analyzer 53a, and if it is addressed to the chiplet 2, it is stored in the received data memory 54a. Similarly, the wavelength λ C The optical signal passes through only the wavelength selection filter 81b among the wavelength selection filters 81a to 81c. The transmission data 10 obtained from the optical signal by photoelectric conversion is stored in the reception data memory 54b according to the analysis result by the destination information analysis unit 53b. D The optical signal passes through only the wavelength selection filter 81c among the wavelength selection filters 81a to 81c. The transmission data 10 obtained from the optical signal by photoelectric conversion is stored in the received data memory 54c according to the analysis result by the destination information analysis unit 53c.

[0095] The wavelength setting unit 55 may set the wavelength for a control object, such as the electro-optical converter 71 (or cutoff filter), the external laser 9, or the wavelength selection filter 81, by using various known control methods such as electrical control or temperature control. Information indicating the wavelength to be set for each of the control objects may be set (specified) in the wavelength setting unit 55 at a predetermined timing such as during design, manufacture, initial setup, or initial operation of the processor 1 having multiple chiplets 2.

[0096] In this way, the wavelength of the optical signal transmitted from TX7 and the transmission wavelength of the wavelength selection filter 81 in RX8 are set to different wavelengths by the wavelength setting unit 55, so that the transmission process by TX7 and the reception process by RX8 can be performed appropriately.

[0097] [B-3] Example of operation Fig. 14 is a diagram for explaining an example of the operation of the processor 1. Fig. 14 shows an example of the operation of the processor 1 when transmission data 10 is transmitted from IO die #0 to IO die #3 and when transmission data 10 is transmitted from IO die #2 to IO die #3. Hereinafter, when TX7 is to be distinguished, it will be written as TX#0 to #3, and when RX8 is to be distinguished, it will be written as RX#0 to #3. Furthermore, the wavelength setting unit 55 sets wavelengths λ0, λ1, λ2, and λ3 as the wavelengths of the optical signals transmitted by each of the IO dies #0 to #3, and sets three wavelengths other than the wavelength of the optical signals to be transmitted as the transmission wavelengths of the wavelength selection filters 81a to 81c.

[0098] The destination information addition units 51 of TX#0 of IO die #0 and TX#2 of IO die #2 store the transmission data 10, in which a destination information section 10a indicating the chiplet 2 having the IO die #3 is added to the data section 10b, in the transmission data memory 52. ​​In FIG. 14, the transmission data 10 of TX#0 is denoted as "D0", and will be referred to as transmission data D0 in the following description. Furthermore, the transmission data 10 of TX#2 is denoted as "D2", and will be referred to as transmission data D2 in the following description.

[0099] TX#0 transmits an optical signal obtained by modulating a signal light of wavelength λ0 using transmission data D0 with an electro-optical converter 71 to the optical wiring unit 3. On the other hand, TX#2 transmits an optical signal obtained by modulating a signal light of wavelength λ2 using transmission data D2 with an electro-optical converter 71 to the optical wiring unit 3. In FIG. 14, the signal light output from the external laser 9 in TX#0 is indicated by a hatched block, and the signal light output from the external laser 9 in TX#2 is indicated by a shaded block. Furthermore, the optical signal on which transmission data D0 is superimposed and transmitted from TX#0 is indicated by a hatched block "D0," and will be referred to as optical signal D0 in the following description. Furthermore, the optical signal on which transmission data D2 is superimposed and transmitted from TX#2 is indicated by a hatched block "D2," and will be referred to as optical signal D2 in the following description.

[0100] An optical signal D0 output from TX #0 to the optical wiring unit 3 reaches a three-way optical splitter 32 (upper side of the drawing) via a one-to-two optical splitter 31, and is output to an optical waveguide 33 branching to the IO die #2 side and an optical waveguide 33 branching to the IO die #1 and #3 sides. Similarly, an optical signal D2 output from TX #2 to the optical wiring unit 3 reaches a three-way optical splitter 32 (upper side of the drawing) via a one-to-two optical splitter 31, and is output to an optical waveguide 33 branching to the IO die #2 side and an optical waveguide 33 branching to the IO die #1 and #3 sides. Furthermore, the optical signals D0 and D2 reach the three-way optical splitter 32 (lower side of the drawing) via the optical waveguide 33, and are output to an optical waveguide 33 branching to the IO die #1 side and an optical waveguide 33 branching to the IO die #3 side, respectively. The optical signals transmitted from each IO die 5 propagate through the optical wiring section 3 at the same time, but since the wavelengths of the optical signals are different, they can be transmitted without interfering with each other.

[0101] Optical signal D0 is input to TX#2 and RX#2 via a 1:2 optical splitter 31 connected to IO die #2. The electro-optical converter 71 of TX#2 has a blocking filter that does not pass optical signals of wavelengths other than the wavelength λ2 of the optical signal D2 it outputs, so the optical signal D0 transmitted from TX#0 is blocked by TX#2 and does not pass through the electro-optical converter 71. The same is true for TX#1 and #3.

[0102] In RX#2, the optical signal D0 reaches a wavelength selection filter 81a that passes an optical signal with a wavelength λ0, a wavelength selection filter 81b that passes an optical signal with a wavelength λ1, and a wavelength selection filter 81c that passes an optical signal with a wavelength λ3. Because the optical signal D0 has a wavelength λ0, it passes through the wavelength selection filter 81a without passing through the wavelength selection filters 81b and 81c. The photoelectric converter 82a demodulates the optical signal D0 that passed through the wavelength selection filter 81a to obtain the transmission data D0. The destination information analysis unit 53a determines whether the demodulated (obtained by demodulation) transmission data D0 is addressed to its own IO die #2 (its own chiplet 2) by comparing the destination information unit 10a with the identification information of the IO die #2. Because the destination information unit 10a indicates IO die #3, the destination information analysis unit 53a determines that the transmission data D0 is not addressed to IO die #2 and discards the transmission data D0. The same is true for RX#1.

[0103] Optical signal D2 is input to TX#0 and RX#0 via a 1:2 optical splitter 31 connected to IO die #0. The electro-optical converter 71 of TX#0 has a blocking filter that does not pass optical signals of wavelengths other than the wavelength λ0 of the optical signal D0 that it outputs, so the optical signal λ2 output from TX#2 is blocked by TX#0 and does not pass through the electro-optical converter 71. The same is true for TX#1 and #3.

[0104] In RX#0, the optical signal D2 reaches the wavelength selection filter 81a, which passes an optical signal with a wavelength λ1, the wavelength selection filter 81b, which passes an optical signal with a wavelength λ2, and the wavelength selection filter 81c, which passes an optical signal with a wavelength λ3. Because the optical signal D2 has a wavelength λ2, it passes through the wavelength selection filter 81b without passing through the wavelength selection filters 81a and 81c. The photoelectric converter 82b demodulates the optical signal D2 that passed through the wavelength selection filter 81b to obtain the transmission data D2. The destination information analysis unit 53b compares the destination information unit 10a with the identification information of the IO die #0 to determine whether the demodulated (obtained by demodulation) transmission data D2 is addressed to its own IO die #0 (the chiplet 2 to which it belongs). Because the destination information unit 10a indicates IO die #3, the destination information analysis unit 53b determines that the transmission data D2 is not addressed to IO die #0 and discards the transmission data D2. The same applies to RX#1.

[0105] In RX#3, the optical signals D0 and D2 reach a wavelength selection filter 81a that passes an optical signal of wavelength λ0, a wavelength selection filter 81b that passes an optical signal of wavelength λ1, and a wavelength selection filter 81c that passes an optical signal of wavelength λ2.

[0106] Since the optical signal D0 has a wavelength λ0, it passes through the wavelength selection filter 81a without passing through the wavelength selection filters 81b and 81c. The photoelectric converter 82a demodulates the optical signal D0 that passed through the wavelength selection filter 81a to obtain the transmission data D0. The destination information analysis unit 53a determines whether the demodulated (obtained by demodulation) transmission data D0 is addressed to its own IO die #3 (the chiplet 2 to which it belongs) by comparing the destination information unit 10a with the identification information of the IO die #3. Because the destination information unit 10a indicates the IO die #3, the destination information analysis unit 53a determines that the transmission data D0 is addressed to the IO die #3 and stores the transmission data D0 in the received data memory 54a. The transmission data D0 is sequentially read from the received data memory 54a and transmitted to the core die 4.

[0107] Since the optical signal D2 has a wavelength λ2, it passes through the wavelength selection filter 81c without passing through the wavelength selection filters 81a and 81b. The photoelectric converter 82c demodulates the optical signal D2 that passed through the wavelength selection filter 81c to obtain the transmission data D2. The destination information analysis unit 53c determines whether the demodulated (obtained by demodulation) transmission data D2 is addressed to its own IO die #3 (the chiplet 2 to which it belongs) by comparing the destination information unit 10a with the identification information of the IO die #3. Because the destination information unit 10a indicates the IO die #3, the destination information analysis unit 53c determines that the transmission data D2 is addressed to the IO die #3 and stores the transmission data D2 in the reception data memory 54c. The transmission data D2 is sequentially read from the reception data memory 54c and transmitted to the core die 4.

[0108] As described above, according to the processor 1 of one embodiment, it is possible to perform communication in parallel (e.g., simultaneously) between multiple chiplets 2 via the optical wiring section 3, which is an example of a single optical waveguide.

[0109] 14 illustrates an example of the operation of the processor 1 in which two optical signals D0 and D2 are simultaneously transmitted and each of the optical signals D0 and D2 is destined for the same IO die #3. However, this is not limiting. For example, three or more optical signals may be simultaneously transmitted. Furthermore, an optical signal transmitted from one IO die 5 may be destined for multiple IO dies 5, including all IO dies 5 other than the IO die 5 itself (i.e., broadcast communication). In either case, one or more IO dies 5 transmit optical signals of different wavelengths, and the RX8 of each IO die 5 receives and processes the optical signals for each wavelength. This allows simultaneous communication between multiple chiplets 2 via multiple chiplets 2 and the optical wiring unit 3 compatible with WDM.

[0110] [B-4] Modified example Fig. 15 is a block diagram showing a modified example of the configuration of the IO die 5 shown in Fig. 3. The IO die 5A shown in Fig. 15 may include one destination information analyzer 56 instead of the three destination information analyzers 53a to 53c shown in Fig. 12. In the IO die 5A, the transmission data 10 obtained by demodulating the optical signals using the photoelectric converters 82a, 82b, and 82c is stored in the corresponding reception data memories 54a, 54b, and 54c.

[0111] The destination information analysis unit 56 may sequentially read out the transmission data 10 from the reception data memories 54a, 54b, and 54c in accordance with a predetermined condition, and analyze the destination information section 10a of the transmission data 10. Note that the predetermined condition may be, for example, a variety of selection (arbitration) orders for the reception data memories 54, such as round robin or the priority of each of the reception data memories 54a, 54b, and 54c.

[0112] If the destination information section 10a matches its own identification information, the destination information analysis section 56 may transmit the read transmission data 10 (data section 10b) to the core die 4. Furthermore, if the destination information section 10a does not match its own identification information, the destination information analysis section 56 may discard the transmission data 10 (data section 10b).

[0113] Thus, according to the modified IO die 5A shown in Figure 15, the destination information analysis unit 56 can be shared between two or more IO dies 5 or 5A that are the source of the transmission data 10, thereby making it possible to reduce the mounting area of ​​the chiplet 2 compared to the IO die 5.

[0114] FIG. 16 is a diagram showing a modified example of the connection between the chiplets 2 of the processor 1 shown in FIG. 3. In FIG. 16, attention is focused on the OE6B, which is a part of each chiplet 2. FIG. 16 shows an example in which six chiplets 2 are implemented in one processor 1. As shown in FIG. 16, each of the multiple chiplets 2 according to the modified example is connected to each other so that they can communicate with each other by optically connecting the OE6B provided in each chiplet 2 with the optical wiring unit 3B. In FIG. 16, the OE6B of the six chiplets 2 are denoted as OE#0 to OE#5, respectively.

[0115] The OE6B may include the TX7 and the RX8, as well as the optical waveguide 33 and the 1:2 optical splitter 31. In this way, compared to the OE6 shown in FIG. 4 , the OE6B can be said to be a configuration in which the optical waveguide 33 and the 1:2 optical splitter 31 included in the optical wiring unit 3 are mounted within the OE6B, in other words, in the chiplet 2.

[0116] 16, the optical wiring unit 3B includes two three-path optical branching units 32 and one four-path optical branching unit 34 as the n-path optical branching unit 30. The optical wiring unit 3B may also include an optical waveguide 33 (not shown) that connects the n-path optical branching unit 30 and the one-to-two optical branching unit 31 included in the OE6B.

[0117] 16, it is possible to mount the 1-to-2 optical splitter 31 in the OE6B (chiplet 2). Generally, by mounting components related to the chiplet 2 together in one chiplet 2, it is possible to reduce the mounting area of ​​the entire package of the processor 1. Furthermore, since the mounting area of ​​the optical wiring unit 3B in the processor 1 can be reduced compared to the optical wiring unit 3 shown in FIG. 4, it is possible to suppress an increase in the area of ​​the entire package of the processor 1.

[0118] [B-5] Example of IO die configuration according to the number of chiplets Fig. 17 is a block diagram showing another configuration example of the IO die 5 shown in Fig. 3. Fig. 17 shows a configuration example of the IO die 5 focusing on one OE 6 when six (n=6) chiplets 2 are implemented in the processor 1 (see Fig. 11).

[0119] 17, the RX8 includes n-1 sets (for example, five sets) of wavelength selection filters 81 and photoelectric converters 82. The wavelength setting unit 55 sets the transmission wavelengths of the wavelength selection filters 81a to 81e so that optical signals of different wavelengths output by the other five chiplets 2 pass through. For example, if the chiplet 2 has a wavelength λ B ~λ FWhen five chiplets 2 are connected to each other, each of the wavelength selection filters 81a to 81e has a wavelength λ B ~λ F is set.

[0120] In this way, by increasing the number of pairs of wavelength-selective filters 81 and photoelectric converters 82, it is possible to increase the number of chiplets 2 that can be connected to each other and simultaneously so as to be able to communicate with each other.

[0121] [C] Example of a computer configuration with a processor 18 is a block diagram showing an example of the hardware configuration of a computer 11 including a processor 1 according to an embodiment. The computer 11 is an example of an information processing device, and may be, for example, a server or a supercomputer.

[0122] As shown in FIG. 18, the computer 11 may illustratively include a processor 1, a graphics processing unit 11a, a memory 11b, a storage unit 11c, an IF (Interface) unit 11d, and an IO (Input / Output) unit 11e.

[0123] The processor 1 is an example of a processing unit that performs various controls and calculations, and may be connected to each block in the computer 11 via a bus 11f so that they can communicate with each other. As described above, the processor 1 may be a multi-core processor having multiple processor cores. The processor 1 may also be a multi-processor including multiple processors, or may have a configuration having multiple multi-core processors.

[0124] The graphics processing device 11a controls screen display for an output device such as a monitor in the IO unit 11e. The graphics processing device 11a may have a configuration as an accelerator that executes machine learning processing and inference processing using a machine learning model.

[0125] The memory 11b and the storage unit 11c each store various types of data, programs, and other information. Examples of the memory 11b include one or both of a volatile memory such as a dynamic random access memory (DRAM) and a nonvolatile memory such as a persistent memory (PM). Examples of the storage unit 11c include various storage devices such as a magnetic disk device such as a hard disk drive (HDD), a semiconductor drive device such as a solid state drive (SSD), and a nonvolatile memory. Examples of the nonvolatile memory include a flash memory, a storage class memory (SCM), and a read-only memory (ROM).

[0126] The storage unit 11c may store programs that realize all or part of the various functions of the computer 11. For example, the processor 1 can realize the functions of various software such as an OS (Operating System) and application programs by expanding the programs stored in the storage unit 11c into the memory 11b and executing them.

[0127] The IF unit 11d is an example of a communication IF that controls connection and communication between the computer 11 and other computers.

[0128] The IO unit 11e includes one or both of an input device such as a keyboard, a mouse, a touch panel, etc. and an output device such as a monitor, a projector, a printer, etc. The output device may be connected to the graphics processing device 11a.

[0129] The above-described hardware configuration of the computer 11 is an example. Therefore, the hardware in the computer 11 may be increased or decreased (for example, adding or deleting any block), divided, integrated in any combination, or buses may be added or deleted as appropriate.

[0130] [D] Other The techniques according to the above-described embodiment and modified examples can be implemented with the following modifications and variations.

[0131] For example, in the processor 1 according to the embodiment and the modified example, four or six chiplets 2 are implemented in the processor 1, but the number of chiplets 2 implemented in the processor 1 may be more than six. When the number of chiplets 2 in the processor 1 is more than six, the number of sets of wavelength selection filters 81 and photoelectric converters 82 in the OE6 or 6B may be increased according to the number of chiplets 2. In this case, the number of either or both of the three-branch optical splitters 32 and the four-branch optical splitters 34 may be increased so as to increase the number n in the n-branch optical splitter 30.

[0132] Furthermore, in the embodiment and modified example, the number of chiplets 2 connected via the optical wiring unit 3 or 3B is described as n, but this is not limited thereto, and it is sufficient that the number of OEs 6 or 6B connected via the optical wiring unit 3 or 3B is n. For example, when two or more OEs 6 or 6B provided in one chiplet 2 are connected to the same optical wiring unit 3 or 3B (n-bifurcation optical branching unit 30), the number of OEs 6 is n, but the number of chiplets 2 is less than n. Even in this case, the OEs 6 or 6B can be connected to each other so that they can communicate with each other via the optical wiring unit 3 or 3B.

[0133] Furthermore, in the embodiment and the modified example, the n-path optical branching unit 30 is exemplified by one or more three-path optical branching units 32, one or more four-path optical branching units 34, or a combination of one or more three-path optical branching units 32 and one or more four-path optical branching units 34, but is not limited to these. For example, an optical branching unit capable of branching into five or more branches may be used as the n-path optical branching unit 30 in addition to or instead of these.

[0134] Furthermore, in the processor 1 according to the embodiment and the modified example, the chiplet 2 and the optical wiring unit 3 or 3B are arranged in a two-dimensional space, but the chiplet 2 and the optical wiring unit 3 or 3B may be arranged in a three-dimensional space.

[0135] [E] Supplementary Note The following additional notes are provided regarding the above-described embodiment and modifications.

[0136] (Appendix 1) a plurality of chiplets each including a core and an input / output unit; a plurality of 1:2 optical branching units, each having two input / output sides connected to the input / output unit; an n (n is an integer of 3 or more) path optical branching unit that is connected to one input / output side of the plurality of one-to-two optical branching units and outputs an optical signal input from any one input / output side of the plurality of one input / output sides to one or more other one input / output sides of the plurality of one input / output sides, The input / output unit transmits optical signals having wavelengths different from each other among the plurality of chiplets to one of the two input / output sides, and receives an optical signal having a wavelength different from the wavelength of the optical signal to be output from the other of the two input / output sides. Processing unit.

[0137] (Appendix 2) the input / output unit includes a transmitter that transmits the optical signal obtained by modulating signal light output from a light source using transmission data including data to be transmitted to one of the two input / output sides; 2. The processing device of claim 1.

[0138] (Appendix 3) The input / output unit a wavelength filter that passes an optical signal of a predetermined wavelength among optical signals input from the other of the two input / output sides; a receiving unit that receives the transmission data by demodulating the optical signal of the predetermined wavelength that has passed through the wavelength filter; 3. The processing device according to claim 2.

[0139] (Appendix 4) The transmission data further includes a destination of the data; The input / output unit a determination unit that determines whether or not to discard the data included in the demodulated transmission data based on the destination included in the demodulated transmission data; 4. The processing device according to claim 3.

[0140] (Appendix 5) The input / output unit a setting unit that sets the wavelength of the optical signal to be transmitted and the predetermined wavelength of the wavelength filter; 5. The processing device according to claim 3 or 4.

[0141] (Appendix 6) Each of the plurality of 1:2 optical branching units is mounted within the chiplet including the input / output unit to which the two input / output sides are connected. The processing device according to any one of Supplementary notes 1 to 5.

[0142] (Appendix 7) The n-path branching unit includes one or both of a three-path branching unit and a four-path branching unit. The arithmetic processing device according to any one of Supplementary notes 1 to 6.

[0143] (Appendix 8) a plurality of chiplets each including a core and an input / output unit; a plurality of 1:2 optical branching units, each having two input / output sides connected to the input / output unit; an n (n is an integer of 3 or more) path optical branching unit that is connected to one input / output side of the plurality of 1:2 optical branching units and outputs an optical signal input from any one input / output side of the plurality of 1 input / output sides to one or more other 1 input / output sides of the plurality of 1 input / output sides, The input / output unit transmits optical signals having wavelengths different from each other among the plurality of chiplets to one of the two input / output sides, and receives an optical signal having a wavelength different from the wavelength of the optical signal to be output from the other of the two input / output sides. Information processing device.

[0144] (Appendix 9) the input / output unit includes a transmitter that transmits the optical signal obtained by modulating signal light output from a light source using transmission data including data to be transmitted to one of the two input / output sides; 9. The information processing device according to claim 8.

[0145] (Appendix 10) The input / output unit a wavelength filter that passes an optical signal of a predetermined wavelength among optical signals input from the other of the two input / output sides; a receiving unit that receives the transmission data by demodulating the optical signal of the predetermined wavelength that has passed through the wavelength filter; 10. The information processing device according to claim 9.

[0146] (Appendix 11) The transmission data further includes a destination of the data; The input / output unit a determination unit that determines whether or not to discard the data included in the demodulated transmission data based on the destination included in the demodulated transmission data; 11. The information processing device according to claim 10.

[0147] (Appendix 12) The input / output unit a setting unit that sets the wavelength of the optical signal to be transmitted and the predetermined wavelength of the wavelength filter; 12. The information processing device according to claim 10 or 11.

[0148] (Appendix 13) Each of the plurality of 1:2 optical branching units is mounted within the chiplet including the input / output unit to which the two input / output sides are connected. The information processing device according to any one of Supplementary notes 8 to 12.

[0149] (Appendix 14) The n-path branching unit includes one or both of a three-path branching unit and a four-path branching unit. An information processing device according to any one of Supplementary notes 8 to 13. [Explanation of symbols]

[0150] 1 processor 10 Transmission Data 10a Destination information section 10b Data section 11 Computer 2 chiplets 3,3B Optical wiring section 30 n-path optical branch 31 1:2 optical splitter 31a, 32b, 34b turnouts 31b,31c,32c,33,34c Optical waveguide 32 Three-way optical splitter 32a, 34a connection 34 4-way optical splitter 4 Core Die 5,5A IO die 51 Destination information addition section 52 Transmission data memory 53, 53a to 53e, 56 Destination information analysis unit 54, 54a to 54e Received data memory 55 Wavelength setting section 6,6B OE 7 TX 71 Electric-to-optical converter 8RX 81, 81a to 81e Wavelength selection filters 82, 82a to 82e Photoelectric converter 9 External Laser

Claims

1. a plurality of chiplets each including a core and an input / output unit; a plurality of one-to-two optical branching units, each having two input / output sides connected to the input / output unit; an n (n is an integer of 3 or more) path optical branching unit connected to one input / output side of the plurality of one-to-two optical branching units, and outputting an optical signal input from any one input / output side of the plurality of one input / output sides to one or more other one input / output sides of the plurality of one input / output sides, the input / output unit transmits optical signals of wavelengths different from each other among the plurality of chiplets to one of the two input / output sides, and receives an optical signal of a wavelength different from the wavelength of the optical signal to be output from the other of the two input / output sides; Processing unit.

2. the input / output unit includes a transmitter that transmits the optical signal obtained by modulating signal light output from a light source using transmission data including data to be transmitted to one of the two input / output sides; The processor according to claim 1 .

3. The input / output unit a wavelength filter that passes an optical signal of a predetermined wavelength among optical signals input from the other of the two input / output sides; a receiving unit that receives the transmission data by demodulating the optical signal of the predetermined wavelength that has passed through the wavelength filter; The processor according to claim 2 .

4. The transmission data further includes a destination of the data; The input / output unit a determination unit that determines whether or not to discard the data included in the demodulated transmission data based on the destination included in the demodulated transmission data; The processor according to claim 3 .

5. The input / output unit a setting unit that sets the wavelength of the optical signal to be transmitted and the predetermined wavelength of the wavelength filter; The processing device according to claim 3 or 4.

6. Each of the plurality of one-to-two optical branching units is mounted within the chiplet including the input / output unit to which the two input / output sides are connected. The processing device according to any one of claims 1 to 4.

7. a plurality of chiplets each including a core and an input / output unit; a plurality of one-to-two optical branching units, each having two input / output sides connected to the input / output unit; an n (n is an integer of 3 or more) path optical branching unit connected to one input / output side of the plurality of one-to-two optical branching units and outputting an optical signal input from any one input / output side of the plurality of one input / output sides to one or more other one input / output sides of the plurality of one input / output sides, the input / output unit transmits optical signals of wavelengths different from each other among the plurality of chiplets to one of the two input / output sides, and receives an optical signal of a wavelength different from the wavelength of the optical signal to be output from the other of the two input / output sides; Information processing device.

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